; --------------------------------------------------------------------------------
; @Title: AM243x On-Chip Peripherals
; @Props: Released
; @Author: CMO
; @Changelog: 2023-12-06 CMO
; @Manufacturer: TI - Texas Instruments
; @Doc: Generated (TRACE32, build: 165918.), based on: AM2434_ALV.xml (CCS 12.5.0)
; @Core: Cortex-R5F, Cortex-M4F, Cortex-M3
; @Chip: AM2431, AM2432, AM2434
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: peram243x.per 17314 2024-01-11 10:19:12Z cmorgenstern $

AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
sif (CORENAME()=="CORTEXM3")
tree.close "Core Registers (Cortex-M3)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
group 0x10--0x1b
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "      CLKSOURCE       ,Clock Source" "External,Core"
bitfld.long 0x00 1. "                  TICKINT        ,SysTick Handler" "Not SysTick,SysTick"
textline "                    "
bitfld.long 0x00 0. " ENABLE       ,Counter Enable" "Disabled,Enabled"
;group 0x14++0x03
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,The value to load into the SYST_CVR when the counter reaches 0"
;group 0x18++0x03
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Current Value"
rgroup 0x1c++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "  SKEW            ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "                   TENMS          ,Holds a reload value to be used for 10ms (100Hz) timing"
textline "                    "
rgroup 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER  ,Implementer Code"
bitfld.long 0x00 20.--23. "               VARIANT         ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "                        CONSTANT       ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.word 0x00 4.--15. 1. " PARTNO       ,Number of Processor"
bitfld.long 0x00 0.--3. "             REVISION        ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group 0xd04--0xd17
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET   ,Set Pending NMI Bit" "Not set,Set"
bitfld.long 0x00 28. "          PENDSVSET       ,Set Pending pendSV Bit" "Not set,Set"
bitfld.long 0x00 27. "                   PENDSVCLR      ,Clear Pending pendSV Bit" "Not cleared,Cleared"
textline "                    "
bitfld.long 0x00 26. " PENDSTSET    ,Set Pending SysTick Bit" "Not set,Set"
bitfld.long 0x00 25. "          PENDSTCLR       ,Clear Pending SysTick Bit" "Not cleared,Cleared"
bitfld.long 0x00 23. "               ISRPREEMPT     ,Use Only at Debug Time" "Not active,Active"
textline "                    "
bitfld.long 0x00 22. " ISRPENDING   ,Interrupt Pending Flag" "Not pending,Pending"
hexmask.long.word 0x00 12.--21. 1. "      VECTPENDING     ,Pending ISR Number Field"
bitfld.long 0x00 11. "                      RETTOBASE      ,Interrupt Exception" "Active,Not active"
textline "                    "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE   ,Active ISR Number Field"
;group 0xd08++0x03
line.long 0x04 "VTOR,Vector Table Offset Register"
bitfld.long 0x04 29. " TBLBASE      ,Table Base" "Code,RAM"
hexmask.long.tbyte 0x04 7.--28. 1. "             TBLOFF          ,Vector Table Base Offset Field"
;group 0xd0c++0x03
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY      ,Register Key"
rbitfld.long 0x08 15. "             ENDIANESS       ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "                    PRIGROUP       ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                    "
bitfld.long 0x08 2. " SYSRESETREQ  ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "    VECTCLRACTIVE   ,Clear Active Vector Bit" "Not cleared,Cleared all"
bitfld.long 0x08 0. "               VECTRESET      ,System Reset" "No reset,Reset"
;group 0xd10++0x03
line.long 0x0c "SCR,System Control Register"
bitfld.long 0x0c 4. " SEVONPEND    ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0c 2. "       SLEEPDEEP       ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline "                    "
bitfld.long 0x0c 1. " SLEEPONEXIT  ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
;group 0xd14++0x03
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 9. " STKALIGN     ,8-byte Stack Frame Alignment" "4-byte,8-byte"
bitfld.long 0x10 8. "           BFHFNMIGN       ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
textline "                    "
bitfld.long 0x10 4. " DIV_0_TRP    ,Trap Divide by Zero" "Disabled,Enabled"
bitfld.long 0x10 3. "         UNALIGN_TRP     ,Trap for Unaligned Access" "Disabled,Enabled"
textline "                    "
bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
bitfld.long 0x10 0. "         NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
group 0xd18--0xd23
line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " PRI_7        ,Priority of System Handler 7"
hexmask.long.byte 0x00 16.--23. 1. "               PRI_6           ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x00 8.--15. 1. "                        PRI_5          ,Priority of system handler 5(BusFault)"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " PRI_4        ,Priority of system handler 4(MemManage)"
line.long 0x04 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x04 24.--31. 1. " PRI_11       ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x04 16.--23. 1. "               PRI_10          ,Priority of System Handler 10"
hexmask.long.byte 0x04 8.--15. 1. "                        PRI_9          ,Priority of System Handler 9"
textline "                    "
hexmask.long.byte 0x04 0.--7. 1. " PRI_8        ,Priority of System Handler 8"
line.long 0x08 "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x08 24.--31. 1. " PRI_15       ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x08 16.--23. 1. "               PRI_14          ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x08 8.--15. 1. "                        PRI_13         ,Priority of System Handler 13"
textline "                    "
hexmask.long.byte 0x08 0.--7. 1. " PRI_12       ,Priority of System Handler 12(DebugMonitor)"
group 0xd24++0x3
line.long 0x00 "SHCSR,System Handler Control and State Register"
bitfld.long 0x00 18. " USGFAULTENA  ,USGFAULTENA" "Disabled,Enabled"
bitfld.long 0x00 17. "         BUSFAULTENA     ,BUSFAULTENA" "Disabled,Enabled"
bitfld.long 0x00 16. "                  MEMFAULTENA    ,MEMFAULTENA" "Disabled,Enabled"
textline "                    "
bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
bitfld.long 0x00 14. "     BUSFAULTPENDED  ,BusFault is Pended Started" "Not replaced,Replaced"
bitfld.long 0x00 13. "              MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
textline "                    "
bitfld.long 0x00 11. " SYSTICKACT   ,SysTick is Active" "Not active,Active"
bitfld.long 0x00 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
bitfld.long 0x00 8. "                MONITORACT     ,Monitor is Active" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " SVCALLACT    ,SVCall is Active" "Not active,Active"
bitfld.long 0x00 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
bitfld.long 0x00 1. "                BUSFAULTACT    ,BusFault is Active" "Not active,Active"
textline "                    "
bitfld.long 0x00 0. " MEMFAULTACT  ,MemManage is Active" "Not active,Active"
group 0xd28--0xd3b
line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
bitfld.byte 0x0 7. "       MMARVALID    ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x0 4. "        MSTKERR         ,Stacking Access Violations" "No error,Error"
bitfld.byte 0x0 3. "                  MUNSTKERR      ,Unstack Access Violations" "No error,Error"
textline "                    "
bitfld.byte 0x0 1. " DACCVIOL     ,Data Access Violation" "No error,Error"
bitfld.byte 0x0 0. "         IACCVIOL        ,Instruction Access Violation" "No error,Error"
;group 0xd29++0x00
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID    ,Address Valid" "Not valid,Valid"
bitfld.byte 0x01 4. "        STKERR          ,Stacking from Exception has Caused Bus Faults" "No error,Error"
bitfld.byte 0x01 3. "                  UNSTKERR       ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
textline "                    "
bitfld.byte 0x01 2. " IMPRECISERR  ,Imprecise Data Bus Error" "No error,Error"
bitfld.byte 0x01 1. "         PRECISERR       ,Precise Data Bus Error Return" "No error,Error"
bitfld.byte 0x01 0. "                  IBUSERR        ,Instruction Bus Error Flag" "No error,Error"
;group 0xd2a++0x01
line.word 0x02 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x02 9. "     DIVBYZERO    ,Illegal PC Load" "No error,Error"
bitfld.word 0x02 8. "         UNALIGNED       ,Illegal Unaligned Access" "No error,Error"
bitfld.word 0x02 3. "                  NOCP           ,Attempt to use a coprocessor instruction" "No error,Error"
textline "                    "
bitfld.word 0x02 2. " INVPC        ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
bitfld.word 0x02 1. "         INVSTATE        , Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x02 0. "                  UNDEFINSTR     ,Illegal Processor State" "No error,Error"
;group 0xd2c++0x03
line.long 0x04 "HFSR,Hard Fault Status Register"
bitfld.long 0x04 31. " DEBUGEVT     ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
bitfld.long 0x04 30. "         FORCED          ,Hard Fault Activated" "No error,Error"
bitfld.long 0x04 1. "                  VECTTBL        ,Bus Fault" "No error,Error"
;group 0xd30++0x03
line.long 0x08 "DFSR,Debug Fault Status Register"
bitfld.long 0x08 4. " EXTERNAL     ,External Debug Request Flag" "Not asserted,Asserted"
bitfld.long 0x08 3. "     VCATCH          ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x08 2. "              DWTTRAP        ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
textline "                    "
bitfld.long 0x08 1. " BKPT         ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x08 0. "     HALTED          ,Halt Request Flag" "Not requested,Requested"
;group 0xd34++0x03
line.long 0xc "MMFAR,Memory Manage Fault Address Register"
;group 0xd38++0x03
line.long 0x10 "BFAR,Bus Fault Address Register"
wgroup 0xf00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID        ,Indicates the interrupt to be triggered"
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
tree "CoreSight Identification Registers"
width 6.
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 1. "   C_HALT             ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 5. " C_SNAPSTALL       ,Halting debug to gain control of the core" "Disabled,Enabled"
bitfld.long 0x00 3. "     C_MASKINTS         ,Interrupts Mask" "Not masked,Masked"
textline "                "
bitfld.long 0x00 2. " C_STEP            ,Core Step" "No step,Step"
bitfld.long 0x00 1. "      C_HALT             ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 2. " C_STEP            ,Core Step" "No step,Step"
bitfld.long 0x00 1. "      C_HALT             ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
endif
wgroup 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR            ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. "        REGSEL             ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
group 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "     MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "         MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
textline "                "
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "  MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "  VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "     VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "  VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "     VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "  VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "     MON_REQ    ,DebugMonitor semaphore bit" "0,1"
textline "                "
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "  MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "  VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "     VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "  VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "     VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "  VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group 0x00--0x27
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "  NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "  KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. "  ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
;group 0x04++0x03
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP   ,Remap Base Address Field"
;group 0x08++0x03
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x8 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x8 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0xC 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0xC 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x10 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x10 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x14 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x14 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x18 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x18 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x1C 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x1C 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x20 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x20 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x24 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x24 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
tree "Coresight Management Registers"
rgroup 0xfd0--0xfff
line.long 0x00 "PID4,Peripheral ID4"
line.long 0x04 "PID5,Peripheral ID5"
line.long 0x08 "PID6,Peripheral ID6"
line.long 0x0c "PID7,Peripheral ID7"
line.long 0x10 "PID0,Peripheral ID0"
line.long 0x14 "PID1,Peripheral ID1"
line.long 0x18 "PID2,Peripheral ID2"
line.long 0x1c "PID3,Peripheral ID3"
line.long 0x20 "CID0,Component ID0"
line.long 0x24 "CID1,Component ID1"
line.long 0x28 "CID2,Component ID2"
line.long 0x2c "CID3,Component ID3"
tree.end
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group 0x00--0x1B
line.long 0x00 "DWT_CTRL,DWT Control Register"
bitfld.long 0x00 28.--31. " NUMCOMP    ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22. "        CYCEVTENA   ,Enables Cycle Count Event" "Disabled,Enabled"
bitfld.long 0x00 21. "  FOLDEVTENA  ,Enables Folded Instruction Count Event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 20. " LSUEVTENA  ,Enables LSU Count Event" "Disabled,Enabled"
bitfld.long 0x00 19. "  SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
bitfld.long 0x00 18. "  EXCEVTENA   ,Enables Interrupt Overhead Event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 17. " CPIEVTENA  ,Enables CPI Count Event" "Disabled,Enabled"
bitfld.long 0x00 16. "  EXCTRCENA   ,Enables Interrupt Event Tracing" "Disabled,Enabled"
bitfld.long 0x00 12. "  PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 10.--11. " SYNCTAP    ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
bitfld.long 0x00 9. "  CYCTAP      ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
bitfld.long 0x00 5.--8. "    POSTCNT     ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        CYCCNTENA   ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
;group 0x04++0x03
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
;group 0x08++0x03
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT     ,The base CPI counter"
;group 0x0c++0x03
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT     ,The exception overhead counter"
;group 0x10++0x03
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT   ,Sleep Counter"
;group 0x14++0x03
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT     ,Load-store counter"
;group 0x18++0x03
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT    ,Folded-instruction counter"
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
group.long 0x24++0x03
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x34++0x03
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44++0x03
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x03
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
group.long 0x38++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x38++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
group.long 0x48++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x48++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
group.long 0x58++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x58++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
tree "Coresight Management Registers"
rgroup 0xfd0--0xfff
line.long 0x00 "PID4,Peripheral ID4"
line.long 0x04 "PID5,Peripheral ID5"
line.long 0x08 "PID6,Peripheral ID6"
line.long 0x0c "PID7,Peripheral ID7"
line.long 0x10 "PID0,Peripheral ID1"
line.long 0x14 "PID1,Peripheral ID2"
line.long 0x18 "PID2,Peripheral ID3"
line.long 0x1c "PID3,Peripheral ID4"
line.long 0x20 "CID0,Component ID0"
line.long 0x24 "CID1,Component ID1"
line.long 0x28 "CID2,Component ID2"
line.long 0x2c "CID3,Component ID3"
tree.end
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
sif (CORENAME()=="CORTEXM4F")
tree.close "Core Registers (Cortex-M4F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 9. " DISFPCA        ,Disables lazy stacking of floating point context" "No,Yes"
bitfld.long 0x00 8. "                   DISOOFP        ,Disables floating point instructions completing" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD         ,Disables folding of IT instructions" "No,Yes"
textline "                     "
bitfld.long 0x00 1. " DISDEFWBUF     ,Disables write buffer use during default memory map accesses" "No,Yes"
bitfld.long 0x00 0. "                   DISMCYCINT     ,Disables interruption of multi-cycle instructions" "No,Yes"
group.long 0x10++0x0B
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x00 16. " COUNTFLAG      ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "           CLKSOURCE      ,SysTick clock source" "External,Core"
bitfld.long 0x00 1. "         TICKINT         ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x00 0. " ENABLE         ,Counter Enable" "Disabled,Enabled"
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD         ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF          ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "       SKEW           ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "          TENMS           ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER    ,Implementer Code"
bitfld.long 0x00 20.--23. "                    VARIANT        ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "       ARCHITECTURE    ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO         ,Indicates part number"
bitfld.long 0x00 0.--3. "                  REVISION       ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET     ,Set Pending NMI Bit" "Inactive,Active"
bitfld.long 0x00 28. "              PENDSVSET      ,Set Pending pendSV Bit" "Not pending,Pending"
bitfld.long 0x00 27. "      PENDSVCLR       ,Removes the pending status of the PendSV exception" "No effect,Removed"
textline "                     "
bitfld.long 0x00 26. " PENDSTSET      ,Set Pending SysTick Bit" "Not pending,Pending"
bitfld.long 0x00 25. "           PENDSTCLR      ,Clear Pending SysTick Bit" "No effect,Removed"
bitfld.long 0x00 23. "        ISRPREEMPT      ,Use Only at Debug Time" "Not active,Active"
textline "                     "
bitfld.long 0x00 22. " ISRPENDING     ,Indicates whether an external interrupt" "Not pending,Pending"
hexmask.long.word 0x00 12.--20. 1. "           VECTPENDING    ,Pending ISR Number Field"
bitfld.long 0x00 11. "             RETTOBASE       ,Interrupt Exception" "Active,Not active"
textline "                     "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF         ,Vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY        ,Register Key"
rbitfld.long 0x08 15. "                  ENDIANESS      ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "           PRIGROUP        ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ    ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "         VECTCLRACTIVE  ,Clear Active Vector Bit" "No effect,Clear"
bitfld.long 0x08 0. "        VECTRESET       ,System Reset" "No effect,Reset"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND      ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 2. "            SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
bitfld.long 0x0C 1. "   SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 18. " BP             ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "              IC             ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "         DC              ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 9. " STKALIGN       ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
bitfld.long 0x10 8. "  BFHFNMIGN      ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
bitfld.long 0x10 4. "         DIV_0_TRP       ,Trap Divide by Zero" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP    ,Trap for Unaligned Access" "Disabled,Enabled"
bitfld.long 0x10 1. "              USERSETMPEND   ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
bitfld.long 0x10 0. "          NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7          ,Priority of System Handler 7"
hexmask.long.byte 0x14 16.--23. 1. "                    PRI_6          ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x14 8.--15. 1. "               PRI_5           ,Priority of system handler 5(BusFault)"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4          ,Priority of system handler 4(MemManage)"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11         ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x18 16.--23. 1. "                    PRI_10         ,Priority of System Handler 10"
hexmask.long.byte 0x18 8.--15. 1. "               PRI_9           ,Priority of System Handler 9"
textline "                     "
hexmask.long.byte 0x18 0.--7. 1. " PRI_8          ,Priority of System Handler 8"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15         ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x1C 16.--23. 1. "                    PRI_14         ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x1C 8.--15. 1. "               PRI_13          ,Priority of System Handler 13"
textline "                     "
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12         ,Priority of System Handler 12(DebugMonitor)"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. " USGFAULTENA    ,Enable UsageFault" "Disabled,Enabled"
bitfld.long 0x20 17. "              BUSFAULTENA    ,Enable BusFault" "Disabled,Enabled"
bitfld.long 0x20 16. "         MEMFAULTENA     ,Enable MemManage fault" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED   ,SVCall is pending" "Not pending,Pending"
bitfld.long 0x20 14. "           BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
bitfld.long 0x20 13. "      MEMFAULTPENDED  ,MemManage is pending" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
bitfld.long 0x20 11. "           SYSTICKACT     ,SysTick is Active" "Not active,Active"
bitfld.long 0x20 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT     ,Monitor is Active" "Not active,Active"
bitfld.long 0x20 7. "            SVCALLACT      ,SVCall is Active" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT    ,BusFault is Active" "Not active,Active"
bitfld.long 0x20 0. "            MEMFAULTACT    ,MemManage is Active" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "             MLSPERR        ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "     MSTKERR         ,tacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR      ,Unstack Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "          DACCVIOL       ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "     IACCVIOL        ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "             LSPERR         ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "     STKERR          ,Derived bus fault(exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR       ,Derived bus fault(exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "          IMPRECISERR    ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "     PRECISERR       ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR        ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x00 9. "     DIVBYZERO      ,Divide by zero error" "No error,Error"
bitfld.word 0x00 8. "              UNALIGNED      ,Unaligned access error" "No error,Error"
bitfld.word 0x00 3. "         NOCP            ,A coprocessor access error" "No error,Error"
textline "                     "
bitfld.word 0x00 2. " INVPC          ,An integrity check error" "No error,Error"
bitfld.word 0x00 1. "              INVSTATE       ,Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x00 0. "         UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x07
line.long 0x00 "HFSR,Hard Fault Status Register"
bitfld.long 0x00 31. " DEBUGEVT       ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "          FORCED         ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
bitfld.long 0x00 1. "     VECTTBL         ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
line.long 0x04 "DFSR,Debug Fault Status Register"
bitfld.long 0x04 4. " EXTERNAL       ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
bitfld.long 0x04 3. "          VCATCH         ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x04 2. "     DWTTRAP         ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
textline "                     "
bitfld.long 0x04 1. " BKPT           ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x04 0. "          HALTED         ,Indicates a debug event generated by either" "Not requested,Requested"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 22.--23. " CP11           ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 20.--21. "       CP10           ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 14.--15. "  CP7             ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 12.--13. " CP6            ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 10.--11. "       CP5            ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 8.--9. "  CP4             ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 6.--7. " CP3            ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 4.--5. "       CP2            ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 2.--3. "  CP1             ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 0.--1. " CP0            ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID          ,Indicates the interrupt to be triggered"
width 10.
tree "Feature Registers"
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif CORENAME()=="CORTEXM4F"
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN    ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 8. "       MONRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 6. " BFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "                      MMRDY    ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
bitfld.long 0x00 4. "       HFRDY   ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 3. " THREAD       ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 1. "                       USER     ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "   LSPACT  ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN       ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ      ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
textline "                 "
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x07
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 24.--27. "                 SRTERR   ,Indicates the hardware support for FP short vectors" "Not supported,?..."
bitfld.long 0x00 20.--23. "  SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " DIV          ,Indicates the hardware support for FP divide operations" ",Supported,?..."
bitfld.long 0x00 12.--15. "                     FPEXTRP  ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
bitfld.long 0x00 8.--11. "  DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SNGLPREC     ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "                     A_SIMD   ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP  ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
textline "                 "
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL     ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP    ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT         ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR       ,Register Read/Write" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group.long 0x00++0x07
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV     ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "     NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
bitfld.long 0x00 1. "  KEY   ,Key Field" "Low,High"
bitfld.long 0x00 0. "      ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline ""
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x04 29. " RMPSPT  ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
hexmask.long.tbyte 0x04 5.--28. 0x20 "               REMAP ,Remap Base Address Field"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0xB
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP     ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "             NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 26. "  NOEXTTRIG   ,Shows whether the implementation includes external match signals" "Supported,Not supported"
textline "                        "
rbitfld.long 0x00 25. " NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
rbitfld.long 0x00 24. "  NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 22. "  CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 21. " FOLDEVTENA  ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "       LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "       SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 18. " EXCEVTENA   ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "       CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "       EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "       SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "     CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                        "
bitfld.long 0x00 5.--8. " POSTINIT    ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "             POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "             CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
line.long 0x08 "DWT_CPICNT,CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT      ,The base CPI counter"
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT      ,The exception overhead counter"
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT    ,Sleep Counter"
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT      ,Load-store counter"
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT     ,Folded-instruction counter"
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                        "
group.long 0x20++0x07
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x30)++0x07
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x40)++0x07
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x50)++0x07
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
sif (CORENAME()=="CORTEXR5F")
tree "Core Registers (Cortex-R5F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
width 0x8
; --------------------------------------------------------------------------------
;    Identification registers
; --------------------------------------------------------------------------------
tree "ID Registers"
rgroup.long c15:0x00++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL     ,Implementer code"
bitfld.long 0x0 20.--23.  "           VAR      ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19.  "           ARCH     ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
textline "                 "
hexmask.long.word 0x0 4.--15. 0x1 " PART     ,Primary Part Number"
bitfld.long 0x0 0.--3. "         REV      ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. " CWG      ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
bitfld.long 0x00 20.--23. " ERG      ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. "           DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
bitfld.long 0x0 14.--15. "  L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
textline "                 "
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
rgroup.long c15:0x400--0x400
line.long 0x0 "MPUIR,MPU type register"
hexmask.long.byte 0x00 8.--15. 1. " REGNUM   ,Number of regions"
bitfld.long 0x00 0. "           TYPE     ,Type of MPU regions" "Unified,Seperated"
rgroup.long c15:0x500++0x00
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
textline "                 "
hexmask.long.byte 0x00 16.--23. 1. " AFFL2    ,Affitnity Level 2"
hexmask.long.byte 0x00 8.--15. 1. "           AFFL1    ,Affitnity Level 1"
hexmask.long.byte 0x00 0.--7. 1. "           AFFL0    ,Affitnity Level 0"
textline "                 "
rgroup.long c15:0x0410++0x00
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. " IT         ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      FCSE       ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " ACR        ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      TCM        ,TCM and Associated DMA Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SL         ,Number of Shareability levels implemented" "1,?..."
bitfld.long 0x00 8.--11. "              OS         ,Outermost Shareability domain support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " PMSA       ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  VMSA       ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. " BTB        ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "   L1TCO      ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " L1UCMO     ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "  L1HCMO     ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " L1UCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "  L1HCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. " HAF        ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "  WFI        ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " MBF        ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      UTLBMO     ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " HTLBMO     ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      HL1CMRO    ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " HL1BPCRO   ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  HL1FPCRO   ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. " SS         ,Supersection support" "Supported,?..."
bitfld.long 0x00 20.--23. "      CW         ,Coherent walk" "Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " MB         ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " HCMOSW     ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      HCMOMVA    ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c15:0x020++0x00
line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVI       ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "  DEBI       ,Debug Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " CI         ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "  CBI        ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " BI         ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "      BCI        ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 0.--3. " SI         ,Swap Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x120++0x00
line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 28.--31. " JI         ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      INTI       ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " IMMI       ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      ITEI       ,If Then Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " EXTI       ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      E2I        ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " E1I        ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      ENDI       ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x220++0x00
line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " RI         ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      PSRI       ,PSR Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " UMI        ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      SMI        ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " MI         ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      II         ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " MHI        ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      LSI        ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x320++0x00
line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 28.--31. " T2E        ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      NOPI       ,True NOP Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " TCI        ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      TBI        ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SPI        ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      SVCI       ,SVC Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SIMDI      ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      SI         ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x420++0x00
line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 28.--31. " SWP_FRAC   ,SWAP_frac" "Supported,?..."
bitfld.long 0x00 24.--27. "      PSR_M_I    ,PSR_M Instructions Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " EI         ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      BI         ,Barrier Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SMII       ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      WBI        ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " WSI        ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      UI         ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
rgroup.long c15:0x0620++0x00
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
rgroup.long c15:0x0720++0x00
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
rgroup.long c15:0x010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "  STATE2 ,Java Extension Interface Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "  STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM    ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. "  SE     ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      PM     ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
textline "                 "
rgroup.long c15:0x210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "  TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "      TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "      SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c15:0x310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c15:0x02f++0x00
line.long 0x00 "BO1R,Build Options 1 Register"
hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR    ,Default high address for the TCM"
bitfld.long 0x00 1. "                  FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented"
textline "                 "
bitfld.long 0x00 0. " PP_BUS_ECC          ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented"
group.long c15:0x12f++0x00
line.long 0x00 "BO2R,Build Options 2 Register"
bitfld.long 0x00 31. " NUM_CPU             ,Number of CPUs" "1,2"
bitfld.long 0x00 30. "                       LOCK_STEP       ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
textline "                 "
bitfld.long 0x00 29. " NO_ICACHE           ,Indicate whether the CPU contains instruction cache" "Yes,No"
bitfld.long 0x00 28. "                     NO_DCACHE       ,Indicate whether the CPU contains data cache" "Yes,No"
textline "                 "
bitfld.long 0x00 26.--27. " ATCM_ES             ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
bitfld.long 0x00 23.--25. "  BTCM_ES         ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
textline "                 "
bitfld.long 0x00 23. " NO_IE               ,Indicate whether the processor supports big-endian instructions" "Yes,No"
bitfld.long 0x00 22. "                     NO_FPU          ,Indicate whether the CPU contains a floating point unit" "Yes,No"
textline "                 "
bitfld.long 0x00 20.--21. " MPU_REGIONS         ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
bitfld.long 0x00 17.--19. "              BREAK_POINTS    ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
textline "                 "
bitfld.long 0x00 14.--16. " WATCH_POINTS        ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "                       NO_A_TCM_INF    ,Indicate whether the CPUs contain ATCM ports" "Yes,No"
textline "                 "
bitfld.long 0x00 12. " NO_B0_TCM_INF       ,Indicate whether the CPUs contain B0TCM ports" "Yes,No"
bitfld.long 0x00 11. "                     NO_B1_TCM_INF   ,Indicate whether the CPUs contain B1TCM ports" "Yes,No"
textline "                 "
bitfld.long 0x00 10. " TCMBUSPARITY        ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes"
bitfld.long 0x00 9. "                     NO_SLAVE        ,Indicate whether the CPU contains an AXI slave port" "Yes,No"
textline "                 "
bitfld.long 0x00 7.--8. " ICACHE_ES           ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
bitfld.long 0x00 5.--6. "         DCACHE_ES       ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
textline "                 "
bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No"
bitfld.long 0x00 3. "                     AXI_BUS_ECC     ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes"
textline "                 "
bitfld.long 0x00 2. " SL                  ,Indicate whether the processor has been built with split/lock logic" "No,Yes"
bitfld.long 0x00 1. "                     AHB_PP          ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes"
textline "                 "
bitfld.long 0x00 0. " MICRO_SCU           ,Indicate whether the processor contain an ACP interface" "No,Yes"
group.long c15:0x72f++0x00
line.long 0x00 "POR,Pin Options Register"
bitfld.long 0x00 4. " DBGNOCLKSTOP        ,Value of the DBGNOCLKSTOP pin" "Low,High"
bitfld.long 0x00 3. "                    INTSYNCEN       ,Value of the INTSYNCEN pin" "Low,High"
textline "                 "
bitfld.long 0x00 2. " IRQADDRVSYNCEN      ,Value of the IRQADDRVSYNCEN pin" "Low,High"
bitfld.long 0x00 1. "                    SLBTCMSB        ,Value of the SLBTCMSBm pin" "Low,High"
textline "                 "
bitfld.long 0x00 0. " PARITYLEVEL         ,Value of the PARITYLEVEL pin" "Low,High"
tree.end
width 0x8
tree "System Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE  ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. "   TE  ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. "    AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. "  TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. "  NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 25. " EE  ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. "   VE  ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI  ,Fast Interrupts enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 19. " DZ  ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. "  BR  ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. "  RR  ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. "   V   ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline "                 "
bitfld.long 0x0 12. " I   ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. "  Z   ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. "  C   ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. "  A   ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. "  M   ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x101++0x00
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 31. " DICDI     ,Disable Case C dual issue control" "Enable,Disable"
bitfld.long 0x00 30. "    DIB2DI    ,Disable Case B2 dual issue control" "Enable,Disable"
bitfld.long 0x00 29. "    DIB1DI    ,Disable Case B1 dual issue control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 28. " DIADI     ,Disable Case A dual issue control" "Enable,Disable"
bitfld.long 0x00 27. "    B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 26. "    B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
textline "                 "
bitfld.long 0x00 25. " ATCMPCEN  ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 24. "    AXISCEN   ,AXI slave cache access enable" "Disable,Enable"
bitfld.long 0x00 23. "    AXISCUEN  ,AXI slave cache User mode access enable" "Disable,Enable"
textline "                 "
bitfld.long 0x00 22. " DILSM     ,Disable LIL on load/store multiples" "Enable,Disable"
bitfld.long 0x00 21. "    DEOLP     ,Disable end of loop prediction" "Enable,Disable"
bitfld.long 0x00 20. "    DBHE      ,Disable BH extension" "Enable,Disable"
textline "                 "
bitfld.long 0x00 19. " FRCDIS    ,Fetch rate control disable" "Enable,Disable"
bitfld.long 0x00 17. "    RSDIS     ,Return stack disable" "Enable,Disable"
bitfld.long 0x00 15.--16. "    BP        ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
textline "                 "
bitfld.long 0x00 14. " DBWR      ,Disable write_burst on AXI master" "Enable,Disable"
bitfld.long 0x00 13. "    DLFO      ,Disable linefill optimization in the AXI master" "Enable,Disable"
bitfld.long 0x00 12. "    ERPEG     ,Enable random parity error generation" "Disable,Enable"
textline "                 "
bitfld.long 0x00 11. " DNCH      ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable"
bitfld.long 0x00 10. "    FORA      ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
bitfld.long 0x00 9. " FWT       ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
textline "                 "
bitfld.long 0x00 8. " FDSnS     ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
bitfld.long 0x00 7. " SMOV      ,sMOV disabled" "Enabled,Disabled"
bitfld.long 0x0 6. "   DILS      ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
textline "                 "
bitfld.long 0x00 3.--5. " CEC       ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..."
textline "                 "
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable"
bitfld.long 0x00 1. "    B0TCMECEN ,B0TCM external error enable" "Disable,Enable"
bitfld.long 0x00 0. "    ATCMECEN  ,ATCM external error enable" "Disable,Enable"
textline " "
group.long c15:0x0f++0x00
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
bitfld.long 0x00 22. " DCHE      ,Disable hard-error support in the caches" "Enable,Disable"
bitfld.long 0x00 21. "    DR2B      ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
bitfld.long 0x00 20. "    DF6DI     ,F6 dual issue control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 19. " DF2DI     ,F2 dual issue control" "Enable,Disable"
bitfld.long 0x00 18. "    DDI       ,F1/F3/F4 dual issue control" "Enable,Disable"
bitfld.long 0x00 17. "    DOODPFP   ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 16. " DOOFMACS  ,Out-of-order FMACS control" "Enable,Disable"
bitfld.long 0x00 13. "    IXC       ,Floating-point inexact exception output mask" "Mask,Propagate"
bitfld.long 0x00 12. "  OFC       ,Floating-point overflow exception output mask" "Mask,Propagate"
textline "                 "
bitfld.long 0x00 11. " UFC       ,Floating-point underflow exception output mask" "Mask,Propagate"
bitfld.long 0x00 10. "  IOC       ,Floating-point invalid operation exception output mask" "Mask,Propagate"
bitfld.long 0x00 9. "  DZC       ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
textline "                 "
bitfld.long 0x00 8. " IDC       ,Floating-point input denormal exception output mask" "Mask,Propagate"
bitfld.long 0x00 3. "  BTCMECC   ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
bitfld.long 0x00 2. "    ATCMECC   ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
textline "                 "
bitfld.long 0x00 1. " BTCMRMW   ,Enable 64-bit stores on BTCMs" "Disable,Enable"
bitfld.long 0x00 0. "    ATCMRMW   ,Enable 64-bit stores on ATCM" "Disable,Enable"
textline " "
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. " ASEDIS    ,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 30. "        D32DIS    ,Disable use of D16-D31 of the VFP register file" "No,Yes"
textline "                 "
bitfld.long 0x0 26.--27. " CP13      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 24.--25. " CP12      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 22.--23. " CP11      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 20.--21. " CP10      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 18.--19. " CP9       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 16.--17. " CP8       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 14.--15. " CP7       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 12.--13. " CP6       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 10.--11. " CP5       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 8.--9. " CP4       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 6.--7. " CP3       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 4.--5. " CP2       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 2.--3. " CP1       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 0.--1. " CP0       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                      "
group.long c15:0x000b++0x00
line.long 0x00 "SPCR,Slave Port Control Register"
bitfld.long 0x00 1. " PRIV    ,Privilege access only" "User/Privilege,Privilege only"
bitfld.long 0x00 0. "  AXISLEN ,AXI slave port disable" "Enabled,Disabled"
tree.end
width 0x8
tree "MPU Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE  ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. "   TE  ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. "    AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. "  TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. "  NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 25. " EE  ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. "   VE  ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI  ,Fast Interrupts enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 19. " DZ  ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. "  BR  ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. "  RR  ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. "   V   ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline "                 "
bitfld.long 0x0 12. " I   ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. "  Z   ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. "  C   ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. "  A   ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. "  M   ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x05++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 12. " EXT      ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 11. "            RW       ,Access Caused an Abort Type" "Read,Write"
textline "                 "
bitfld.long 0x00 4.--7. " DOMAIN   ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10.  "               STATUS   ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x15++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. "                SIDE     ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline "                 "
bitfld.long 0x00 21. " REC_ERR  ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. "   SIDE_EXT ,Source of the error" "Internal,External"
textline "                 "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,Index Value for The Access Giving the Error Register"
group.long c15:0x06++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
textline " "
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. " EXT      ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 0.--3. 10. "            STATUS   ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. "                SIDE     ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline "                 "
bitfld.long 0x00 21. " REC_ERR  ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. "   SIDE_EXT ,Source of the error" "Internal,External"
textline "                 "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,Index Value for The Access Giving the Error Register"
group.long c15:0x206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
textline " "
group.long c15:0x0016++0x00
line.long 0x00 "RBAR,Region Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group.long c15:0x0216++0x00
line.long 0x00 "RSER,Region Size and Enable Register"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group.long c15:0x0416++0x00
line.long 0x00 "RACR,Region Access Control Register"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " TYPE  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
group.long c15:0x0026++0x00
line.long 0x00 "MRNR,Memory Region Number Register"
bitfld.long 0x00 0.--3. " REGION  ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
group.long c15:0x010d++0x00
line.long 0x00 "CIDR,Context ID Register"
group.long c15:0x20d++0x00
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
group.long c15:0x30d++0x00
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
group.long c15:0x40d++0x00
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
width 0x08
tree "MPU regions"
group c15:0x0016++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RBAR0,Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RSER0,Region Size and Enable Register 0"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RACR0,Region Access Control Register 0"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RBAR1,Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RSER1,Region Size and Enable Register 1"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RACR1,Region Access Control Register 1"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RBAR2,Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RSER2,Region Size and Enable Register 2"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RACR2,Region Access Control Register 2"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RBAR3,Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RSER3,Region Size and Enable Register 3"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RACR3,Region Access Control Register 3"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RBAR4,Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RSER4,Region Size and Enable Register 4"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RACR4,Region Access Control Register 4"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RBAR5,Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RSER5,Region Size and Enable Register 5"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RACR5,Region Access Control Register 5"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RBAR6,Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RSER6,Region Size and Enable Register 6"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RACR6,Region Access Control Register 6"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RBAR7,Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RSER7,Region Size and Enable Register 7"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RACR7,Region Access Control Register 7"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RBAR8,Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RSER8,Region Size and Enable Register 8"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RACR8,Region Access Control Register 8"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RBAR9,Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RSER9,Region Size and Enable Register 9"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RACR9,Region Access Control Register 9"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RBAR10,Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RSER10,Region Size and Enable Register 10"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RACR10,Region Access Control Register 10"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RBAR11,Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RSER11,Region Size and Enable Register 11"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RACR11,Region Access Control Register 11"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RBAR12,Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RSER12,Region Size and Enable Register 12"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RACR12,Region Access Control Register 12"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RBAR13,Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RSER13,Region Size and Enable Register 13"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RACR13,Region Access Control Register 13"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RBAR14,Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RSER14,Region Size and Enable Register 14"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RACR14,Region Access Control Register 14"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RBAR15,Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RSER15,Region Size and Enable Register 15"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RACR15,Region Access Control Register 15"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
tree.end
tree.end
width 0x9
tree "TCM Control and Configuration"
rgroup.long c15:0x200++0x00
line.long 0x00 "TCMTR,TCM Type Register"
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
group.long c15:0x019++0x00
line.long 0x00 "BTCMRR,BTCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address (physical address)"
bitfld.long 0x00 2.--6. "  SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Enable instruction TCM" "Disabled,Enabled"
group.long c15:0x119++0x00
line.long 0x00 "ATCMRR,ATCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address (physical address)"
bitfld.long 0x00 2.--6. "  SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Enable instruction TCM" "Disabled,Enabled"
rgroup.long c15:0x29++0x00
line.long 0x00 "TCMSEL,TCM Selection Register"
textline " "
group.long c15:0x10f++0x00
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x20f++0x00
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x30f++0x00
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
tree.end
width 0xC
tree "Cache Control and Configuration"
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. " LOU      ,Level of Unification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "  LOC       ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
textline "                     "
bitfld.long 0x00 21.--23. " CL8      ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "  CL7       ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 15.--17. " CL6      ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "  CL5       ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 9.--11. " CL4      ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "  CL3       ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 3.--5. " CL2      ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "  CL1       ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
rgroup.long c15:0x1700++0x00
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x00
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT       ,Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. "  WB     ,Write-Back" "Not supported,Supported"
textline "                     "
bitfld.long 0x00 29. " RA       ,Read-Allocate" "Not supported,Supported"
bitfld.long 0x00 28. "  WA     ,Write-Allocate" "Not supported,Supported"
textline "                     "
hexmask.long.word 0x00 13.--27. 1. " NUMSETS  ,Number of sets"
hexmask.long.word 0x00 3.--12. 1. "           ASSOCIATIVITY ,Associativity"
textline "                     "
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
group.long c15:0x2000++0x00
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL    ,Cache level to select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "              IND    ,Instruction or data or unified cache to use" "Data/unified,Instruction"
group.long c15:0x03f++0x00
line.long 0x00 "CFLR,Correctable Fault Location Register"
bitfld.long 0x00 26.--29. " WAY      ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--25. "             SIDE   ,Source of the error" "0,1,2,3"
textline "                     "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,index of the location where the error occurred"
bitfld.long 0x00 0.--1. "           TYPE   ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
group.long c15:0x5f++0x00
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
bitfld.long 0x00 30.--31. " WAY      ,Cache way to invalidate or clean" "0,1,2,3"
hexmask.long.byte 0x00 5.--10. 1. "              SET    ,Cache set to invalidate or clean"
group.long c15:0xef++0x00
line.long 0x00 "CSOR,Cache Size Override Register"
bitfld.long 0x00 4.--7. " Dcache   ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
bitfld.long 0x00 0.--3. "       Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
tree.end
width 12.
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x00 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "           IDCODE ,Identification code"
bitfld.long 0x00 11.--15. "           N  ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. "           DP ,Disable PMCCNTR when prohibited" "No,Yes"
textline "                     "
bitfld.long 0x00 4. " X   ,Export enable" "Disabled,Enabled"
bitfld.long 0x00 3. "     D      ,Clock divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "  C  ,Clock counter reset" "No action,Reset"
bitfld.long 0x00 1. "    P  ,Event counter reset" "No action,Reset"
textline "                     "
bitfld.long 0x00 0. " E   ,Enable" "Disabled,Enabled"
group.long c15:0x1c9++0x00
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
eventfld.long 0x00 31. " C   ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,PMN2 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,PMN1 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,PMN0 Enabled / Enable / Disable  counter" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. " C   ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,PMN2 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,PMN1 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,PMN0 Enabled / Enable / Disable  counter" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
eventfld.long 0x00 31. " C   ,CCNT overflowed" "No overflow,Overflow"
eventfld.long 0x00  2. "  P2     ,PMN2 overflowed" "No overflow,Overflow"
eventfld.long 0x00  1. "  P1 ,PMN1 overflowed" "No overflow,Overflow"
eventfld.long 0x00  0. "  P0 ,PMN0 overflowed" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x0 "PMSWINC,Software Increment Register"
eventfld.long 0x00  2. " P2  ,Increment  PMN2" "No action,Increment"
eventfld.long 0x00  1. "    P1     ,Increment  PMN1" "No action,Increment"
eventfld.long 0x00  0. "    P0 ,Increment  PMN0" "No action,Increment"
group.long c15:0x01d9++0x00
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
group.long c15:0x02d9++0x00
line.long 0x00 "PMXEVCNTR,Event Count Register"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Counter Selection Register"
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Cycle Count Register"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "ESR0,Event Selection Register 0"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "ESR1,Event Selection Register 1"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "ESR2,Event Selection Register 2"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,User Enable Register"
bitfld.long 0x00  0. " EN  ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
eventfld.long 0x00 31. " C   ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,Interrupt on PMN2 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
eventfld.long 0x00 31. " C   ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,Interrupt on PMN2 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
tree "Validation Registers"
group.long c15:0x01f++0x00
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x11f++0x00
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x21f++0x00
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow reset request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x31f++0x00
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow debug request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
group.long c15:0x41f++0x00
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x51f++0x00
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x61f++0x00
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow reset request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x71f++0x00
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow debug request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
tree.end
tree.end
width 11.
width 18.
tree "Debug Registers"
tree "Processor Identifier Registers"
rgroup.long c14:832.++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL       ,Implementer code"
hexmask.long.byte 0x0 20.--23. 0x1 "               SPECREV    ,Variant number"
textline "                           "
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH       ,Architecture"
hexmask.long.word 0x0 4.--15. 0x1 "               PARTNUM    ,Part Number"
textline "                           "
hexmask.long.byte 0x0 0.--3. 0x1 " REV        ,Layout Revision"
rgroup.long c14:833.++0x00
line.long 0x00 "CACHETYPE,Cache Type Register"
bitfld.long 0x00 16.--19. " DMINLINE   ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
bitfld.long 0x00 14.--15. "  L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " IMINLINE   ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
rgroup.long c14:834.++0x00
line.long 0x00 "TCMTR,TCM Type Register"
group.long c14:835.++0x00
line.long 0x00 "AMIDR,Alias of MIDR"
rgroup.long c14:836.++0x00
line.long 0x00 "MPUTR,MPU Type Register"
rgroup.long c14:837.++0x00
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
group.long c14:838.++0x00
line.long 0x00 "AMIDR0,Alias of MIDR"
group.long c14:839.++0x00
line.long 0x00 "AMIDR1,Alias of MIDR"
rgroup.long c14:840.++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3     ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        STATE2     ,Java Extension Interface Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " STATE1     ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        STATE0     ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c14:841.++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM        ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. "        SE         ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " PM         ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup.long c14:842.++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM     ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "    TDM_MM     ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " TDM_CB     ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    CDM_MM     ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " SDM_CB     ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    CDM_CB     ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c14:843.++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c14:844.++0x00
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
bitfld.long 0x00 28.--31. " IT         ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        FCSE       ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " ACR        ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        TCM        ,TCM and Associated DMA Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " CC_PLEA    ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    CC_CPUA    ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " PMSA       ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    VMSA       ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c14:845.++0x00
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. " BTB        ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "     L1TCO      ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " L1UCMO     ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "    L1HCMO     ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " L1UCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    L1HCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c14:846.++0x00
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
bitfld.long 0x00 28.--31. " HAF        ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "    WFI        ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " MBF        ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        UTLBMO     ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " HTLBMO     ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        HL1CMRO    ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " HL1BPCRO   ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    HL1FPCRO   ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c14:847.++0x00
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
bitfld.long 0x00 4.--7. " HCMOSW     ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        HCMOMVA    ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c14:848.++0x00
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
bitfld.long 0x00 24.--27. " DIVI       ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "    DEBI       ,Debug Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 16.--19. " CI         ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "    CBI        ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 8.--11. " BI         ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "        BCI        ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " AI         ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:849.++0x00
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
bitfld.long 0x00 28.--31. " JI         ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        INTI       ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " IMMI       ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        ITEI       ,If Then Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " EXTI       ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        E2I        ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " E1I        ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        ENDI       ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:850.++0x00
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
bitfld.long 0x00 28.--31. " RI         ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        PSRI       ,PSR Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " UMI        ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        SMI        ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " MI         ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        II         ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " MHI        ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        LSI        ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:851.++0x00
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
bitfld.long 0x00 28.--31. " T2E        ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        NOPI       ,True NOP Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " TCI        ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        TBI        ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " SPI        ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        SWII       ,SWI Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " SIMDI      ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        SI         ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:852.++0x00
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
bitfld.long 0x00 20.--23. " EI         ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        BI         ,Barrier Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " SMII       ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        WBI        ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " WSI        ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        UI         ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c14:853.++0x00
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
tree.end
width 15.
tree "Coresight Management Registers"
group.long c14:960.++0x00
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
bitfld.long 0x00 0. " INTMODE      ,Processor integration mode" "Normal,Integration"
group.long c14:1000.++0x00
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
hexmask.long.byte 0x00 0.--7. 1. " CTS          ,Claim tag set"
group.long c14:1001.++0x00
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
hexmask.long.byte 0x00 0.--7. 1. " CTC          ,Claim tag clear"
wgroup.long c14:1004.++0x00
line.long 0x00 "DBGLAR,Lock Access Register"
rgroup.long c14:1005.++0x00
line.long 0x00 "DBGLSR,Lock Status Register"
bitfld.long 0x00 2. " 32BA         ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
textline "                        "
bitfld.long 0x00 1. " LB           ,Lock bit" "Not locked,Locked"
bitfld.long 0x00 0. "              LIB          ,Lock implemented bit" "Not locked,Locked"
rgroup.long c14:1006.++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
bitfld.long 0x00 7. " SNDFI        ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "         SNDFE        ,Secure non-invasive debug features enable" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " SIDFI        ,Secure invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "         SIDFE        ,Secure invasive debug features enabled" "Disabled,Enabled"
rgroup.long c14:1011.++0x00
line.long 0x00 "DBGDEVTYPE,Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE      ,Subtype"
hexmask.long.byte 0x00 0.--3. 1. "                      MAIN_CLASS   ,Main class"
tree.end
textline "                     "
width 12.
rgroup.long c14:0.++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. " WRP          ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
bitfld.long 0x0 24.--27. "                       BRP          ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
textline "                     "
bitfld.long 0x0 20.--23. " CTX_CMP      ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
hexmask.long.byte 0x0 16.--19. 1. "                      VERSION      ,Debug Architecture Version"
textline "                     "
bitfld.long 0x0 15. " DEVID        ,Debug Device ID" "Low,High"
bitfld.long 0x0 14. "                    NSUHD        ,Secure User halting debug-mode" "Low,High"
textline "                     "
bitfld.long 0x0 13. " PCSR         ,PC Sample register implemented" "Low,High"
bitfld.long 0x0 12. "                    SE           ,Security Extensions implemented" "Low,High"
textline "                     "
hexmask.long.byte 0x0 4.--7. 1. " VARIANT      ,Implementation-defined Variant Number"
hexmask.long.byte 0x0 0.--3. 1. "                      REVISION     ,Implementation-defined Revision Number"
group.long c14:34.++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
bitfld.long 0x00 30. " RXFULL       ,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "                   TXFULL       ,DBGDTRTX Register full" "Empty,Full"
textline "                     "
bitfld.long 0x00 25. " PIPEADV      ,PIPEADV Processor Idle flag" "Not idle,Idle"
bitfld.long 0x00 24. "                INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
textline "                     "
bitfld.long 0x00 20.--21. " EXTDCCMODE   ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
bitfld.long 0x00 19. "            ADADISCARD   ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
bitfld.long 0x00 18. "         NS      ,Non-secure status bit" "Secure,Non-secure"
textline "                     "
bitfld.long 0x00 17. " SPNIDDIS     ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "                     SPIDDIS      ,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "            MDBGEN  ,Monitor debug-mode enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 14. " HDBGEN       ,Halting debug-mode" "Disabled,Enabled"
bitfld.long 0x00 13. "                ITREN        ,Execute ARM instruction enable" "Disabled,Enabled"
bitfld.long 0x00 12. "       UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
textline "                     "
bitfld.long 0x00 11. " INTDIS       ,Interrupt disable" "No,Yes"
bitfld.long 0x00 10. "                     DBGACK       ,Force debug acknowledge" "Normal,Forced"
textline "                     "
bitfld.long 0x00 8. " UND_L        ,Sticky undefined bit" "Not occurred,Occurred"
bitfld.long 0x00 7. "            ADABORT      ,Asynchronous data abort" "Not aborted,Aborted"
bitfld.long 0x00 6. "    SDABORT ,Synchronous data abort" "Not aborted,Aborted"
textline "                     "
bitfld.long 0x00 2.--5. " MOE          ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
bitfld.long 0x00 1. "  RESTARTED    ,Processor restarted" "Pending,Exited"
bitfld.long 0x00 0. "        HALTED  ,Processor halted" "Non-debug,Debug"
group.long c14:0x7++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 7. " FIQVCE_S     ,FIQ vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 6. " IRQVCE_S     ,IRQ vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "                DAVCE_S      ,Data Abort vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 3. " PAVCE_S      ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 2. "                SVCVCE_S     ,SVC vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 1. " UIVCE_S      ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "                RVCE         ,Reset vector catch enable" "Disabled,Enabled"
hgroup.long c14:32.++0x0
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
in
group.long c14:35.++0x00
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
hexmask.long 0x00 0.--31. 1. " HTD          ,Host -> target data"
group.long c14:10.++0x0
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
bitfld.long 0x00 2. " NWT          ,Write through disable" "No,Yes"
bitfld.long 0x00 1. "                     NIL          ,L1 instruction cache line-fills disable" "No,Yes"
textline "                     "
bitfld.long 0x00 0. " NDL          ,L1 data cache line-fills disable" "No,Yes"
wgroup.long c14:33.++0x0
line.long 0x00 "DBGITR,Instruction Transfer Register"
wgroup.long c14:36.++0x0
line.long 0x00 "DBGDRCR,Debug Run Control Register"
bitfld.long 0x00 4. " CMR          ,Cancel memory requests" "Not cancel,Cancel"
bitfld.long 0x00 3. "              CSPA         ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
textline "                     "
bitfld.long 0x00 2. " CSE          ,Clear Sticky Exceptions bits" "No effect,Clear"
bitfld.long 0x00 1. "               RR           ,Restart request" "No effect,Restart"
textline "                     "
bitfld.long 0x00 0. " HR           ,Halt request" "No effect,Halt"
textline "                     "
rgroup.long c14:193.++0x0
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented"
group.long c14:196.++0x0
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
bitfld.long 0x00 2. " HCWR         ,Hold core warm reset" "Not held,Held"
textline "                     "
bitfld.long 0x00 1. " CWRR         ,Reset reguest" "Not requested,Requested"
bitfld.long 0x00 0. "    CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
rgroup.long c14:197.++0x0
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
bitfld.long 0x00 3. " SR           ,Sticky Reset Status" "Not reset,Reset"
bitfld.long 0x00 2. "        R         ,Reset Status" "No reset,Reset"
textline "                     "
bitfld.long 0x00 1. " SPD          ,Sticky Power-down Status" "Not reset,Reset"
bitfld.long 0x00 0. "        PU        ,Power-up Status" "Powered down,Powered up"
tree.end
width 7.
tree "Breakpoint Registers"
group.long c14:64.++0x0
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
group.long c14:80.++0x0
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:65.++0x0
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
group.long c14:81.++0x0
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:66.++0x0
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
group.long c14:82.++0x0
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:67.++0x0
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
group.long c14:83.++0x0
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:68.++0x0
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
group.long c14:84.++0x0
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:69.++0x0
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
group.long c14:85.++0x0
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:70.++0x0
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
group.long c14:86.++0x0
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:71.++0x0
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
group.long c14:87.++0x0
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.long c14:96.++0x0
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:112.++0x0
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:97.++0x0
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:113.++0x0
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:98.++0x0
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:114.++0x0
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:99.++0x0
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:115.++0x0
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:100.++0x0
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:116.++0x0
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:101.++0x0
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:117.++0x0
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:102.++0x0
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:118.++0x0
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:103.++0x0
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:119.++0x0
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:6.++0x0
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
tree.end
width 11.
AUTOINDENT.POP
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "ADC0"
base ad:0x0
tree "ADC0 (ADC0)"
base ad:0x28001000
rgroup.long 0x0++0x3
line.long 0x0 "ADCREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility"
hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision"
group.long 0x38++0xB
line.long 0x0 "ADCREGS_DMAENABLE_SET,The DMAENABLE_SET register allows the enabling of DMA requests"
bitfld.long 0x0 1. "ENABLE1,enable DMA reguest FIFO1" "0,1"
bitfld.long 0x0 0. "ENABLE0,enable DMA reguest FIFO0" "0,1"
line.long 0x4 "ADCREGS_DMAENABLE_CLR,The DMAENABLE_CLR register allows the disabling of DMA requests"
bitfld.long 0x4 1. "ENABLE1,clears the enable of the DMA reguest FIFO1. Disables DMA request when writing 1" "0,1"
bitfld.long 0x4 0. "ENABLE0,clears the enable of the DMA reguest FIFO0. Disables DMA request when writing 1" "0,1"
line.long 0x8 "ADCREGS_CONTROL,Controls various parameters of the cotroller state."
bitfld.long 0x8 11. "HI_MID_SEL,Functional safety debug mode. =1 choose ADCREFP  =0 VMID reference input to ADC" "0,1"
bitfld.long 0x8 10. "HI_MID_EN,Functional safety debug mode. enable fixed reference to ADC for testing" "0,1"
newline
bitfld.long 0x8 9. "HW_PREEMPT,1 steps are preempted" "0,1"
bitfld.long 0x8 8. "HW_MAP,1 = hw events enabled" "?,1: hw events enabled"
newline
bitfld.long 0x8 4. "PD,AFE powered down" "0,1"
bitfld.long 0x8 3. "BIAS_SEL,AFE select bias control" "0,1"
newline
bitfld.long 0x8 1. "STEP_ID_EN,writing 1 will store the stepid number with the captured adc data in the fifo" "0,1"
bitfld.long 0x8 0. "MODULE_ENABLE,ADC12_SS module enable bit. After programming all the configuration and step enable registers  write a 1 to this bit to start conversion. Writing a 0 will disable the module after the current conversion. Before turning on again  the.." "0,1"
rgroup.long 0x44++0x3
line.long 0x0 "ADCREGS_SEQUENCER_STAT,SW can read this register to find out the currently"
bitfld.long 0x0 8. "GPADC_BUSY,Monitor the AFE internal calibration  busy bit" "0,1"
bitfld.long 0x0 6. "MEM_INIT_DONE,status of ram initialization  1= ram initialization to 0 after reset is done." "?,1: ram initialization to 0 after reset is done"
newline
bitfld.long 0x0 5. "FSM_BUSY,status of fsm  1= conversion in progress" "?,1: conversion in progress"
hexmask.long.byte 0x0 0.--4. 1. "STEP_IDLE,10000 = idle  000000 -> 01111 corresponds to step 1 -> step 16"
group.long 0x48++0x3
line.long 0x0 "ADCREGS_RANGE,This feature requires the range check interrupt bit to be enabled first."
hexmask.long.word 0x0 16.--27. 1. "HIRANGE,If the sampled data is > value  then interrupt is generated"
hexmask.long.word 0x0 0.--11. 1. "LOWRANGE,If the sampled data is < value  then interrupt is generated"
group.long 0x50++0x7
line.long 0x0 "ADCREGS_MISC,Spare inputs of the AFE are driven by this register. spare outputs from the AFE are read."
hexmask.long.byte 0x0 8.--11. 1. "AFE_SPARE_OUT,Spare outputs from AFE"
hexmask.long.byte 0x0 0.--3. 1. "AFE_SPARE_IN,Spare inputs to AFE"
line.long 0x4 "ADCREGS_STEPENABLE,Contains the enable bit for each step in the sequencer."
bitfld.long 0x4 16. "STEP16,Enable step" "0,1"
bitfld.long 0x4 15. "STEP15,Enable step" "0,1"
newline
bitfld.long 0x4 14. "STEP14,Enable step" "0,1"
bitfld.long 0x4 13. "STEP13,Enable step" "0,1"
newline
bitfld.long 0x4 12. "STEP12,Enable step" "0,1"
bitfld.long 0x4 11. "STEP11,Enable step" "0,1"
newline
bitfld.long 0x4 10. "STEP10,Enable step" "0,1"
bitfld.long 0x4 9. "STEP9,Enable step" "0,1"
newline
bitfld.long 0x4 8. "STEP8,Enable step" "0,1"
bitfld.long 0x4 7. "STEP7,Enable step" "0,1"
newline
bitfld.long 0x4 6. "STEP6,Enable step" "0,1"
bitfld.long 0x4 5. "STEP5,Enable step" "0,1"
newline
bitfld.long 0x4 4. "STEP4,Enable step" "0,1"
bitfld.long 0x4 3. "STEP3,Enable step" "0,1"
newline
bitfld.long 0x4 2. "STEP2,Enable step" "0,1"
bitfld.long 0x4 1. "STEP1,Enable step" "0,1"
rgroup.long 0xE4++0x3
line.long 0x0 "ADCREGS_FIFO0WC,FIFO word count status"
hexmask.long.word 0x0 0.--8. 1. "NUMWDS,number of words in the FIFO"
group.long 0xE8++0x7
line.long 0x0 "ADCREGS_FIFO0THRESHOLD,FIFO threshold"
hexmask.long.byte 0x0 0.--7. 1. "THRESHOLD,Program the desired FIFO0 data sample level minus 1 to reach before generating interrupt to CPU"
line.long 0x4 "ADCREGS_FIFO0DMAREQ,dma request."
hexmask.long.byte 0x4 0.--7. 1. "DMAREQLEVEL,Number of words minus 1 in FIFO0 before generating a DMA request"
rgroup.long 0xF0++0x3
line.long 0x0 "ADCREGS_FIFO1WC,FIFO word count status"
hexmask.long.word 0x0 0.--8. 1. "NUMWDS,number of words in the FIFO"
group.long 0xF4++0x7
line.long 0x0 "ADCREGS_FIFO1THRESHOLD,FIFO threshold"
hexmask.long.byte 0x0 0.--7. 1. "THRESHOLD,Program the desired FIFO1 data sample level minus 1 to reach before generating interrupt to CPU"
line.long 0x4 "ADCREGS_FIFO1DMAREQ,dma request."
hexmask.long.byte 0x4 0.--7. 1. "DMAREQLEVEL,Number of words minus 1 in FIFO1 before generating a DMA request"
rgroup.long 0x100++0x3
line.long 0x0 "ADCREGS_FIFO0DATA,A read from this register will auto increment the FIFO read pointer."
hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled  these bits will be 0"
hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO"
rgroup.long 0x200++0x3
line.long 0x0 "ADCREGS_FIFO1DATA,A read from this register will auto increment the FIFO read pointer."
hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled  these bits will be 0"
hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO"
wgroup.long 0x20++0x3
line.long 0x0 "ADCREGS_EOI,The End of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the EOI for MISC interrupt sources. An eoi_write signal will be generated and another interrupt will be triggered if interrupt.."
bitfld.long 0x0 0. "LINENUMEOI,Write 0 to flag End Of Interrupt." "0,1"
group.long 0x24++0xF
line.long 0x0 "ADCREGS_STATUS_RAW,The IRQ_STATUS_RAW register allows the adc12 interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x0 8. "OUTOFRANGE,sample out of range" "0,1"
bitfld.long 0x0 7. "FIFO1UNFL,fifo under flow" "0,1"
newline
bitfld.long 0x0 6. "FIFO1OVFL,fifo over flow" "0,1"
bitfld.long 0x0 5. "FIFO1THRS,fifo thresholds met" "0,1"
newline
bitfld.long 0x0 4. "FIFO0UNFL,fifo under flow" "0,1"
bitfld.long 0x0 3. "FIFO0OVFL,fifo over flow" "0,1"
newline
bitfld.long 0x0 2. "FIFO0THRS,fifo thresholds met" "0,1"
bitfld.long 0x0 1. "ENDOFEQUENCE,end of sequence" "0,1"
newline
bitfld.long 0x0 0. "AFE_EOC_MISSING,eoc from the analog front end missing at expected time after soc" "0,1"
line.long 0x4 "ADCREGS_STATUS,The IRQ_STATUS register allows the adc12 interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x4 8. "OUTOFRANGE,sample out of range" "0,1"
bitfld.long 0x4 7. "FIFO1UNFL,fifo under flow" "0,1"
newline
bitfld.long 0x4 6. "FIFO1OVFL,fifo over flow" "0,1"
bitfld.long 0x4 5. "FIFO1THRS,fifo thresholds met" "0,1"
newline
bitfld.long 0x4 4. "FIFO0UNFL,fifo under flow" "0,1"
bitfld.long 0x4 3. "FIFO0OVFL,fifo over flow" "0,1"
newline
bitfld.long 0x4 2. "FIFO0THRS,fifo thresholds met" "0,1"
bitfld.long 0x4 1. "ENDOFEQUENCE,end of sequence" "0,1"
newline
bitfld.long 0x4 0. "AFE_EOC_MISSING,eoc from the analog front end missing at expected time after soc" "0,1"
line.long 0x8 "ADCREGS_ENABLE_SET,The IRQ_ENABLE_SET register allows the adc12 interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled"
bitfld.long 0x8 8. "OUTOFRANGE,sample out of range" "0,1"
bitfld.long 0x8 7. "FIFO1UNFL,fifo under flow" "0,1"
newline
bitfld.long 0x8 6. "FIFO1OVFL,fifo over flow" "0,1"
bitfld.long 0x8 5. "FIFO1THRS,fifo thresholds met" "0,1"
newline
bitfld.long 0x8 4. "FIFO0UNFL,fifo under flow" "0,1"
bitfld.long 0x8 3. "FIFO0OVFL,fifo over flow" "0,1"
newline
bitfld.long 0x8 2. "FIFO0THRS,fifo thresholds met" "0,1"
bitfld.long 0x8 1. "ENDOFEQUENCE,end of sequence" "0,1"
newline
bitfld.long 0x8 0. "AFE_EOC_MISSING,eoc from the analog front end missing at expected time after soc" "0,1"
line.long 0xC "ADCREGS_ENABLE_CLR,The IRQ_ENABLE_CLR register allows the adc12 interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled"
bitfld.long 0xC 8. "OUTOFRANGE,sample out of range" "0,1"
bitfld.long 0xC 7. "FIFO1UNFL,fifo under flow" "0,1"
newline
bitfld.long 0xC 6. "FIFO1OVFL,fifo over flow" "0,1"
bitfld.long 0xC 5. "FIFO1THRS,fifo thresholds met" "0,1"
newline
bitfld.long 0xC 4. "FIFO0UNFL,fifo under flow" "0,1"
bitfld.long 0xC 3. "FIFO0OVFL,fifo over flow" "0,1"
newline
bitfld.long 0xC 2. "FIFO0THRS,fifo thresholds met" "0,1"
bitfld.long 0xC 1. "ENDOFEQUENCE,end of sequence" "0,1"
newline
bitfld.long 0xC 0. "AFE_EOC_MISSING,eoc from the analog front end missing at expected time after soc" "0,1"
group.long 0x64++0x7F
line.long 0x0 "ADCREGS_STEPCONFIG_0,The user should write to this register the values"
bitfld.long 0x0 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x0 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x0 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x0 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x0 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x0 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x0 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x4 "ADCREGS_STEPDELAY_0,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x4 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x4 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x8 "ADCREGS_STEPCONFIG_1,The user should write to this register the values"
bitfld.long 0x8 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x8 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x8 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x8 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x8 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x8 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x8 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0xC "ADCREGS_STEPDELAY_1,Controls number of clock periods to sample and delay"
hexmask.long.byte 0xC 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0xC 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x10 "ADCREGS_STEPCONFIG_2,The user should write to this register the values"
bitfld.long 0x10 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x10 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x10 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x10 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x10 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x10 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x10 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x14 "ADCREGS_STEPDELAY_2,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x14 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x14 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x18 "ADCREGS_STEPCONFIG_3,The user should write to this register the values"
bitfld.long 0x18 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x18 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x18 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x18 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x18 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x18 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x18 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x1C "ADCREGS_STEPDELAY_3,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x1C 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x1C 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x20 "ADCREGS_STEPCONFIG_4,The user should write to this register the values"
bitfld.long 0x20 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x20 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x20 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x20 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x20 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x20 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x20 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x24 "ADCREGS_STEPDELAY_4,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x24 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x24 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x28 "ADCREGS_STEPCONFIG_5,The user should write to this register the values"
bitfld.long 0x28 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x28 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x28 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x28 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x28 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x28 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x28 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x2C "ADCREGS_STEPDELAY_5,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x2C 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x2C 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x30 "ADCREGS_STEPCONFIG_6,The user should write to this register the values"
bitfld.long 0x30 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x30 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x30 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x30 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x30 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x30 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x30 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x34 "ADCREGS_STEPDELAY_6,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x34 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x34 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x38 "ADCREGS_STEPCONFIG_7,The user should write to this register the values"
bitfld.long 0x38 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x38 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x38 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x38 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x38 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x38 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x38 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x3C "ADCREGS_STEPDELAY_7,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x3C 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x3C 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x40 "ADCREGS_STEPCONFIG_8,The user should write to this register the values"
bitfld.long 0x40 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x40 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x40 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x40 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x40 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x40 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x40 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x44 "ADCREGS_STEPDELAY_8,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x44 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x44 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x48 "ADCREGS_STEPCONFIG_9,The user should write to this register the values"
bitfld.long 0x48 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x48 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x48 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x48 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x48 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x48 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x48 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x4C "ADCREGS_STEPDELAY_9,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x4C 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x4C 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x50 "ADCREGS_STEPCONFIG_10,The user should write to this register the values"
bitfld.long 0x50 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x50 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x50 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x50 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x50 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x50 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x50 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x54 "ADCREGS_STEPDELAY_10,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x54 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x54 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x58 "ADCREGS_STEPCONFIG_11,The user should write to this register the values"
bitfld.long 0x58 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x58 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x58 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x58 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x58 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x58 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x58 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x5C "ADCREGS_STEPDELAY_11,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x5C 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x5C 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x60 "ADCREGS_STEPCONFIG_12,The user should write to this register the values"
bitfld.long 0x60 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x60 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x60 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x60 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x60 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x60 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x60 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x64 "ADCREGS_STEPDELAY_12,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x64 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x64 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x68 "ADCREGS_STEPCONFIG_13,The user should write to this register the values"
bitfld.long 0x68 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x68 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x68 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x68 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x68 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x68 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x68 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x6C "ADCREGS_STEPDELAY_13,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x6C 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x6C 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x70 "ADCREGS_STEPCONFIG_14,The user should write to this register the values"
bitfld.long 0x70 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x70 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x70 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x70 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x70 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x70 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x70 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x74 "ADCREGS_STEPDELAY_14,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x74 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x74 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
line.long 0x78 "ADCREGS_STEPCONFIG_15,The user should write to this register the values"
bitfld.long 0x78 27. "RANGECHECK,0 = no range sel 1 = compare ADC data with range" "0: no range sel,1: compare ADC data with range"
bitfld.long 0x78 26. "FIFOSEL,Sampled data will be stored in FIFO0 when = 0  FIFO1 when = 1" "0,1"
newline
bitfld.long 0x78 25. "DIFF_CNTRL,Differential control. Single ended when = 0  differential input when = 1" "0,1"
hexmask.long.byte 0x78 19.--22. 1. "SEL_INP_SWC,SEL_INP pins SW configuration"
newline
hexmask.long.byte 0x78 15.--18. 1. "SEL_INM_SWM,SEL_INM pins  negative differential"
bitfld.long 0x78 2.--4. "AVERAGING,000 -> no average 001 -> 2 samples average 010 -> 4 samples average 011 -> 8 samples average 100 -> 16 samples average" "0: no average,1: 2 samples average,?,?,?,?,?,?"
newline
bitfld.long 0x78 0.--1. "MODE,00 SW enabled one shot 01 SW enabled continuous 10 HW synchronized one-shot 11 HW synchronized continuous" "0,1,2,3"
line.long 0x7C "ADCREGS_STEPDELAY_15,Controls number of clock periods to sample and delay"
hexmask.long.byte 0x7C 24.--31. 1. "SAMPLEDELAY,number of ADC clock cycles to sample. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x7C 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
tree.end
tree "ADC0_ECC_REGS (ADC0_ECC_REGS)"
base ad:0x71A000
rgroup.long 0x0++0x3
line.long 0x0 "ECCREGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECCREGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECCREGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x7
line.long 0x0 "ECCREGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECCREGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1"
bitfld.long 0x4 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECCREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1"
bitfld.long 0x0 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECCREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1"
bitfld.long 0x0 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECCREGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECCREGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1"
bitfld.long 0x4 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECCREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1"
bitfld.long 0x0 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECCREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1"
bitfld.long 0x0 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECCREGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECCREGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECCREGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECCREGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "ADC0_FIFO (ADC0_FIFO)"
base ad:0x28000000
rgroup.long 0x100++0x3
line.long 0x0 "ADC12_FIFO_DMA_FIFO0DMADATA,DMA sample FIFO"
hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled  these bits will be 0"
hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO"
rgroup.long 0x200++0x3
line.long 0x0 "ADC12_FIFO_DMA_FIFO1DMADATA,DMA sample FIFO"
hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of channel that captured the data. If tag option is disabled  these bits will be 0"
hexmask.long.word 0x0 0.--11. 1. "ADCDATA,sampled ADC converted data value stored in FIFO"
tree.end
tree.end
tree "CBASS"
base ad:0x0
tree "CBASS0"
tree "CBASS0_ERR (CBASS0_ERR)"
base ad:0x3A000000
rgroup.long 0x0++0x3
line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
rgroup.long 0x24++0x17
line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error."
line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits."
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x50++0x13
line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1"
line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CBASS0_FW (CBASS0_FW)"
base ad:0x45000000
group.long 0x400++0xFF
line.long 0x0 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isam64_ddr_wrap_main_0.ddrss region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_ddr_wrap_main_0.ddrss region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_ddr_wrap_main_0.ddrss region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isam64_ddr_wrap_main_0.ddrss region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_ddr_wrap_main_0.ddrss region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_ddr_wrap_main_0.ddrss region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isam64_ddr_wrap_main_0.ddrss region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_ddr_wrap_main_0.ddrss region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_ddr_wrap_main_0.ddrss region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isam64_ddr_wrap_main_0.ddrss region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_ddr_wrap_main_0.ddrss region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_ddr_wrap_main_0.ddrss region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x80 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isam64_ddr_wrap_main_0.ddrss region 4 firewall."
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x84 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 4 firewall."
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x88 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 4 firewall."
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8C "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 4 firewall."
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x90 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_ddr_wrap_main_0.ddrss region 4 firewall."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x94 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_ddr_wrap_main_0.ddrss region 4 firewall."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x98 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 4 firewall."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x9C "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 4 firewall."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xA0 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isam64_ddr_wrap_main_0.ddrss region 5 firewall."
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xA4 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 5 firewall."
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xA8 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 5 firewall."
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xAC "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 5 firewall."
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xB0 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_ddr_wrap_main_0.ddrss region 5 firewall."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xB4 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_ddr_wrap_main_0.ddrss region 5 firewall."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xB8 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 5 firewall."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xBC "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 5 firewall."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xC0 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isam64_ddr_wrap_main_0.ddrss region 6 firewall."
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xC4 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 6 firewall."
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC8 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 6 firewall."
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xCC "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 6 firewall."
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xD0 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_ddr_wrap_main_0.ddrss region 6 firewall."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xD4 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_ddr_wrap_main_0.ddrss region 6 firewall."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xD8 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 6 firewall."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xDC "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 6 firewall."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xE0 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isam64_ddr_wrap_main_0.ddrss region 7 firewall."
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xE4 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 7 firewall."
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xE8 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 7 firewall."
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xEC "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isam64_ddr_wrap_main_0.ddrss region 7 firewall."
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xF0 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_ddr_wrap_main_0.ddrss region 7 firewall."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xF4 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_ddr_wrap_main_0.ddrss region 7 firewall."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xF8 "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 7 firewall."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xFC "FW_REGS_Isam64_ddr_wrap_main_0_ddrss_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_ddr_wrap_main_0.ddrss region 7 firewall."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x800++0xFF
line.long 0x0 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 0.."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 0.."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 0.."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 1.."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 1.."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 1.."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 2.."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 2.."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 2.."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 3.."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 3.."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 3.."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x80 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 4 firewall."
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x84 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 4 firewall."
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x88 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 4 firewall."
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8C "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 4 firewall."
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x90 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 4 firewall."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x94 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 4.."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x98 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 4.."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x9C "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 4.."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xA0 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 5 firewall."
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xA4 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 5 firewall."
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xA8 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 5 firewall."
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xAC "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 5 firewall."
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xB0 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 5 firewall."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xB4 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 5.."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xB8 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 5.."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xBC "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 5.."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xC0 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 6 firewall."
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xC4 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 6 firewall."
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC8 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 6 firewall."
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xCC "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 6 firewall."
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xD0 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 6 firewall."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xD4 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 6.."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xD8 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 6.."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xDC "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 6.."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xE0 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 7 firewall."
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xE4 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 7 firewall."
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xE8 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 7 firewall."
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xEC "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 7 firewall."
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xF0 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 7 firewall."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xF4 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 7.."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xF8 "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 7.."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xFC "FW_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_acp_w_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_acp_w region 7.."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x3800++0x7F
line.long 0x0 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Imsram32kx64e_main_0.slv region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_0.slv region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_0.slv region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_0.slv region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_0.slv region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Imsram32kx64e_main_0.slv region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_0.slv region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_0.slv region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_0.slv region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_0.slv region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Imsram32kx64e_main_0.slv region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_0.slv region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_0.slv region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_0.slv region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_0.slv region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Imsram32kx64e_main_0.slv region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_0.slv region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_0.slv region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_0.slv region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_0.slv region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Imsram32kx64e_main_0_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_0.slv region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x3C00++0x7F
line.long 0x0 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Imsram32kx64e_main_1.slv region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_1.slv region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_1.slv region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_1.slv region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_1.slv region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Imsram32kx64e_main_1.slv region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_1.slv region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_1.slv region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_1.slv region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_1.slv region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Imsram32kx64e_main_1.slv region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_1.slv region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_1.slv region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_1.slv region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_1.slv region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Imsram32kx64e_main_1.slv region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_1.slv region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_1.slv region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_1.slv region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_1.slv region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Imsram32kx64e_main_1_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_1.slv region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x4000++0x7F
line.long 0x0 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Imsram32kx64e_main_2.slv region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_2.slv region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_2.slv region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_2.slv region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_2.slv region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Imsram32kx64e_main_2.slv region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_2.slv region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_2.slv region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_2.slv region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_2.slv region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Imsram32kx64e_main_2.slv region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_2.slv region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_2.slv region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_2.slv region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_2.slv region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Imsram32kx64e_main_2.slv region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_2.slv region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_2.slv region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_2.slv region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_2.slv region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Imsram32kx64e_main_2_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_2.slv region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x4400++0x7F
line.long 0x0 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Imsram32kx64e_main_5.slv region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_5.slv region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_5.slv region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_5.slv region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_5.slv region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Imsram32kx64e_main_5.slv region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_5.slv region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_5.slv region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_5.slv region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_5.slv region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Imsram32kx64e_main_5.slv region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_5.slv region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_5.slv region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_5.slv region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_5.slv region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Imsram32kx64e_main_5.slv region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_5.slv region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_5.slv region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_5.slv region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_5.slv region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Imsram32kx64e_main_5_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_5.slv region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x4800++0x7F
line.long 0x0 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Imsram32kx64e_main_4.slv region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_4.slv region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_4.slv region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_4.slv region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_4.slv region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Imsram32kx64e_main_4.slv region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_4.slv region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_4.slv region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_4.slv region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_4.slv region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Imsram32kx64e_main_4.slv region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_4.slv region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_4.slv region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_4.slv region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_4.slv region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Imsram32kx64e_main_4.slv region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_4.slv region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_4.slv region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_4.slv region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_4.slv region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Imsram32kx64e_main_4_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_4.slv region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x4C00++0x7F
line.long 0x0 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Imsram32kx64e_main_3.slv region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_3.slv region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_3.slv region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_3.slv region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_3.slv region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Imsram32kx64e_main_3.slv region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_3.slv region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_3.slv region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_3.slv region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_3.slv region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Imsram32kx64e_main_3.slv region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_3.slv region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_3.slv region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_3.slv region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_3.slv region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Imsram32kx64e_main_3.slv region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_3.slv region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_3.slv region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_3.slv region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_3.slv region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Imsram32kx64e_main_3_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_3.slv region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x5000++0xFF
line.long 0x0 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Idmss_am64_main_0.ipcss_vbm_dst region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Idmss_am64_main_0.ipcss_vbm_dst region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Idmss_am64_main_0.ipcss_vbm_dst region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Idmss_am64_main_0.ipcss_vbm_dst region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x80 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Idmss_am64_main_0.ipcss_vbm_dst region 4 firewall."
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x84 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 4 firewall."
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x88 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 4 firewall."
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8C "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 4 firewall."
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x90 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 4 firewall."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x94 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 4 firewall."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x98 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 4 firewall."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x9C "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 4 firewall."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xA0 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Idmss_am64_main_0.ipcss_vbm_dst region 5 firewall."
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xA4 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 5 firewall."
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xA8 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 5 firewall."
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xAC "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 5 firewall."
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xB0 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 5 firewall."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xB4 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 5 firewall."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xB8 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 5 firewall."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xBC "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 5 firewall."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xC0 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Idmss_am64_main_0.ipcss_vbm_dst region 6 firewall."
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xC4 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 6 firewall."
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC8 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 6 firewall."
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xCC "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 6 firewall."
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xD0 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 6 firewall."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xD4 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 6 firewall."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xD8 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 6 firewall."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xDC "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 6 firewall."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xE0 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Idmss_am64_main_0.ipcss_vbm_dst region 7 firewall."
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xE4 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 7 firewall."
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xE8 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 7 firewall."
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xEC "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Idmss_am64_main_0.ipcss_vbm_dst region 7 firewall."
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xF0 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 7 firewall."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xF4 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am64_main_0.ipcss_vbm_dst region 7 firewall."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xF8 "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 7 firewall."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xFC "FW_REGS_Idmss_am64_main_0_ipcss_vbm_dst_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am64_main_0.ipcss_vbm_dst region 7 firewall."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x5400++0xFF
line.long 0x0 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x80 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 4 firewall."
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x84 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 4 firewall."
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x88 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 4 firewall."
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8C "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 4 firewall."
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x90 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 4 firewall."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x94 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 4 firewall."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x98 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 4 firewall."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x9C "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 4 firewall."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xA0 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 5 firewall."
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xA4 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 5 firewall."
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xA8 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 5 firewall."
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xAC "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 5 firewall."
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xB0 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 5 firewall."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xB4 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 5 firewall."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xB8 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 5 firewall."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xBC "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 5 firewall."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xC0 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 6 firewall."
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xC4 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 6 firewall."
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC8 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 6 firewall."
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xCC "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 6 firewall."
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xD0 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 6 firewall."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xD4 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 6 firewall."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xD8 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 6 firewall."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xDC "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 6 firewall."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xE0 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 7 firewall."
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xE4 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 7 firewall."
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xE8 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 7 firewall."
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xEC "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 7 firewall."
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xF0 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 7 firewall."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xF4 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 7 firewall."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xF8 "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 7 firewall."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xFC "FW_REGS_Iexport_vbusm_32b_slv_main2mcu_slv_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Iexport_vbusm_32b_slv_main2mcu.slv region 7 firewall."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x5800++0x1FF
line.long 0x0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x80 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 4 firewall."
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x84 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 4 firewall."
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x88 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 4 firewall."
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 4 firewall."
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x90 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 4 firewall."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x94 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 4 firewall."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x98 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 4 firewall."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x9C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 4 firewall."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xA0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 5 firewall."
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xA4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 5 firewall."
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xA8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 5 firewall."
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xAC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 5 firewall."
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xB0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 5 firewall."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xB4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 5 firewall."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xB8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 5 firewall."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xBC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 5 firewall."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xC0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 6 firewall."
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xC4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 6 firewall."
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 6 firewall."
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xCC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 6 firewall."
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xD0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 6 firewall."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xD4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 6 firewall."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xD8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 6 firewall."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xDC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 6 firewall."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xE0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 7 firewall."
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xE4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 7 firewall."
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xE8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 7 firewall."
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xEC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 7 firewall."
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xF0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 7 firewall."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xF4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 7 firewall."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xF8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 7 firewall."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xFC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 7 firewall."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x100 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 8 firewall."
bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x100 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x100 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x100 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x104 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 8 firewall."
hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x108 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 8 firewall."
hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 8 firewall."
hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x110 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 8 firewall."
hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x114 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 8 firewall."
hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x118 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 8 firewall."
hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x11C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 8 firewall."
hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x120 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 9 firewall."
bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x120 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x120 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x120 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x124 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 9 firewall."
hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x128 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 9 firewall."
hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x12C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 9 firewall."
hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x130 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 9 firewall."
hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x134 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 9 firewall."
hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x138 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 9 firewall."
hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x13C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 9 firewall."
hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x140 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 10 firewall."
bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x140 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x140 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x140 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x144 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 10 firewall."
hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x148 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 10 firewall."
hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x14C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 10 firewall."
hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x150 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 10 firewall."
hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x154 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 10 firewall."
hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x158 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 10 firewall."
hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x15C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 10 firewall."
hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x160 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 11 firewall."
bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x160 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x160 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x160 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x164 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 11 firewall."
hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x168 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 11 firewall."
hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x16C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 11 firewall."
hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x170 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 11 firewall."
hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x174 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 11 firewall."
hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x178 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 11 firewall."
hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x17C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 11 firewall."
hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x180 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 12 firewall."
bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x180 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x180 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x180 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x184 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 12 firewall."
hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x188 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 12 firewall."
hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x18C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 12 firewall."
hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x190 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 12 firewall."
hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x194 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 12 firewall."
hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x198 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 12 firewall."
hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x19C "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 12 firewall."
hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x1A0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 13 firewall."
bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x1A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x1A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x1A4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 13 firewall."
hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x1A8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 13 firewall."
hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x1AC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 13 firewall."
hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x1B0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 13 firewall."
hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x1B4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 13 firewall."
hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x1B8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 13 firewall."
hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1BC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 13 firewall."
hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x1C0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 14 firewall."
bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x1C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x1C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x1C4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 14 firewall."
hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x1C8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 14 firewall."
hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x1CC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 14 firewall."
hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x1D0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 14 firewall."
hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x1D4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 14 firewall."
hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x1D8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 14 firewall."
hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1DC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 14 firewall."
hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x1E0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 15 firewall."
bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x1E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x1E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x1E4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 15 firewall."
hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x1E8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 15 firewall."
hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x1EC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 15 firewall."
hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x1F0 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 15 firewall."
hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x1F4 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 15 firewall."
hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x1F8 "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 15 firewall."
hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1FC "FW_REGS_br_scrm_64b_clk2_to_scrp_misc_clk2_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave br_scrm_64b_clk2_to_scrp_misc_clk2_l0 region 15 firewall."
hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x5C00++0xFF
line.long 0x0 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Imsram32kx64e_main_6.slv region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_6.slv region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_6.slv region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_6.slv region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_6.slv region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Imsram32kx64e_main_6.slv region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_6.slv region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_6.slv region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_6.slv region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_6.slv region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Imsram32kx64e_main_6.slv region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_6.slv region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_6.slv region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_6.slv region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_6.slv region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Imsram32kx64e_main_6.slv region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_6.slv region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_6.slv region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_6.slv region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_6.slv region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x80 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Imsram32kx64e_main_6.slv region 4 firewall."
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x84 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 4 firewall."
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x88 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 4 firewall."
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8C "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 4 firewall."
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x90 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_6.slv region 4 firewall."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x94 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_6.slv region 4 firewall."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x98 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_6.slv region 4 firewall."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x9C "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_6.slv region 4 firewall."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xA0 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Imsram32kx64e_main_6.slv region 5 firewall."
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xA4 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 5 firewall."
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xA8 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 5 firewall."
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xAC "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 5 firewall."
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xB0 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_6.slv region 5 firewall."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xB4 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_6.slv region 5 firewall."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xB8 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_6.slv region 5 firewall."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xBC "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_6.slv region 5 firewall."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xC0 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Imsram32kx64e_main_6.slv region 6 firewall."
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xC4 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 6 firewall."
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC8 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 6 firewall."
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xCC "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 6 firewall."
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xD0 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_6.slv region 6 firewall."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xD4 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_6.slv region 6 firewall."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xD8 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_6.slv region 6 firewall."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xDC "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_6.slv region 6 firewall."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xE0 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Imsram32kx64e_main_6.slv region 7 firewall."
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xE4 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 7 firewall."
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xE8 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 7 firewall."
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xEC "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_6.slv region 7 firewall."
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xF0 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_6.slv region 7 firewall."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xF4 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_6.slv region 7 firewall."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xF8 "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_6.slv region 7 firewall."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xFC "FW_REGS_Imsram32kx64e_main_6_slv_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_6.slv region 7 firewall."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0x6000++0xFF
line.long 0x0 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Imsram32kx64e_main_7.slv region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_7.slv region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_7.slv region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_7.slv region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_7.slv region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Imsram32kx64e_main_7.slv region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_7.slv region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_7.slv region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_7.slv region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_7.slv region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Imsram32kx64e_main_7.slv region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_7.slv region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_7.slv region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_7.slv region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_7.slv region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Imsram32kx64e_main_7.slv region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_7.slv region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_7.slv region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_7.slv region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_7.slv region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x80 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Imsram32kx64e_main_7.slv region 4 firewall."
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x84 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 4 firewall."
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x88 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 4 firewall."
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8C "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 4 firewall."
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x90 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_7.slv region 4 firewall."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x94 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_7.slv region 4 firewall."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x98 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_7.slv region 4 firewall."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x9C "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_7.slv region 4 firewall."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xA0 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Imsram32kx64e_main_7.slv region 5 firewall."
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xA4 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 5 firewall."
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xA8 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 5 firewall."
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xAC "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 5 firewall."
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xB0 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_7.slv region 5 firewall."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xB4 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_7.slv region 5 firewall."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xB8 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_7.slv region 5 firewall."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xBC "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_7.slv region 5 firewall."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xC0 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Imsram32kx64e_main_7.slv region 6 firewall."
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xC4 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 6 firewall."
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC8 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 6 firewall."
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xCC "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 6 firewall."
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xD0 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_7.slv region 6 firewall."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xD4 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_7.slv region 6 firewall."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xD8 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_7.slv region 6 firewall."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xDC "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_7.slv region 6 firewall."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xE0 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Imsram32kx64e_main_7.slv region 7 firewall."
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xE4 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 7 firewall."
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xE8 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 7 firewall."
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xEC "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Imsram32kx64e_main_7.slv region 7 firewall."
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xF0 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram32kx64e_main_7.slv region 7 firewall."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xF4 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram32kx64e_main_7.slv region 7 firewall."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xF8 "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram32kx64e_main_7.slv region 7 firewall."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xFC "FW_REGS_Imsram32kx64e_main_7_slv_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram32kx64e_main_7.slv region 7 firewall."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
tree.end
tree "CBASS0_GLB (CBASS0_GLB)"
base ad:0x45B08000
rgroup.long 0x0++0x3
line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
group.long 0x20++0x3
line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1"
bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1"
rgroup.long 0x24++0x17
line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code."
line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits."
line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x40++0x7
line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal."
bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1"
line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal."
bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1"
tree.end
tree "CBASS0_ISC (CBASS0_ISC)"
base ad:0x45880000
group.long 0x400++0x3
line.long 0x0 "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_r_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_r region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x410++0x13
line.long 0x0 "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_r_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_r region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_r_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_r region 0.."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_r_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_r region 0.."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_r_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_r region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_r_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_r region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x800++0x3
line.long 0x0 "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_w_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_w region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x810++0x13
line.long 0x0 "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_w_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_w region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_w_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_w region 0.."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_w_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_w region 0.."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_w_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_w region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_w_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_w region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x1000++0x3
line.long 0x0 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x1010++0x13
line.long 0x0 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmc8ss_16ffc_main_0.emmcss_wr region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x1400++0x3
line.long 0x0 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x1410++0x13
line.long 0x0 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmc8ss_16ffc_main_0.emmcss_rd region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x2000++0x3
line.long 0x0 "ISC_REGS_Igic500ss_1_2_main_0_mem_wr_vbusm_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Igic500ss_1_2_main_0.mem_wr_vbusm region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x2010++0x13
line.long 0x0 "ISC_REGS_Igic500ss_1_2_main_0_mem_wr_vbusm_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Igic500ss_1_2_main_0.mem_wr_vbusm region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Igic500ss_1_2_main_0_mem_wr_vbusm_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Igic500ss_1_2_main_0.mem_wr_vbusm region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Igic500ss_1_2_main_0_mem_wr_vbusm_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Igic500ss_1_2_main_0.mem_wr_vbusm region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Igic500ss_1_2_main_0_mem_wr_vbusm_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Igic500ss_1_2_main_0.mem_wr_vbusm region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Igic500ss_1_2_main_0_mem_wr_vbusm_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Igic500ss_1_2_main_0.mem_wr_vbusm region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x2400++0x3
line.long 0x0 "ISC_REGS_Igic500ss_1_2_main_0_mem_rd_vbusm_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Igic500ss_1_2_main_0.mem_rd_vbusm region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x2410++0x13
line.long 0x0 "ISC_REGS_Igic500ss_1_2_main_0_mem_rd_vbusm_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Igic500ss_1_2_main_0.mem_rd_vbusm region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Igic500ss_1_2_main_0_mem_rd_vbusm_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Igic500ss_1_2_main_0.mem_rd_vbusm region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Igic500ss_1_2_main_0_mem_rd_vbusm_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Igic500ss_1_2_main_0.mem_rd_vbusm region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Igic500ss_1_2_main_0_mem_rd_vbusm_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Igic500ss_1_2_main_0.mem_rd_vbusm region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Igic500ss_1_2_main_0_mem_rd_vbusm_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Igic500ss_1_2_main_0.mem_rd_vbusm region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x2800++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu0_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu0_rmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x2810++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu0_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu0_rmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_0_cpu0_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu0_rmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_0_cpu0_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu0_rmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_0_cpu0_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu0_rmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_0_cpu0_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu0_rmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x2C00++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu0_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu0_wmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x2C10++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu0_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu0_wmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_0_cpu0_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu0_wmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_0_cpu0_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu0_wmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_0_cpu0_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu0_wmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_0_cpu0_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu0_wmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x3C00++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu1_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu1_rmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x3C10++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu1_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu1_rmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_0_cpu1_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu1_rmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_0_cpu1_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu1_rmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_0_cpu1_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu1_rmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_0_cpu1_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu1_rmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x4000++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu1_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu1_wmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x4010++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu1_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu1_wmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_0_cpu1_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu1_wmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_0_cpu1_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu1_wmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_0_cpu1_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu1_wmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_0_cpu1_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu1_wmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x5000++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu0_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu0_rmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x5010++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu0_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu0_rmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_1_cpu0_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu0_rmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_1_cpu0_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu0_rmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_1_cpu0_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu0_rmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_1_cpu0_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu0_rmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x5400++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu0_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu0_wmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x5410++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu0_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu0_wmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_1_cpu0_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu0_wmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_1_cpu0_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu0_wmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_1_cpu0_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu0_wmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_1_cpu0_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu0_wmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x6400++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu1_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu1_rmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x6410++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu1_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu1_rmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_1_cpu1_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu1_rmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_1_cpu1_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu1_rmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_1_cpu1_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu1_rmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_1_cpu1_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu1_rmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x6800++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu1_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu1_wmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x6810++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu1_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu1_wmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_1_cpu1_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu1_wmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_1_cpu1_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu1_wmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_1_cpu1_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu1_wmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_1_cpu1_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu1_wmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7800++0x3
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7810++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7830++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 1 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 1 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 1 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 1 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 2 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7850++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 2 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 2 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 2 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 2 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 3 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7870++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 3 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 3 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 3 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 3 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 4 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7890++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 4 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 4 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 4 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 4 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 5 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x78B0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 5 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 5 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 5 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 5 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 6 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x78D0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 6 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 6 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 6 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 6 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 7 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x78F0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 7 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 7 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 7 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 7 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_8_control,The ISC Region 8 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 8 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7910++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_8_start_address_l,The ISC Region 8 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 8 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_8_start_address_h,The ISC Region 8 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 8 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_8_end_address_l,The ISC Region 8 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 8 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_8_end_address_h,The ISC Region 8 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 8 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_9_control,The ISC Region 9 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 9 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7930++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_9_start_address_l,The ISC Region 9 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 9 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_9_start_address_h,The ISC Region 9 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 9 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_9_end_address_l,The ISC Region 9 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 9 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_9_end_address_h,The ISC Region 9 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 9 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_10_control,The ISC Region 10 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 10 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7950++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_10_start_address_l,The ISC Region 10 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 10 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_10_start_address_h,The ISC Region 10 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 10 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_10_end_address_l,The ISC Region 10 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 10 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_10_end_address_h,The ISC Region 10 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 10 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_11_control,The ISC Region 11 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 11 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7970++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_11_start_address_l,The ISC Region 11 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 11 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_11_start_address_h,The ISC Region 11 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 11 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_11_end_address_l,The ISC Region 11 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 11 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_11_end_address_h,The ISC Region 11 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 11 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_12_control,The ISC Region 12 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 12 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7990++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_12_start_address_l,The ISC Region 12 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 12 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_12_start_address_h,The ISC Region 12 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 12 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_12_end_address_l,The ISC Region 12 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 12 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_12_end_address_h,The ISC Region 12 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 12 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_13_control,The ISC Region 13 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 13 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x79B0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_13_start_address_l,The ISC Region 13 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 13 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_13_start_address_h,The ISC Region 13 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 13 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_13_end_address_l,The ISC Region 13 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 13 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_13_end_address_h,The ISC Region 13 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 13 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_14_control,The ISC Region 14 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 14 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x79D0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_14_start_address_l,The ISC Region 14 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 14 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_14_start_address_h,The ISC Region 14 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 14 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_14_end_address_l,The ISC Region 14 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 14 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_14_end_address_h,The ISC Region 14 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 14 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_15_control,The ISC Region 15 Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 15 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x79F0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_15_start_address_l,The ISC Region 15 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 15 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_15_start_address_h,The ISC Region 15 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 15 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_15_end_address_l,The ISC Region 15 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 15 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_15_end_address_h,The ISC Region 15 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 15 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm region 16 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7C00++0x3
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7C10++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7C30++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 1 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 1 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 1 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 1 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 2 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7C50++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 2 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 2 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 2 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 2 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 3 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7C70++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 3 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 3 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 3 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 3 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 4 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7C90++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 4 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 4 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 4 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 4 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 5 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7CB0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 5 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 5 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 5 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 5 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 6 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7CD0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 6 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 6 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 6 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 6 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 7 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7CF0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 7 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 7 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 7 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 7 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_8_control,The ISC Region 8 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 8 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7D10++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_8_start_address_l,The ISC Region 8 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 8 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_8_start_address_h,The ISC Region 8 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 8 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_8_end_address_l,The ISC Region 8 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 8 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_8_end_address_h,The ISC Region 8 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 8 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_9_control,The ISC Region 9 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 9 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7D30++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_9_start_address_l,The ISC Region 9 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 9 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_9_start_address_h,The ISC Region 9 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 9 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_9_end_address_l,The ISC Region 9 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 9 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_9_end_address_h,The ISC Region 9 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 9 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_10_control,The ISC Region 10 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 10 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7D50++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_10_start_address_l,The ISC Region 10 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 10 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_10_start_address_h,The ISC Region 10 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 10 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_10_end_address_l,The ISC Region 10 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 10 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_10_end_address_h,The ISC Region 10 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 10 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_11_control,The ISC Region 11 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 11 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7D70++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_11_start_address_l,The ISC Region 11 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 11 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_11_start_address_h,The ISC Region 11 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 11 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_11_end_address_l,The ISC Region 11 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 11 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_11_end_address_h,The ISC Region 11 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 11 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_12_control,The ISC Region 12 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 12 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7D90++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_12_start_address_l,The ISC Region 12 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 12 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_12_start_address_h,The ISC Region 12 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 12 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_12_end_address_l,The ISC Region 12 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 12 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_12_end_address_h,The ISC Region 12 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 12 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_13_control,The ISC Region 13 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 13 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7DB0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_13_start_address_l,The ISC Region 13 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 13 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_13_start_address_h,The ISC Region 13 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 13 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_13_end_address_l,The ISC Region 13 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 13 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_13_end_address_h,The ISC Region 13 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 13 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_14_control,The ISC Region 14 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 14 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7DD0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_14_start_address_l,The ISC Region 14 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 14 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_14_start_address_h,The ISC Region 14 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 14 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_14_end_address_l,The ISC Region 14 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 14 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_14_end_address_h,The ISC Region 14 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 14 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_15_control,The ISC Region 15 Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 15 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x7DF0++0x13
line.long 0x0 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_15_start_address_l,The ISC Region 15 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 15 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_15_start_address_h,The ISC Region 15 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 15 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_15_end_address_l,The ISC Region 15 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 15 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_15_end_address_h,The ISC Region 15 End Address High Register defines the end address bits 47 to 32 for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 15 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm region 16 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8000++0x3
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8010++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8030++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 1 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 1 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 1 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 1 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 2 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8050++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 2 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 2 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 2 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 2 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 3 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8070++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 3 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 3 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 3 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 3 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 4 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8090++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 4 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 4 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 4 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 4 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 5 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x80B0++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 5 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 5 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 5 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 5 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 6 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x80D0++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 6 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 6 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 6 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 6 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 7 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x80F0++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 7 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 7 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 7 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 7 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd region 8 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8400++0x3
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8410++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8430++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 1 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 1 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 1 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 1 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 2 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8450++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 2 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 2 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 2 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 2 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 3 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8470++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 3 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 3 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 3 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 3 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 4 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8490++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 4 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 4 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 4 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 4 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 5 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x84B0++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 5 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 5 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 5 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 5 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 6 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x84D0++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 6 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 6 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 6 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 6 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 7 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x84F0++0x13
line.long 0x0 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 7 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 7 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 7 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 7 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr region 8 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8800++0x3
line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8810++0x13
line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_wr region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8C00++0x3
line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x8C10++0x13
line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_rd region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9000++0x3
line.long 0x0 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isa2_ul_main_0.ctxcach_ext_dma region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9010++0x13
line.long 0x0 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isa2_ul_main_0.ctxcach_ext_dma region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isa2_ul_main_0.ctxcach_ext_dma region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isa2_ul_main_0.ctxcach_ext_dma region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isa2_ul_main_0.ctxcach_ext_dma region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Isa2_ul_main_0_ctxcach_ext_dma_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isa2_ul_main_0.ctxcach_ext_dma region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9400++0x3
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9410++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9430++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 1 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 1 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 1 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 1 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 2 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9450++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 2 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 2 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 2 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 2 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 3 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9470++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 3 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 3 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 3 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 3 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 4 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9490++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 4 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 4 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 4 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 4 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 5 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x94B0++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 5 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 5 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 5 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 5 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 6 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x94D0++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 6 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 6 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 6 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 6 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 7 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x94F0++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 7 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 7 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 7 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 7 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 region 8 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9800++0x3
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9810++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9830++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 1 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 1 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 1 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 1 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 2 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9850++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 2 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 2 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 2 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 2 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 3 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9870++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 3 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 3 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 3 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 3 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 4 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9890++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 4 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 4 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 4 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 4 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 5 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x98B0++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 5 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 5 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 5 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 5 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_6_control,The ISC Region 6 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 6 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x98D0++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_6_start_address_l,The ISC Region 6 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 6 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_6_start_address_h,The ISC Region 6 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 6 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_6_end_address_l,The ISC Region 6 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 6 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_6_end_address_h,The ISC Region 6 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 6 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_7_control,The ISC Region 7 Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 7 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x98F0++0x13
line.long 0x0 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_7_start_address_l,The ISC Region 7 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 7 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_7_start_address_h,The ISC Region 7 Start Address High Register defines the start address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 7 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_7_end_address_l,The ISC Region 7 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 7 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_7_end_address_h,The ISC Region 7 End Address High Register defines the end address bits 47 to 32 for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 7 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 region 8 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9C00++0x3
line.long 0x0 "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ij7_led_main_0.vbusp region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x9C10++0x13
line.long 0x0 "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ij7_led_main_0.vbusp region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ij7_led_main_0.vbusp region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ij7_led_main_0.vbusp region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ij7_led_main_0.vbusp region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ij7_led_main_0_vbusp_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ij7_led_main_0.vbusp region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0xA000++0x3
line.long 0x0 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0xA010++0x13
line.long 0x0 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0xA400++0x3
line.long 0x0 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
newline
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0xA410++0x13
line.long 0x0 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
tree.end
tree "CBASS0_QOS (CBASS0_QOS)"
base ad:0x45D80000
group.long 0x500++0x3
line.long 0x0 "QOS_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_r_map0,The Map Register defines the fields for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_r per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x900++0x3
line.long 0x0 "QOS_REGS_Isam64_a53_256kb_wrap_main_0_a53_dual_wrap_cba_axi_w_map0,The Map Register defines the fields for the master Isam64_a53_256kb_wrap_main_0.a53_dual_wrap_cba_axi_w per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1100++0x3
line.long 0x0 "QOS_REGS_Iemmc8ss_16ffc_main_0_emmcss_wr_map0,The Map Register defines the fields for the master Iemmc8ss_16ffc_main_0.emmcss_wr per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1500++0x3
line.long 0x0 "QOS_REGS_Iemmc8ss_16ffc_main_0_emmcss_rd_map0,The Map Register defines the fields for the master Iemmc8ss_16ffc_main_0.emmcss_rd per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2100++0x3
line.long 0x0 "QOS_REGS_Igic500ss_1_2_main_0_mem_wr_vbusm_map0,The Map Register defines the fields for the master Igic500ss_1_2_main_0.mem_wr_vbusm per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2500++0x3
line.long 0x0 "QOS_REGS_Igic500ss_1_2_main_0_mem_rd_vbusm_map0,The Map Register defines the fields for the master Igic500ss_1_2_main_0.mem_rd_vbusm per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2900++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_0_cpu0_rmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_0.cpu0_rmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D00++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_0_cpu0_wmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_0.cpu0_wmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3D00++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_0_cpu1_rmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_0.cpu1_rmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4100++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_0_cpu1_wmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_0.cpu1_wmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5100++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_1_cpu0_rmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_1.cpu0_rmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5500++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_1_cpu0_wmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_1.cpu0_wmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6500++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_1_cpu1_rmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_1.cpu1_rmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6900++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_1_cpu1_wmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_1.cpu1_wmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7900++0x3F
line.long 0x0 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map0,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x4 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map1,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x8 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map2,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0xC "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map3,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x10 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map4,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x14 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map5,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x18 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map6,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x1C "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map7,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x20 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map8,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x20 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x24 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map9,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x24 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x28 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map10,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x28 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x28 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x2C "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map11,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x2C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x30 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map12,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x30 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x30 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x34 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map13,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x34 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x34 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x38 "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map14,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x38 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x38 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x3C "QOS_REGS_Iicss_g_16ff_main_0_pr1_ext_vbusm_map15,The Map Register defines the fields for the master Iicss_g_16ff_main_0.pr1_ext_vbusm per channel."
bitfld.long 0x3C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x3C 4.--7. 1. "ORDERID,orderid signal for channel N."
group.long 0x7D00++0x3F
line.long 0x0 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map0,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x4 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map1,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x8 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map2,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0xC "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map3,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x10 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map4,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x14 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map5,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x18 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map6,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x1C "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map7,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x20 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map8,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x20 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x24 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map9,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x24 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x28 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map10,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x28 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x28 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x2C "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map11,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x2C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x30 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map12,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x30 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x30 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x34 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map13,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x34 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x34 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x38 "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map14,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x38 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x38 4.--7. 1. "ORDERID,orderid signal for channel N."
line.long 0x3C "QOS_REGS_Iicss_g_16ff_main_1_pr1_ext_vbusm_map15,The Map Register defines the fields for the master Iicss_g_16ff_main_1.pr1_ext_vbusm per channel."
bitfld.long 0x3C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x3C 4.--7. 1. "ORDERID,orderid signal for channel N."
group.long 0x8100++0x1F
line.long 0x0 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_map0,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x4 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_map1,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd per channel."
bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x8 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_map2,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd per channel."
bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0xC "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_map3,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd per channel."
bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x10 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_map4,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd per channel."
bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x14 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_map5,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd per channel."
bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x18 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_map6,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd per channel."
bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x1C "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_rd_map7,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_rd per channel."
bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8500++0x1F
line.long 0x0 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_map0,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x4 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_map1,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr per channel."
bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x8 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_map2,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr per channel."
bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0xC "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_map3,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr per channel."
bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x10 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_map4,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr per channel."
bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x14 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_map5,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr per channel."
bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x18 "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_map6,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr per channel."
bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x1C "QOS_REGS_Ipcie_g2x1_64_main_0_pcie_mst_wr_map7,The Map Register defines the fields for the master Ipcie_g2x1_64_main_0.pcie_mst_wr per channel."
bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8900++0x3
line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_0.emmcsdss_wr per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8D00++0x3
line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_0.emmcsdss_rd per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9100++0x3
line.long 0x0 "QOS_REGS_Isa2_ul_main_0_ctxcach_ext_dma_map0,The Map Register defines the fields for the master Isa2_ul_main_0.ctxcach_ext_dma per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9500++0x1F
line.long 0x0 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_map0,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x4 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_map1,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 per channel."
bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x8 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_map2,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 per channel."
bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0xC "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_map3,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 per channel."
bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x10 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_map4,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 per channel."
bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x14 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_map5,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 per channel."
bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x18 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_map6,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 per channel."
bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x1C "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstr0_map7,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstr0 per channel."
bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9900++0x1F
line.long 0x0 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_map0,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x4 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_map1,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 per channel."
bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x8 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_map2,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 per channel."
bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0xC "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_map3,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 per channel."
bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x10 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_map4,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 per channel."
bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x14 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_map5,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 per channel."
bitfld.long 0x14 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x14 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x14 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x18 "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_map6,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 per channel."
bitfld.long 0x18 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x18 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x18 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
line.long 0x1C "QOS_REGS_Iusb3p0ss64_16ffc_main_0_mstw0_map7,The Map Register defines the fields for the master Iusb3p0ss64_16ffc_main_0.mstw0 per channel."
bitfld.long 0x1C 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x1C 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x1C 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA100++0x3
line.long 0x0 "QOS_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_map0,The Map Register defines the fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmr per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA500++0x3
line.long 0x0 "QOS_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_map0,The Map Register defines the fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmw per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "CBASS_DBG0_ERR (CBASS_DBG0_ERR)"
base ad:0x200000
rgroup.long 0x0++0x3
line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
rgroup.long 0x24++0x17
line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error."
line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits."
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x50++0x13
line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1"
line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CBASS_FW0_ERR (CBASS_FW0_ERR)"
base ad:0x220000
rgroup.long 0x0++0x3
line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
rgroup.long 0x24++0x17
line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error."
line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits."
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x50++0x13
line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1"
line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
base ad:0x0
tree "CBASS_INFRA1"
tree "CBASS_INFRA1_ERR (CBASS_INFRA1_ERR)"
base ad:0x210000
rgroup.long 0x0++0x3
line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
rgroup.long 0x24++0x17
line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error."
line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits."
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x50++0x13
line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1"
line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CBASS_INFRA1_FW (CBASS_INFRA1_FW)"
base ad:0x45008000
group.long 0x800++0xFF
line.long 0x0 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x80 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 4 firewall."
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x84 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 4 firewall."
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x88 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 4 firewall."
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8C "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 4 firewall."
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x90 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 4 firewall."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x94 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 4 firewall."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x98 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 4 firewall."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x9C "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 4 firewall."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xA0 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 5 firewall."
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xA4 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 5 firewall."
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xA8 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 5 firewall."
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xAC "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 5 firewall."
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xB0 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 5 firewall."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xB4 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 5 firewall."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xB8 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 5 firewall."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xBC "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 5 firewall."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xC0 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 6 firewall."
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xC4 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 6 firewall."
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC8 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 6 firewall."
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xCC "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 6 firewall."
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xD0 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 6 firewall."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xD4 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 6 firewall."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xD8 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 6 firewall."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xDC "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 6 firewall."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xE0 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 7 firewall."
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xE4 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 7 firewall."
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xE8 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 7 firewall."
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xEC "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 7 firewall."
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xF0 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 7 firewall."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xF4 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 7 firewall."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xF8 "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 7 firewall."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xFC "FW_REGS_br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP0_32b_clk4_l0 region 7 firewall."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
group.long 0xC00++0xFF
line.long 0x0 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 0 firewall."
bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 0 firewall."
hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 0 firewall."
hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 0 firewall."
hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x10 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 0 firewall."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x14 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 0 firewall."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x18 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 0 firewall."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x1C "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 0 firewall."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x20 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 1 firewall."
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x24 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 1 firewall."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x28 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 1 firewall."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x2C "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 1 firewall."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x30 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 1 firewall."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x34 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 1 firewall."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x38 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 1 firewall."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x3C "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 1 firewall."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x40 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 2 firewall."
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x44 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 2 firewall."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x48 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 2 firewall."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x4C "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 2 firewall."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x50 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 2 firewall."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x54 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 2 firewall."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x58 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 2 firewall."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x5C "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 2 firewall."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x60 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 3 firewall."
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x64 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 3 firewall."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x68 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 3 firewall."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x6C "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 3 firewall."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x70 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 3 firewall."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x74 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 3 firewall."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x78 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 3 firewall."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x7C "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 3 firewall."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0x80 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 4 firewall."
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x84 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 4 firewall."
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x88 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 4 firewall."
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x8C "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 4 firewall."
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0x90 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 4 firewall."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0x94 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 4 firewall."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x98 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 4 firewall."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0x9C "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 4 firewall."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xA0 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 5 firewall."
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xA4 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 5 firewall."
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xA8 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 5 firewall."
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xAC "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 5 firewall."
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xB0 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 5 firewall."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xB4 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 5 firewall."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xB8 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 5 firewall."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xBC "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 5 firewall."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xC0 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 6 firewall."
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xC4 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 6 firewall."
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xC8 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 6 firewall."
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xCC "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 6 firewall."
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xD0 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 6 firewall."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xD4 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 6 firewall."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xD8 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 6 firewall."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xDC "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 6 firewall."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
line.long 0xE0 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 7 firewall."
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1"
newline
hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0xE4 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 7 firewall."
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xE8 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 7 firewall."
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xEC "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 7 firewall."
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid."
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1"
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1"
newline
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1"
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1"
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1"
newline
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1"
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1"
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1"
newline
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1"
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1"
line.long 0xF0 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 7 firewall."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
line.long 0xF4 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 7 firewall."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0xF8 "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 7 firewall."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
line.long 0xFC "FW_REGS_br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_motor_to_SCRP_32b_miscIO_l0 region 7 firewall."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match."
tree.end
tree "CBASS_INFRA1_GLB (CBASS_INFRA1_GLB)"
base ad:0x45B01000
rgroup.long 0x0++0x3
line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
group.long 0x20++0x3
line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1"
bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1"
rgroup.long 0x24++0x17
line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code."
line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits."
line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x40++0x7
line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal."
bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1"
line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal."
bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1"
tree.end
tree "CBASS_INFRA1_ISC (CBASS_INFRA1_ISC)"
base ad:0x45820000
group.long 0x0++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu0_pmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu0_pmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
newline
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x10++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu0_pmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu0_pmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_0_cpu0_pmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu0_pmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_0_cpu0_pmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu0_pmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_0_cpu0_pmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu0_pmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_0_cpu0_pmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu0_pmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x400++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu1_pmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu1_pmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
newline
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x410++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_0_cpu1_pmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu1_pmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_0_cpu1_pmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu1_pmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_0_cpu1_pmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_0.cpu1_pmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_0_cpu1_pmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_0.cpu1_pmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_0_cpu1_pmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_0.cpu1_pmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x800++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu0_pmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu0_pmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
newline
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x810++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu0_pmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu0_pmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_1_cpu0_pmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu0_pmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_1_cpu0_pmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu0_pmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_1_cpu0_pmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu0_pmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_1_cpu0_pmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu0_pmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0xC00++0x3
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu1_pmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu1_pmst region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
newline
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0xC10++0x13
line.long 0x0 "ISC_REGS_Ipulsar_lite_main_1_cpu1_pmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu1_pmst region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Ipulsar_lite_main_1_cpu1_pmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu1_pmst region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Ipulsar_lite_main_1_cpu1_pmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_lite_main_1.cpu1_pmst region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Ipulsar_lite_main_1_cpu1_pmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_lite_main_1.cpu1_pmst region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Ipulsar_lite_main_1_cpu1_pmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_lite_main_1.cpu1_pmst region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
tree.end
tree "CBASS_INFRA1_QOS (CBASS_INFRA1_QOS)"
base ad:0x45D20000
group.long 0x100++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_0_cpu0_pmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_0.cpu0_pmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x500++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_0_cpu1_pmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_0.cpu1_pmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x900++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_1_cpu0_pmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_1.cpu0_pmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD00++0x3
line.long 0x0 "QOS_REGS_Ipulsar_lite_main_1_cpu1_pmst_map0,The Map Register defines the fields for the master Ipulsar_lite_main_1.cpu1_pmst per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree.end
tree "CMP_EVENT_INTROUTER0_CFG (CMP_EVENT_INTROUTER0_CFG)"
base ad:0xA30000
rgroup.long 0x0++0x3
line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register"
bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function"
hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version"
bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version"
group.long 0x4++0x3
line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register"
bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "MUX_CNTL,Mux control for interrupt N"
tree.end
tree "CPSW0"
base ad:0x0
tree "CPSW0_ECC (CPSW0_ECC)"
base ad:0x704000
rgroup.long 0x0++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "CPSW_NUSS_VBUSP_ECC_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
newline
bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
newline
bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
newline
bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
newline
bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
newline
bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
newline
bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
newline
bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
newline
bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
newline
bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
newline
bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
newline
bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
newline
bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
newline
bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
newline
bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
newline
bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
newline
bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "CPSW_NUSS_VBUSP_ECC_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
newline
bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
newline
bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
newline
bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
newline
bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
newline
bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
newline
bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
newline
bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
newline
bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
newline
bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
newline
bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
newline
bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
newline
bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
newline
bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
newline
bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
newline
bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
newline
bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "CPSW_NUSS_VBUSP_ECC_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "CPSW_NUSS_VBUSP_ECC_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "CPSW_NUSS_VBUSP_ECC_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "CPSW_NUSS_VBUSP_ECC_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "CPSW0_NUSS (CPSW0_NUSS)"
base ad:0x8000000
rgroup.long 0x0++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_CPSW_NUSS_IDVER_REG,ID Version Register"
hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification value"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value"
newline
bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value"
group.long 0x4++0x13
line.long 0x0 "CPSW_NUSS_VBUSP_SYNCE_COUNT_REG,SyncE Count Register"
hexmask.long 0x0 0.--31. 1. "SYNCE_CNT,Sync E Count Value"
line.long 0x4 "CPSW_NUSS_VBUSP_SYNCE_MUX_REG,SyncE Mux Register"
hexmask.long.byte 0x4 0.--5. 1. "SYNCE_SEL,Sync E Select Value"
line.long 0x8 "CPSW_NUSS_VBUSP_CONTROL_REG,Control Register"
bitfld.long 0x8 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode: 0=The low power indicate state includes gating off the CPPI_GCLK to the CPSW  1=The low power indicate state does not gate the clock to the CPSW" "0: The low power indicate state includes gating off..,1: The low power indicate state does not gate the.."
newline
bitfld.long 0x8 0. "EEE_EN,Energy Efficient Ethernet Enable: 0=EEE is disabled  1=EEE is enabled" "0: EEE is disabled,1: EEE is enabled"
line.long 0xC "CPSW_NUSS_VBUSP_SGMII_NON_FIBER_MODE_REG,SGMII NON FIBER Mode Register"
bitfld.long 0xC 0.--1. "SGMII_NON_FIBER_MODE,This register bit goes to the CPSGMII mode input only" "0,1,2,3"
line.long 0x10 "CPSW_NUSS_VBUSP_SERDES_RESET_ISO_REG,SyncE Mux Register"
bitfld.long 0x10 0.--1. "SERDES_RESET_ISO,These bits control whether the SERDES ignores the hard reset for isolation or not" "0,1,2,3"
rgroup.long 0x1C++0x7
line.long 0x0 "CPSW_NUSS_VBUSP_SUBSSYSTEM_STATUS_REG,Subsystem Status Register"
bitfld.long 0x0 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1"
line.long 0x4 "CPSW_NUSS_VBUSP_SUBSYSTEM_CONFIG_REG,Subsystem Configuration Register"
hexmask.long.byte 0x4 20.--27. 1. "XGMII,The Number of XGMII Ports included in the CPSW_NUSS"
newline
bitfld.long 0x4 19. "QSGMII,QSGMII is included in the CPSW_NUSS" "0,1"
newline
bitfld.long 0x4 18. "SGMII,SGMII is included in the CPSW_NUSS" "0,1"
newline
bitfld.long 0x4 17. "RGMII,RGMII is included in the CPSW_NUSS" "0,1"
newline
bitfld.long 0x4 16. "RMII,RMII is included in the CPSW_NUSS" "0,1"
newline
hexmask.long.byte 0x4 8.--12. 1. "NUM_GENF,The number of CPTS GENF outputs"
newline
hexmask.long.byte 0x4 0.--7. 1. "NUM_PORTS,The total number of ports including the host port 0"
rgroup.long 0x30++0x7
line.long 0x0 "CPSW_NUSS_VBUSP_RGMII1_STATUS_REG,RGMII1 Status Register"
bitfld.long 0x0 3. "FULLDUPLEX,Rgmii1 full dulex: 0=Half-duplex  1=Full-duplex" "0: Half-duplex,1: Full-duplex"
newline
bitfld.long 0x0 1.--2. "SPEED,Rgmii1 speed: 00=10Mbps  01=100Mbps  10=1000Mbps  11=reserved" "0: 10Mbps,1: 100Mbps,?,?"
newline
bitfld.long 0x0 0. "LINK,Rgmii1 link indicator: 0=Link is down  1=Link is up" "0: Link is down,1: Link is up"
line.long 0x4 "CPSW_NUSS_VBUSP_RGMII2_STATUS_REG,RGMII2 Status Register"
bitfld.long 0x4 3. "FULLDUPLEX,Rgmii2 full dulex: 0=Half-duplex  1=Full-duplex" "0: Half-duplex,1: Full-duplex"
newline
bitfld.long 0x4 1.--2. "SPEED,Rgmii2 speed: 00=10Mbps  01=100Mbps  10=1000Mbps  11=reserved" "0: 10Mbps,1: 100Mbps,?,?"
newline
bitfld.long 0x4 0. "LINK,Rgmii2 link indicator: 0=Link is down  1=Link is up" "0: Link is down,1: Link is up"
rgroup.long 0x100++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_SGMII_IDVER_REG,SGMII IDVER register"
hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,MODULE value"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value"
newline
bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value"
group.long 0x104++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_SOFT_RESET_REG,SGMII Soft Reset Register"
bitfld.long 0x0 1. "RT_SOFT_RESET,Transmit and receive software reset" "0,1"
newline
bitfld.long 0x0 0. "SOFT_RESET,Software reset" "0,1"
group.long 0x110++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_CONTROL_REG,SGMII Control Register"
bitfld.long 0x0 6. "TEST_PATTERN_EN,Test pattern enable" "0,1"
newline
bitfld.long 0x0 5. "MASTER,Master mode" "0,1"
newline
bitfld.long 0x0 4. "LOOPBACK,Loopback mode" "0,1"
newline
bitfld.long 0x0 3. "MR_NP_LOADED,Next page loaded" "0,1"
newline
bitfld.long 0x0 2. "FAST_LINK_TIMER,Fast link timer" "0,1"
newline
bitfld.long 0x0 1. "MR_AN_RESTART,Auto-negotiation restart" "0,1"
newline
bitfld.long 0x0 0. "MR_AN_ENABLE,Auto-negotiation enable" "0,1"
rgroup.long 0x114++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_STATUS_REG,SGMII Status Register"
bitfld.long 0x0 5. "FIB_SIG_DETECT,Fiber signal detect" "0,1"
newline
bitfld.long 0x0 4. "LOCK,Lock" "0,1"
newline
bitfld.long 0x0 3. "MR_PAGE_RX,Next page received" "0,1"
newline
bitfld.long 0x0 2. "MR_AN_COMPLETE,Auto-negotiation complete" "0,1"
newline
bitfld.long 0x0 1. "AN_ERROR,Auto-negotiation error" "0,1"
newline
bitfld.long 0x0 0. "LINK,Link indicator" "0,1"
group.long 0x118++0x7
line.long 0x0 "CPSW_NUSS_VBUSP_MR_ADV_ABILITY_REG,SGMII MR Advertized Ability Register"
hexmask.long.word 0x0 0.--15. 1. "MR_ADV_ABILITY,Advertised ability"
line.long 0x4 "CPSW_NUSS_VBUSP_MR_NP_TX_REG,SGMII Next Pate Transmit Register"
hexmask.long.word 0x4 0.--15. 1. "MR_NP_TX,Next page transmit"
rgroup.long 0x120++0x7
line.long 0x0 "CPSW_NUSS_VBUSP_MR_LP_ADV_ABILITY_REG,SGMII Link Partner Advertized Ability Register"
hexmask.long.word 0x0 0.--15. 1. "MR_LP_ADV_ABILITY,Link partner advertised ability"
line.long 0x4 "CPSW_NUSS_VBUSP_MR_LP_NP_RX_REG,SGMII Link Partner Next Page Receive Register"
hexmask.long.word 0x4 0.--15. 1. "MR_LP_NP_RX,Link Partner Next Page Received"
group.long 0x140++0x7
line.long 0x0 "CPSW_NUSS_VBUSP_DIAG_CLEAR_REG,SGMII Diagnostics Clear Register"
bitfld.long 0x0 0. "DIAG_CLEAR,Diagnostics clear" "0,1"
line.long 0x4 "CPSW_NUSS_VBUSP_DIAG_CONTROL_REG,SGMII Diagnostics Control Register"
bitfld.long 0x4 4.--6. "DIAG_SM_SEL,Diagnostic select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0.--1. "DIAG_EDGE_SEL,Diagnostics hold signals edge select" "0,1,2,3"
rgroup.long 0x148++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_DIAG_STATUS_REG,SGMII Diagnostics Status Register"
hexmask.long.word 0x0 0.--15. 1. "DIAG_STATUS,Diagnostics status"
rgroup.long 0xF00++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_MDIO_VERSION_REG,MDIO Version Register"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0xF04++0x7
line.long 0x0 "CPSW_NUSS_VBUSP_CONTROL_REG,MDIO Control Register"
rbitfld.long 0x0 31. "IDLE,MDIO state machine idle" "0,1"
newline
bitfld.long 0x0 30. "ENABLE,Enable control" "0,1"
newline
hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel"
newline
bitfld.long 0x0 20. "PREAMBLE,Preamble disable" "0,1"
newline
bitfld.long 0x0 19. "FAULT,Fault indicator" "0,1"
newline
bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
newline
bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock divider"
line.long 0x4 "CPSW_NUSS_VBUSP_ALIVE_REG,MDIO Alive Register"
hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO alive"
rgroup.long 0xF0C++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_LINK_REG,MDIO Link Register"
hexmask.long 0x0 0.--31. 1. "LINK,MDIO link state"
group.long 0xF10++0x37
line.long 0x0 "CPSW_NUSS_VBUSP_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x4 "CPSW_NUSS_VBUSP_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x8 "CPSW_NUSS_VBUSP_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0xC "CPSW_NUSS_VBUSP_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x10 "CPSW_NUSS_VBUSP_USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
bitfld.long 0x10 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
line.long 0x14 "CPSW_NUSS_VBUSP_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
bitfld.long 0x14 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
line.long 0x18 "CPSW_NUSS_VBUSP_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
line.long 0x1C "CPSW_NUSS_VBUSP_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
line.long 0x20 "CPSW_NUSS_VBUSP_MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
newline
bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable" "0,1"
newline
bitfld.long 0x20 0. "MDIO_PIN,MDIO Pin" "0,1"
line.long 0x24 "CPSW_NUSS_VBUSP_POLL_REG,MDIO Poll Register"
bitfld.long 0x24 31. "MANUALMODE,MDIO Manual Mode" "0,1"
newline
bitfld.long 0x24 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
newline
hexmask.long.byte 0x24 0.--7. 1. "IPG,MDIO IPG"
line.long 0x28 "CPSW_NUSS_VBUSP_POLL_EN_REG,MDIO Poll Enable Register"
hexmask.long 0x28 0.--31. 1. "POLL_EN,MDIO Poll Enable"
line.long 0x2C "CPSW_NUSS_VBUSP_CLAUS45_REG,MDIO Clause45 Register"
hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO Clause 45"
line.long 0x30 "CPSW_NUSS_VBUSP_USER_ADDR0_REG,MDIO Address 0 Register"
hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
line.long 0x34 "CPSW_NUSS_VBUSP_USER_ADDR1_REG,MDIO Address 1 Register"
hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
rgroup.long 0x1000++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_REVISION,Revision Register"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions"
newline
bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision"
group.long 0x1010++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_eoi_reg,End of Interrupt Register"
hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
rgroup.long 0x1014++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_intr_vector_reg,Interrupt Vector Register"
hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register"
group.long 0x1100++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_enable_reg_out_pulse_0,Enable Register 0"
bitfld.long 0x0 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA,Enable Set for out_pulse_en_stat_penda" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA,Enable Set for out_pulse_en_mdio_penda" "0,1"
newline
bitfld.long 0x0 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA,Enable Set for out_pulse_en_evnt_penda" "0,1"
group.long 0x1300++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_enable_clr_reg_out_pulse_0,Enable Clear Register 0"
bitfld.long 0x0 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR,Enable Clear for out_pulse_en_stat_penda" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR,Enable Clear for out_pulse_en_mdio_penda" "0,1"
newline
bitfld.long 0x0 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR,Enable Clear for out_pulse_en_evnt_penda" "0,1"
rgroup.long 0x1500++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_status_reg_out_pulse_0,Status Register 0"
bitfld.long 0x0 2. "STATUS_OUT_PULSE_STAT_PENDA,Status for out_pulse_en_stat_penda" "0,1"
newline
bitfld.long 0x0 1. "STATUS_OUT_PULSE_MDIO_PENDA,Status for out_pulse_en_mdio_penda" "0,1"
newline
bitfld.long 0x0 0. "STATUS_OUT_PULSE_EVNT_PENDA,Status for out_pulse_en_evnt_penda" "0,1"
rgroup.long 0x1A80++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_intr_vector_reg_out_pulse,Interrupt Vector for out_pulse"
hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_OUT_PULSE,Interrupt Vector"
rgroup.long 0x20000++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_CPSW_ID_VER_REG,CPSW ID Version"
hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification Value"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL Version Value"
newline
bitfld.long 0x0 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor Version Value"
group.long 0x20004++0x3
line.long 0x0 "CPSW_NUSS_VBUSP_CONTROL_REG,CPSW Switch Control"
bitfld.long 0x0 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1"
newline
bitfld.long 0x0 19. "CUT_THRU_ENABLE,Cut-Thru enable" "0,1"
newline
bitfld.long 0x0 18. "EST_ENABLE,Intersperced Express Traffic enable" "0,1"
newline
bitfld.long 0x0 17. "IET_ENABLE,Intersperced Express Traffic enable" "0,1"
newline
bitfld.long 0x0 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1"
newline
bitfld.long 0x0 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1"
newline
bitfld.long 0x0 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1"
newline
bitfld.long 0x0 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1"
newline
bitfld.long 0x0 12. "P0_TX_CRC_TYPE,Port 0 Transmit CRC Type" "0,1"
newline
bitfld.long 0x0 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x0 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x0 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x0 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x0 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x0 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x0 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x0 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x0 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x0 2. "P0_ENABLE,Port 0 Enable" "0,1"
newline
bitfld.long 0x0 1. "VLAN_AWARE,VLAN Aware Mode" "0,1"
newline
bitfld.long 0x0 0. "S_CN_SWITCH,VLAN Aware Mode" "0,1"
group.long 0x20010++0x17
line.long 0x0 "CPSW_NUSS_VBUSP_EM_CONTROL_REG,CPSW Emulation Control"
bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1"
newline
bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x4 "CPSW_NUSS_VBUSP_STAT_PORT_EN_REG,CPSW Statistics Port Enable"
bitfld.long 0x4 8. "P8_STAT_EN,Port 8 Statistics Enable" "0,1"
newline
bitfld.long 0x4 7. "P7_STAT_EN,Port 7 Statistics Enable" "0,1"
newline
bitfld.long 0x4 6. "P6_STAT_EN,Port 6 Statistics Enable" "0,1"
newline
bitfld.long 0x4 5. "P5_STAT_EN,Port 5 Statistics Enable" "0,1"
newline
bitfld.long 0x4 4. "P4_STAT_EN,Port 4 Statistics Enable" "0,1"
newline
bitfld.long 0x4 3. "P3_STAT_EN,Port 3 Statistics Enable" "0,1"
newline
bitfld.long 0x4 2. "P2_STAT_EN,Port 2 Statistics Enable" "0,1"
newline
bitfld.long 0x4 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1"
newline
bitfld.long 0x4 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1"
line.long 0x8 "CPSW_NUSS_VBUSP_PTYPE_REG,CPSW Transmit Priority Type"
bitfld.long 0x8 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate" "0,1"
newline
bitfld.long 0x8 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate" "0,1"
newline
bitfld.long 0x8 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate" "0,1"
newline
bitfld.long 0x8 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate" "0,1"
newline
bitfld.long 0x8 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate" "0,1"
newline
bitfld.long 0x8 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate" "0,1"
newline
bitfld.long 0x8 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "0,1"
newline
bitfld.long 0x8 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1"
newline
bitfld.long 0x8 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1"
newline
hexmask.long.byte 0x8 0.--4. 1. "ESC_PRI_LD_VAL,Escalate Priority Load Value"
line.long 0xC "CPSW_NUSS_VBUSP_SOFT_IDLE_REG,CPSW Software Idle"
bitfld.long 0xC 0. "SOFT_IDLE,Software Idle" "0,1"
line.long 0x10 "CPSW_NUSS_VBUSP_THRU_RATE_REG,CPSW Thru Rate"
hexmask.long.byte 0x10 12.--15. 1. "SL_RX_THRU_RATE,Switch FIFO receive through rate"
newline
hexmask.long.byte 0x10 0.--3. 1. "P0_RX_THRU_RATE,CPPI FIFO receive through rate"
line.long 0x14 "CPSW_NUSS_VBUSP_GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold"
hexmask.long.byte 0x14 0.--4. 1. "GAP_THRESH,Short Gap Threshold"
group.long 0x2002C++0x1B
line.long 0x0 "CPSW_NUSS_VBUSP_EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value"
hexmask.long.word 0x0 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value"
line.long 0x4 "CPSW_NUSS_VBUSP_TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set"
hexmask.long.byte 0x4 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7"
newline
hexmask.long.byte 0x4 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6"
newline
hexmask.long.byte 0x4 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5"
newline
hexmask.long.byte 0x4 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4"
newline
hexmask.long.byte 0x4 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3"
newline
hexmask.long.byte 0x4 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2"
newline
hexmask.long.byte 0x4 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1"
newline
hexmask.long.byte 0x4 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0"
line.long 0x8 "CPSW_NUSS_VBUSP_TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear"
hexmask.long.byte 0x8 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7"
newline
hexmask.long.byte 0x8 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5"
newline
hexmask.long.byte 0x8 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3"
newline
hexmask.long.byte 0x8 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1"
newline
hexmask.long.byte 0x8 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0"
line.long 0xC "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low"
hexmask.long.byte 0xC 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
newline
hexmask.long.byte 0xC 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
newline
hexmask.long.byte 0xC 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
newline
hexmask.long.byte 0xC 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x10 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High"
hexmask.long.byte 0x10 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
newline
hexmask.long.byte 0x10 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
newline
hexmask.long.byte 0x10 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
newline
hexmask.long.byte 0x10 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
line.long 0x14 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low"
hexmask.long.byte 0x14 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
newline
hexmask.long.byte 0x14 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
newline
hexmask.long.byte 0x14 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
newline
hexmask.long.byte 0x14 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x18 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High"
hexmask.long.byte 0x18 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
newline
hexmask.long.byte 0x18 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
newline
hexmask.long.byte 0x18 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
newline
hexmask.long.byte 0x18 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
group.long 0x20050++0x13
line.long 0x0 "CPSW_NUSS_VBUSP_VLAN_LTYPE_REG,VLAN Length/type"
hexmask.long.word 0x0 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType"
newline
hexmask.long.word 0x0 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType"
line.long 0x4 "CPSW_NUSS_VBUSP_EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain"
hexmask.long.byte 0x4 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain"
line.long 0x8 "CPSW_NUSS_VBUSP_CUT_THRESHOLD_REG,Cut-thru Threshold"
hexmask.long.byte 0x8 0.--3. 1. "CUT_THRESH,Cut-thru Threshold"
line.long 0xC "CPSW_NUSS_VBUSP_FREQUENCY_REG,CPSW CPPI_CLK Frequency in Mhz"
hexmask.long.word 0xC 0.--9. 1. "CUT_THRESH,CPSW CPPI_CLK Frequency in Mhz"
line.long 0x10 "CPSW_NUSS_VBUSP_IET_HOLD_CNT_LD_VAL_REG,IET Hold Count Load Value"
hexmask.long.byte 0x10 0.--7. 1. "IET_HOLD_CNT_LD_VAL,IET_HOLD_CNT_LD_VAL"
group.long 0x20100++0x1F
line.long 0x0 "CPSW_NUSS_VBUSP_TX_PRI0_MAXLEN_REG,Transmit Priority 0 Maximum Length"
hexmask.long.word 0x0 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Length"
line.long 0x4 "CPSW_NUSS_VBUSP_TX_PRI1_MAXLEN_REG,Transmit Priority 1 Maximum Length"
hexmask.long.word 0x4 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Length"
line.long 0x8 "CPSW_NUSS_VBUSP_TX_PRI2_MAXLEN_REG,Transmit Priority 2 Maximum Length"
hexmask.long.word 0x8 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Length"
line.long 0xC "CPSW_NUSS_VBUSP_TX_PRI3_MAXLEN_REG,Transmit Priority 3 Maximum Length"
hexmask.long.word 0xC 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Length"
line.long 0x10 "CPSW_NUSS_VBUSP_TX_PRI4_MAXLEN_REG,Transmit Priority 4 Maximum Length"
hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Length"
line.long 0x14 "CPSW_NUSS_VBUSP_TX_PRI5_MAXLEN_REG,Transmit Priority 5 Maximum Length"
hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Length"
line.long 0x18 "CPSW_NUSS_VBUSP_TX_PRI6_MAXLEN_REG,Transmit Priority 6 Maximum Length"
hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Length"
line.long 0x1C "CPSW_NUSS_VBUSP_TX_PRI7_MAXLEN_REG,Transmit Priority 7 Maximum Length"
hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Length"
tree.end
tree.end
tree "CPTS0 (CPTS0)"
base ad:0x39000000
rgroup.long 0x0++0x3
line.long 0x0 "CPTS_VBUSP_CPTS_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value"
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value"
bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value"
group.long 0x4++0x7
line.long 0x0 "CPTS_VBUSP_CONTROL_REG,Time Sync Control Register"
hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select"
bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1"
bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1"
newline
bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
newline
bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
newline
bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1"
newline
bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode  1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode"
bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1"
bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1"
newline
bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1"
bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1"
bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1"
newline
bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1"
line.long 0x4 "CPTS_VBUSP_RFTCLK_SEL_REG,RFTCLK Select Register"
hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select"
wgroup.long 0xC++0x3
line.long 0x0 "CPTS_VBUSP_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1"
group.long 0x10++0x3
line.long 0x0 "CPTS_VBUSP_TS_LOAD_LOW_VAL_REG,Time Stamp Load Low Value Register"
hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value"
wgroup.long 0x14++0x3
line.long 0x0 "CPTS_VBUSP_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1"
group.long 0x18++0xB
line.long 0x0 "CPTS_VBUSP_TS_COMP_LOW_VAL_REG,Time Stamp Comparison Low Value Register"
hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value"
line.long 0x4 "CPTS_VBUSP_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length"
line.long 0x8 "CPTS_VBUSP_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "CPTS_VBUSP_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
group.long 0x28++0x7
line.long 0x0 "CPTS_VBUSP_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x4 "CPTS_VBUSP_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
wgroup.long 0x30++0x3
line.long 0x0 "CPTS_VBUSP_EVENT_POP_REG,Event Pop Register"
bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1"
rgroup.long 0x34++0xF
line.long 0x0 "CPTS_VBUSP_EVENT_0_REG,Event 0 Register"
hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp"
line.long 0x4 "CPTS_VBUSP_EVENT_1_REG,Event 1 Register"
bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number"
hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type"
newline
hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type"
hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID"
line.long 0x8 "CPTS_VBUSP_EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain"
line.long 0xC "CPTS_VBUSP_EVENT_3_REG,Event 3 Register"
hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp"
group.long 0x44++0x17
line.long 0x0 "CPTS_VBUSP_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value"
line.long 0x4 "CPTS_VBUSP_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value"
line.long 0x8 "CPTS_VBUSP_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7"
line.long 0xC "CPTS_VBUSP_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value"
line.long 0x10 "CPTS_VBUSP_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value"
line.long 0x14 "CPTS_VBUSP_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value"
rgroup.long 0xD0++0x3
line.long 0x0 "CPTS_VBUSP_TS_CONFIG,Time Stamp Configuration Read"
hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,The Event FIFO Depth"
hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,The number of CPTS GENF outputs"
group.long 0xE0++0x1B
line.long 0x0 "CPTS_VBUSP_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value"
line.long 0x4 "CPTS_VBUSP_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value"
line.long 0x8 "CPTS_VBUSP_CONTROL_REG,Time Stamp Generate Function Control"
bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1"
bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1"
line.long 0xC "CPTS_VBUSP_LENGTH_REG,Time Stamp Generate Function Length Value"
hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value"
line.long 0x10 "CPTS_VBUSP_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value"
line.long 0x14 "CPTS_VBUSP_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
line.long 0x18 "CPTS_VBUSP_NUDGE_REG,Time Stamp Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
group.long 0x200++0x1B
line.long 0x0 "CPTS_VBUSP_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value"
hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value"
line.long 0x4 "CPTS_VBUSP_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value"
hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value"
line.long 0x8 "CPTS_VBUSP_CONTROL_REG,Time Stamp ESTF Generate Function Control"
bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1"
bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1"
line.long 0xC "CPTS_VBUSP_LENGTH_REG,Time Stamp ESTF Generate Function Length Value"
hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value"
line.long 0x10 "CPTS_VBUSP_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value"
hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value"
line.long 0x14 "CPTS_VBUSP_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value"
line.long 0x18 "CPTS_VBUSP_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value"
tree.end
tree "CTRL_MMR0_CFG0 (CTRL_MMR0_CFG0)"
base ad:0x43000000
rgroup.long 0x0++0x3
line.long 0x0 "CFG0_PID,"
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
newline
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
rgroup.long 0x8++0x3
line.long 0x0 "CFG0_MMR_CFG1,"
bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN,Proxy addressing activated" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions"
rgroup.long 0x14++0x7
line.long 0x0 "CFG0_JTAGID,"
hexmask.long.byte 0x0 28.--31. 1. "JTAGID_VARIANT,Used to indicate new PGs"
hexmask.long.word 0x0 12.--27. 1. "JTAGID_PARTNO,Part number for boundary scan"
newline
hexmask.long.word 0x0 1.--11. 1. "JTAGID_MFG,Indicates manufacturer"
bitfld.long 0x0 0. "JTAGID_LSB,Always 1" "0,1"
line.long 0x4 "CFG0_JTAG_USER_ID,"
hexmask.long 0x4 0.--31. 1. "JTAG_USER_ID_USERCODE,Device information"
group.long 0x30++0x3
line.long 0x0 "CFG0_MAIN_DEVSTAT,"
hexmask.long.word 0x0 0.--15. 1. "MAIN_DEVSTAT_BOOTMODE,Specifies the device Primary and Backup boot media."
rgroup.long 0x34++0x3
line.long 0x0 "CFG0_MAIN_BOOTCFG,"
hexmask.long.word 0x0 0.--15. 1. "MAIN_BOOTCFG_BOOTMODE,Specifies the device Primary and Backup boot media as latched at PORz"
group.long 0x44++0x3
line.long 0x0 "CFG0_BOOT_PROGRESS,"
hexmask.long 0x0 0.--31. 1. "BOOT_PROGRESS_PROGRESS,Written by ROM to indicate boot progression. Values and their meaning are determined by the ROM."
rgroup.long 0x60++0x3
line.long 0x0 "CFG0_DEVICE_FEATURE0,"
bitfld.long 0x0 19. "DEVICE_FEATURE0_R5FSS1_CORE1,R5FSS1 CPU1 activated when set. CPU0 must also be activated." "0,1"
bitfld.long 0x0 18. "DEVICE_FEATURE0_R5FSS1_CORE0,R5FSS1 CPU0 activated when set." "0,1"
newline
bitfld.long 0x0 17. "DEVICE_FEATURE0_R5FSS0_CORE1,R5FSS0 CPU1 activated when set. CPU0 must also be activated." "0,1"
bitfld.long 0x0 16. "DEVICE_FEATURE0_R5FSS0_CORE0,R5FSS0 CPU0 activated when set." "0,1"
newline
bitfld.long 0x0 1. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE1,MPU Cluster0 Core 1 is activated when set" "0,1"
bitfld.long 0x0 0. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE0,MPU Cluster0 Core 0 is activated when set" "0,1"
rgroup.long 0x68++0x3
line.long 0x0 "CFG0_DEVICE_FEATURE2,"
bitfld.long 0x0 10. "DEVICE_FEATURE2_CRYPTO_PKA_EN,SA2_UL Crypto Module PKA activated" "0,1"
bitfld.long 0x0 9. "DEVICE_FEATURE2_CRYPTO_ENCR_EN,SA2_UL Crypto Module AES/3DES/DBRG activated" "0,1"
newline
bitfld.long 0x0 8. "DEVICE_FEATURE2_CRYPTO_SHA_EN,SA2_UL Crypto Module SHA/MD5 activated" "0,1"
bitfld.long 0x0 7. "DEVICE_FEATURE2_AES_AUTH_EN,AES authentication is activated in FlashSS and DMSC when set" "0,1"
newline
bitfld.long 0x0 0. "DEVICE_FEATURE2_MCAN_FD_MODE,FD mode is supported on MCAN[1:0] when set" "0,1"
group.long 0x78++0x3
line.long 0x0 "CFG0_DEVICE_FEATURE6,"
bitfld.long 0x0 26. "RESERVED,Main Domain Reserved 2 LPSC is activated when set" "0,1"
bitfld.long 0x0 25. "RESERVED,Main Domain Reserved 1 LPSC is activated when set" "0,1"
newline
bitfld.long 0x0 24. "RESERVED,Main Domain Reserved 0 LPSC is activated when set" "0,1"
rbitfld.long 0x0 17. "DEVICE_FEATURE6_SPARE1,Spare1 LPSC is activated when set" "0,1"
newline
rbitfld.long 0x0 16. "DEVICE_FEATURE6_SPARE0,Spare0 LPSC is activated when set" "0,1"
rbitfld.long 0x0 5. "DEVICE_FEATURE6_SA2_UL,MAIN domain security accelerator is activated when set" "0,1"
group.long 0x200++0x7
line.long 0x0 "CFG0_MAC_ID0,"
hexmask.long 0x0 0.--31. 1. "MAC_ID0_MACID_LO,32 lsbs of MAC address"
line.long 0x4 "CFG0_MAC_ID1,"
hexmask.long.word 0x4 0.--15. 1. "MAC_ID1_MACID_HI,16 msbs of MAC address"
group.long 0x210++0x7
line.long 0x0 "CFG0_PCI_DEVICE_ID0,"
hexmask.long 0x0 0.--31. 1. "PCI_DEVICE_ID0_ID0,ROM can optionally update this register with a 32 bit value from Customer OTP."
line.long 0x4 "CFG0_PCI_DEVICE_ID1,"
hexmask.long 0x4 0.--31. 1. "PCI_DEVICE_ID1_ID1,ROM can optionally update this register with a 32 bit value from Customer OTP."
group.long 0x220++0x7
line.long 0x0 "CFG0_USB_DEVICE_ID0,"
hexmask.long 0x0 0.--31. 1. "USB_DEVICE_ID0_ID0,ROM can optionally update this register with a 32 bit value from Customer OTP."
line.long 0x4 "CFG0_USB_DEVICE_ID1,"
hexmask.long 0x4 0.--31. 1. "USB_DEVICE_ID1_ID1,ROM can optionally update this register with a 32 bit value from Customer OTP."
rgroup.long 0x230++0xF
line.long 0x0 "CFG0_GP_SW0,"
hexmask.long 0x0 0.--31. 1. "GP_SW0_VAL,general purpose value"
line.long 0x4 "CFG0_GP_SW1,"
hexmask.long 0x4 0.--31. 1. "GP_SW1_VAL,general purpose value"
line.long 0x8 "CFG0_GP_SW2,"
hexmask.long 0x8 0.--31. 1. "GP_SW2_VAL,general purpose value"
line.long 0xC "CFG0_GP_SW3,"
hexmask.long.byte 0xC 0.--3. 1. "GP_SW3_VAL,general purpose value"
rgroup.long 0x270++0x3
line.long 0x0 "CFG0_CBA_ERR_STAT,"
bitfld.long 0x0 31. "CBA_ERR_STAT_DBG_CBA_ERR," "0,1"
bitfld.long 0x0 16. "CBA_ERR_STAT_MCU_CBA_ERR," "0,1"
newline
bitfld.long 0x0 1. "CBA_ERR_STAT_MAIN_INFRA_CBA_ERR," "0,1"
bitfld.long 0x0 0. "CBA_ERR_STAT_MAIN_CBA_ERR," "0,1"
group.long 0x1008++0x1B
line.long 0x0 "CFG0_LOCK0_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK0_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component"
line.long 0x8 "CFG0_intr_raw_status,"
bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
line.long 0xC "CFG0_intr_enabled_status_clear,"
bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
line.long 0x10 "CFG0_intr_enable,"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
line.long 0x14 "CFG0_intr_enable_clear,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
line.long 0x18 "CFG0_eoi,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip."
rgroup.long 0x1024++0xB
line.long 0x0 "CFG0_fault_address,"
hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address."
line.long 0x4 "CFG0_fault_type_status,"
bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1"
hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
line.long 0x8 "CFG0_fault_attr_status,"
hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID."
hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID."
newline
hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID."
wgroup.long 0x1030++0x3
line.long 0x0 "CFG0_fault_clear,"
bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
rgroup.long 0x1100++0x1B
line.long 0x0 "CFG0_CLAIMREG_P0_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0_READONLY,Claim bits for Partition 0"
line.long 0x4 "CFG0_CLAIMREG_P0_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1_READONLY,Claim bits for Partition 0"
line.long 0x8 "CFG0_CLAIMREG_P0_R2_READONLY,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2_READONLY,Claim bits for Partition 0"
line.long 0xC "CFG0_CLAIMREG_P0_R3_READONLY,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3_READONLY,Claim bits for Partition 0"
line.long 0x10 "CFG0_CLAIMREG_P0_R4_READONLY,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4_READONLY,Claim bits for Partition 0"
line.long 0x14 "CFG0_CLAIMREG_P0_R5_READONLY,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P0_R5_READONLY,Claim bits for Partition 0"
line.long 0x18 "CFG0_CLAIMREG_P0_R6_READONLY,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P0_R6_READONLY,Claim bits for Partition 0"
rgroup.long 0x2000++0x3
line.long 0x0 "CFG0_PID_PROXY,"
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY,"
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY,"
newline
bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY,"
rgroup.long 0x2008++0x3
line.long 0x0 "CFG0_MMR_CFG1_PROXY,"
bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing activated" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions"
rgroup.long 0x2014++0x7
line.long 0x0 "CFG0_JTAGID_PROXY,"
hexmask.long.byte 0x0 28.--31. 1. "JTAGID_VARIANT_PROXY,Used to indicate new PGs"
hexmask.long.word 0x0 12.--27. 1. "JTAGID_PARTNO_PROXY,Part number for boundary scan"
newline
hexmask.long.word 0x0 1.--11. 1. "JTAGID_MFG_PROXY,Indicates manufacturer"
bitfld.long 0x0 0. "JTAGID_LSB_PROXY,Always 1" "0,1"
line.long 0x4 "CFG0_JTAG_USER_ID_PROXY,"
hexmask.long 0x4 0.--31. 1. "JTAG_USER_ID_USERCODE_PROXY,Device information"
group.long 0x2030++0x3
line.long 0x0 "CFG0_MAIN_DEVSTAT_PROXY,"
hexmask.long.word 0x0 0.--15. 1. "MAIN_DEVSTAT_BOOTMODE_PROXY,Specifies the device Primary and Backup boot media."
rgroup.long 0x2034++0x3
line.long 0x0 "CFG0_MAIN_BOOTCFG_PROXY,"
hexmask.long.word 0x0 0.--15. 1. "MAIN_BOOTCFG_BOOTMODE_PROXY,Specifies the device Primary and Backup boot media as latched at PORz"
group.long 0x2044++0x3
line.long 0x0 "CFG0_BOOT_PROGRESS_PROXY,"
hexmask.long 0x0 0.--31. 1. "BOOT_PROGRESS_PROGRESS_PROXY,Written by ROM to indicate boot progression. Values and their meaning are determined by the ROM."
rgroup.long 0x2060++0x3
line.long 0x0 "CFG0_DEVICE_FEATURE0_PROXY,"
bitfld.long 0x0 19. "DEVICE_FEATURE0_R5FSS1_CORE1_PROXY,R5FSS1 CPU1 activated when set. CPU0 must also be activated." "0,1"
bitfld.long 0x0 18. "DEVICE_FEATURE0_R5FSS1_CORE0_PROXY,R5FSS1 CPU0 activated when set." "0,1"
newline
bitfld.long 0x0 17. "DEVICE_FEATURE0_R5FSS0_CORE1_PROXY,R5FSS0 CPU1 activated when set. CPU0 must also be activated." "0,1"
bitfld.long 0x0 16. "DEVICE_FEATURE0_R5FSS0_CORE0_PROXY,R5FSS0 CPU0 activated when set." "0,1"
newline
bitfld.long 0x0 1. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE1_PROXY,MPU Cluster0 Core 1 is activated when set" "0,1"
bitfld.long 0x0 0. "DEVICE_FEATURE0_MPU_CLUSTER0_CORE0_PROXY,MPU Cluster0 Core 0 is activated when set" "0,1"
rgroup.long 0x2068++0x3
line.long 0x0 "CFG0_DEVICE_FEATURE2_PROXY,"
bitfld.long 0x0 10. "DEVICE_FEATURE2_CRYPTO_PKA_EN_PROXY,SA2_UL Crypto Module PKA activated" "0,1"
bitfld.long 0x0 9. "DEVICE_FEATURE2_CRYPTO_ENCR_EN_PROXY,SA2_UL Crypto Module AES/3DES/DBRG activated" "0,1"
newline
bitfld.long 0x0 8. "DEVICE_FEATURE2_CRYPTO_SHA_EN_PROXY,SA2_UL Crypto Module SHA/MD5 activated" "0,1"
bitfld.long 0x0 7. "DEVICE_FEATURE2_AES_AUTH_EN_PROXY,AES authentication is activated in FlashSS and DMSC when set" "0,1"
newline
bitfld.long 0x0 0. "DEVICE_FEATURE2_MCAN_FD_MODE_PROXY,FD mode is supported on MCAN[1:0] when set" "0,1"
group.long 0x2078++0x3
line.long 0x0 "CFG0_DEVICE_FEATURE6_PROXY,"
bitfld.long 0x0 26. "RESERVED,Main Domain Reserved 2 LPSC is activated when set" "0,1"
bitfld.long 0x0 25. "RESERVED,Main Domain Reserved 1 LPSC is activated when set" "0,1"
newline
bitfld.long 0x0 24. "RESERVED,Main Domain Reserved 0 LPSC is activated when set" "0,1"
rbitfld.long 0x0 17. "DEVICE_FEATURE6_SPARE1_PROXY,Spare1 LPSC is activated when set" "0,1"
newline
rbitfld.long 0x0 16. "DEVICE_FEATURE6_SPARE0_PROXY,Spare0 LPSC is activated when set" "0,1"
rbitfld.long 0x0 5. "DEVICE_FEATURE6_SA2_UL_PROXY,MAIN domain security accelerator is activated when set" "0,1"
group.long 0x2200++0x7
line.long 0x0 "CFG0_MAC_ID0_PROXY,"
hexmask.long 0x0 0.--31. 1. "MAC_ID0_MACID_LO_PROXY,32 lsbs of MAC address"
line.long 0x4 "CFG0_MAC_ID1_PROXY,"
hexmask.long.word 0x4 0.--15. 1. "MAC_ID1_MACID_HI_PROXY,16 msbs of MAC address"
group.long 0x2210++0x7
line.long 0x0 "CFG0_PCI_DEVICE_ID0_PROXY,"
hexmask.long 0x0 0.--31. 1. "PCI_DEVICE_ID0_ID0_PROXY,ROM can optionally update this register with a 32 bit value from Customer OTP."
line.long 0x4 "CFG0_PCI_DEVICE_ID1_PROXY,"
hexmask.long 0x4 0.--31. 1. "PCI_DEVICE_ID1_ID1_PROXY,ROM can optionally update this register with a 32 bit value from Customer OTP."
group.long 0x2220++0x7
line.long 0x0 "CFG0_USB_DEVICE_ID0_PROXY,"
hexmask.long 0x0 0.--31. 1. "USB_DEVICE_ID0_ID0_PROXY,ROM can optionally update this register with a 32 bit value from Customer OTP."
line.long 0x4 "CFG0_USB_DEVICE_ID1_PROXY,"
hexmask.long 0x4 0.--31. 1. "USB_DEVICE_ID1_ID1_PROXY,ROM can optionally update this register with a 32 bit value from Customer OTP."
rgroup.long 0x2230++0xF
line.long 0x0 "CFG0_GP_SW0_PROXY,"
hexmask.long 0x0 0.--31. 1. "GP_SW0_VAL_PROXY,general purpose value"
line.long 0x4 "CFG0_GP_SW1_PROXY,"
hexmask.long 0x4 0.--31. 1. "GP_SW1_VAL_PROXY,general purpose value"
line.long 0x8 "CFG0_GP_SW2_PROXY,"
hexmask.long 0x8 0.--31. 1. "GP_SW2_VAL_PROXY,general purpose value"
line.long 0xC "CFG0_GP_SW3_PROXY,"
hexmask.long.byte 0xC 0.--3. 1. "GP_SW3_VAL_PROXY,general purpose value"
rgroup.long 0x2270++0x3
line.long 0x0 "CFG0_CBA_ERR_STAT_PROXY,"
bitfld.long 0x0 31. "CBA_ERR_STAT_DBG_CBA_ERR_PROXY," "0,1"
bitfld.long 0x0 16. "CBA_ERR_STAT_MCU_CBA_ERR_PROXY," "0,1"
newline
bitfld.long 0x0 1. "CBA_ERR_STAT_MAIN_INFRA_CBA_ERR_PROXY," "0,1"
bitfld.long 0x0 0. "CBA_ERR_STAT_MAIN_CBA_ERR_PROXY," "0,1"
group.long 0x3008++0x1B
line.long 0x0 "CFG0_LOCK0_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK0_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component"
line.long 0x8 "CFG0_intr_raw_status_PROXY,"
bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
line.long 0xC "CFG0_intr_enabled_status_clear_PROXY,"
bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
line.long 0x10 "CFG0_intr_enable_PROXY,"
bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
line.long 0x14 "CFG0_intr_enable_clear_PROXY,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
line.long 0x18 "CFG0_eoi_PROXY,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip."
rgroup.long 0x3024++0xB
line.long 0x0 "CFG0_fault_address_PROXY,"
hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address."
line.long 0x4 "CFG0_fault_type_status_PROXY,"
bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1"
hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.."
line.long 0x8 "CFG0_fault_attr_status_PROXY,"
hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID."
hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID."
newline
hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID."
wgroup.long 0x3030++0x3
line.long 0x0 "CFG0_fault_clear_PROXY,"
bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
group.long 0x3100++0x1B
line.long 0x0 "CFG0_CLAIMREG_P0_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0,Claim bits for Partition 0"
line.long 0x4 "CFG0_CLAIMREG_P0_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1,Claim bits for Partition 0"
line.long 0x8 "CFG0_CLAIMREG_P0_R2,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2,Claim bits for Partition 0"
line.long 0xC "CFG0_CLAIMREG_P0_R3,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3,Claim bits for Partition 0"
line.long 0x10 "CFG0_CLAIMREG_P0_R4,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4,Claim bits for Partition 0"
line.long 0x14 "CFG0_CLAIMREG_P0_R5,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P0_R5,Claim bits for Partition 0"
line.long 0x18 "CFG0_CLAIMREG_P0_R6,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P0_R6,Claim bits for Partition 0"
group.long 0x4008++0x3
line.long 0x0 "CFG0_USB0_PHY_CTRL,"
bitfld.long 0x0 31. "USB0_PHY_CTRL_CORE_VOLTAGE,Selects the USB PHY Core Voltage" "0,1"
bitfld.long 0x0 16.--17. "USB0_PHY_CTRL_LOOPBACK_MODE,Activates USB0 PHY loopback operation" "0,1,2,3"
newline
bitfld.long 0x0 15. "USB0_PHY_CTRL_PLL_STANDALONE,Activates USB0 PHY as a standalone PLL" "0,1"
bitfld.long 0x0 11. "USB0_PHY_CTRL_PLL_CLKOUT_ON,Controls USB0 PLL clock output" "0,1"
newline
bitfld.long 0x0 8.--9. "USB0_PHY_CTRL_PLL_CLKOUT_SEL,Selects the frequency of the USB0 PLL output clock" "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "USB0_PHY_CTRL_PLL_REF_SEL,Indicates the frequency of the REF_CLOCK input used by the USB PLL. This value should match the frequency value of either the HFOSC0 or HFOSC1 oscillator as selected by the USB0_CLKSEL register"
group.long 0x4044++0x7
line.long 0x0 "CFG0_ENET1_CTRL,"
bitfld.long 0x0 4. "ENET1_CTRL_RGMII_ID_MODE,Port1 RGMII internal transmit delay selection" "0,1"
bitfld.long 0x0 0.--2. "ENET1_CTRL_PORT_MODE_SEL,Selects Ethernet switch Port1 interface" "0,1,2,3,4,5,6,7"
line.long 0x4 "CFG0_ENET2_CTRL,"
bitfld.long 0x4 4. "ENET2_CTRL_RGMII_ID_MODE,Port2 RGMII internal transmit delay selection" "0,1"
bitfld.long 0x4 0.--2. "ENET2_CTRL_PORT_MODE_SEL,Selects Ethernet switch Port2 interface" "0,1,2,3,4,5,6,7"
group.long 0x4070++0x3
line.long 0x0 "CFG0_PCIE0_CTRL,"
bitfld.long 0x0 7. "PCIE0_CTRL_MODE_SEL,Selects the operating mode" "0,1"
bitfld.long 0x0 0.--1. "PCIE0_CTRL_GENERATION_SEL,Configures the PCIe generation support in the PCIe capabilities linked-list" "0,1,2,3"
group.long 0x4080++0x3
line.long 0x0 "CFG0_SERDES0_LN0_CTRL,"
bitfld.long 0x0 0.--1. "SERDES0_LN0_CTRL_LANE_FUNC_SEL,Selects the SERDES0 lane0 function" "0,1,2,3"
group.long 0x40C0++0x3
line.long 0x0 "CFG0_ADC0_TRIM,"
bitfld.long 0x0 24.--26. "ADC0_TRIM_TRIM5,Trims Nonlinearities from ADC" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 21.--23. "ADC0_TRIM_TRIM4,Trims Nonlinearities from ADC" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "ADC0_TRIM_TRIM3,Trims Nonlinearities from ADC" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 14.--17. 1. "ADC0_TRIM_TRIM2,Trims Nonlinearities from ADC"
newline
hexmask.long.byte 0x0 10.--13. 1. "ADC0_TRIM_TRIM1,Trims Nonlinearities from ADC"
hexmask.long.byte 0x0 5.--9. 1. "ADC0_TRIM_ENABLE_CALB,Trims Nonlinearities from ADC"
newline
hexmask.long.byte 0x0 0.--4. 1. "ADC0_TRIM_ENABLE_CAL,Trims Nonlinearities from ADC"
group.long 0x40E0++0x3
line.long 0x0 "CFG0_SERDES0_CTRL,"
bitfld.long 0x0 12. "SERDES0_CTRL_REF_SEL,REFCLK output select" "0,1"
bitfld.long 0x0 8. "SERDES0_CTRL_RET_EN,Retention activate" "0,1"
group.long 0x4100++0x7
line.long 0x0 "CFG0_ICSSG0_CTRL0,"
bitfld.long 0x0 24. "ICSSG0_CTRL0_RGMII0_ID_MODE,Controls the ICSS_G0 RGMII0 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x0 0.--19. 1. "ICSSG0_CTRL0_GPM_BIDI,Controls operation of the ICSS_G0 PRU0_GPO pins. Each bit n controls the corresponding PRG0_PRU0GPOn I/O"
line.long 0x4 "CFG0_ICSSG0_CTRL1,"
bitfld.long 0x4 24. "ICSSG0_CTRL1_RGMII1_ID_MODE,Controls the ICSS_G0 RGMII1 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x4 0.--19. 1. "ICSSG0_CTRL1_GPM_BIDI,Controls operation of the ICSS_G0 PRU1_GPO pins. Each bit n controls the corresponding PRG0_PRU1GPOn I/O"
group.long 0x4110++0x7
line.long 0x0 "CFG0_ICSSG1_CTRL0,"
bitfld.long 0x0 24. "ICSSG1_CTRL0_RGMII0_ID_MODE,Controls the ICSS_G1 RGMII0 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x0 0.--19. 1. "ICSSG1_CTRL0_GPM_BIDI,Controls operation of the ICSS_G1 PRU0_GPO pins. Each bit n controls the corresponding PRG1_PRU0GPOn I/O"
line.long 0x4 "CFG0_ICSSG1_CTRL1,"
bitfld.long 0x4 24. "ICSSG1_CTRL1_RGMII1_ID_MODE,Controls the ICSS_G1 RGMII1 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x4 0.--19. 1. "ICSSG1_CTRL1_GPM_BIDI,Controls operation of the ICSS_G1 PRU1_GPO pins. Each bit n controls the corresponding PRG1_PRU1GPOn I/O"
group.long 0x4130++0xB
line.long 0x0 "CFG0_EPWM_TB_CLKEN,"
bitfld.long 0x0 8. "EPWM_TB_CLKEN_EPWM8_TB_CLKEN,Activates Timebase Clock of EPWM8 When Set" "0,1"
bitfld.long 0x0 7. "EPWM_TB_CLKEN_EPWM7_TB_CLKEN,Activates Timebase Clock of EPWM7 When Set" "0,1"
newline
bitfld.long 0x0 6. "EPWM_TB_CLKEN_EPWM6_TB_CLKEN,Activates Timebase Clock of EPWM6 When Set" "0,1"
bitfld.long 0x0 5. "EPWM_TB_CLKEN_EPWM5_TB_CLKEN,Activates Timebase Clock of EPWM5 When Set" "0,1"
newline
bitfld.long 0x0 4. "EPWM_TB_CLKEN_EPWM4_TB_CLKEN,Activates Timebase Clock of EPWM4 When Set" "0,1"
bitfld.long 0x0 3. "EPWM_TB_CLKEN_EPWM3_TB_CLKEN,Activates Timebase Clock of EPWM3 When Set" "0,1"
newline
bitfld.long 0x0 2. "EPWM_TB_CLKEN_EPWM2_TB_CLKEN,Activates Timebase Clock of EPWM2 When Set" "0,1"
bitfld.long 0x0 1. "EPWM_TB_CLKEN_EPWM1_TB_CLKEN,Activates Timebase Clock of EPWM1 When Set" "0,1"
newline
bitfld.long 0x0 0. "EPWM_TB_CLKEN_EPWM0_TB_CLKEN,Activates Timebase Clock of EPWM0 When Set" "0,1"
line.long 0x4 "CFG0_EPWM_TB_CLKEN_SET,"
bitfld.long 0x4 8. "EPWM_TB_CLKEN_SET_EPWM8_TB_CLKEN,Writing One Activates Timebase Clock of EPWM8" "0,1"
bitfld.long 0x4 7. "EPWM_TB_CLKEN_SET_EPWM7_TB_CLKEN,Writing One Activates Timebase Clock of EPWM7" "0,1"
newline
bitfld.long 0x4 6. "EPWM_TB_CLKEN_SET_EPWM6_TB_CLKEN,Writing One Activates Timebase Clock of EPWM6" "0,1"
bitfld.long 0x4 5. "EPWM_TB_CLKEN_SET_EPWM5_TB_CLKEN,Writing One Activates Timebase Clock of EPWM5" "0,1"
newline
bitfld.long 0x4 4. "EPWM_TB_CLKEN_SET_EPWM4_TB_CLKEN,Writing One Activates Timebase Clock of EPWM4" "0,1"
bitfld.long 0x4 3. "EPWM_TB_CLKEN_SET_EPWM3_TB_CLKEN,Writing One Activates Timebase Clock of EPWM3" "0,1"
newline
bitfld.long 0x4 2. "EPWM_TB_CLKEN_SET_EPWM2_TB_CLKEN,Writing One Activates Timebase Clock of EPWM2" "0,1"
bitfld.long 0x4 1. "EPWM_TB_CLKEN_SET_EPWM1_TB_CLKEN,Writing One Activates Timebase Clock of EPWM1" "0,1"
newline
bitfld.long 0x4 0. "EPWM_TB_CLKEN_SET_EPWM0_TB_CLKEN,Writing One Activates Timebase Clock of EPWM0" "0,1"
line.long 0x8 "CFG0_EPWM_TB_CLKEN_CLR,"
bitfld.long 0x8 8. "EPWM_TB_CLKEN_CLR_EPWM8_TB_CLKEN,Writing One Deactivates Timebase Clock of EPWM8" "0,1"
bitfld.long 0x8 7. "EPWM_TB_CLKEN_CLR_EPWM7_TB_CLKEN,Writing One Deactivates Timebase Clock of EPWM7" "0,1"
newline
bitfld.long 0x8 6. "EPWM_TB_CLKEN_CLR_EPWM6_TB_CLKEN,Writing One Deactivates Timebase Clock of EPWM6" "0,1"
bitfld.long 0x8 5. "EPWM_TB_CLKEN_CLR_EPWM5_TB_CLKEN,Writing One Deactivates Timebase Clock of EPWM5" "0,1"
newline
bitfld.long 0x8 4. "EPWM_TB_CLKEN_CLR_EPWM4_TB_CLKEN,Writing One Deactivates Timebase Clock of EPWM4" "0,1"
bitfld.long 0x8 3. "EPWM_TB_CLKEN_CLR_EPWM3_TB_CLKEN,Writing One Deactivates Timebase Clock of EPWM3" "0,1"
newline
bitfld.long 0x8 2. "EPWM_TB_CLKEN_CLR_EPWM2_TB_CLKEN,Writing One Deactivates Timebase Clock of EPWM2" "0,1"
bitfld.long 0x8 1. "EPWM_TB_CLKEN_CLR_EPWM1_TB_CLKEN,Writing One Deactivates Timebase Clock of EPWM1" "0,1"
newline
bitfld.long 0x8 0. "EPWM_TB_CLKEN_CLR_EPWM0_TB_CLKEN,Writing One Deactivates Timebase Clock of EPWM0" "0,1"
group.long 0x4140++0x23
line.long 0x0 "CFG0_EPWM0_CTRL,"
bitfld.long 0x0 8.--10. "EPWM0_CTRL_SYNCIN_SEL,Selects the source of the EPWM0 synchronization input" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4. "EPWM0_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x4 "CFG0_EPWM1_CTRL,"
bitfld.long 0x4 4. "EPWM1_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x8 "CFG0_EPWM2_CTRL,"
bitfld.long 0x8 4. "EPWM2_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "0,1"
line.long 0xC "CFG0_EPWM3_CTRL,"
bitfld.long 0xC 8.--10. "EPWM3_CTRL_SYNCIN_SEL,Selects the source of the EPWM3 synchronization input" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 4. "EPWM3_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x10 "CFG0_EPWM4_CTRL,"
bitfld.long 0x10 4. "EPWM4_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x14 "CFG0_EPWM5_CTRL,"
bitfld.long 0x14 4. "EPWM5_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x18 "CFG0_EPWM6_CTRL,"
bitfld.long 0x18 8.--10. "EPWM6_CTRL_SYNCIN_SEL,Selects the source of the EPWM6 synchronization input" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 4. "EPWM6_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x1C "CFG0_EPWM7_CTRL,"
bitfld.long 0x1C 4. "EPWM7_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x20 "CFG0_EPWM8_CTRL,"
bitfld.long 0x20 4. "EPWM8_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "0,1"
group.long 0x4170++0x7
line.long 0x0 "CFG0_SOCA_SEL,"
bitfld.long 0x0 0.--1. "SOCA_SEL_SOCA_SEL,Selects the SOC A output source" "0,1,2,3"
line.long 0x4 "CFG0_SOCB_SEL,"
bitfld.long 0x4 0.--1. "SOCB_SEL_SOCB_SEL,Selects the SOC B output source" "0,1,2,3"
group.long 0x4180++0xB
line.long 0x0 "CFG0_EQEP0_CTRL,"
hexmask.long.byte 0x0 0.--4. 1. "EQEP0_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP0"
line.long 0x4 "CFG0_EQEP1_CTRL,"
hexmask.long.byte 0x4 0.--4. 1. "EQEP1_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP1"
line.long 0x8 "CFG0_EQEP2_CTRL,"
hexmask.long.byte 0x8 0.--4. 1. "EQEP2_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP2"
rgroup.long 0x41A0++0x3
line.long 0x0 "CFG0_EQEP_STAT,"
bitfld.long 0x0 2. "EQEP_STAT_PHASE_ERR2,EQEP2 Phase error status" "0,1"
bitfld.long 0x0 1. "EQEP_STAT_PHASE_ERR1,EQEP1 Phase error status" "0,1"
newline
bitfld.long 0x0 0. "EQEP_STAT_PHASE_ERR0,EQEP0 Phase error status" "0,1"
group.long 0x41B4++0x3
line.long 0x0 "CFG0_SDIO1_CTRL,"
hexmask.long.byte 0x0 0.--4. 1. "SDIO1_CTRL_DRV_STR,Selects the SDIO drive strength"
group.long 0x4204++0x3
line.long 0x0 "CFG0_TIMER1_CTRL,"
bitfld.long 0x0 8. "TIMER1_CTRL_CASCADE_EN,Activates cascading of TIMER1 to TIMER0" "0,1"
group.long 0x420C++0x3
line.long 0x0 "CFG0_TIMER3_CTRL,"
bitfld.long 0x0 8. "TIMER3_CTRL_CASCADE_EN,Activates cascading of TIMER3 to TIMER2" "0,1"
group.long 0x4214++0x3
line.long 0x0 "CFG0_TIMER5_CTRL,"
bitfld.long 0x0 8. "TIMER5_CTRL_CASCADE_EN,Activates cascading of TIMER5 to TIMER4" "0,1"
group.long 0x421C++0x3
line.long 0x0 "CFG0_TIMER7_CTRL,"
bitfld.long 0x0 8. "TIMER7_CTRL_CASCADE_EN,Activates cascading of TIMER7 to TIMER6" "0,1"
group.long 0x4224++0x3
line.long 0x0 "CFG0_TIMER9_CTRL,"
bitfld.long 0x0 8. "TIMER9_CTRL_CASCADE_EN,Activates cascading of TIMER9 to TIMER8" "0,1"
group.long 0x422C++0x3
line.long 0x0 "CFG0_TIMER11_CTRL,"
bitfld.long 0x0 8. "TIMER11_CTRL_CASCADE_EN,Activates cascading of TIMER11 to TIMER10" "0,1"
group.long 0x42E0++0x3
line.long 0x0 "CFG0_I2C0_CTRL,"
bitfld.long 0x0 0. "I2C0_CTRL_HS_MCS_EN,HS Mode controller current source activate." "0,1"
group.long 0x4700++0x3
line.long 0x0 "CFG0_FSS_CTRL,"
bitfld.long 0x0 8. "FSS_CTRL_S0_BOOT_SIZE,Selects the size of the boot block to be used for the S0 (OSPI0) flash interface" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "FSS_CTRL_S0_BOOT_SEG,Selects the boot block to be used for the S0 (OSPI0) flash interface. If the s0_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off or wrap.."
group.long 0x4710++0x3
line.long 0x0 "CFG0_ADC0_CTRL,"
bitfld.long 0x0 16. "ADC0_CTRL_GPI_MODE_EN,Activates ADC0 data pins to be used as general purpose inputs when set. This signal is tied to the en_dig_test input of MCU_ADC0" "0,1"
hexmask.long.byte 0x0 0.--4. 1. "ADC0_CTRL_TRIG_SEL,Selects the source of the ADC hardware event trigger"
rgroup.long 0x4750++0x3
line.long 0x0 "CFG0_DCC_STAT,"
bitfld.long 0x0 16. "DCC_STAT_MCU_DCC0_INTR_DONE,MCU_DCC0 Done Interrupt Status" "0,1"
bitfld.long 0x0 5. "DCC_STAT_DCC5_INTR_DONE,DCC5 Done Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "DCC_STAT_DCC4_INTR_DONE,DCC4 Done Interrupt Status" "0,1"
bitfld.long 0x0 3. "DCC_STAT_DCC3_INTR_DONE,DCC3 Done Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "DCC_STAT_DCC2_INTR_DONE,DCC2 Done Interrupt Status" "0,1"
bitfld.long 0x0 1. "DCC_STAT_DCC1_INTR_DONE,DCC1 Done Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "DCC_STAT_DCC0_INTR_DONE,DCC0 Done Interrupt Status" "0,1"
group.long 0x5008++0x7
line.long 0x0 "CFG0_LOCK1_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK1_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component"
rgroup.long 0x5100++0x3B
line.long 0x0 "CFG0_CLAIMREG_P1_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0_READONLY,Claim bits for Partition 1"
line.long 0x4 "CFG0_CLAIMREG_P1_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1_READONLY,Claim bits for Partition 1"
line.long 0x8 "CFG0_CLAIMREG_P1_R2_READONLY,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2_READONLY,Claim bits for Partition 1"
line.long 0xC "CFG0_CLAIMREG_P1_R3_READONLY,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3_READONLY,Claim bits for Partition 1"
line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4_READONLY,Claim bits for Partition 1"
line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5_READONLY,Claim bits for Partition 1"
line.long 0x18 "CFG0_CLAIMREG_P1_R6_READONLY,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6_READONLY,Claim bits for Partition 1"
line.long 0x1C "CFG0_CLAIMREG_P1_R7_READONLY,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P1_R7_READONLY,Claim bits for Partition 1"
line.long 0x20 "CFG0_CLAIMREG_P1_R8_READONLY,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P1_R8_READONLY,Claim bits for Partition 1"
line.long 0x24 "CFG0_CLAIMREG_P1_R9_READONLY,"
hexmask.long 0x24 0.--31. 1. "CLAIMREG_P1_R9_READONLY,Claim bits for Partition 1"
line.long 0x28 "CFG0_CLAIMREG_P1_R10_READONLY,"
hexmask.long 0x28 0.--31. 1. "CLAIMREG_P1_R10_READONLY,Claim bits for Partition 1"
line.long 0x2C "CFG0_CLAIMREG_P1_R11_READONLY,"
hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P1_R11_READONLY,Claim bits for Partition 1"
line.long 0x30 "CFG0_CLAIMREG_P1_R12_READONLY,"
hexmask.long 0x30 0.--31. 1. "CLAIMREG_P1_R12_READONLY,Claim bits for Partition 1"
line.long 0x34 "CFG0_CLAIMREG_P1_R13_READONLY,"
hexmask.long 0x34 0.--31. 1. "CLAIMREG_P1_R13_READONLY,Claim bits for Partition 1"
line.long 0x38 "CFG0_CLAIMREG_P1_R14_READONLY,"
hexmask.long 0x38 0.--31. 1. "CLAIMREG_P1_R14_READONLY,Claim bits for Partition 1"
group.long 0x6008++0x3
line.long 0x0 "CFG0_USB0_PHY_CTRL_PROXY,"
bitfld.long 0x0 31. "USB0_PHY_CTRL_CORE_VOLTAGE_PROXY,Selects the USB PHY Core Voltage" "0,1"
bitfld.long 0x0 16.--17. "USB0_PHY_CTRL_LOOPBACK_MODE_PROXY,Activates USB0 PHY loopback operation" "0,1,2,3"
newline
bitfld.long 0x0 15. "USB0_PHY_CTRL_PLL_STANDALONE_PROXY,Activates USB0 PHY as a standalone PLL" "0,1"
bitfld.long 0x0 11. "USB0_PHY_CTRL_PLL_CLKOUT_ON_PROXY,Controls USB0 PLL clock output" "0,1"
newline
bitfld.long 0x0 8.--9. "USB0_PHY_CTRL_PLL_CLKOUT_SEL_PROXY,Selects the frequency of the USB0 PLL output clock" "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "USB0_PHY_CTRL_PLL_REF_SEL_PROXY,Indicates the frequency of the REF_CLOCK input used by the USB PLL. This value should match the frequency value of either the HFOSC0 or HFOSC1 oscillator as selected by the USB0_CLKSEL register"
group.long 0x6044++0x7
line.long 0x0 "CFG0_ENET1_CTRL_PROXY,"
bitfld.long 0x0 4. "ENET1_CTRL_RGMII_ID_MODE_PROXY,Port1 RGMII internal transmit delay selection" "0,1"
bitfld.long 0x0 0.--2. "ENET1_CTRL_PORT_MODE_SEL_PROXY,Selects Ethernet switch Port1 interface" "0,1,2,3,4,5,6,7"
line.long 0x4 "CFG0_ENET2_CTRL_PROXY,"
bitfld.long 0x4 4. "ENET2_CTRL_RGMII_ID_MODE_PROXY,Port2 RGMII internal transmit delay selection" "0,1"
bitfld.long 0x4 0.--2. "ENET2_CTRL_PORT_MODE_SEL_PROXY,Selects Ethernet switch Port2 interface" "0,1,2,3,4,5,6,7"
group.long 0x6070++0x3
line.long 0x0 "CFG0_PCIE0_CTRL_PROXY,"
bitfld.long 0x0 7. "PCIE0_CTRL_MODE_SEL_PROXY,Selects the operating mode" "0,1"
bitfld.long 0x0 0.--1. "PCIE0_CTRL_GENERATION_SEL_PROXY,Configures the PCIe generation support in the PCIe capabilities linked-list" "0,1,2,3"
group.long 0x6080++0x3
line.long 0x0 "CFG0_SERDES0_LN0_CTRL_PROXY,"
bitfld.long 0x0 0.--1. "SERDES0_LN0_CTRL_LANE_FUNC_SEL_PROXY,Selects the SERDES0 lane0 function" "0,1,2,3"
group.long 0x60C0++0x3
line.long 0x0 "CFG0_ADC0_TRIM_PROXY,"
bitfld.long 0x0 24.--26. "ADC0_TRIM_TRIM5_PROXY,Trims Nonlinearities from ADC" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 21.--23. "ADC0_TRIM_TRIM4_PROXY,Trims Nonlinearities from ADC" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "ADC0_TRIM_TRIM3_PROXY,Trims Nonlinearities from ADC" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 14.--17. 1. "ADC0_TRIM_TRIM2_PROXY,Trims Nonlinearities from ADC"
newline
hexmask.long.byte 0x0 10.--13. 1. "ADC0_TRIM_TRIM1_PROXY,Trims Nonlinearities from ADC"
hexmask.long.byte 0x0 5.--9. 1. "ADC0_TRIM_ENABLE_CALB_PROXY,Trims Nonlinearities from ADC"
newline
hexmask.long.byte 0x0 0.--4. 1. "ADC0_TRIM_ENABLE_CAL_PROXY,Trims Nonlinearities from ADC"
group.long 0x60E0++0x3
line.long 0x0 "CFG0_SERDES0_CTRL_PROXY,"
bitfld.long 0x0 12. "SERDES0_CTRL_REF_SEL_PROXY,REFCLK output select" "0,1"
bitfld.long 0x0 8. "SERDES0_CTRL_RET_EN_PROXY,Retention activate" "0,1"
group.long 0x6100++0x7
line.long 0x0 "CFG0_ICSSG0_CTRL0_PROXY,"
bitfld.long 0x0 24. "ICSSG0_CTRL0_RGMII0_ID_MODE_PROXY,Controls the ICSS_G0 RGMII0 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x0 0.--19. 1. "ICSSG0_CTRL0_GPM_BIDI_PROXY,Controls operation of the ICSS_G0 PRU0_GPO pins. Each bit n controls the corresponding PRG0_PRU0GPOn I/O"
line.long 0x4 "CFG0_ICSSG0_CTRL1_PROXY,"
bitfld.long 0x4 24. "ICSSG0_CTRL1_RGMII1_ID_MODE_PROXY,Controls the ICSS_G0 RGMII1 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x4 0.--19. 1. "ICSSG0_CTRL1_GPM_BIDI_PROXY,Controls operation of the ICSS_G0 PRU1_GPO pins. Each bit n controls the corresponding PRG0_PRU1GPOn I/O"
group.long 0x6110++0x7
line.long 0x0 "CFG0_ICSSG1_CTRL0_PROXY,"
bitfld.long 0x0 24. "ICSSG1_CTRL0_RGMII0_ID_MODE_PROXY,Controls the ICSS_G1 RGMII0 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x0 0.--19. 1. "ICSSG1_CTRL0_GPM_BIDI_PROXY,Controls operation of the ICSS_G1 PRU0_GPO pins. Each bit n controls the corresponding PRG1_PRU0GPOn I/O"
line.long 0x4 "CFG0_ICSSG1_CTRL1_PROXY,"
bitfld.long 0x4 24. "ICSSG1_CTRL1_RGMII1_ID_MODE_PROXY,Controls the ICSS_G1 RGMII1 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x4 0.--19. 1. "ICSSG1_CTRL1_GPM_BIDI_PROXY,Controls operation of the ICSS_G1 PRU1_GPO pins. Each bit n controls the corresponding PRG1_PRU1GPOn I/O"
group.long 0x6130++0xB
line.long 0x0 "CFG0_EPWM_TB_CLKEN_PROXY,"
bitfld.long 0x0 8. "EPWM_TB_CLKEN_EPWM8_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM8 When Set" "0,1"
bitfld.long 0x0 7. "EPWM_TB_CLKEN_EPWM7_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM7 When Set" "0,1"
newline
bitfld.long 0x0 6. "EPWM_TB_CLKEN_EPWM6_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM6 When Set" "0,1"
bitfld.long 0x0 5. "EPWM_TB_CLKEN_EPWM5_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM5 When Set" "0,1"
newline
bitfld.long 0x0 4. "EPWM_TB_CLKEN_EPWM4_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM4 When Set" "0,1"
bitfld.long 0x0 3. "EPWM_TB_CLKEN_EPWM3_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM3 When Set" "0,1"
newline
bitfld.long 0x0 2. "EPWM_TB_CLKEN_EPWM2_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM2 When Set" "0,1"
bitfld.long 0x0 1. "EPWM_TB_CLKEN_EPWM1_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM1 When Set" "0,1"
newline
bitfld.long 0x0 0. "EPWM_TB_CLKEN_EPWM0_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM0 When Set" "0,1"
line.long 0x4 "CFG0_EPWM_TB_CLKEN_SET_PROXY,"
bitfld.long 0x4 8. "EPWM_TB_CLKEN_SET_EPWM8_TB_CLKEN_PROXY,Writing One Activates Timebase Clock of EPWM8" "0,1"
bitfld.long 0x4 7. "EPWM_TB_CLKEN_SET_EPWM7_TB_CLKEN_PROXY,Writing One Activates Timebase Clock of EPWM7" "0,1"
newline
bitfld.long 0x4 6. "EPWM_TB_CLKEN_SET_EPWM6_TB_CLKEN_PROXY,Writing One Activates Timebase Clock of EPWM6" "0,1"
bitfld.long 0x4 5. "EPWM_TB_CLKEN_SET_EPWM5_TB_CLKEN_PROXY,Writing One Activates Timebase Clock of EPWM5" "0,1"
newline
bitfld.long 0x4 4. "EPWM_TB_CLKEN_SET_EPWM4_TB_CLKEN_PROXY,Writing One Activates Timebase Clock of EPWM4" "0,1"
bitfld.long 0x4 3. "EPWM_TB_CLKEN_SET_EPWM3_TB_CLKEN_PROXY,Writing One Activates Timebase Clock of EPWM3" "0,1"
newline
bitfld.long 0x4 2. "EPWM_TB_CLKEN_SET_EPWM2_TB_CLKEN_PROXY,Writing One Activates Timebase Clock of EPWM2" "0,1"
bitfld.long 0x4 1. "EPWM_TB_CLKEN_SET_EPWM1_TB_CLKEN_PROXY,Writing One Activates Timebase Clock of EPWM1" "0,1"
newline
bitfld.long 0x4 0. "EPWM_TB_CLKEN_SET_EPWM0_TB_CLKEN_PROXY,Writing One Activates Timebase Clock of EPWM0" "0,1"
line.long 0x8 "CFG0_EPWM_TB_CLKEN_CLR_PROXY,"
bitfld.long 0x8 8. "EPWM_TB_CLKEN_CLR_EPWM8_TB_CLKEN_PROXY,Writing One Deactivates Timebase Clock of EPWM8" "0,1"
bitfld.long 0x8 7. "EPWM_TB_CLKEN_CLR_EPWM7_TB_CLKEN_PROXY,Writing One Deactivates Timebase Clock of EPWM7" "0,1"
newline
bitfld.long 0x8 6. "EPWM_TB_CLKEN_CLR_EPWM6_TB_CLKEN_PROXY,Writing One Deactivates Timebase Clock of EPWM6" "0,1"
bitfld.long 0x8 5. "EPWM_TB_CLKEN_CLR_EPWM5_TB_CLKEN_PROXY,Writing One Deactivates Timebase Clock of EPWM5" "0,1"
newline
bitfld.long 0x8 4. "EPWM_TB_CLKEN_CLR_EPWM4_TB_CLKEN_PROXY,Writing One Deactivates Timebase Clock of EPWM4" "0,1"
bitfld.long 0x8 3. "EPWM_TB_CLKEN_CLR_EPWM3_TB_CLKEN_PROXY,Writing One Deactivates Timebase Clock of EPWM3" "0,1"
newline
bitfld.long 0x8 2. "EPWM_TB_CLKEN_CLR_EPWM2_TB_CLKEN_PROXY,Writing One Deactivates Timebase Clock of EPWM2" "0,1"
bitfld.long 0x8 1. "EPWM_TB_CLKEN_CLR_EPWM1_TB_CLKEN_PROXY,Writing One Deactivates Timebase Clock of EPWM1" "0,1"
newline
bitfld.long 0x8 0. "EPWM_TB_CLKEN_CLR_EPWM0_TB_CLKEN_PROXY,Writing One Deactivates Timebase Clock of EPWM0" "0,1"
group.long 0x6140++0x23
line.long 0x0 "CFG0_EPWM0_CTRL_PROXY,"
bitfld.long 0x0 8.--10. "EPWM0_CTRL_SYNCIN_SEL_PROXY,Selects the source of the EPWM0 synchronization input" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4. "EPWM0_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x4 "CFG0_EPWM1_CTRL_PROXY,"
bitfld.long 0x4 4. "EPWM1_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x8 "CFG0_EPWM2_CTRL_PROXY,"
bitfld.long 0x8 4. "EPWM2_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "0,1"
line.long 0xC "CFG0_EPWM3_CTRL_PROXY,"
bitfld.long 0xC 8.--10. "EPWM3_CTRL_SYNCIN_SEL_PROXY,Selects the source of the EPWM3 synchronization input" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 4. "EPWM3_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x10 "CFG0_EPWM4_CTRL_PROXY,"
bitfld.long 0x10 4. "EPWM4_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x14 "CFG0_EPWM5_CTRL_PROXY,"
bitfld.long 0x14 4. "EPWM5_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x18 "CFG0_EPWM6_CTRL_PROXY,"
bitfld.long 0x18 8.--10. "EPWM6_CTRL_SYNCIN_SEL_PROXY,Selects the source of the EPWM6 synchronization input" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 4. "EPWM6_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x1C "CFG0_EPWM7_CTRL_PROXY,"
bitfld.long 0x1C 4. "EPWM7_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "0,1"
line.long 0x20 "CFG0_EPWM8_CTRL_PROXY,"
bitfld.long 0x20 4. "EPWM8_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "0,1"
group.long 0x6170++0x7
line.long 0x0 "CFG0_SOCA_SEL_PROXY,"
bitfld.long 0x0 0.--1. "SOCA_SEL_SOCA_SEL_PROXY,Selects the SOC A output source" "0,1,2,3"
line.long 0x4 "CFG0_SOCB_SEL_PROXY,"
bitfld.long 0x4 0.--1. "SOCB_SEL_SOCB_SEL_PROXY,Selects the SOC B output source" "0,1,2,3"
group.long 0x6180++0xB
line.long 0x0 "CFG0_EQEP0_CTRL_PROXY,"
hexmask.long.byte 0x0 0.--4. 1. "EQEP0_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP0"
line.long 0x4 "CFG0_EQEP1_CTRL_PROXY,"
hexmask.long.byte 0x4 0.--4. 1. "EQEP1_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP1"
line.long 0x8 "CFG0_EQEP2_CTRL_PROXY,"
hexmask.long.byte 0x8 0.--4. 1. "EQEP2_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP2"
rgroup.long 0x61A0++0x3
line.long 0x0 "CFG0_EQEP_STAT_PROXY,"
bitfld.long 0x0 2. "EQEP_STAT_PHASE_ERR2_PROXY,EQEP2 Phase error status" "0,1"
bitfld.long 0x0 1. "EQEP_STAT_PHASE_ERR1_PROXY,EQEP1 Phase error status" "0,1"
newline
bitfld.long 0x0 0. "EQEP_STAT_PHASE_ERR0_PROXY,EQEP0 Phase error status" "0,1"
group.long 0x61B4++0x3
line.long 0x0 "CFG0_SDIO1_CTRL_PROXY,"
hexmask.long.byte 0x0 0.--4. 1. "SDIO1_CTRL_DRV_STR_PROXY,Selects the SDIO drive strength"
group.long 0x6204++0x3
line.long 0x0 "CFG0_TIMER1_CTRL_PROXY,"
bitfld.long 0x0 8. "TIMER1_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER1 to TIMER0" "0,1"
group.long 0x620C++0x3
line.long 0x0 "CFG0_TIMER3_CTRL_PROXY,"
bitfld.long 0x0 8. "TIMER3_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER3 to TIMER2" "0,1"
group.long 0x6214++0x3
line.long 0x0 "CFG0_TIMER5_CTRL_PROXY,"
bitfld.long 0x0 8. "TIMER5_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER5 to TIMER4" "0,1"
group.long 0x621C++0x3
line.long 0x0 "CFG0_TIMER7_CTRL_PROXY,"
bitfld.long 0x0 8. "TIMER7_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER7 to TIMER6" "0,1"
group.long 0x6224++0x3
line.long 0x0 "CFG0_TIMER9_CTRL_PROXY,"
bitfld.long 0x0 8. "TIMER9_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER9 to TIMER8" "0,1"
group.long 0x622C++0x3
line.long 0x0 "CFG0_TIMER11_CTRL_PROXY,"
bitfld.long 0x0 8. "TIMER11_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER11 to TIMER10" "0,1"
group.long 0x62E0++0x3
line.long 0x0 "CFG0_I2C0_CTRL_PROXY,"
bitfld.long 0x0 0. "I2C0_CTRL_HS_MCS_EN_PROXY,HS Mode controller current source activate." "0,1"
group.long 0x6700++0x3
line.long 0x0 "CFG0_FSS_CTRL_PROXY,"
bitfld.long 0x0 8. "FSS_CTRL_S0_BOOT_SIZE_PROXY,Selects the size of the boot block to be used for the S0 (OSPI0) flash interface" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "FSS_CTRL_S0_BOOT_SEG_PROXY,Selects the boot block to be used for the S0 (OSPI0) flash interface. If the s0_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off or.."
group.long 0x6710++0x3
line.long 0x0 "CFG0_ADC0_CTRL_PROXY,"
bitfld.long 0x0 16. "ADC0_CTRL_GPI_MODE_EN_PROXY,Activates ADC0 data pins to be used as general purpose inputs when set. This signal is tied to the en_dig_test input of MCU_ADC0" "0,1"
hexmask.long.byte 0x0 0.--4. 1. "ADC0_CTRL_TRIG_SEL_PROXY,Selects the source of the ADC hardware event trigger"
rgroup.long 0x6750++0x3
line.long 0x0 "CFG0_DCC_STAT_PROXY,"
bitfld.long 0x0 16. "DCC_STAT_MCU_DCC0_INTR_DONE_PROXY,MCU_DCC0 Done Interrupt Status" "0,1"
bitfld.long 0x0 5. "DCC_STAT_DCC5_INTR_DONE_PROXY,DCC5 Done Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "DCC_STAT_DCC4_INTR_DONE_PROXY,DCC4 Done Interrupt Status" "0,1"
bitfld.long 0x0 3. "DCC_STAT_DCC3_INTR_DONE_PROXY,DCC3 Done Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "DCC_STAT_DCC2_INTR_DONE_PROXY,DCC2 Done Interrupt Status" "0,1"
bitfld.long 0x0 1. "DCC_STAT_DCC1_INTR_DONE_PROXY,DCC1 Done Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "DCC_STAT_DCC0_INTR_DONE_PROXY,DCC0 Done Interrupt Status" "0,1"
group.long 0x7008++0x7
line.long 0x0 "CFG0_LOCK1_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK1_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component"
group.long 0x7100++0x3B
line.long 0x0 "CFG0_CLAIMREG_P1_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0,Claim bits for Partition 1"
line.long 0x4 "CFG0_CLAIMREG_P1_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1,Claim bits for Partition 1"
line.long 0x8 "CFG0_CLAIMREG_P1_R2,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2,Claim bits for Partition 1"
line.long 0xC "CFG0_CLAIMREG_P1_R3,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3,Claim bits for Partition 1"
line.long 0x10 "CFG0_CLAIMREG_P1_R4,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4,Claim bits for Partition 1"
line.long 0x14 "CFG0_CLAIMREG_P1_R5,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5,Claim bits for Partition 1"
line.long 0x18 "CFG0_CLAIMREG_P1_R6,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6,Claim bits for Partition 1"
line.long 0x1C "CFG0_CLAIMREG_P1_R7,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P1_R7,Claim bits for Partition 1"
line.long 0x20 "CFG0_CLAIMREG_P1_R8,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P1_R8,Claim bits for Partition 1"
line.long 0x24 "CFG0_CLAIMREG_P1_R9,"
hexmask.long 0x24 0.--31. 1. "CLAIMREG_P1_R9,Claim bits for Partition 1"
line.long 0x28 "CFG0_CLAIMREG_P1_R10,"
hexmask.long 0x28 0.--31. 1. "CLAIMREG_P1_R10,Claim bits for Partition 1"
line.long 0x2C "CFG0_CLAIMREG_P1_R11,"
hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P1_R11,Claim bits for Partition 1"
line.long 0x30 "CFG0_CLAIMREG_P1_R12,"
hexmask.long 0x30 0.--31. 1. "CLAIMREG_P1_R12,Claim bits for Partition 1"
line.long 0x34 "CFG0_CLAIMREG_P1_R13,"
hexmask.long 0x34 0.--31. 1. "CLAIMREG_P1_R13,Claim bits for Partition 1"
line.long 0x38 "CFG0_CLAIMREG_P1_R14,"
hexmask.long 0x38 0.--31. 1. "CLAIMREG_P1_R14,Claim bits for Partition 1"
group.long 0x8000++0x3
line.long 0x0 "CFG0_OBSCLK0_CTRL,"
bitfld.long 0x0 16. "OBSCLK0_CTRL_CLK_DIV_LD,Load the output divider value" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "OBSCLK0_CTRL_CLK_DIV,OBSCLK0 output divider"
newline
hexmask.long.byte 0x0 0.--3. 1. "OBSCLK0_CTRL_CLK_SEL,OBSCLK0 clock source selection."
group.long 0x8010++0x3
line.long 0x0 "CFG0_CLKOUT_CTRL,"
bitfld.long 0x0 4. "CLKOUT_CTRL_CLK_EN,When set  activates CLKOUT output" "0,1"
bitfld.long 0x0 0. "CLKOUT_CTRL_CLK_SEL,Selects CLKOUT clock source" "0,1"
group.long 0x8030++0x3
line.long 0x0 "CFG0_GTC_CLKSEL,"
bitfld.long 0x0 0.--2. "GTC_CLKSEL_CLK_SEL,Selects the GTC timebase clock source" "0,1,2,3,4,5,6,7"
group.long 0x803C++0xB
line.long 0x0 "CFG0_EFUSE_CLKSEL,"
bitfld.long 0x0 0. "EFUSE_CLKSEL_CLK_SEL,Selects the clock source" "0,1"
line.long 0x4 "CFG0_ICSSG0_CLKSEL,"
bitfld.long 0x4 16.--18. "ICSSG0_CLKSEL_IEP_CLKSEL,Selects the ICSSG0 IEP clock source" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "ICSSG0_CLKSEL_CORE_CLKSEL,Selects the ICSSG0 functional clock source" "0,1"
line.long 0x8 "CFG0_ICSSG1_CLKSEL,"
bitfld.long 0x8 16.--18. "ICSSG1_CLKSEL_IEP_CLKSEL,Selects the ICSSG1 IEP clock source" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 0. "ICSSG1_CLKSEL_CORE_CLKSEL,Selects the ICSSG1 functional clock source" "0,1"
group.long 0x8060++0xB
line.long 0x0 "CFG0_MAIN_PLL0_CLKSEL,"
bitfld.long 0x0 31. "MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x0 23. "MAIN_PLL0_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset." "0,1"
line.long 0x4 "CFG0_MAIN_PLL1_CLKSEL,"
bitfld.long 0x4 31. "MAIN_PLL1_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x4 23. "MAIN_PLL1_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset." "0,1"
line.long 0x8 "CFG0_MAIN_PLL2_CLKSEL,"
bitfld.long 0x8 31. "MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x8 23. "MAIN_PLL2_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset." "0,1"
group.long 0x8080++0x3
line.long 0x0 "CFG0_MAIN_PLL8_CLKSEL,"
bitfld.long 0x0 31. "MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x0 23. "MAIN_PLL8_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset." "0,1"
group.long 0x8090++0x3
line.long 0x0 "CFG0_MAIN_PLL12_CLKSEL,"
bitfld.long 0x0 31. "MAIN_PLL12_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x0 23. "MAIN_PLL12_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset." "0,1"
group.long 0x8098++0x3
line.long 0x0 "CFG0_MAIN_PLL14_CLKSEL,"
bitfld.long 0x0 31. "MAIN_PLL14_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x0 23. "MAIN_PLL14_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset." "0,1"
group.long 0x8120++0x3
line.long 0x0 "CFG0_PCIE0_CLKSEL,"
bitfld.long 0x0 0.--2. "PCIE0_CLKSEL_CPTS_CLKSEL,Selects the clock source for the PCIE0 Common Platform Time Stamp module" "0,1,2,3,4,5,6,7"
group.long 0x8140++0x3
line.long 0x0 "CFG0_CPSW_CLKSEL,"
hexmask.long.byte 0x0 0.--3. 1. "CPSW_CLKSEL_CPTS_CLKSEL,Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module"
group.long 0x8150++0x3
line.long 0x0 "CFG0_CPTS_CLKSEL,"
bitfld.long 0x0 0.--2. "CPTS_CLKSEL_CPTS_CLKSEL,Selects the clock source for the SoC Common Platform Time Stamp module" "0,1,2,3,4,5,6,7"
group.long 0x8160++0x3
line.long 0x0 "CFG0_EMMC0_CLKSEL,"
bitfld.long 0x0 0. "EMMC0_CLKSEL_EMMCSD0_REFCLK_SEL,eMMC XIN_CLK selection" "0,1"
group.long 0x8168++0x3
line.long 0x0 "CFG0_EMMC1_CLKSEL,"
bitfld.long 0x0 16. "EMMC1_CLKSEL_EMMCSD1_IO_CLKLB_SEL,eMMC IO Clock Selection:" "0,1"
bitfld.long 0x0 0. "EMMC1_CLKSEL_EMMCSD1_REFCLK_SEL,eMMC XIN_CLK selection" "0,1"
group.long 0x8180++0x3
line.long 0x0 "CFG0_GPMC_CLKSEL,"
bitfld.long 0x0 0. "GPMC_CLKSEL_CLK_SEL,Selects the GPMC clock source" "0,1"
group.long 0x8190++0x3
line.long 0x0 "CFG0_USB0_CLKSEL,"
bitfld.long 0x0 0. "USB0_CLKSEL_REFCLK_SEL,Selects the clock source for the USB0 ref_clk." "0,1"
group.long 0x81B0++0x2F
line.long 0x0 "CFG0_TIMER0_CLKSEL,"
hexmask.long.byte 0x0 0.--3. 1. "TIMER0_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x4 "CFG0_TIMER1_CLKSEL,"
hexmask.long.byte 0x4 0.--3. 1. "TIMER1_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x8 "CFG0_TIMER2_CLKSEL,"
hexmask.long.byte 0x8 0.--3. 1. "TIMER2_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0xC "CFG0_TIMER3_CLKSEL,"
hexmask.long.byte 0xC 0.--3. 1. "TIMER3_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x10 "CFG0_TIMER4_CLKSEL,"
hexmask.long.byte 0x10 0.--3. 1. "TIMER4_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x14 "CFG0_TIMER5_CLKSEL,"
hexmask.long.byte 0x14 0.--3. 1. "TIMER5_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x18 "CFG0_TIMER6_CLKSEL,"
hexmask.long.byte 0x18 0.--3. 1. "TIMER6_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x1C "CFG0_TIMER7_CLKSEL,"
hexmask.long.byte 0x1C 0.--3. 1. "TIMER7_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x20 "CFG0_TIMER8_CLKSEL,"
hexmask.long.byte 0x20 0.--3. 1. "TIMER8_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x24 "CFG0_TIMER9_CLKSEL,"
hexmask.long.byte 0x24 0.--3. 1. "TIMER9_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x28 "CFG0_TIMER10_CLKSEL,"
hexmask.long.byte 0x28 0.--3. 1. "TIMER10_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x2C "CFG0_TIMER11_CLKSEL,"
hexmask.long.byte 0x2C 0.--3. 1. "TIMER11_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
group.long 0x8200++0x13
line.long 0x0 "CFG0_SPI0_CLKSEL,"
bitfld.long 0x0 16. "SPI0_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "0,1"
line.long 0x4 "CFG0_SPI1_CLKSEL,"
bitfld.long 0x4 16. "SPI1_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "0,1"
line.long 0x8 "CFG0_SPI2_CLKSEL,"
bitfld.long 0x8 16. "SPI2_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "0,1"
line.long 0xC "CFG0_SPI3_CLKSEL,"
bitfld.long 0xC 16. "SPI3_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "0,1"
line.long 0x10 "CFG0_SPI4_CLKSEL,"
bitfld.long 0x10 16. "SPI4_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "0,1"
group.long 0x8240++0x1B
line.long 0x0 "CFG0_USART0_CLK_CTRL,"
bitfld.long 0x0 16. "USART0_CLK_CTRL_CLK_DIV_LD,Load the output divider value" "0,1"
bitfld.long 0x0 0.--1. "USART0_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0x4 "CFG0_USART1_CLK_CTRL,"
bitfld.long 0x4 16. "USART1_CLK_CTRL_CLK_DIV_LD,Load the output divider value" "0,1"
bitfld.long 0x4 0.--1. "USART1_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0x8 "CFG0_USART2_CLK_CTRL,"
bitfld.long 0x8 16. "USART2_CLK_CTRL_CLK_DIV_LD,Load the output divider value" "0,1"
bitfld.long 0x8 0.--1. "USART2_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0xC "CFG0_USART3_CLK_CTRL,"
bitfld.long 0xC 16. "USART3_CLK_CTRL_CLK_DIV_LD,Load the output divider value" "0,1"
bitfld.long 0xC 0.--1. "USART3_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0x10 "CFG0_USART4_CLK_CTRL,"
bitfld.long 0x10 16. "USART4_CLK_CTRL_CLK_DIV_LD,Load the output divider value" "0,1"
bitfld.long 0x10 0.--1. "USART4_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0x14 "CFG0_USART5_CLK_CTRL,"
bitfld.long 0x14 16. "USART5_CLK_CTRL_CLK_DIV_LD,Load the output divider value" "0,1"
bitfld.long 0x14 0.--1. "USART5_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0x18 "CFG0_USART6_CLK_CTRL,"
bitfld.long 0x18 16. "USART6_CLK_CTRL_CLK_DIV_LD,Load the output divider value" "0,1"
bitfld.long 0x18 0.--1. "USART6_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
group.long 0x8280++0x1B
line.long 0x0 "CFG0_USART0_CLKSEL,"
bitfld.long 0x0 0. "USART0_CLKSEL_CLK_SEL,Selects the clock source for UART0:" "0,1"
line.long 0x4 "CFG0_USART1_CLKSEL,"
bitfld.long 0x4 0. "USART1_CLKSEL_CLK_SEL,Selects the clock source for UART1:" "0,1"
line.long 0x8 "CFG0_USART2_CLKSEL,"
bitfld.long 0x8 0. "USART2_CLKSEL_CLK_SEL,Selects the clock source for UART2:" "0,1"
line.long 0xC "CFG0_USART3_CLKSEL,"
bitfld.long 0xC 0. "USART3_CLKSEL_CLK_SEL,Selects the clock source for UART3:" "0,1"
line.long 0x10 "CFG0_USART4_CLKSEL,"
bitfld.long 0x10 0. "USART4_CLKSEL_CLK_SEL,Selects the clock source for UART4:" "0,1"
line.long 0x14 "CFG0_USART5_CLKSEL,"
bitfld.long 0x14 0. "USART5_CLKSEL_CLK_SEL,Selects the clock source for UART5:" "0,1"
line.long 0x18 "CFG0_USART6_CLKSEL,"
bitfld.long 0x18 0. "USART6_CLKSEL_CLK_SEL,Selects the clock source for UART6:" "0,1"
group.long 0x8380++0x7
line.long 0x0 "CFG0_WWD0_CLKSEL,"
bitfld.long 0x0 31. "WWD0_CLKSEL_WRTLOCK,When set  locks WWD0_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0x0 0.--1. "WWD0_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
line.long 0x4 "CFG0_WWD1_CLKSEL,"
bitfld.long 0x4 31. "WWD1_CLKSEL_WRTLOCK,When set  locks WWD1_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0x4 0.--1. "WWD1_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
group.long 0x83A0++0xF
line.long 0x0 "CFG0_WWD8_CLKSEL,"
bitfld.long 0x0 31. "WWD8_CLKSEL_WRTLOCK,When set  locks WWD8_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0x0 0.--1. "WWD8_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
line.long 0x4 "CFG0_WWD9_CLKSEL,"
bitfld.long 0x4 31. "WWD9_CLKSEL_WRTLOCK,When set  locks WWD9_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0x4 0.--1. "WWD9_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
line.long 0x8 "CFG0_WWD10_CLKSEL,"
bitfld.long 0x8 31. "WWD10_CLKSEL_WRTLOCK,When set  locks WWD10_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0x8 0.--1. "WWD10_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
line.long 0xC "CFG0_WWD11_CLKSEL,"
bitfld.long 0xC 31. "WWD11_CLKSEL_WRTLOCK,When set  locks WWD11_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0xC 0.--1. "WWD11_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
group.long 0x8400++0x3
line.long 0x0 "CFG0_SERDES0_CLKSEL,"
bitfld.long 0x0 0.--1. "SERDES0_CLKSEL_CORE_REFCLK_SEL,Selects the source for the core_refclk input" "0,1,2,3"
group.long 0x8480++0x7
line.long 0x0 "CFG0_MCAN0_CLKSEL,"
bitfld.long 0x0 0.--1. "MCAN0_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x4 "CFG0_MCAN1_CLKSEL,"
bitfld.long 0x4 0.--1. "MCAN1_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
group.long 0x8500++0x3
line.long 0x0 "CFG0_OSPI0_CLKSEL,"
bitfld.long 0x0 4. "OSPI0_CLKSEL_LOOPCLK_SEL,OBSPI0 Loopback clock source" "0,1"
bitfld.long 0x0 0. "OSPI0_CLKSEL_CLK_SEL,OSPI0 reference clock selection" "0,1"
group.long 0x8510++0x3
line.long 0x0 "CFG0_ADC0_CLKSEL,"
bitfld.long 0x0 0.--1. "ADC0_CLKSEL_CLK_SEL,Selects the sampling clock source for ADC0" "0,1,2,3"
group.long 0x9008++0x7
line.long 0x0 "CFG0_LOCK2_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK2_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1,- KICK1 component"
rgroup.long 0x9100++0x2B
line.long 0x0 "CFG0_CLAIMREG_P2_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0_READONLY,Claim bits for Partition 2"
line.long 0x4 "CFG0_CLAIMREG_P2_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1_READONLY,Claim bits for Partition 2"
line.long 0x8 "CFG0_CLAIMREG_P2_R2_READONLY,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P2_R2_READONLY,Claim bits for Partition 2"
line.long 0xC "CFG0_CLAIMREG_P2_R3_READONLY,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P2_R3_READONLY,Claim bits for Partition 2"
line.long 0x10 "CFG0_CLAIMREG_P2_R4_READONLY,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P2_R4_READONLY,Claim bits for Partition 2"
line.long 0x14 "CFG0_CLAIMREG_P2_R5_READONLY,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P2_R5_READONLY,Claim bits for Partition 2"
line.long 0x18 "CFG0_CLAIMREG_P2_R6_READONLY,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P2_R6_READONLY,Claim bits for Partition 2"
line.long 0x1C "CFG0_CLAIMREG_P2_R7_READONLY,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P2_R7_READONLY,Claim bits for Partition 2"
line.long 0x20 "CFG0_CLAIMREG_P2_R8_READONLY,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P2_R8_READONLY,Claim bits for Partition 2"
line.long 0x24 "CFG0_CLAIMREG_P2_R9_READONLY,"
hexmask.long 0x24 0.--31. 1. "CLAIMREG_P2_R9_READONLY,Claim bits for Partition 2"
line.long 0x28 "CFG0_CLAIMREG_P2_R10_READONLY,"
hexmask.long 0x28 0.--31. 1. "CLAIMREG_P2_R10_READONLY,Claim bits for Partition 2"
group.long 0xA000++0x3
line.long 0x0 "CFG0_OBSCLK0_CTRL_PROXY,"
bitfld.long 0x0 16. "OBSCLK0_CTRL_CLK_DIV_LD_PROXY,Load the output divider value" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "OBSCLK0_CTRL_CLK_DIV_PROXY,OBSCLK0 output divider"
newline
hexmask.long.byte 0x0 0.--3. 1. "OBSCLK0_CTRL_CLK_SEL_PROXY,OBSCLK0 clock source selection."
group.long 0xA010++0x3
line.long 0x0 "CFG0_CLKOUT_CTRL_PROXY,"
bitfld.long 0x0 4. "CLKOUT_CTRL_CLK_EN_PROXY,When set  activates CLKOUT output" "0,1"
bitfld.long 0x0 0. "CLKOUT_CTRL_CLK_SEL_PROXY,Selects CLKOUT clock source" "0,1"
group.long 0xA030++0x3
line.long 0x0 "CFG0_GTC_CLKSEL_PROXY,"
bitfld.long 0x0 0.--2. "GTC_CLKSEL_CLK_SEL_PROXY,Selects the GTC timebase clock source" "0,1,2,3,4,5,6,7"
group.long 0xA03C++0xB
line.long 0x0 "CFG0_EFUSE_CLKSEL_PROXY,"
bitfld.long 0x0 0. "EFUSE_CLKSEL_CLK_SEL_PROXY,Selects the clock source" "0,1"
line.long 0x4 "CFG0_ICSSG0_CLKSEL_PROXY,"
bitfld.long 0x4 16.--18. "ICSSG0_CLKSEL_IEP_CLKSEL_PROXY,Selects the ICSSG0 IEP clock source" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "ICSSG0_CLKSEL_CORE_CLKSEL_PROXY,Selects the ICSSG0 functional clock source" "0,1"
line.long 0x8 "CFG0_ICSSG1_CLKSEL_PROXY,"
bitfld.long 0x8 16.--18. "ICSSG1_CLKSEL_IEP_CLKSEL_PROXY,Selects the ICSSG1 IEP clock source" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 0. "ICSSG1_CLKSEL_CORE_CLKSEL_PROXY,Selects the ICSSG1 functional clock source" "0,1"
group.long 0xA060++0xB
line.long 0x0 "CFG0_MAIN_PLL0_CLKSEL_PROXY,"
bitfld.long 0x0 31. "MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x0 23. "MAIN_PLL0_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset." "0,1"
line.long 0x4 "CFG0_MAIN_PLL1_CLKSEL_PROXY,"
bitfld.long 0x4 31. "MAIN_PLL1_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x4 23. "MAIN_PLL1_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset." "0,1"
line.long 0x8 "CFG0_MAIN_PLL2_CLKSEL_PROXY,"
bitfld.long 0x8 31. "MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x8 23. "MAIN_PLL2_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset." "0,1"
group.long 0xA080++0x3
line.long 0x0 "CFG0_MAIN_PLL8_CLKSEL_PROXY,"
bitfld.long 0x0 31. "MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x0 23. "MAIN_PLL8_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset." "0,1"
group.long 0xA090++0x3
line.long 0x0 "CFG0_MAIN_PLL12_CLKSEL_PROXY,"
bitfld.long 0x0 31. "MAIN_PLL12_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x0 23. "MAIN_PLL12_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset." "0,1"
group.long 0xA098++0x3
line.long 0x0 "CFG0_MAIN_PLL14_CLKSEL_PROXY,"
bitfld.long 0x0 31. "MAIN_PLL14_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x0 23. "MAIN_PLL14_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset." "0,1"
group.long 0xA120++0x3
line.long 0x0 "CFG0_PCIE0_CLKSEL_PROXY,"
bitfld.long 0x0 0.--2. "PCIE0_CLKSEL_CPTS_CLKSEL_PROXY,Selects the clock source for the PCIE0 Common Platform Time Stamp module" "0,1,2,3,4,5,6,7"
group.long 0xA140++0x3
line.long 0x0 "CFG0_CPSW_CLKSEL_PROXY,"
hexmask.long.byte 0x0 0.--3. 1. "CPSW_CLKSEL_CPTS_CLKSEL_PROXY,Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module"
group.long 0xA150++0x3
line.long 0x0 "CFG0_CPTS_CLKSEL_PROXY,"
bitfld.long 0x0 0.--2. "CPTS_CLKSEL_CPTS_CLKSEL_PROXY,Selects the clock source for the SoC Common Platform Time Stamp module" "0,1,2,3,4,5,6,7"
group.long 0xA160++0x3
line.long 0x0 "CFG0_EMMC0_CLKSEL_PROXY,"
bitfld.long 0x0 0. "EMMC0_CLKSEL_EMMCSD0_REFCLK_SEL_PROXY,eMMC XIN_CLK selection" "0,1"
group.long 0xA168++0x3
line.long 0x0 "CFG0_EMMC1_CLKSEL_PROXY,"
bitfld.long 0x0 16. "EMMC1_CLKSEL_EMMCSD1_IO_CLKLB_SEL_PROXY,eMMC IO Clock Selection:" "0,1"
bitfld.long 0x0 0. "EMMC1_CLKSEL_EMMCSD1_REFCLK_SEL_PROXY,eMMC XIN_CLK selection" "0,1"
group.long 0xA180++0x3
line.long 0x0 "CFG0_GPMC_CLKSEL_PROXY,"
bitfld.long 0x0 0. "GPMC_CLKSEL_CLK_SEL_PROXY,Selects the GPMC clock source" "0,1"
group.long 0xA190++0x3
line.long 0x0 "CFG0_USB0_CLKSEL_PROXY,"
bitfld.long 0x0 0. "USB0_CLKSEL_REFCLK_SEL_PROXY,Selects the clock source for the USB0 ref_clk." "0,1"
group.long 0xA1B0++0x2F
line.long 0x0 "CFG0_TIMER0_CLKSEL_PROXY,"
hexmask.long.byte 0x0 0.--3. 1. "TIMER0_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x4 "CFG0_TIMER1_CLKSEL_PROXY,"
hexmask.long.byte 0x4 0.--3. 1. "TIMER1_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x8 "CFG0_TIMER2_CLKSEL_PROXY,"
hexmask.long.byte 0x8 0.--3. 1. "TIMER2_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0xC "CFG0_TIMER3_CLKSEL_PROXY,"
hexmask.long.byte 0xC 0.--3. 1. "TIMER3_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x10 "CFG0_TIMER4_CLKSEL_PROXY,"
hexmask.long.byte 0x10 0.--3. 1. "TIMER4_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x14 "CFG0_TIMER5_CLKSEL_PROXY,"
hexmask.long.byte 0x14 0.--3. 1. "TIMER5_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x18 "CFG0_TIMER6_CLKSEL_PROXY,"
hexmask.long.byte 0x18 0.--3. 1. "TIMER6_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x1C "CFG0_TIMER7_CLKSEL_PROXY,"
hexmask.long.byte 0x1C 0.--3. 1. "TIMER7_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x20 "CFG0_TIMER8_CLKSEL_PROXY,"
hexmask.long.byte 0x20 0.--3. 1. "TIMER8_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x24 "CFG0_TIMER9_CLKSEL_PROXY,"
hexmask.long.byte 0x24 0.--3. 1. "TIMER9_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x28 "CFG0_TIMER10_CLKSEL_PROXY,"
hexmask.long.byte 0x28 0.--3. 1. "TIMER10_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
line.long 0x2C "CFG0_TIMER11_CLKSEL_PROXY,"
hexmask.long.byte 0x2C 0.--3. 1. "TIMER11_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)"
group.long 0xA200++0x13
line.long 0x0 "CFG0_SPI0_CLKSEL_PROXY,"
bitfld.long 0x0 16. "SPI0_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "0,1"
line.long 0x4 "CFG0_SPI1_CLKSEL_PROXY,"
bitfld.long 0x4 16. "SPI1_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "0,1"
line.long 0x8 "CFG0_SPI2_CLKSEL_PROXY,"
bitfld.long 0x8 16. "SPI2_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "0,1"
line.long 0xC "CFG0_SPI3_CLKSEL_PROXY,"
bitfld.long 0xC 16. "SPI3_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "0,1"
line.long 0x10 "CFG0_SPI4_CLKSEL_PROXY,"
bitfld.long 0x10 16. "SPI4_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "0,1"
group.long 0xA240++0x1B
line.long 0x0 "CFG0_USART0_CLK_CTRL_PROXY,"
bitfld.long 0x0 16. "USART0_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value" "0,1"
bitfld.long 0x0 0.--1. "USART0_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0x4 "CFG0_USART1_CLK_CTRL_PROXY,"
bitfld.long 0x4 16. "USART1_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value" "0,1"
bitfld.long 0x4 0.--1. "USART1_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0x8 "CFG0_USART2_CLK_CTRL_PROXY,"
bitfld.long 0x8 16. "USART2_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value" "0,1"
bitfld.long 0x8 0.--1. "USART2_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0xC "CFG0_USART3_CLK_CTRL_PROXY,"
bitfld.long 0xC 16. "USART3_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value" "0,1"
bitfld.long 0xC 0.--1. "USART3_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0x10 "CFG0_USART4_CLK_CTRL_PROXY,"
bitfld.long 0x10 16. "USART4_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value" "0,1"
bitfld.long 0x10 0.--1. "USART4_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0x14 "CFG0_USART5_CLK_CTRL_PROXY,"
bitfld.long 0x14 16. "USART5_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value" "0,1"
bitfld.long 0x14 0.--1. "USART5_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
line.long 0x18 "CFG0_USART6_CLK_CTRL_PROXY,"
bitfld.long 0x18 16. "USART6_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value" "0,1"
bitfld.long 0x18 0.--1. "USART6_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3"
group.long 0xA280++0x1B
line.long 0x0 "CFG0_USART0_CLKSEL_PROXY,"
bitfld.long 0x0 0. "USART0_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART0:" "0,1"
line.long 0x4 "CFG0_USART1_CLKSEL_PROXY,"
bitfld.long 0x4 0. "USART1_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART1:" "0,1"
line.long 0x8 "CFG0_USART2_CLKSEL_PROXY,"
bitfld.long 0x8 0. "USART2_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART2:" "0,1"
line.long 0xC "CFG0_USART3_CLKSEL_PROXY,"
bitfld.long 0xC 0. "USART3_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART3:" "0,1"
line.long 0x10 "CFG0_USART4_CLKSEL_PROXY,"
bitfld.long 0x10 0. "USART4_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART4:" "0,1"
line.long 0x14 "CFG0_USART5_CLKSEL_PROXY,"
bitfld.long 0x14 0. "USART5_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART5:" "0,1"
line.long 0x18 "CFG0_USART6_CLKSEL_PROXY,"
bitfld.long 0x18 0. "USART6_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART6:" "0,1"
group.long 0xA380++0x7
line.long 0x0 "CFG0_WWD0_CLKSEL_PROXY,"
bitfld.long 0x0 31. "WWD0_CLKSEL_WRTLOCK_PROXY,When set  locks WWD0_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0x0 0.--1. "WWD0_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
line.long 0x4 "CFG0_WWD1_CLKSEL_PROXY,"
bitfld.long 0x4 31. "WWD1_CLKSEL_WRTLOCK_PROXY,When set  locks WWD1_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0x4 0.--1. "WWD1_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
group.long 0xA3A0++0xF
line.long 0x0 "CFG0_WWD8_CLKSEL_PROXY,"
bitfld.long 0x0 31. "WWD8_CLKSEL_WRTLOCK_PROXY,When set  locks WWD8_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0x0 0.--1. "WWD8_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
line.long 0x4 "CFG0_WWD9_CLKSEL_PROXY,"
bitfld.long 0x4 31. "WWD9_CLKSEL_WRTLOCK_PROXY,When set  locks WWD9_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0x4 0.--1. "WWD9_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
line.long 0x8 "CFG0_WWD10_CLKSEL_PROXY,"
bitfld.long 0x8 31. "WWD10_CLKSEL_WRTLOCK_PROXY,When set  locks WWD10_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0x8 0.--1. "WWD10_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
line.long 0xC "CFG0_WWD11_CLKSEL_PROXY,"
bitfld.long 0xC 31. "WWD11_CLKSEL_WRTLOCK_PROXY,When set  locks WWD11_CLKSEL from further writes until the next module reset." "0,1"
bitfld.long 0xC 0.--1. "WWD11_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
group.long 0xA400++0x3
line.long 0x0 "CFG0_SERDES0_CLKSEL_PROXY,"
bitfld.long 0x0 0.--1. "SERDES0_CLKSEL_CORE_REFCLK_SEL_PROXY,Selects the source for the core_refclk input" "0,1,2,3"
group.long 0xA480++0x7
line.long 0x0 "CFG0_MCAN0_CLKSEL_PROXY,"
bitfld.long 0x0 0.--1. "MCAN0_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x4 "CFG0_MCAN1_CLKSEL_PROXY,"
bitfld.long 0x4 0.--1. "MCAN1_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection" "0,1,2,3"
group.long 0xA500++0x3
line.long 0x0 "CFG0_OSPI0_CLKSEL_PROXY,"
bitfld.long 0x0 4. "OSPI0_CLKSEL_LOOPCLK_SEL_PROXY,OBSPI0 Loopback clock source" "0,1"
bitfld.long 0x0 0. "OSPI0_CLKSEL_CLK_SEL_PROXY,OSPI0 reference clock selection" "0,1"
group.long 0xA510++0x3
line.long 0x0 "CFG0_ADC0_CLKSEL_PROXY,"
bitfld.long 0x0 0.--1. "ADC0_CLKSEL_CLK_SEL_PROXY,Selects the sampling clock source for ADC0" "0,1,2,3"
group.long 0xB008++0x7
line.long 0x0 "CFG0_LOCK2_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK2_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1_PROXY,- KICK1 component"
group.long 0xB100++0x2B
line.long 0x0 "CFG0_CLAIMREG_P2_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0,Claim bits for Partition 2"
line.long 0x4 "CFG0_CLAIMREG_P2_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1,Claim bits for Partition 2"
line.long 0x8 "CFG0_CLAIMREG_P2_R2,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P2_R2,Claim bits for Partition 2"
line.long 0xC "CFG0_CLAIMREG_P2_R3,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P2_R3,Claim bits for Partition 2"
line.long 0x10 "CFG0_CLAIMREG_P2_R4,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P2_R4,Claim bits for Partition 2"
line.long 0x14 "CFG0_CLAIMREG_P2_R5,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P2_R5,Claim bits for Partition 2"
line.long 0x18 "CFG0_CLAIMREG_P2_R6,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P2_R6,Claim bits for Partition 2"
line.long 0x1C "CFG0_CLAIMREG_P2_R7,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P2_R7,Claim bits for Partition 2"
line.long 0x20 "CFG0_CLAIMREG_P2_R8,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P2_R8,Claim bits for Partition 2"
line.long 0x24 "CFG0_CLAIMREG_P2_R9,"
hexmask.long 0x24 0.--31. 1. "CLAIMREG_P2_R9,Claim bits for Partition 2"
line.long 0x28 "CFG0_CLAIMREG_P2_R10,"
hexmask.long 0x28 0.--31. 1. "CLAIMREG_P2_R10,Claim bits for Partition 2"
rgroup.long 0xC320++0x3
line.long 0x0 "CFG0_FUSE_CRC_STAT,"
bitfld.long 0x0 7. "FUSE_CRC_STAT_CRC_ERR_7,Indicates eFuse CRC error on chain 7" "0,1"
bitfld.long 0x0 6. "FUSE_CRC_STAT_CRC_ERR_6,Indicates eFuse CRC error on chain 6" "0,1"
newline
bitfld.long 0x0 5. "FUSE_CRC_STAT_CRC_ERR_5,Indicates eFuse CRC error on chain 5" "0,1"
bitfld.long 0x0 4. "FUSE_CRC_STAT_CRC_ERR_4,Indicates eFuse CRC error on chain 4" "0,1"
newline
bitfld.long 0x0 3. "FUSE_CRC_STAT_CRC_ERR_3,Indicates eFuse CRC error on chain 3" "0,1"
bitfld.long 0x0 2. "FUSE_CRC_STAT_CRC_ERR_2,Indicates eFuse CRC error on chain 2" "0,1"
newline
bitfld.long 0x0 1. "FUSE_CRC_STAT_CRC_ERR_1,Indicates eFuse CRC error on chain 1" "0,1"
group.long 0xC400++0x3
line.long 0x0 "CFG0_PBIST_EN,"
bitfld.long 0x0 8. "PBIST_EN_PCIE0,Activates PBIST Access to PCIE0 Memories" "0,1"
bitfld.long 0x0 4. "PBIST_EN_USB0,Activates PBIST Access to USB0 Memories" "0,1"
newline
bitfld.long 0x0 1. "PBIST_EN_EMMC1,Activates PBIST Access to MMC1 Memories" "0,1"
bitfld.long 0x0 0. "PBIST_EN_EMMC0,Activates PBIST Access to MMC0 Memories" "0,1"
group.long 0xD008++0x7
line.long 0x0 "CFG0_LOCK3_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK3_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1,- KICK1 component"
rgroup.long 0xD100++0x23
line.long 0x0 "CFG0_CLAIMREG_P3_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0_READONLY,Claim bits for Partition 3"
line.long 0x4 "CFG0_CLAIMREG_P3_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P3_R1_READONLY,Claim bits for Partition 3"
line.long 0x8 "CFG0_CLAIMREG_P3_R2_READONLY,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P3_R2_READONLY,Claim bits for Partition 3"
line.long 0xC "CFG0_CLAIMREG_P3_R3_READONLY,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P3_R3_READONLY,Claim bits for Partition 3"
line.long 0x10 "CFG0_CLAIMREG_P3_R4_READONLY,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P3_R4_READONLY,Claim bits for Partition 3"
line.long 0x14 "CFG0_CLAIMREG_P3_R5_READONLY,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P3_R5_READONLY,Claim bits for Partition 3"
line.long 0x18 "CFG0_CLAIMREG_P3_R6_READONLY,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P3_R6_READONLY,Claim bits for Partition 3"
line.long 0x1C "CFG0_CLAIMREG_P3_R7_READONLY,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P3_R7_READONLY,Claim bits for Partition 3"
line.long 0x20 "CFG0_CLAIMREG_P3_R8_READONLY,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P3_R8_READONLY,Claim bits for Partition 3"
rgroup.long 0xE320++0x3
line.long 0x0 "CFG0_FUSE_CRC_STAT_PROXY,"
bitfld.long 0x0 7. "FUSE_CRC_STAT_CRC_ERR_7_PROXY,Indicates eFuse CRC error on chain 7" "0,1"
bitfld.long 0x0 6. "FUSE_CRC_STAT_CRC_ERR_6_PROXY,Indicates eFuse CRC error on chain 6" "0,1"
newline
bitfld.long 0x0 5. "FUSE_CRC_STAT_CRC_ERR_5_PROXY,Indicates eFuse CRC error on chain 5" "0,1"
bitfld.long 0x0 4. "FUSE_CRC_STAT_CRC_ERR_4_PROXY,Indicates eFuse CRC error on chain 4" "0,1"
newline
bitfld.long 0x0 3. "FUSE_CRC_STAT_CRC_ERR_3_PROXY,Indicates eFuse CRC error on chain 3" "0,1"
bitfld.long 0x0 2. "FUSE_CRC_STAT_CRC_ERR_2_PROXY,Indicates eFuse CRC error on chain 2" "0,1"
newline
bitfld.long 0x0 1. "FUSE_CRC_STAT_CRC_ERR_1_PROXY,Indicates eFuse CRC error on chain 1" "0,1"
group.long 0xE400++0x3
line.long 0x0 "CFG0_PBIST_EN_PROXY,"
bitfld.long 0x0 8. "PBIST_EN_PCIE0_PROXY,Activates PBIST Access to PCIE0 Memories" "0,1"
bitfld.long 0x0 4. "PBIST_EN_USB0_PROXY,Activates PBIST Access to USB0 Memories" "0,1"
newline
bitfld.long 0x0 1. "PBIST_EN_EMMC1_PROXY,Activates PBIST Access to MMC1 Memories" "0,1"
bitfld.long 0x0 0. "PBIST_EN_EMMC0_PROXY,Activates PBIST Access to MMC0 Memories" "0,1"
group.long 0xF008++0x7
line.long 0x0 "CFG0_LOCK3_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK3_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1_PROXY,- KICK1 component"
group.long 0xF100++0x23
line.long 0x0 "CFG0_CLAIMREG_P3_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0,Claim bits for Partition 3"
line.long 0x4 "CFG0_CLAIMREG_P3_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P3_R1,Claim bits for Partition 3"
line.long 0x8 "CFG0_CLAIMREG_P3_R2,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P3_R2,Claim bits for Partition 3"
line.long 0xC "CFG0_CLAIMREG_P3_R3,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P3_R3,Claim bits for Partition 3"
line.long 0x10 "CFG0_CLAIMREG_P3_R4,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P3_R4,Claim bits for Partition 3"
line.long 0x14 "CFG0_CLAIMREG_P3_R5,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P3_R5,Claim bits for Partition 3"
line.long 0x18 "CFG0_CLAIMREG_P3_R6,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P3_R6,Claim bits for Partition 3"
line.long 0x1C "CFG0_CLAIMREG_P3_R7,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P3_R7,Claim bits for Partition 3"
line.long 0x20 "CFG0_CLAIMREG_P3_R8,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P3_R8,Claim bits for Partition 3"
group.long 0x11008++0x7
line.long 0x0 "CFG0_LOCK4_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK4_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1,- KICK1 component"
rgroup.long 0x11100++0x33
line.long 0x0 "CFG0_CLAIMREG_P4_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0_READONLY,Claim bits for Partition 4"
line.long 0x4 "CFG0_CLAIMREG_P4_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1_READONLY,Claim bits for Partition 4"
line.long 0x8 "CFG0_CLAIMREG_P4_R2_READONLY,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2_READONLY,Claim bits for Partition 4"
line.long 0xC "CFG0_CLAIMREG_P4_R3_READONLY,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3_READONLY,Claim bits for Partition 4"
line.long 0x10 "CFG0_CLAIMREG_P4_R4_READONLY,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4_READONLY,Claim bits for Partition 4"
line.long 0x14 "CFG0_CLAIMREG_P4_R5_READONLY,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5_READONLY,Claim bits for Partition 4"
line.long 0x18 "CFG0_CLAIMREG_P4_R6_READONLY,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6_READONLY,Claim bits for Partition 4"
line.long 0x1C "CFG0_CLAIMREG_P4_R7_READONLY,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7_READONLY,Claim bits for Partition 4"
line.long 0x20 "CFG0_CLAIMREG_P4_R8_READONLY,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8_READONLY,Claim bits for Partition 4"
line.long 0x24 "CFG0_CLAIMREG_P4_R9_READONLY,"
hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9_READONLY,Claim bits for Partition 4"
line.long 0x28 "CFG0_CLAIMREG_P4_R10_READONLY,"
hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10_READONLY,Claim bits for Partition 4"
line.long 0x2C "CFG0_CLAIMREG_P4_R11_READONLY,"
hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P4_R11_READONLY,Claim bits for Partition 4"
line.long 0x30 "CFG0_CLAIMREG_P4_R12_READONLY,"
hexmask.long 0x30 0.--31. 1. "CLAIMREG_P4_R12_READONLY,Claim bits for Partition 4"
group.long 0x13008++0x7
line.long 0x0 "CFG0_LOCK4_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK4_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1_PROXY,- KICK1 component"
group.long 0x13100++0x33
line.long 0x0 "CFG0_CLAIMREG_P4_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0,Claim bits for Partition 4"
line.long 0x4 "CFG0_CLAIMREG_P4_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1,Claim bits for Partition 4"
line.long 0x8 "CFG0_CLAIMREG_P4_R2,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2,Claim bits for Partition 4"
line.long 0xC "CFG0_CLAIMREG_P4_R3,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3,Claim bits for Partition 4"
line.long 0x10 "CFG0_CLAIMREG_P4_R4,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4,Claim bits for Partition 4"
line.long 0x14 "CFG0_CLAIMREG_P4_R5,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5,Claim bits for Partition 4"
line.long 0x18 "CFG0_CLAIMREG_P4_R6,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6,Claim bits for Partition 4"
line.long 0x1C "CFG0_CLAIMREG_P4_R7,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7,Claim bits for Partition 4"
line.long 0x20 "CFG0_CLAIMREG_P4_R8,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8,Claim bits for Partition 4"
line.long 0x24 "CFG0_CLAIMREG_P4_R9,"
hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9,Claim bits for Partition 4"
line.long 0x28 "CFG0_CLAIMREG_P4_R10,"
hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10,Claim bits for Partition 4"
line.long 0x2C "CFG0_CLAIMREG_P4_R11,"
hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P4_R11,Claim bits for Partition 4"
line.long 0x30 "CFG0_CLAIMREG_P4_R12,"
hexmask.long 0x30 0.--31. 1. "CLAIMREG_P4_R12,Claim bits for Partition 4"
group.long 0x14000++0x3
line.long 0x0 "CFG0_CHNG_DDR4_FSP_REQ,"
bitfld.long 0x0 8. "CHNG_DDR4_FSP_REQ_REQ,Initiate FSP frequency change" "0,1"
bitfld.long 0x0 0.--1. "CHNG_DDR4_FSP_REQ_REQ_TYPE,Frequency request type" "0,1,2,3"
rgroup.long 0x14004++0x3
line.long 0x0 "CFG0_CHNG_DDR4_FSP_ACK,"
bitfld.long 0x0 7. "CHNG_DDR4_FSP_ACK_ACK,Frequency change acknowledge." "0,1"
bitfld.long 0x0 0. "CHNG_DDR4_FSP_ACK_ERROR,Frequency change error" "0,1"
rgroup.long 0x14080++0x3
line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_REQ,"
bitfld.long 0x0 7. "DDR4_FSP_CLKCHNG_REQ_REQ,DDR Controller FSP clock change request" "0,1"
bitfld.long 0x0 0.--1. "DDR4_FSP_CLKCHNG_REQ_REQ_TYPE,Frequency request type" "0,1,2,3"
group.long 0x140C0++0x3
line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_ACK,"
bitfld.long 0x0 0. "DDR4_FSP_CLKCHNG_ACK_ACK,DDR FSP clock change ackowledge" "0,1"
group.long 0x15008++0x7
line.long 0x0 "CFG0_LOCK5_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK5_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK5_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK5_KICK1,- KICK1 component"
rgroup.long 0x15100++0x7
line.long 0x0 "CFG0_CLAIMREG_P5_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P5_R0_READONLY,Claim bits for Partition 5"
line.long 0x4 "CFG0_CLAIMREG_P5_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P5_R1_READONLY,Claim bits for Partition 5"
group.long 0x16000++0x3
line.long 0x0 "CFG0_CHNG_DDR4_FSP_REQ_PROXY,"
bitfld.long 0x0 8. "CHNG_DDR4_FSP_REQ_REQ_PROXY,Initiate FSP frequency change" "0,1"
bitfld.long 0x0 0.--1. "CHNG_DDR4_FSP_REQ_REQ_TYPE_PROXY,Frequency request type" "0,1,2,3"
rgroup.long 0x16004++0x3
line.long 0x0 "CFG0_CHNG_DDR4_FSP_ACK_PROXY,"
bitfld.long 0x0 7. "CHNG_DDR4_FSP_ACK_ACK_PROXY,Frequency change acknowledge." "0,1"
bitfld.long 0x0 0. "CHNG_DDR4_FSP_ACK_ERROR_PROXY,Frequency change error" "0,1"
rgroup.long 0x16080++0x3
line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_REQ_PROXY,"
bitfld.long 0x0 7. "DDR4_FSP_CLKCHNG_REQ_REQ_PROXY,DDR Controller FSP clock change request" "0,1"
bitfld.long 0x0 0.--1. "DDR4_FSP_CLKCHNG_REQ_REQ_TYPE_PROXY,Frequency request type" "0,1,2,3"
group.long 0x160C0++0x3
line.long 0x0 "CFG0_DDR4_FSP_CLKCHNG_ACK_PROXY,"
bitfld.long 0x0 0. "DDR4_FSP_CLKCHNG_ACK_ACK_PROXY,DDR FSP clock change ackowledge" "0,1"
group.long 0x17008++0x7
line.long 0x0 "CFG0_LOCK5_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK5_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK5_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK5_KICK1_PROXY,- KICK1 component"
group.long 0x17100++0x7
line.long 0x0 "CFG0_CLAIMREG_P5_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P5_R0,Claim bits for Partition 5"
line.long 0x4 "CFG0_CLAIMREG_P5_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P5_R1,Claim bits for Partition 5"
group.long 0x18170++0x3
line.long 0x0 "CFG0_RST_CTRL,"
bitfld.long 0x0 18. "RST_CTRL_MAIN_RESET_ISO_DONE_Z,Main Domain CPUs can set this bit to block warm reset in the main domain which is useful when the Main domain may be accessing" "0,1"
bitfld.long 0x0 17. "RST_CTRL_MAIN_ESM_ERROR_RST_EN_Z,Deactivate Reset of Main by ESM" "0,1"
newline
bitfld.long 0x0 16. "RST_CTRL_DMSC_COLD_RESET_EN_Z,Deactivate Reset of Main by DMSC" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "RST_CTRL_SW_MAIN_POR,Causes Main Domain Power On Reset when set to 4'b0110  Bits will reset to 4'b1111"
newline
hexmask.long.byte 0x0 0.--3. 1. "RST_CTRL_SW_MAIN_WARMRST,Causes Main Domain Warm Reset when set to 4'b0110  Bits will reset to 4'b1111"
rgroup.long 0x18174++0xB
line.long 0x0 "CFG0_RST_STAT,"
bitfld.long 0x0 0. "RST_STAT_MCU_RESET_ISO_DONE_Z,is an outstanding warm reset request for the main domain. Once notified  MCU needs to finish any outstanding" "0,1"
line.long 0x4 "CFG0_RST_SRC,"
bitfld.long 0x4 31. "RST_SRC_SAFETY_ERROR,Reset Caused by MCU ESM Error" "0,1"
bitfld.long 0x4 30. "RST_SRC_MAIN_ESM_ERROR,Reset Caused by Main ESM Error" "0,1"
newline
bitfld.long 0x4 25. "RST_SRC_SW_MAIN_POR_FROM_MAIN,Software Main Power On Reset From MAIN CTRL MMR" "0,1"
bitfld.long 0x4 24. "RST_SRC_SW_MAIN_POR_FROM_MCU,Software Main Power On Reset From MCU CTRL MMR" "0,1"
newline
bitfld.long 0x4 21. "RST_SRC_SW_MAIN_WARMRST_FROM_MAIN,Software Main Warm Reset from MAIN CTRL MMR" "0,1"
bitfld.long 0x4 20. "RST_SRC_SW_MAIN_WARMRST_FROM_MCU,Software Main Warm Reset From MCU CTRL MMR" "0,1"
newline
bitfld.long 0x4 16. "RST_SRC_SW_MCU_WARMRST,Software Warm Reset" "0,1"
bitfld.long 0x4 13. "RST_SRC_WARM_OUT_RST,DMSC Warm Reset" "0,1"
newline
bitfld.long 0x4 12. "RST_SRC_COLD_OUT_RST,DMSC Cold Reset" "0,1"
bitfld.long 0x4 8. "RST_SRC_DEBUG_RST,Debug Subsystem Initiated Reset" "0,1"
newline
bitfld.long 0x4 4. "RST_SRC_THERMAL_RST,Thermal Reset" "0,1"
bitfld.long 0x4 2. "RST_SRC_MAIN_RESET_REQ,Main Reset Pin" "0,1"
newline
bitfld.long 0x4 0. "RST_SRC_MCU_RESET_PIN,Rest Caused by MCU Reset Pin" "0,1"
line.long 0x8 "CFG0_RST_MAGIC_WORD,"
hexmask.long 0x8 0.--31. 1. "RST_MAGIC_WORD_MCU_MAGIC_WORD,Magic Word Indicating Status of MCU Subsystem Boot"
group.long 0x19008++0x7
line.long 0x0 "CFG0_LOCK6_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK6_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK6_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK6_KICK1,- KICK1 component"
rgroup.long 0x19100++0xB
line.long 0x0 "CFG0_CLAIMREG_P6_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0_READONLY,Claim bits for Partition 6"
line.long 0x4 "CFG0_CLAIMREG_P6_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1_READONLY,Claim bits for Partition 6"
line.long 0x8 "CFG0_CLAIMREG_P6_R2_READONLY,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P6_R2_READONLY,Claim bits for Partition 6"
group.long 0x1A170++0x3
line.long 0x0 "CFG0_RST_CTRL_PROXY,"
bitfld.long 0x0 18. "RST_CTRL_MAIN_RESET_ISO_DONE_Z_PROXY,Main Domain CPUs can set this bit to block warm reset in the main domain which is useful when the Main domain may be accessing" "0,1"
bitfld.long 0x0 17. "RST_CTRL_MAIN_ESM_ERROR_RST_EN_Z_PROXY,Deactivate Reset of Main by ESM" "0,1"
newline
bitfld.long 0x0 16. "RST_CTRL_DMSC_COLD_RESET_EN_Z_PROXY,Deactivate Reset of Main by DMSC" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "RST_CTRL_SW_MAIN_POR_PROXY,Causes Main Domain Power On Reset when set to 4'b0110  Bits will reset to 4'b1111"
newline
hexmask.long.byte 0x0 0.--3. 1. "RST_CTRL_SW_MAIN_WARMRST_PROXY,Causes Main Domain Warm Reset when set to 4'b0110  Bits will reset to 4'b1111"
rgroup.long 0x1A174++0xB
line.long 0x0 "CFG0_RST_STAT_PROXY,"
bitfld.long 0x0 0. "RST_STAT_MCU_RESET_ISO_DONE_Z_PROXY,is an outstanding warm reset request for the main domain. Once notified  MCU needs to finish any outstanding" "0,1"
line.long 0x4 "CFG0_RST_SRC_PROXY,"
bitfld.long 0x4 31. "RST_SRC_SAFETY_ERROR_PROXY,Reset Caused by MCU ESM Error" "0,1"
bitfld.long 0x4 30. "RST_SRC_MAIN_ESM_ERROR_PROXY,Reset Caused by Main ESM Error" "0,1"
newline
bitfld.long 0x4 25. "RST_SRC_SW_MAIN_POR_FROM_MAIN_PROXY,Software Main Power On Reset From MAIN CTRL MMR" "0,1"
bitfld.long 0x4 24. "RST_SRC_SW_MAIN_POR_FROM_MCU_PROXY,Software Main Power On Reset From MCU CTRL MMR" "0,1"
newline
bitfld.long 0x4 21. "RST_SRC_SW_MAIN_WARMRST_FROM_MAIN_PROXY,Software Main Warm Reset from MAIN CTRL MMR" "0,1"
bitfld.long 0x4 20. "RST_SRC_SW_MAIN_WARMRST_FROM_MCU_PROXY,Software Main Warm Reset From MCU CTRL MMR" "0,1"
newline
bitfld.long 0x4 16. "RST_SRC_SW_MCU_WARMRST_PROXY,Software Warm Reset" "0,1"
bitfld.long 0x4 13. "RST_SRC_WARM_OUT_RST_PROXY,DMSC Warm Reset" "0,1"
newline
bitfld.long 0x4 12. "RST_SRC_COLD_OUT_RST_PROXY,DMSC Cold Reset" "0,1"
bitfld.long 0x4 8. "RST_SRC_DEBUG_RST_PROXY,Debug Subsystem Initiated Reset" "0,1"
newline
bitfld.long 0x4 4. "RST_SRC_THERMAL_RST_PROXY,Thermal Reset" "0,1"
bitfld.long 0x4 2. "RST_SRC_MAIN_RESET_REQ_PROXY,Main Reset Pin" "0,1"
newline
bitfld.long 0x4 0. "RST_SRC_MCU_RESET_PIN_PROXY,Rest Caused by MCU Reset Pin" "0,1"
line.long 0x8 "CFG0_RST_MAGIC_WORD_PROXY,"
hexmask.long 0x8 0.--31. 1. "RST_MAGIC_WORD_MCU_MAGIC_WORD_PROXY,Magic Word Indicating Status of MCU Subsystem Boot"
group.long 0x1B008++0x7
line.long 0x0 "CFG0_LOCK6_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK6_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK6_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK6_KICK1_PROXY,- KICK1 component"
group.long 0x1B100++0xB
line.long 0x0 "CFG0_CLAIMREG_P6_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0,Claim bits for Partition 6"
line.long 0x4 "CFG0_CLAIMREG_P6_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1,Claim bits for Partition 6"
line.long 0x8 "CFG0_CLAIMREG_P6_R2,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P6_R2,Claim bits for Partition 6"
tree.end
tree "DCC"
base ad:0x0
tree "DCC0 (DCC0)"
base ad:0x800000
group.long 0x0++0x3
line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal."
hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal  but has no effect on the done status flag in DCCSTAT register. User  privilege  and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.."
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User  privilege  and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.."
newline
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User  privilege  and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.."
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User  privilege  and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.."
rgroup.long 0x4++0x3
line.long 0x0 "CFG_DCCREV,Specifies the module version."
bitfld.long 0x0 30.--31. "SCHEME,User  privilege  and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability  a unique func number is assigned; for compatible modules  the same number is maintained. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write):.."
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect."
bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User  privilege  and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User  privilege  and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect."
group.long 0x8++0xF
line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User  privilege  and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User  privilege  and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.."
line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User  privilege  and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module."
bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag"
bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag"
rgroup.long 0x18++0xB
line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0."
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User  privilege  and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect."
line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User  privilege  and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect."
line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User  privilege  and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect."
group.long 0x24++0xB
line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1."
hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1  when the KEY field enables this feature. User  privilege  and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC."
line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0."
hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User  privilege  and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0."
line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC."
hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
newline
hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.."
rgroup.long 0x30++0x3
line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs."
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User  privilege  and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full"
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User  privilege  and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full"
newline
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User  privilege  and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full"
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User  privilege  and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
newline
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User  privilege  and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User  privilege  and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
group.long 0x34++0x3
line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear."
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
tree.end
tree "DCC1 (DCC1)"
base ad:0x804000
group.long 0x0++0x3
line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal."
hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal  but has no effect on the done status flag in DCCSTAT register. User  privilege  and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.."
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User  privilege  and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.."
newline
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User  privilege  and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.."
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User  privilege  and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.."
rgroup.long 0x4++0x3
line.long 0x0 "CFG_DCCREV,Specifies the module version."
bitfld.long 0x0 30.--31. "SCHEME,User  privilege  and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability  a unique func number is assigned; for compatible modules  the same number is maintained. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write):.."
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect."
bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User  privilege  and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User  privilege  and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect."
group.long 0x8++0xF
line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User  privilege  and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User  privilege  and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.."
line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User  privilege  and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module."
bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag"
bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag"
rgroup.long 0x18++0xB
line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0."
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User  privilege  and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect."
line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User  privilege  and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect."
line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User  privilege  and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect."
group.long 0x24++0xB
line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1."
hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1  when the KEY field enables this feature. User  privilege  and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC."
line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0."
hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User  privilege  and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0."
line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC."
hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
newline
hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.."
rgroup.long 0x30++0x3
line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs."
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User  privilege  and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full"
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User  privilege  and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full"
newline
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User  privilege  and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full"
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User  privilege  and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
newline
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User  privilege  and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User  privilege  and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
group.long 0x34++0x3
line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear."
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
tree.end
tree "DCC2 (DCC2)"
base ad:0x808000
group.long 0x0++0x3
line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal."
hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal  but has no effect on the done status flag in DCCSTAT register. User  privilege  and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.."
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User  privilege  and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.."
newline
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User  privilege  and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.."
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User  privilege  and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.."
rgroup.long 0x4++0x3
line.long 0x0 "CFG_DCCREV,Specifies the module version."
bitfld.long 0x0 30.--31. "SCHEME,User  privilege  and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability  a unique func number is assigned; for compatible modules  the same number is maintained. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write):.."
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect."
bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User  privilege  and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User  privilege  and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect."
group.long 0x8++0xF
line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User  privilege  and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User  privilege  and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.."
line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User  privilege  and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module."
bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag"
bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag"
rgroup.long 0x18++0xB
line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0."
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User  privilege  and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect."
line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User  privilege  and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect."
line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User  privilege  and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect."
group.long 0x24++0xB
line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1."
hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1  when the KEY field enables this feature. User  privilege  and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC."
line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0."
hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User  privilege  and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0."
line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC."
hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
newline
hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.."
rgroup.long 0x30++0x3
line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs."
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User  privilege  and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full"
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User  privilege  and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full"
newline
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User  privilege  and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full"
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User  privilege  and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
newline
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User  privilege  and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User  privilege  and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
group.long 0x34++0x3
line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear."
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
tree.end
tree "DCC3 (DCC3)"
base ad:0x80C000
group.long 0x0++0x3
line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal."
hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal  but has no effect on the done status flag in DCCSTAT register. User  privilege  and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.."
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User  privilege  and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.."
newline
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User  privilege  and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.."
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User  privilege  and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.."
rgroup.long 0x4++0x3
line.long 0x0 "CFG_DCCREV,Specifies the module version."
bitfld.long 0x0 30.--31. "SCHEME,User  privilege  and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability  a unique func number is assigned; for compatible modules  the same number is maintained. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write):.."
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect."
bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User  privilege  and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User  privilege  and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect."
group.long 0x8++0xF
line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User  privilege  and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User  privilege  and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.."
line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User  privilege  and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module."
bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag"
bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag"
rgroup.long 0x18++0xB
line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0."
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User  privilege  and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect."
line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User  privilege  and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect."
line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User  privilege  and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect."
group.long 0x24++0xB
line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1."
hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1  when the KEY field enables this feature. User  privilege  and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC."
line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0."
hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User  privilege  and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0."
line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC."
hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
newline
hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.."
rgroup.long 0x30++0x3
line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs."
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User  privilege  and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full"
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User  privilege  and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full"
newline
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User  privilege  and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full"
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User  privilege  and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
newline
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User  privilege  and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User  privilege  and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
group.long 0x34++0x3
line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear."
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
tree.end
tree "DCC4 (DCC4)"
base ad:0x810000
group.long 0x0++0x3
line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal."
hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal  but has no effect on the done status flag in DCCSTAT register. User  privilege  and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.."
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User  privilege  and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.."
newline
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User  privilege  and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.."
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User  privilege  and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.."
rgroup.long 0x4++0x3
line.long 0x0 "CFG_DCCREV,Specifies the module version."
bitfld.long 0x0 30.--31. "SCHEME,User  privilege  and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability  a unique func number is assigned; for compatible modules  the same number is maintained. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write):.."
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect."
bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User  privilege  and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User  privilege  and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect."
group.long 0x8++0xF
line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User  privilege  and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User  privilege  and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.."
line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User  privilege  and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module."
bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag"
bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag"
rgroup.long 0x18++0xB
line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0."
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User  privilege  and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect."
line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User  privilege  and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect."
line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User  privilege  and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect."
group.long 0x24++0xB
line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1."
hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1  when the KEY field enables this feature. User  privilege  and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC."
line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0."
hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User  privilege  and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0."
line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC."
hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
newline
hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.."
rgroup.long 0x30++0x3
line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs."
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User  privilege  and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full"
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User  privilege  and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full"
newline
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User  privilege  and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full"
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User  privilege  and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
newline
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User  privilege  and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User  privilege  and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
group.long 0x34++0x3
line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear."
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
tree.end
tree "DCC5 (DCC5)"
base ad:0x814000
group.long 0x0++0x3
line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal."
hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal  but has no effect on the done status flag in DCCSTAT register. User  privilege  and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.."
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User  privilege  and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.."
newline
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User  privilege  and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.."
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User  privilege  and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.."
rgroup.long 0x4++0x3
line.long 0x0 "CFG_DCCREV,Specifies the module version."
bitfld.long 0x0 30.--31. "SCHEME,User  privilege  and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability  a unique func number is assigned; for compatible modules  the same number is maintained. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write):.."
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hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect."
bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User  privilege  and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User  privilege  and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect."
group.long 0x8++0xF
line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User  privilege  and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User  privilege  and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.."
line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User  privilege  and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module."
bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag"
bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag"
rgroup.long 0x18++0xB
line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0."
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User  privilege  and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect."
line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User  privilege  and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect."
line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User  privilege  and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect."
group.long 0x24++0xB
line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1."
hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1  when the KEY field enables this feature. User  privilege  and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC."
line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0."
hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User  privilege  and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0."
line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC."
hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
newline
hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.."
rgroup.long 0x30++0x3
line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs."
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User  privilege  and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full"
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User  privilege  and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full"
newline
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User  privilege  and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full"
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User  privilege  and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
newline
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User  privilege  and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User  privilege  and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
group.long 0x34++0x3
line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear."
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
tree.end
tree.end
tree "DDR16SS0"
base ad:0x0
tree "DDR16SS0_CTLPHY_WRAP_CTL_CFG_CTLCFG (DDR16SS0_CTLPHY_WRAP_CTL_CFG_CTLCFG)"
base ad:0xF308000
group.long 0x0++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_0,"
hexmask.long.word 0x0 16.--31. 1. "CONTROLLER_ID,Holds the controller product id number. READ-ONLY"
newline
hexmask.long.byte 0x0 8.--11. 1. "DRAM_CLASS,Defines the class of DRAM memory which is connected to the controller."
newline
bitfld.long 0x0 0. "START,Initiate command processing in the controller. Set to 1 to initiate." "0,1"
rgroup.long 0x4++0x17
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_1,"
hexmask.long 0x0 0.--31. 1. "CONTROLLER_VERSION_0,Holds the controller version id. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_2,"
hexmask.long 0x4 0.--31. 1. "CONTROLLER_VERSION_1,Holds the controller version id. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_3,"
hexmask.long.byte 0x8 24.--31. 1. "READ_DATA_FIFO_DEPTH,Reports the depth of the controller core read data queue. READ-ONLY"
newline
bitfld.long 0x8 16.--17. "MAX_CS_REG,Holds the maximum number of chip selects available. READ-ONLY" "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--11. 1. "MAX_COL_REG,Holds the maximum width of column address in DRAMs. READ-ONLY"
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hexmask.long.byte 0x8 0.--4. 1. "MAX_ROW_REG,Holds the maximum width of memory address bus. READ-ONLY"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_4,"
hexmask.long.byte 0xC 16.--23. 1. "WRITE_DATA_FIFO_PTR_WIDTH,Reports the width of the controller core write data latency queue pointer. READ-ONLY"
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hexmask.long.byte 0xC 8.--15. 1. "WRITE_DATA_FIFO_DEPTH,Reports the depth of the controller core write data latency queue. READ-ONLY"
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hexmask.long.byte 0xC 0.--7. 1. "READ_DATA_FIFO_PTR_WIDTH,Reports the width of the controller core read data queue pointer. READ-ONLY"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_5,"
hexmask.long.byte 0x10 24.--31. 1. "ASYNC_CDC_STAGES,Reports the number of synchronizer delays specified for the asynchronous boundary crossings. READ-ONLY"
newline
hexmask.long.byte 0x10 16.--23. 1. "MEMCD_RMODW_FIFO_PTR_WIDTH,Reports the width of the controller core read/modify/write FIFO pointer. READ-ONLY"
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hexmask.long.word 0x10 0.--15. 1. "MEMCD_RMODW_FIFO_DEPTH,Reports the depth of the controller core read/modify/write FIFO. READ-ONLY"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_6,"
hexmask.long.byte 0x14 24.--31. 1. "AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH,Reports the depth of the AXI port 0 write command processing FIFO. Value is the log2 value of the depth. READ-ONLY"
newline
hexmask.long.byte 0x14 16.--23. 1. "AXI0_WR_ARRAY_LOG2_DEPTH,Reports the depth of the AXI port 0 write data array. Value is the log2 value of the depth. READ-ONLY"
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hexmask.long.byte 0x14 8.--15. 1. "AXI0_RDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 0 read data FIFO. Value is the log2 value of the depth. READ-ONLY"
newline
hexmask.long.byte 0x14 0.--7. 1. "AXI0_CMDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 0 command FIFO. Value is the log2 value of the depth. READ-ONLY"
group.long 0x1C++0x73
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_7,"
hexmask.long.tbyte 0x0 0.--23. 1. "TINIT_F0,DRAM TINIT value in cycles. FC=0"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_8,"
hexmask.long.tbyte 0x4 0.--23. 1. "TINIT3_F0,DRAM TINIT3 value in cycles. FC=0"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_9,"
hexmask.long.tbyte 0x8 0.--23. 1. "TINIT4_F0,DRAM TINIT4 value in cycles. FC=0"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_10,"
hexmask.long.tbyte 0xC 0.--23. 1. "TINIT5_F0,DRAM TINIT5 value in cycles. FC=0"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_11,"
hexmask.long.tbyte 0x10 0.--23. 1. "TINIT_F1,DRAM TINIT value in cycles. FC=1"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_12,"
hexmask.long.tbyte 0x14 0.--23. 1. "TINIT3_F1,DRAM TINIT3 value in cycles. FC=1"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_13,"
hexmask.long.tbyte 0x18 0.--23. 1. "TINIT4_F1,DRAM TINIT4 value in cycles. FC=1"
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_14,"
hexmask.long.tbyte 0x1C 0.--23. 1. "TINIT5_F1,DRAM TINIT5 value in cycles. FC=1"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_15,"
hexmask.long.tbyte 0x20 0.--23. 1. "TINIT_F2,DRAM TINIT value in cycles. FC=2"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_16,"
hexmask.long.tbyte 0x24 0.--23. 1. "TINIT3_F2,DRAM TINIT3 value in cycles. FC=2"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_17,"
hexmask.long.tbyte 0x28 0.--23. 1. "TINIT4_F2,DRAM TINIT4 value in cycles. FC=2"
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_18,"
bitfld.long 0x2C 24. "NO_AUTO_MRR_INIT,Disable MRR commands during initialization. Set to 1 to disable." "0,1"
newline
hexmask.long.tbyte 0x2C 0.--23. 1. "TINIT5_F2,DRAM TINIT5 value in cycles. FC=2"
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_19,"
bitfld.long 0x30 24.--25. "DFI_FREQ_RATIO_F2,Defines how dfi_freq_ratio is driven on the DFI bus. For LPDDR5  specifies the DFI clock to WCK ratio. For all other memory classes  specifies the controller clock to DFI PHY clock ratio. Program to zero for a 1:1 ratio  one for a.." "?,1: 4 ratio,?,?"
newline
bitfld.long 0x30 16.--17. "DFI_FREQ_RATIO_F1,Defines how dfi_freq_ratio is driven on the DFI bus. For LPDDR5  specifies the DFI clock to WCK ratio. For all other memory classes  specifies the controller clock to DFI PHY clock ratio. Program to zero for a 1:1 ratio  one for a.." "?,1: 4 ratio,?,?"
newline
bitfld.long 0x30 8.--9. "DFI_FREQ_RATIO_F0,Defines how dfi_freq_ratio is driven on the DFI bus. For LPDDR5  specifies the DFI clock to WCK ratio. For all other memory classes  specifies the controller clock to DFI PHY clock ratio. Program to zero for a 1:1 ratio  one for a.." "?,1: 4 ratio,?,?"
newline
rbitfld.long 0x30 0. "MRR_ERROR_STATUS,Indicates that an MRR was issued while in self-refresh. Value of 1 indicates a violation. READ-ONLY" "0,1"
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_20,"
bitfld.long 0x34 24. "PHY_INDEP_TRAIN_MODE,Enable PHY independent training mode commands during initialization. Set to 1 to enable." "0,1"
newline
bitfld.long 0x34 16.--17. "ODT_VALUE,When using LPDDR4  this value will be driven out on the dfi_odt signal." "0,1,2,3"
newline
bitfld.long 0x34 8. "NO_MRW_INIT,Disable MRW commands during initialization. Set to 1 to disable." "0,1"
newline
rbitfld.long 0x34 0. "DFI_CMD_RATIO,Indicates the controller clock to DFI PHY clock ratio for the DFI command interface. For LPDDR5  this is always a 1:1 ratio. For all other memory classes  this will be the same as the dfi_freq_ratio. Zero specifies a 1:1 ratio and one.." "?,1: 2 ratio"
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_21,"
hexmask.long.byte 0x38 24.--28. 1. "DFIBUS_FREQ_F1,Defines the DFI bus frequency. FC=1"
newline
hexmask.long.byte 0x38 16.--20. 1. "DFIBUS_FREQ_F0,Defines the DFI bus frequency. FC=0"
newline
bitfld.long 0x38 8. "PHY_INDEP_INIT_MODE,Enable PHY independent initailization mode commands during initialization. Set to 1 to enable." "0,1"
newline
hexmask.long.byte 0x38 0.--5. 1. "TSREF2PHYMSTR,Specifies the minimum time after a self-refresh exit command on the DFI bus that the Controller will wait for the PHY to assert the dfi_phymstr_req signal  before completing other commands. Used when the low power control logic is expected.."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_22,"
bitfld.long 0x3C 24.--25. "FREQ_CHANGE_TYPE_F2,Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation. FC=2" "0,1,2,3"
newline
bitfld.long 0x3C 16.--17. "FREQ_CHANGE_TYPE_F1,Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation. FC=1" "0,1,2,3"
newline
bitfld.long 0x3C 8.--9. "FREQ_CHANGE_TYPE_F0,Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation. FC=0" "0,1,2,3"
newline
hexmask.long.byte 0x3C 0.--4. 1. "DFIBUS_FREQ_F2,Defines the DFI bus frequency. FC=2"
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_23,"
hexmask.long 0x40 0.--31. 1. "TRST_PWRON,Duration of memory reset during power-on initialization."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_24,"
hexmask.long 0x44 0.--31. 1. "CKE_INACTIVE,Number of cycles after reset before CKE will be active."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_25,"
hexmask.long.word 0x48 16.--31. 1. "TDLL_F1,DRAM TDLL value in cycles. FC=1"
newline
hexmask.long.word 0x48 0.--15. 1. "TDLL_F0,DRAM TDLL value in cycles. FC=0"
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_26,"
rbitfld.long 0x4C 24.--25. "DQS_OSC_PER_CS_OOV_TRAINING_STATUS,Set the CS information for which DQS oscillator is having out of variance value. READ-ONLY" "0,1,2,3"
newline
rbitfld.long 0x4C 16. "LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS,Error response for Software issued Low power command while DQS Oscillator is in progress. READ-ONLY" "0,1"
newline
hexmask.long.word 0x4C 0.--15. 1. "TDLL_F2,DRAM TDLL value in cycles. FC=2"
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_27,"
hexmask.long.tbyte 0x50 8.--31. 1. "DQS_OSC_MPC_CMD,Set MPC encoding for DQS Oscillator TEST mode."
newline
bitfld.long 0x50 0. "DQS_OSC_TST,Enable DQS Oscillator TEST mode." "0,1"
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_28,"
bitfld.long 0x54 16. "DQS_OSC_ENABLE,Enable DQS oscillator measurement function in DRAM. Set to 1 to enable." "0,1"
newline
hexmask.long.byte 0x54 8.--15. 1. "MRR_MSB_REG,Set MSB MRR register number for DQS Oscillator TEST mode."
newline
hexmask.long.byte 0x54 0.--7. 1. "MRR_LSB_REG,Set LSB MRR register number for DQS Oscillator TEST mode."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_29,"
hexmask.long.byte 0x58 16.--19. 1. "FUNC_VALID_CYCLES,Number of cycles to hold dfi_function_valid asserted."
newline
hexmask.long.word 0x58 0.--14. 1. "DQS_OSC_PERIOD,Number of cycles to run the oscillator measurement. Must reflect cycles programmed into mode register."
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_30,"
hexmask.long 0x5C 0.--31. 1. "DQS_OSC_NORM_THRESHOLD,Number of long counts until the normal priority request is asserted for DQS Oscillator."
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_31,"
hexmask.long 0x60 0.--31. 1. "DQS_OSC_HIGH_THRESHOLD,Number of long counts until the high priority request is asserted for DQS Oscillator."
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_32,"
hexmask.long 0x64 0.--31. 1. "DQS_OSC_TIMEOUT,Number of long counts until the timeout is asserted for DQS Oscillator."
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_33,"
hexmask.long 0x68 0.--31. 1. "DQS_OSC_PROMOTE_THRESHOLD,Number of long counts until a software request for the DQS Oscillator is promoted to high priority."
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_34,"
hexmask.long.byte 0x6C 24.--31. 1. "TOSCO_F0,Number of cycles for tOSCO timing parameter  the time for the DQS Oscillator measurement to be available in the mode registers. FC=0"
newline
bitfld.long 0x6C 16. "DQS_OSC_REQUEST,Software request for DQS Oscillator measurement function in DRAM. WRITE-ONLY" "0,1"
newline
hexmask.long.word 0x6C 0.--15. 1. "OSC_VARIANCE_LIMIT,Allowed difference between base value and DQS Oscillator measurement."
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_35,"
hexmask.long.word 0x70 16.--31. 1. "DQS_OSC_BASE_VALUE_0_CS0,Base value for device 0 on chip 0. READ-ONLY DEV=0"
newline
hexmask.long.byte 0x70 8.--15. 1. "TOSCO_F2,Number of cycles for tOSCO timing parameter  the time for the DQS Oscillator measurement to be available in the mode registers. FC=2"
newline
hexmask.long.byte 0x70 0.--7. 1. "TOSCO_F1,Number of cycles for tOSCO timing parameter  the time for the DQS Oscillator measurement to be available in the mode registers. FC=1"
rgroup.long 0x90++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_36,"
hexmask.long.word 0x0 16.--31. 1. "DQS_OSC_BASE_VALUE_0_CS1,Base value for device 0 on chip 1. READ-ONLY DEV=0"
newline
hexmask.long.word 0x0 0.--15. 1. "DQS_OSC_BASE_VALUE_1_CS0,Base value for device 1 on chip 0. READ-ONLY DEV=1"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_37,"
bitfld.long 0x4 24. "DQS_OSC_IN_PROGRESS_STATUS,DQS Oscillator is in progress.Set '1' DQS OSC is in progress READ-ONLY" "0,1"
newline
hexmask.long.byte 0x4 16.--19. 1. "DQS_OSC_STATUS,Holds the overflow and out of variance status associated with the resp. interrupts. Bit [0] set indicates overflow of DQS oscillator bit [1] set indicates overflow of WCKO oscillator bit [2] set.."
newline
hexmask.long.word 0x4 0.--15. 1. "DQS_OSC_BASE_VALUE_1_CS1,Base value for device 1 on chip 1. READ-ONLY DEV=1"
group.long 0x98++0xCB
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_38,"
hexmask.long.byte 0x0 24.--27. 1. "CA_PARITY_LAT_F0,DRAM CA parity latency value in cycles. FC=0"
newline
hexmask.long.byte 0x0 16.--21. 1. "ADDITIVE_LAT_F0,DRAM additive latency value in cycles. FC=0"
newline
hexmask.long.byte 0x0 8.--14. 1. "WRLAT_F0,DRAM WRLAT value in cycles. FC=0"
newline
hexmask.long.byte 0x0 0.--6. 1. "CASLAT_LIN_F0,Sets latency from read command send to data receive from/to controller. Bit [0] is half-cycle increment and the upper bits define memory CAS latency for the controller. FC=0"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_39,"
hexmask.long.byte 0x4 24.--31. 1. "TMRD_PAR_MAX_PL_F0,DRAM TMRD value with maximum CA parity for frequency copy 2 in cycles. Used during changes of CA parity latency value in DRAM. FC=0"
newline
hexmask.long.byte 0x4 16.--23. 1. "TMOD_PAR_MAX_PL_F0,DRAM TMOD value with maximum CA parity for frequency copy 2 in cycles. Used during changes of CA parity latency value in DRAM. FC=0"
newline
hexmask.long.byte 0x4 8.--15. 1. "TMRD_PAR_F0,DRAM TMRD value when CA parity is enabled in cycles. FC=0"
newline
hexmask.long.byte 0x4 0.--7. 1. "TMOD_PAR_F0,DRAM TMOD value when CA parity is enabled in cycles. FC=0"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_40,"
hexmask.long.byte 0x8 24.--27. 1. "CA_PARITY_LAT_F1,DRAM CA parity latency value in cycles. FC=1"
newline
hexmask.long.byte 0x8 16.--21. 1. "ADDITIVE_LAT_F1,DRAM additive latency value in cycles. FC=1"
newline
hexmask.long.byte 0x8 8.--14. 1. "WRLAT_F1,DRAM WRLAT value in cycles. FC=1"
newline
hexmask.long.byte 0x8 0.--6. 1. "CASLAT_LIN_F1,Sets latency from read command send to data receive from/to controller. Bit [0] is half-cycle increment and the upper bits define memory CAS latency for the controller. FC=1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_41,"
hexmask.long.byte 0xC 24.--31. 1. "TMRD_PAR_MAX_PL_F1,DRAM TMRD value with maximum CA parity for frequency copy 2 in cycles. Used during changes of CA parity latency value in DRAM. FC=1"
newline
hexmask.long.byte 0xC 16.--23. 1. "TMOD_PAR_MAX_PL_F1,DRAM TMOD value with maximum CA parity for frequency copy 2 in cycles. Used during changes of CA parity latency value in DRAM. FC=1"
newline
hexmask.long.byte 0xC 8.--15. 1. "TMRD_PAR_F1,DRAM TMRD value when CA parity is enabled in cycles. FC=1"
newline
hexmask.long.byte 0xC 0.--7. 1. "TMOD_PAR_F1,DRAM TMOD value when CA parity is enabled in cycles. FC=1"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_42,"
hexmask.long.byte 0x10 24.--27. 1. "CA_PARITY_LAT_F2,DRAM CA parity latency value in cycles. FC=2"
newline
hexmask.long.byte 0x10 16.--21. 1. "ADDITIVE_LAT_F2,DRAM additive latency value in cycles. FC=2"
newline
hexmask.long.byte 0x10 8.--14. 1. "WRLAT_F2,DRAM WRLAT value in cycles. FC=2"
newline
hexmask.long.byte 0x10 0.--6. 1. "CASLAT_LIN_F2,Sets latency from read command send to data receive from/to controller. Bit [0] is half-cycle increment and the upper bits define memory CAS latency for the controller. FC=2"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_43,"
hexmask.long.byte 0x14 24.--31. 1. "TMRD_PAR_MAX_PL_F2,DRAM TMRD value with maximum CA parity for frequency copy 2 in cycles. Used during changes of CA parity latency value in DRAM. FC=2"
newline
hexmask.long.byte 0x14 16.--23. 1. "TMOD_PAR_MAX_PL_F2,DRAM TMOD value with maximum CA parity for frequency copy 2 in cycles. Used during changes of CA parity latency value in DRAM. FC=2"
newline
hexmask.long.byte 0x14 8.--15. 1. "TMRD_PAR_F2,DRAM TMRD value when CA parity is enabled in cycles. FC=2"
newline
hexmask.long.byte 0x14 0.--7. 1. "TMOD_PAR_F2,DRAM TMOD value when CA parity is enabled in cycles. FC=2"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_44,"
hexmask.long.byte 0x18 24.--31. 1. "TRRD_F0,DRAM TRRD value in cycles. FC=0"
newline
hexmask.long.byte 0x18 16.--20. 1. "TCCD_L_F0,DRAM CAS-to-CAS value within the same bank group in cycles. FC=0"
newline
hexmask.long.byte 0x18 8.--12. 1. "TCCD,DRAM CAS-to-CAS value in cycles."
newline
bitfld.long 0x18 0.--2. "TBST_INT_INTERVAL,DRAM burst interrupt interval value in cycles." "0,1,2,3,4,5,6,7"
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_45,"
hexmask.long.word 0x1C 8.--16. 1. "TRC_F0,DRAM TRC value in cycles. FC=0"
newline
hexmask.long.byte 0x1C 0.--7. 1. "TRRD_L_F0,DRAM TRRD_L value in cycles. FC=0"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_46,"
hexmask.long.byte 0x20 24.--29. 1. "TWTR_L_F0,DRAM TWTR_L value in cycles. FC=0"
newline
hexmask.long.byte 0x20 16.--21. 1. "TWTR_F0,DRAM TWTR value in cycles. FC=0"
newline
hexmask.long.word 0x20 0.--8. 1. "TRAS_MIN_F0,DRAM TRAS_MIN value in cycles. FC=0"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_47,"
hexmask.long.byte 0x24 24.--28. 1. "TCCD_L_F1,DRAM CAS-to-CAS value within the same bank group in cycles. FC=1"
newline
hexmask.long.word 0x24 8.--16. 1. "TFAW_F0,DRAM TFAW value in cycles. FC=0"
newline
hexmask.long.byte 0x24 0.--7. 1. "TRP_F0,DRAM TRP value in cycles. FC=0"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_48,"
hexmask.long.word 0x28 16.--24. 1. "TRC_F1,DRAM TRC value in cycles. FC=1"
newline
hexmask.long.byte 0x28 8.--15. 1. "TRRD_L_F1,DRAM TRRD_L value in cycles. FC=1"
newline
hexmask.long.byte 0x28 0.--7. 1. "TRRD_F1,DRAM TRRD value in cycles. FC=1"
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_49,"
hexmask.long.byte 0x2C 24.--29. 1. "TWTR_L_F1,DRAM TWTR_L value in cycles. FC=1"
newline
hexmask.long.byte 0x2C 16.--21. 1. "TWTR_F1,DRAM TWTR value in cycles. FC=1"
newline
hexmask.long.word 0x2C 0.--8. 1. "TRAS_MIN_F1,DRAM TRAS_MIN value in cycles. FC=1"
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_50,"
hexmask.long.byte 0x30 24.--28. 1. "TCCD_L_F2,DRAM CAS-to-CAS value within the same bank group in cycles. FC=2"
newline
hexmask.long.word 0x30 8.--16. 1. "TFAW_F1,DRAM TFAW value in cycles. FC=1"
newline
hexmask.long.byte 0x30 0.--7. 1. "TRP_F1,DRAM TRP value in cycles. FC=1"
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_51,"
hexmask.long.word 0x34 16.--24. 1. "TRC_F2,DRAM TRC value in cycles. FC=2"
newline
hexmask.long.byte 0x34 8.--15. 1. "TRRD_L_F2,DRAM TRRD_L value in cycles. FC=2"
newline
hexmask.long.byte 0x34 0.--7. 1. "TRRD_F2,DRAM TRRD value in cycles. FC=2"
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_52,"
hexmask.long.byte 0x38 24.--29. 1. "TWTR_L_F2,DRAM TWTR_L value in cycles. FC=2"
newline
hexmask.long.byte 0x38 16.--21. 1. "TWTR_F2,DRAM TWTR value in cycles. FC=2"
newline
hexmask.long.word 0x38 0.--8. 1. "TRAS_MIN_F2,DRAM TRAS_MIN value in cycles. FC=2"
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_53,"
hexmask.long.byte 0x3C 24.--31. 1. "TRTP_F0,DRAM TRTP value in cycles. FC=0"
newline
hexmask.long.word 0x3C 8.--16. 1. "TFAW_F2,DRAM TFAW value in cycles. FC=2"
newline
hexmask.long.byte 0x3C 0.--7. 1. "TRP_F2,DRAM TRP value in cycles. FC=2"
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_54,"
hexmask.long.byte 0x40 16.--23. 1. "TMOD_F0,Number of cycles after MRS command and before any other command. FC=0"
newline
hexmask.long.byte 0x40 8.--15. 1. "TMRD_F0,DRAM TMRD value in cycles. FC=0"
newline
hexmask.long.byte 0x40 0.--7. 1. "TRTP_AP_F0,DRAM TRTP for auto-precharge value in cycles. FC=0"
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_55,"
hexmask.long.byte 0x44 24.--28. 1. "TCKE_F0,Minimum CKE pulse width. FC=0"
newline
hexmask.long.tbyte 0x44 0.--19. 1. "TRAS_MAX_F0,DRAM TRAS_MAX value in cycles. FC=0"
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_56,"
hexmask.long.byte 0x48 24.--31. 1. "TRTP_AP_F1,DRAM TRTP for auto-precharge value in cycles. FC=1"
newline
hexmask.long.byte 0x48 16.--23. 1. "TRTP_F1,DRAM TRTP value in cycles. FC=1"
newline
hexmask.long.byte 0x48 8.--13. 1. "TCCDMW_F0,DRAM CAS-to-CAS masked write value in cycles. FC=0"
newline
hexmask.long.byte 0x48 0.--7. 1. "TCKESR_F0,Minimum CKE low pulse width during a self-refresh. FC=0"
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_57,"
hexmask.long.byte 0x4C 8.--15. 1. "TMOD_F1,Number of cycles after MRS command and before any other command. FC=1"
newline
hexmask.long.byte 0x4C 0.--7. 1. "TMRD_F1,DRAM TMRD value in cycles. FC=1"
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_58,"
hexmask.long.byte 0x50 24.--28. 1. "TCKE_F1,Minimum CKE pulse width. FC=1"
newline
hexmask.long.tbyte 0x50 0.--19. 1. "TRAS_MAX_F1,DRAM TRAS_MAX value in cycles. FC=1"
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_59,"
hexmask.long.byte 0x54 24.--31. 1. "TRTP_AP_F2,DRAM TRTP for auto-precharge value in cycles. FC=2"
newline
hexmask.long.byte 0x54 16.--23. 1. "TRTP_F2,DRAM TRTP value in cycles. FC=2"
newline
hexmask.long.byte 0x54 8.--13. 1. "TCCDMW_F1,DRAM CAS-to-CAS masked write value in cycles. FC=1"
newline
hexmask.long.byte 0x54 0.--7. 1. "TCKESR_F1,Minimum CKE low pulse width during a self-refresh. FC=1"
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_60,"
hexmask.long.byte 0x58 8.--15. 1. "TMOD_F2,Number of cycles after MRS command and before any other command. FC=2"
newline
hexmask.long.byte 0x58 0.--7. 1. "TMRD_F2,DRAM TMRD value in cycles. FC=2"
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_61,"
hexmask.long.byte 0x5C 24.--28. 1. "TCKE_F2,Minimum CKE pulse width. FC=2"
newline
hexmask.long.tbyte 0x5C 0.--19. 1. "TRAS_MAX_F2,DRAM TRAS_MAX value in cycles. FC=2"
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_62,"
bitfld.long 0x60 16.--18. "TPPD,DRAM TPPD value in cycles." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x60 8.--13. 1. "TCCDMW_F2,DRAM CAS-to-CAS masked write value in cycles. FC=2"
newline
hexmask.long.byte 0x60 0.--7. 1. "TCKESR_F2,Minimum CKE low pulse width during a self-refresh. FC=2"
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_63,"
hexmask.long.byte 0x64 24.--31. 1. "TWR_F0,DRAM TWR value in cycles. FC=0"
newline
hexmask.long.byte 0x64 16.--23. 1. "TRCD_F0,DRAM TRCD value in cycles. FC=0"
newline
bitfld.long 0x64 8. "WRITEINTERP,Allow controller to interrupt a write burst to the DRAMs with a read command. Set to 1 to allow interruption." "0,1"
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_64,"
hexmask.long.byte 0x68 24.--31. 1. "TWR_F2,DRAM TWR value in cycles. FC=2"
newline
hexmask.long.byte 0x68 16.--23. 1. "TRCD_F2,DRAM TRCD value in cycles. FC=2"
newline
hexmask.long.byte 0x68 8.--15. 1. "TWR_F1,DRAM TWR value in cycles. FC=1"
newline
hexmask.long.byte 0x68 0.--7. 1. "TRCD_F1,DRAM TRCD value in cycles. FC=1"
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_65,"
bitfld.long 0x6C 24. "TRAS_LOCKOUT,IF the DRAM supports it  this allows the controller to execute auto pre-charge commands before the TRAS_MIN parameter expires. Set to 1 to enable." "0,1"
newline
bitfld.long 0x6C 16. "CONCURRENTAP,IF the DRAM supports it  this allows the controller to issue commands to other banks while a bank is in auto pre-charge. Set to 1 to enable." "0,1"
newline
bitfld.long 0x6C 8. "AP,Enable auto pre-charge mode of controller. Set to 1 to enable." "0,1"
newline
hexmask.long.byte 0x6C 0.--3. 1. "TMRR,DRAM TMRR value in cycles."
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_66,"
hexmask.long.byte 0x70 24.--29. 1. "BSTLEN,Encoded burst length sent to DRAMs during initialization. Program to 1 for BL2  program to 2 for BL4  program to 3 for BL8  program to 4 for BL16  or program to 5 for BL32. All other settings are reserved."
newline
hexmask.long.byte 0x70 16.--23. 1. "TDAL_F2,DRAM TDAL value in cycles. FC=2"
newline
hexmask.long.byte 0x70 8.--15. 1. "TDAL_F1,DRAM TDAL value in cycles. FC=1"
newline
hexmask.long.byte 0x70 0.--7. 1. "TDAL_F0,DRAM TDAL value in cycles. FC=0"
line.long 0x74 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_67,"
hexmask.long.byte 0x74 24.--31. 1. "TRP_AB_F0_1,DRAM TRP all bank value in cycles. FC=0"
newline
hexmask.long.byte 0x74 16.--23. 1. "TRP_AB_F2_0,DRAM TRP all bank value in cycles. FC=2"
newline
hexmask.long.byte 0x74 8.--15. 1. "TRP_AB_F1_0,DRAM TRP all bank value in cycles. FC=1"
newline
hexmask.long.byte 0x74 0.--7. 1. "TRP_AB_F0_0,DRAM TRP all bank value in cycles. FC=0"
line.long 0x78 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_68,"
bitfld.long 0x78 24.--25. "ADDRESS_MIRRORING,Indicates which chip selects support address mirroring. Bit [0] controls cs0  bit [1] controls cs1  etc. Set each bit to 1 to enable." "0,1,2,3"
newline
bitfld.long 0x78 16. "REG_DIMM_ENABLE,Enable registered DIMM operation of the controller. Set to 1 to enable." "0,1"
newline
hexmask.long.byte 0x78 8.--15. 1. "TRP_AB_F2_1,DRAM TRP all bank value in cycles. FC=2"
newline
hexmask.long.byte 0x78 0.--7. 1. "TRP_AB_F1_1,DRAM TRP all bank value in cycles. FC=1"
line.long 0x7C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_69,"
bitfld.long 0x7C 16. "NO_MEMORY_DM,Indicates that the external DRAM does not support DM masking. Set to 1 for no DM masking at the DRAM." "0,1"
newline
bitfld.long 0x7C 0. "OPTIMAL_RMODW_EN,Enables optimized RMODW logic in the controller. A value of 1 enables optimized RMODW operation. All RMODW operations are still supported in a non-optimal manner when the value is 0." "0,1"
line.long 0x80 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_70,"
hexmask.long 0x80 0.--25. 1. "CA_PARITY_ERROR_INJECT,Selects bit to corrupt on the CA bus for CA parity error injection."
line.long 0x84 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_71,"
bitfld.long 0x84 24. "TREF_ENABLE,Issue auto-refresh commands to the DRAMs at the interval defined in the TREF parameter. Set to 1 to enable." "0,1"
newline
rbitfld.long 0x84 16. "AREF_STATUS,Indicates a SR error associated with the AREF interrupt. Value of 1 indicates a violation. READ-ONLY" "0,1"
newline
bitfld.long 0x84 8. "AREFRESH,Initiate auto-refresh at the end of the current burst boundary. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
rbitfld.long 0x84 0. "CA_PARITY_ERROR,Contains one hot indication of registered DIMM parity errors. Value of 1 indicates an error on that DIMM. READ-ONLY" "0,1"
line.long 0x88 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_72,"
hexmask.long.word 0x88 16.--25. 1. "TRFC_F0,DRAM TRFC value in cycles. FC=0"
newline
hexmask.long.byte 0x88 8.--13. 1. "CS_COMPARISON_FOR_REFRESH_DEPTH,Defines the number of entries of the command queue that the refresh logic will consider for sending a refresh command. A non-zero value limits the decode to a subset of the full command pipeline."
newline
bitfld.long 0x88 0.--2. "TRFC_OPT_THRESHOLD,Number of clocks before TRFC expires when the refresh task will deassert its request for optimal command to command turn-around timing." "0,1,2,3,4,5,6,7"
line.long 0x8C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_73,"
hexmask.long.tbyte 0x8C 0.--19. 1. "TREF_F0,DRAM TREF value in cycles. FC=0"
line.long 0x90 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_74,"
hexmask.long.word 0x90 0.--9. 1. "TRFC_F1,DRAM TRFC value in cycles. FC=1"
line.long 0x94 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_75,"
hexmask.long.tbyte 0x94 0.--19. 1. "TREF_F1,DRAM TREF value in cycles. FC=1"
line.long 0x98 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_76,"
hexmask.long.word 0x98 0.--9. 1. "TRFC_F2,DRAM TRFC value in cycles. FC=2"
line.long 0x9C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_77,"
hexmask.long.tbyte 0x9C 0.--19. 1. "TREF_F2,DRAM TREF value in cycles. FC=2"
line.long 0xA0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_78,"
hexmask.long.tbyte 0xA0 0.--19. 1. "TREF_INTERVAL,Defines the cycles between refreshes to different chip selects."
line.long 0xA4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_79,"
hexmask.long.word 0xA4 0.--9. 1. "TRFC_PB_F0,DRAM TRFC_PB value in cycles. FC=0"
line.long 0xA8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_80,"
hexmask.long.tbyte 0xA8 0.--19. 1. "TREFI_PB_F0,DRAM TREFI_PB value in cycles. FC=0"
line.long 0xAC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_81,"
hexmask.long.word 0xAC 0.--9. 1. "TRFC_PB_F1,DRAM TRFC_PB value in cycles. FC=1"
line.long 0xB0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_82,"
hexmask.long.tbyte 0xB0 0.--19. 1. "TREFI_PB_F1,DRAM TREFI_PB value in cycles. FC=1"
line.long 0xB4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_83,"
hexmask.long.word 0xB4 0.--9. 1. "TRFC_PB_F2,DRAM TRFC_PB value in cycles. FC=2"
line.long 0xB8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_84,"
bitfld.long 0xB8 24. "PBR_EN,Enables the per-bank refresh feature. Set to 1 to enable." "0,1"
newline
hexmask.long.tbyte 0xB8 0.--19. 1. "TREFI_PB_F2,DRAM TREFI_PB value in cycles. FC=2"
line.long 0xBC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_85,"
hexmask.long.byte 0xBC 24.--27. 1. "PBR_BANK_SELECT_DELAY,Defines the PBR bank select to command delay  the time from bank selection to when the command queue bank selection logic is guaranteed to have blocked the bank."
newline
hexmask.long.word 0xBC 8.--23. 1. "PBR_MAX_BANK_WAIT,Defines the maximum number of cycles that the PBR module will wait for Strategy to release the target bank until the PBR will assert the inhibit and close the target bank."
newline
bitfld.long 0xBC 0. "PBR_NUMERIC_ORDER,Enables the PBR to run REFpb commands in numeric bank order [0 1 2 3  etc.] When disabled  the order may be modified if supported by the memory type. Set to 1 to enable." "0,1"
line.long 0xC0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_86,"
hexmask.long.byte 0xC0 16.--20. 1. "AREF_PBR_CONT_DIS_THRESHOLD,Sets the auto-refresh request count threshold when the PBR continuous refresh request enable will be deasserted."
newline
hexmask.long.byte 0xC0 8.--12. 1. "AREF_PBR_CONT_EN_THRESHOLD,Sets the auto-refresh request count threshold when the PBR continuous refresh request enable will be asserted."
newline
bitfld.long 0xC0 0. "PBR_CONT_REQ_EN,Enables the per-bank refresh continuous request feature. Set to 1 to enable." "0,1"
line.long 0xC4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_87,"
hexmask.long.word 0xC4 16.--31. 1. "TPDEX_F1,DRAM TPDEX value in cycles. FC=1"
newline
hexmask.long.word 0xC4 0.--15. 1. "TPDEX_F0,DRAM TPDEX value in cycles. FC=0"
line.long 0xC8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_88,"
hexmask.long.word 0xC8 0.--15. 1. "TPDEX_F2,DRAM TPDEX value in cycles. FC=2"
rgroup.long 0x164++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_89,"
hexmask.long 0x0 0.--31. 1. "CTL_UNUSED_REG_0,Place-holder for register map preservation"
group.long 0x168++0x18F
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_90,"
hexmask.long.byte 0x0 24.--28. 1. "TCKELCS_F0,DRAM TCKELCS value in cycles. FC=0"
newline
hexmask.long.byte 0x0 16.--23. 1. "TMRRI_F2,DRAM TMRRI value in cycles. FC=2"
newline
hexmask.long.byte 0x0 8.--15. 1. "TMRRI_F1,DRAM TMRRI value in cycles. FC=1"
newline
hexmask.long.byte 0x0 0.--7. 1. "TMRRI_F0,DRAM TMRRI value in cycles. FC=0"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_91,"
hexmask.long.byte 0x4 24.--28. 1. "TCKELCS_F1,DRAM TCKELCS value in cycles. FC=1"
newline
hexmask.long.byte 0x4 16.--19. 1. "TZQCKE_F0,DRAM TZQCKE value in cycles. FC=0"
newline
hexmask.long.byte 0x4 8.--12. 1. "TMRWCKEL_F0,DRAM TMRWCKEL value in cycles. FC=0"
newline
hexmask.long.byte 0x4 0.--4. 1. "TCKEHCS_F0,DRAM TCKEHCS value in cycles. FC=0"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_92,"
hexmask.long.byte 0x8 24.--28. 1. "TCKELCS_F2,DRAM TCKELCS value in cycles. FC=2"
newline
hexmask.long.byte 0x8 16.--19. 1. "TZQCKE_F1,DRAM TZQCKE value in cycles. FC=1"
newline
hexmask.long.byte 0x8 8.--12. 1. "TMRWCKEL_F1,DRAM TMRWCKEL value in cycles. FC=1"
newline
hexmask.long.byte 0x8 0.--4. 1. "TCKEHCS_F1,DRAM TCKEHCS value in cycles. FC=1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_93,"
hexmask.long.byte 0xC 24.--28. 1. "TCSCKE_F0,DRAM TCSCKE value in cycles. FC=0"
newline
hexmask.long.byte 0xC 16.--19. 1. "TZQCKE_F2,DRAM TZQCKE value in cycles. FC=2"
newline
hexmask.long.byte 0xC 8.--12. 1. "TMRWCKEL_F2,DRAM TMRWCKEL value in cycles. FC=2"
newline
hexmask.long.byte 0xC 0.--4. 1. "TCKEHCS_F2,DRAM TCKEHCS value in cycles. FC=2"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_94,"
hexmask.long.byte 0x10 24.--28. 1. "TCSCKE_F2,DRAM TCSCKE value in cycles. FC=2"
newline
bitfld.long 0x10 16. "CA_DEFAULT_VAL_F1,Defines how unused address/command bits are driven. Set to 1 to use last value or clear to 0 to drive low. FC=1" "0,1"
newline
hexmask.long.byte 0x10 8.--12. 1. "TCSCKE_F1,DRAM TCSCKE value in cycles. FC=1"
newline
bitfld.long 0x10 0. "CA_DEFAULT_VAL_F0,Defines how unused address/command bits are driven. Set to 1 to use last value or clear to 0 to drive low. FC=0" "0,1"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_95,"
hexmask.long.word 0x14 8.--23. 1. "TXSR_F0,DRAM TXSR value in cycles. FC=0"
newline
bitfld.long 0x14 0. "CA_DEFAULT_VAL_F2,Defines how unused address/command bits are driven. Set to 1 to use last value or clear to 0 to drive low. FC=2" "0,1"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_96,"
hexmask.long.word 0x18 16.--31. 1. "TXSR_F1,DRAM TXSR value in cycles. FC=1"
newline
hexmask.long.word 0x18 0.--15. 1. "TXSNR_F0,DRAM TXSNR value in cycles. FC=0"
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_97,"
hexmask.long.word 0x1C 16.--31. 1. "TXSR_F2,DRAM TXSR value in cycles. FC=2"
newline
hexmask.long.word 0x1C 0.--15. 1. "TXSNR_F1,DRAM TXSNR value in cycles. FC=1"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_98,"
hexmask.long.word 0x20 16.--31. 1. "TXPR_F0,DRAM TXPR value in cycles. This parameter defines reset exit time from CKE HIGH to a valid command. FC=0"
newline
hexmask.long.word 0x20 0.--15. 1. "TXSNR_F2,DRAM TXSNR value in cycles. FC=2"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_99,"
hexmask.long.word 0x24 16.--31. 1. "TXPR_F2,DRAM TXPR value in cycles. This parameter defines reset exit time from CKE HIGH to a valid command. FC=2"
newline
hexmask.long.word 0x24 0.--15. 1. "TXPR_F1,DRAM TXPR value in cycles. This parameter defines reset exit time from CKE HIGH to a valid command. FC=1"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_100,"
hexmask.long.byte 0x28 24.--28. 1. "TCKELCMD_F0,DRAM TCKELCMD value in cycles. FC=0"
newline
hexmask.long.byte 0x28 16.--20. 1. "TCSCKEH_F0,DRAM TCSCKEH value in cycles. FC=0"
newline
bitfld.long 0x28 8.--10. "TESCKE_F0,DRAM TESCKE value in cycles. FC=0" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 0.--7. 1. "TSR_F0,DRAM TSR value in cycles. FC=0"
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_101,"
hexmask.long.byte 0x2C 24.--31. 1. "TSR_F1,DRAM TSR value in cycles. FC=1"
newline
hexmask.long.byte 0x2C 16.--20. 1. "TCKELPD_F0,DRAM TCKELPD value in cycles. FC=0"
newline
hexmask.long.byte 0x2C 8.--12. 1. "TCKCKEL_F0,DRAM TCKCKEL value in cycles. FC=0"
newline
hexmask.long.byte 0x2C 0.--4. 1. "TCKEHCMD_F0,DRAM TCKEHCMD value in cycles. FC=0"
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_102,"
hexmask.long.byte 0x30 24.--28. 1. "TCKEHCMD_F1,DRAM TCKEHCMD value in cycles. FC=1"
newline
hexmask.long.byte 0x30 16.--20. 1. "TCKELCMD_F1,DRAM TCKELCMD value in cycles. FC=1"
newline
hexmask.long.byte 0x30 8.--12. 1. "TCSCKEH_F1,DRAM TCSCKEH value in cycles. FC=1"
newline
bitfld.long 0x30 0.--2. "TESCKE_F1,DRAM TESCKE value in cycles. FC=1" "0,1,2,3,4,5,6,7"
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_103,"
bitfld.long 0x34 24.--26. "TESCKE_F2,DRAM TESCKE value in cycles. FC=2" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x34 16.--23. 1. "TSR_F2,DRAM TSR value in cycles. FC=2"
newline
hexmask.long.byte 0x34 8.--12. 1. "TCKELPD_F1,DRAM TCKELPD value in cycles. FC=1"
newline
hexmask.long.byte 0x34 0.--4. 1. "TCKCKEL_F1,DRAM TCKCKEL value in cycles. FC=1"
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_104,"
hexmask.long.byte 0x38 24.--28. 1. "TCKCKEL_F2,DRAM TCKCKEL value in cycles. FC=2"
newline
hexmask.long.byte 0x38 16.--20. 1. "TCKEHCMD_F2,DRAM TCKEHCMD value in cycles. FC=2"
newline
hexmask.long.byte 0x38 8.--12. 1. "TCKELCMD_F2,DRAM TCKELCMD value in cycles. FC=2"
newline
hexmask.long.byte 0x38 0.--4. 1. "TCSCKEH_F2,DRAM TCSCKEH value in cycles. FC=2"
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_105,"
hexmask.long.byte 0x3C 24.--28. 1. "TCMDCKE_F2,DRAM TCMDCKE value in cycles. FC=2"
newline
hexmask.long.byte 0x3C 16.--20. 1. "TCMDCKE_F1,DRAM TCMDCKE value in cycles. FC=1"
newline
hexmask.long.byte 0x3C 8.--12. 1. "TCMDCKE_F0,DRAM TCMDCKE value in cycles. FC=0"
newline
hexmask.long.byte 0x3C 0.--4. 1. "TCKELPD_F2,DRAM TCKELPD value in cycles. FC=2"
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_106,"
bitfld.long 0x40 24.--26. "CKE_DELAY,Additional cycles to delay CKE for status reporting." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 16. "ENABLE_QUICK_SREFRESH,Allow user to interrupt memory initialization to enter self-refresh mode. Set to 1 to allow interruption." "0,1"
newline
bitfld.long 0x40 8. "SREFRESH_EXIT_NO_REFRESH,Disables the automatic refresh request associated with self-refresh exit. Set to 1 to disable." "0,1"
newline
bitfld.long 0x40 0. "PWRUP_SREFRESH_EXIT,Allow powerup via self-refresh instead of full memory initialization. Set to 1 to enable." "0,1"
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_107,"
bitfld.long 0x44 16. "DFS_ZQ_EN,Enables ZQ calibration across all ranks during a DFS exit. Set to 1 to enable. Not valid when operating in ZQ background mode." "0,1"
newline
hexmask.long.byte 0x44 8.--14. 1. "DFS_STATUS,Contains status and interrupt information related to DFS. Bit [0] set indicates that the DFS request from the hardware interface was ignored because param_dfs_enable was zero or because another HWI-initiated DFS operation was already in.."
newline
hexmask.long.byte 0x44 0.--4. 1. "DFS_CMD,lt Currently not supported gt DFS software command request interface. Bit [0] sends the DFS exit request when set. Bit [1] sends the DFS enter request when set. Bit [2] tells the controller to gate the memory clock before handing control to the.."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_108,"
hexmask.long.word 0x48 16.--31. 1. "DFS_PROMOTE_THRESHOLD_F1,DFS promotion number of long counts until the high priority request is asserted for frequency copy 1. Applies to SW and HW DFS commands. FC=1"
newline
hexmask.long.word 0x48 0.--15. 1. "DFS_PROMOTE_THRESHOLD_F0,DFS promotion number of long counts until the high priority request is asserted for frequency copy 0. Applies to SW and HW DFS commands. FC=0"
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_109,"
rbitfld.long 0x4C 16.--18. "ZQ_STATUS_LOG,Indicates what kind of ZQ command was terminated without execution that caused the ZQ status interrupt to assert. Bit [0] correlates to a ZQ cal init  reset  short or long command. Bit [1] correlates to a ZQ cal start command. Bit [2].." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x4C 0.--15. 1. "DFS_PROMOTE_THRESHOLD_F2,DFS promotion number of long counts until the high priority request is asserted for frequency copy 2. Applies to SW and HW DFS commands. FC=2"
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_110,"
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_111,"
hexmask.long.word 0x54 16.--31. 1. "UPD_CTRLUPD_HIGH_THRESHOLD_F0,DFI control update number of long counts until the high priority request is asserted. FC=0"
newline
hexmask.long.word 0x54 0.--15. 1. "UPD_CTRLUPD_NORM_THRESHOLD_F0,DFI control update number of long counts until the normal priority request is asserted. FC=0"
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_112,"
hexmask.long.word 0x58 16.--31. 1. "UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0,DFI control update SW promotion number of long counts until the high priority request is asserted. FC=0"
newline
hexmask.long.word 0x58 0.--15. 1. "UPD_CTRLUPD_TIMEOUT_F0,DFI control update number of long counts until the timeout is asserted. FC=0"
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_113,"
hexmask.long.word 0x5C 16.--31. 1. "UPD_CTRLUPD_NORM_THRESHOLD_F1,DFI control update number of long counts until the normal priority request is asserted. FC=1"
newline
hexmask.long.word 0x5C 0.--15. 1. "UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0,DFI PHY update DFI promotion number of long counts until the high priority request is asserted. FC=0"
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_114,"
hexmask.long.word 0x60 16.--31. 1. "UPD_CTRLUPD_TIMEOUT_F1,DFI control update number of long counts until the timeout is asserted. FC=1"
newline
hexmask.long.word 0x60 0.--15. 1. "UPD_CTRLUPD_HIGH_THRESHOLD_F1,DFI control update number of long counts until the high priority request is asserted. FC=1"
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_115,"
hexmask.long.word 0x64 16.--31. 1. "UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1,DFI PHY update DFI promotion number of long counts until the high priority request is asserted. FC=1"
newline
hexmask.long.word 0x64 0.--15. 1. "UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1,DFI control update SW promotion number of long counts until the high priority request is asserted. FC=1"
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_116,"
hexmask.long.word 0x68 16.--31. 1. "UPD_CTRLUPD_HIGH_THRESHOLD_F2,DFI control update number of long counts until the high priority request is asserted. FC=2"
newline
hexmask.long.word 0x68 0.--15. 1. "UPD_CTRLUPD_NORM_THRESHOLD_F2,DFI control update number of long counts until the normal priority request is asserted. FC=2"
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_117,"
hexmask.long.word 0x6C 16.--31. 1. "UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2,DFI control update SW promotion number of long counts until the high priority request is asserted. FC=2"
newline
hexmask.long.word 0x6C 0.--15. 1. "UPD_CTRLUPD_TIMEOUT_F2,DFI control update number of long counts until the timeout is asserted. FC=2"
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_118,"
hexmask.long.word 0x70 0.--15. 1. "UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2,DFI PHY update DFI promotion number of long counts until the high priority request is asserted. FC=2"
line.long 0x74 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_119,"
hexmask.long 0x74 0.--31. 1. "TDFI_PHYMSTR_MAX_F0,Defines the DFI tPHYMSTR_MAX timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack. If programmed to a non-zero  a timing violation will cause an interrupt.."
line.long 0x78 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_120,"
hexmask.long 0x78 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE0_F0,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE0 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=0. If programmed to a non-zero  a.."
line.long 0x7C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_121,"
hexmask.long 0x7C 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE1_F0,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE1 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=1. If programmed to a non-zero  a.."
line.long 0x80 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_122,"
hexmask.long 0x80 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE2_F0,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE2 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=2. If programmed to a non-zero  a.."
line.long 0x84 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_123,"
hexmask.long 0x84 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE3_F0,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE3 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=3. If programmed to a non-zero  a.."
line.long 0x88 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_124,"
hexmask.long.word 0x88 0.--15. 1. "PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0,Defines the DFI[4.0 and 4.0v2] PHY master request promotion number of regular [not long] counts until the high priority request is asserted. FC=0"
line.long 0x8C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_125,"
hexmask.long.tbyte 0x8C 0.--19. 1. "TDFI_PHYMSTR_RESP_F0,Defines the DFI tPHYMSTR_RESP timing parameter [in DFI clocks]  the maximum cycles between a dfi_phymstr_req assertion and a dfi_phymstr_ack assertion. If programmed to a non-zero  a timing violation will cause an interrupt and bit.."
line.long 0x90 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_126,"
hexmask.long 0x90 0.--31. 1. "TDFI_PHYMSTR_MAX_F1,Defines the DFI tPHYMSTR_MAX timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack. If programmed to a non-zero  a timing violation will cause an interrupt.."
line.long 0x94 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_127,"
hexmask.long 0x94 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE0_F1,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE0 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=0. If programmed to a non-zero  a.."
line.long 0x98 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_128,"
hexmask.long 0x98 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE1_F1,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE1 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=1. If programmed to a non-zero  a.."
line.long 0x9C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_129,"
hexmask.long 0x9C 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE2_F1,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE2 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=2. If programmed to a non-zero  a.."
line.long 0xA0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_130,"
hexmask.long 0xA0 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE3_F1,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE3 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=3. If programmed to a non-zero  a.."
line.long 0xA4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_131,"
hexmask.long.word 0xA4 0.--15. 1. "PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1,Defines the DFI[4.0 and 4.0v2] PHY master request promotion number of regular [not long] counts until the high priority request is asserted. FC=1"
line.long 0xA8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_132,"
hexmask.long.tbyte 0xA8 0.--19. 1. "TDFI_PHYMSTR_RESP_F1,Defines the DFI tPHYMSTR_RESP timing parameter [in DFI clocks]  the maximum cycles between a dfi_phymstr_req assertion and a dfi_phymstr_ack assertion. If programmed to a non-zero  a timing violation will cause an interrupt and bit.."
line.long 0xAC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_133,"
hexmask.long 0xAC 0.--31. 1. "TDFI_PHYMSTR_MAX_F2,Defines the DFI tPHYMSTR_MAX timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack. If programmed to a non-zero  a timing violation will cause an interrupt.."
line.long 0xB0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_134,"
hexmask.long 0xB0 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE0_F2,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE0 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=0. If programmed to a non-zero  a.."
line.long 0xB4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_135,"
hexmask.long 0xB4 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE1_F2,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE1 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=1. If programmed to a non-zero  a.."
line.long 0xB8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_136,"
hexmask.long 0xB8 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE2_F2,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE2 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=2. If programmed to a non-zero  a.."
line.long 0xBC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_137,"
hexmask.long 0xBC 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE3_F2,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE3 timing parameter [in DFI clocks]  the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=3. If programmed to a non-zero  a.."
line.long 0xC0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_138,"
hexmask.long.word 0xC0 0.--15. 1. "PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2,Defines the DFI[4.0 and 4.0v2] PHY master request promotion number of regular [not long] counts until the high priority request is asserted. FC=2"
line.long 0xC4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_139,"
bitfld.long 0xC4 24. "PHYMSTR_NO_AREF,isables refreshes during the PHY master interface sequence. Set to 1 to disable. Refreshes during reset are only supported for DFI 4.0 and this parameter may be set or cleared for DFI 4.0. For all other DFI versions  this parameter must.." "0,1"
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hexmask.long.tbyte 0xC4 0.--19. 1. "TDFI_PHYMSTR_RESP_F2,Defines the DFI tPHYMSTR_RESP timing parameter [in DFI clocks]  the maximum cycles between a dfi_phymstr_req assertion and a dfi_phymstr_ack assertion. If programmed to a non-zero  a timing violation will cause an interrupt and bit.."
line.long 0xC8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_140,"
bitfld.long 0xC8 16. "PHYMSTR_TRAIN_AFTER_INIT_COMPLETE,Defines how the PHY will use the PHY Master Interface for training. Clear to 0 to perform training without the PHY Master Interface  or set to 1 to use the PHY Master Interface to gain control over the DFI bus after the.." "0,1"
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bitfld.long 0xC8 8. "PHYMSTR_DFI_VERSION_4P0V1,Defines the version of the DFI 4.0 specification supported. Clear to 0 for DFI 4.0 version 2 PHY Master Interface  or set to 1 for DFI 4.0 version 1 PHY Master Interface. Default is cleared to 0 for version 2." "0,1"
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rbitfld.long 0xC8 0.--1. "PHYMSTR_ERROR_STATUS,Identifies the source of any DFI PHY Master Interface errors. Value of 1 indicates a timing violation of the associated timing parameter. Bit [0] set indicates a TDFI_PHYMSTR_MAX or TDFI_PHYMSTR_TYPEn_MAX parmaeter violation and bit.." "0,1,2,3"
line.long 0xCC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_141,"
hexmask.long.tbyte 0xCC 0.--23. 1. "MRR_TEMPCHK_NORM_THRESHOLD_F0,MRR temp check number of long counts until the normal priority request is asserted. FC=0"
line.long 0xD0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_142,"
hexmask.long.tbyte 0xD0 0.--23. 1. "MRR_TEMPCHK_HIGH_THRESHOLD_F0,MRR temp check number of long counts until the high priority request is asserted. FC=0"
line.long 0xD4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_143,"
hexmask.long.tbyte 0xD4 0.--23. 1. "MRR_TEMPCHK_TIMEOUT_F0,MRR temp check number of long counts until the timeout is asserted. FC=0"
line.long 0xD8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_144,"
hexmask.long.tbyte 0xD8 0.--23. 1. "MRR_TEMPCHK_NORM_THRESHOLD_F1,MRR temp check number of long counts until the normal priority request is asserted. FC=1"
line.long 0xDC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_145,"
hexmask.long.tbyte 0xDC 0.--23. 1. "MRR_TEMPCHK_HIGH_THRESHOLD_F1,MRR temp check number of long counts until the high priority request is asserted. FC=1"
line.long 0xE0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_146,"
hexmask.long.tbyte 0xE0 0.--23. 1. "MRR_TEMPCHK_TIMEOUT_F1,MRR temp check number of long counts until the timeout is asserted. FC=1"
line.long 0xE4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_147,"
hexmask.long.tbyte 0xE4 0.--23. 1. "MRR_TEMPCHK_NORM_THRESHOLD_F2,MRR temp check number of long counts until the normal priority request is asserted. FC=2"
line.long 0xE8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_148,"
hexmask.long.tbyte 0xE8 0.--23. 1. "MRR_TEMPCHK_HIGH_THRESHOLD_F2,MRR temp check number of long counts until the high priority request is asserted. FC=2"
line.long 0xEC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_149,"
bitfld.long 0xEC 24. "PPR_CONTROL,Enables the post-package repair feature. Set to 1 to enable. This parameter may only be programmed before initialization begins." "0,1"
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hexmask.long.tbyte 0xEC 0.--23. 1. "MRR_TEMPCHK_TIMEOUT_F2,MRR temp check number of long counts until the timeout is asserted. FC=2"
line.long 0xF0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_150,"
hexmask.long.byte 0xF0 8.--15. 1. "PPR_COMMAND_MRW_REGNUM,Specifies the mode register to be used. Clear to 0 for MRW0 or program to 4 for MRW4. All other values are reserved.."
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bitfld.long 0xF0 0.--2. "PPR_COMMAND,Specifies the type of PPR command. Program to 1 for pre-charge all  program to 2 for MRW  program to 3 for activate  or program to 5 for write. All other values are reserved. WRITE-ONLY" "0,1,2,3,4,5,6,7"
line.long 0xF4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_151,"
hexmask.long.tbyte 0xF4 0.--16. 1. "PPR_COMMAND_MRW_DATA,Specifies the data for the mode register write."
line.long 0xF8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_152,"
hexmask.long.byte 0xF8 24.--27. 1. "PPR_BANK_ADDRESS,Specifies the bank for the row to be repaired."
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hexmask.long.tbyte 0xF8 0.--16. 1. "PPR_ROW_ADDRESS,Specifies the encoded row address to be repaired."
line.long 0xFC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_153,"
bitfld.long 0xFC 0. "PPR_CS_ADDRESS,Specifies the chip select for the row to be repaired." "0,1"
line.long 0x100 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_154,"
hexmask.long 0x100 0.--31. 1. "PPR_DATA_0,Holds the data pattern to be written to memory for all data phases. This is specific to DDR4 memories."
line.long 0x104 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_155,"
hexmask.long 0x104 0.--31. 1. "PPR_DATA_1,Holds the data pattern to be written to memory for all data phases. This is specific to DDR4 memories."
line.long 0x108 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_156,"
hexmask.long.byte 0x108 24.--31. 1. "CKSRX_F0,Clock stable delay on self-refresh exit. FC=0"
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hexmask.long.byte 0x108 16.--23. 1. "CKSRE_F0,Clock hold delay on self-refresh entry. FC=0"
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bitfld.long 0x108 8. "FM_OVRIDE_CONTROL,Enables the FM Override feature. Set to 1 to enable." "0,1"
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rbitfld.long 0x108 0.--1. "PPR_STATUS,Reports the status of the PPR operation. Bit [0] set indicates that PPR operations are now allowed and bit [1] set indicates if the last PPR command is complete. READ-ONLY" "0,1,2,3"
line.long 0x10C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_157,"
hexmask.long.byte 0x10C 24.--31. 1. "CKSRX_F2,Clock stable delay on self-refresh exit. FC=2"
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hexmask.long.byte 0x10C 16.--23. 1. "CKSRE_F2,Clock hold delay on self-refresh entry. FC=2"
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hexmask.long.byte 0x10C 8.--15. 1. "CKSRX_F1,Clock stable delay on self-refresh exit. FC=1"
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hexmask.long.byte 0x10C 0.--7. 1. "CKSRE_F1,Clock hold delay on self-refresh entry. FC=1"
line.long 0x110 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_158,"
hexmask.long.byte 0x110 24.--27. 1. "LPI_SR_SHORT_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when LPDDR4 memory is in the self-refresh short state [with or without memory clock gating]. For LPDDR4  SR_SHORT is used to send few commands so this wakeup.."
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hexmask.long.byte 0x110 16.--19. 1. "LPI_IDLE_WAKEUP_F0,Defines the DFI tLP_CTRL_WAKEUP timing parameter [in DFI clocks] to be driven when controller is idle. FC=0"
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hexmask.long.byte 0x110 8.--14. 1. "LP_CMD,Low power software command request interface. Bit [0] controls exit  bit [1] controls entry  bits [4:2] define the low power state  bit [5] controls memory clock gating  bit [6] controls controller clock gating  and bit [7] controls lock. WRITE-ONLY"
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bitfld.long 0x110 0.--1. "LOWPOWER_REFRESH_ENABLE,Enable refreshes while in low power mode. Bit [0] controls cs0  bit [1] controls cs1  etc. Set each bit to 1 to disable." "0,1,2,3"
line.long 0x114 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_159,"
hexmask.long.byte 0x114 24.--27. 1. "LPI_SRPD_SHORT_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh power-down short state [with or without memory clock gating]. FC=0"
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hexmask.long.byte 0x114 16.--19. 1. "LPI_PD_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in any of the power-down states [with or without memory clock gating]. FC=0"
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hexmask.long.byte 0x114 8.--11. 1. "LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh long with memory and controller clock gating state. FC=0"
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hexmask.long.byte 0x114 0.--3. 1. "LPI_SR_LONG_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh long state [with or without memory clock gating]. FC=0"
line.long 0x118 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_160,"
hexmask.long.byte 0x118 24.--27. 1. "LPI_IDLE_WAKEUP_F1,Defines the DFI tLP_CTRL_WAKEUP timing parameter [in DFI clocks] to be driven when controller is idle. FC=1"
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hexmask.long.byte 0x118 16.--19. 1. "LPI_TIMER_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when the LPI timer expires. FC=0"
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hexmask.long.byte 0x118 8.--11. 1. "LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh power-down long with memory and controller clock gating state. FC=0"
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hexmask.long.byte 0x118 0.--3. 1. "LPI_SRPD_LONG_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh power-down long state [with or without memory clock gating]. FC=0"
line.long 0x11C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_161,"
hexmask.long.byte 0x11C 24.--27. 1. "LPI_PD_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in any of the power-down states [with or without memory clock gating]. FC=1"
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hexmask.long.byte 0x11C 16.--19. 1. "LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh long with memory and controller clock gating state. FC=1"
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hexmask.long.byte 0x11C 8.--11. 1. "LPI_SR_LONG_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh long state [with or without memory clock gating]. FC=1"
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hexmask.long.byte 0x11C 0.--3. 1. "LPI_SR_SHORT_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when LPDDR4 memory is in the self-refresh short state [with or without memory clock gating]. For LPDDR4  SR_SHORT is used to send few commands so this wakeup.."
line.long 0x120 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_162,"
hexmask.long.byte 0x120 24.--27. 1. "LPI_TIMER_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when the LPI timer expires. FC=1"
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hexmask.long.byte 0x120 16.--19. 1. "LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh power-down long with memory and controller clock gating state. FC=1"
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hexmask.long.byte 0x120 8.--11. 1. "LPI_SRPD_LONG_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh power-down long state [with or without memory clock gating]. FC=1"
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hexmask.long.byte 0x120 0.--3. 1. "LPI_SRPD_SHORT_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh power-down short state [with or without memory clock gating]. FC=1"
line.long 0x124 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_163,"
hexmask.long.byte 0x124 24.--27. 1. "LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh long with memory and controller clock gating state. FC=2"
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hexmask.long.byte 0x124 16.--19. 1. "LPI_SR_LONG_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh long state [with or without memory clock gating]. FC=2"
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hexmask.long.byte 0x124 8.--11. 1. "LPI_SR_SHORT_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when LPDDR4 memory is in the self-refresh short state [with or without memory clock gating]. For LPDDR4  SR_SHORT is used to send few commands so this wakeup.."
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hexmask.long.byte 0x124 0.--3. 1. "LPI_IDLE_WAKEUP_F2,Defines the DFI tLP_CTRL_WAKEUP timing parameter [in DFI clocks] to be driven when controller is idle. FC=2"
line.long 0x128 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_164,"
hexmask.long.byte 0x128 24.--27. 1. "LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh power-down long with memory and controller clock gating state. FC=2"
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hexmask.long.byte 0x128 16.--19. 1. "LPI_SRPD_LONG_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh power-down long state [with or without memory clock gating]. FC=2"
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hexmask.long.byte 0x128 8.--11. 1. "LPI_SRPD_SHORT_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in the self-refresh power-down short state [with or without memory clock gating]. FC=2"
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hexmask.long.byte 0x128 0.--3. 1. "LPI_PD_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when memory is in any of the power-down states [with or without memory clock gating]. FC=2"
line.long 0x12C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_165,"
bitfld.long 0x12C 16. "LPI_CTRL_REQ_EN,Enables the dfi_lpi_ctrl_req signal for the LPI. This signal is only relevant for DFI versions 3.1 and beyond. Set to 1 to enable or clear to 0 to disable." "0,1"
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hexmask.long.byte 0x12C 8.--13. 1. "LPI_WAKEUP_EN,Enables the various low power state wakeup parameters for LPI request uses. Bit [0] enables controller idle wakeup  bit [1] enables power-down wakeup  bit [2] enables either self-refresh short  self-refresh long with or without mem clk.."
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hexmask.long.byte 0x12C 0.--3. 1. "LPI_TIMER_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter [in DFI clocks] to be driven when the LPI timer expires. FC=2"
line.long 0x130 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_166,"
hexmask.long.word 0x130 16.--27. 1. "LPI_WAKEUP_TIMEOUT,Defines the LPI timeout time  the maximum cycles between a dfi_lp_req de-assertion and a dfi_lp_ack de-assertion. If this value is exceeded  an interrupt will occur."
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hexmask.long.word 0x130 0.--11. 1. "LPI_TIMER_COUNT,Defines the LPI timer count."
line.long 0x134 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_167,"
hexmask.long.byte 0x134 24.--27. 1. "LP_AUTO_EXIT_EN,Enable auto exit from each of the low power states when a read or write command enters the command queue. Bit [0] controls power-down  bit [1] controls self-refresh long or self-refresh power-down long  bit [2] controls self-refresh long.."
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hexmask.long.byte 0x134 16.--19. 1. "LP_AUTO_ENTRY_EN,Enable auto entry into each of the low power states when the associated idle timer expires. Bit [0] controls power-down  bit [1] controls self-refresh long or self-refresh power-down long  bit [2] controls self-refresh long with memory.."
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hexmask.long.byte 0x134 8.--14. 1. "LP_STATE,Low power state status parameter. Bits [5:0] indicate the current low power state and bit [6] set indicates that status bits are valid. READ-ONLY"
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bitfld.long 0x134 0.--2. "TDFI_LP_RESP,Defines the DFI tLP_RESP timing parameter [in DFI clocks]  the maximum cycles between a dfi_lp_req assertion and a dfi_lp_ack assertion." "0,1,2,3,4,5,6,7"
line.long 0x138 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_168,"
hexmask.long.word 0x138 8.--19. 1. "LP_AUTO_PD_IDLE,Defines the idle time [in controller clocks] until the controller will automatically issue an entry into one of the power-down low power states."
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bitfld.long 0x138 0.--2. "LP_AUTO_MEM_GATE_EN,Enable memory clock gating when entering a low power state via the auto low power counters. Bit [0] controls power-down  bit [1] controls self-refresh long or self-refresh power-down long  and bit [2] controls self-refresh short or.." "0,1,2,3,4,5,6,7"
line.long 0x13C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_169,"
hexmask.long.byte 0x13C 24.--31. 1. "LP_AUTO_SR_LONG_MC_GATE_IDLE,Defines the idle time [in long counts] until the controller will automatically issue an entry into the self-refresh long with memory and controller clock gating or self-refresh power-down long with memory and controller clock.."
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hexmask.long.byte 0x13C 16.--23. 1. "LP_AUTO_SR_LONG_IDLE,Defines the idle time [in long counts] until the controller will automatically issue an entry into the self-refresh long or self-refresh power-down long [with or without memory clock gating] low power states."
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hexmask.long.word 0x13C 0.--11. 1. "LP_AUTO_SR_SHORT_IDLE,Defines the idle time [in controller clocks] until the controller will automatically issue an entry into the self-refresh short or self-refresh power-down short [with or without memory clock gating] low power states."
line.long 0x140 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_170,"
hexmask.long.word 0x140 16.--31. 1. "HW_PROMOTE_THRESHOLD_F1,HW interface promotion number of long counts until the high priority request is asserted. FC=1"
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hexmask.long.word 0x140 0.--15. 1. "HW_PROMOTE_THRESHOLD_F0,HW interface promotion number of long counts until the high priority request is asserted. FC=0"
line.long 0x144 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_171,"
hexmask.long.word 0x144 16.--31. 1. "LPC_PROMOTE_THRESHOLD_F0,LPC promotion number of long counts until the high priority request is asserted for frequency copy 2. Applies to SW and auto low power commands. FC=0"
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hexmask.long.word 0x144 0.--15. 1. "HW_PROMOTE_THRESHOLD_F2,HW interface promotion number of long counts until the high priority request is asserted. FC=2"
line.long 0x148 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_172,"
hexmask.long.word 0x148 16.--31. 1. "LPC_PROMOTE_THRESHOLD_F2,LPC promotion number of long counts until the high priority request is asserted for frequency copy 2. Applies to SW and auto low power commands. FC=2"
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hexmask.long.word 0x148 0.--15. 1. "LPC_PROMOTE_THRESHOLD_F1,LPC promotion number of long counts until the high priority request is asserted for frequency copy 2. Applies to SW and auto low power commands. FC=1"
line.long 0x14C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_173,"
bitfld.long 0x14C 24. "LPC_SR_EXIT_CMD_EN,Enable LPC to execute any of the commands on self-refresh exit while exiting. Set to 1 to enable." "0,1"
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bitfld.long 0x14C 16. "LPC_SR_PHYMSTR_EN,Enable LPC to execute a DFI PHY Master request on a self-refresh exit sequence. Set to 1 to enable." "0,1"
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bitfld.long 0x14C 8. "LPC_SR_PHYUPD_EN,Enable LPC to execute a DFI PHY update on a self-refresh exit sequence. Set to 1 to enable." "0,1"
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bitfld.long 0x14C 0. "LPC_SR_CTRLUPD_EN,Enable LPC to execute a DFI control update on a self-refresh exit sequence. Set to 1 to enable." "0,1"
line.long 0x150 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_174,"
bitfld.long 0x150 24. "DFS_ENABLE,Enable hardware dynamic frequency scaling. Set to 1 to enable." "0,1"
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hexmask.long.word 0x150 8.--16. 1. "PWRDN_SHIFT_DELAY,This parameter should be programmed to zero. Manual adjustment of inhibit_pwrdn_shift in memcd_strategy_data_delay."
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bitfld.long 0x150 0. "LPC_SR_ZQ_EN,Enable LPC to execute a ZQ calibration on a self-refresh exit sequence. Set to 1 to enable." "0,1"
line.long 0x154 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_175,"
bitfld.long 0x154 8. "DFS_PHY_REG_WRITE_EN,Enable a register write to the PHY during a frequency change. Set to 1 to enable." "0,1"
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bitfld.long 0x154 0.--2. "DFS_DLL_OFF,Defines if the memory DLL must be off for the associated frequency set. Bit [0] corresponds to frequency set 0  bit [1] corresponds to frequency set 1  etc. Set each bit to 1 to require DLL off." "0,1,2,3,4,5,6,7"
line.long 0x158 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_176,"
hexmask.long 0x158 0.--31. 1. "DFS_PHY_REG_WRITE_ADDR,Register address which will be written during a frequency change. Must be a PHY register address."
line.long 0x15C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_177,"
rbitfld.long 0x15C 24.--25. "CURRENT_REG_COPY,Indicates the current copy of timing parameters that is in use by the controller." "0,1,2,3"
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hexmask.long.word 0x15C 8.--23. 1. "DFS_PHY_REG_WRITE_WAIT,Defines the number of DFI PHY clocks that the controller will wait after issuing the register write to the PHY during a frequency change."
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hexmask.long.byte 0x15C 0.--3. 1. "DFS_PHY_REG_WRITE_MASK,Register mask which will be written during a frequency change."
line.long 0x160 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_178,"
bitfld.long 0x160 8.--9. "DFIBUS_BOOT_FREQ,Defines the DFI bus boot frequency register copy" "0,1,2,3"
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bitfld.long 0x160 0.--1. "INIT_FREQ,Specifies what frequency register copy will be in use by the memory after initialization completes." "0,1,2,3"
line.long 0x164 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_179,"
hexmask.long 0x164 0.--31. 1. "DFS_PHY_REG_WRITE_DATA_F0,Register data which will be written during a frequency change. FC=0"
line.long 0x168 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_180,"
hexmask.long 0x168 0.--31. 1. "DFS_PHY_REG_WRITE_DATA_F1,Register data which will be written during a frequency change. FC=1"
line.long 0x16C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_181,"
hexmask.long 0x16C 0.--31. 1. "DFS_PHY_REG_WRITE_DATA_F2,Register data which will be written during a frequency change. FC=2"
line.long 0x170 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_182,"
hexmask.long.tbyte 0x170 0.--23. 1. "TDFI_INIT_START_F0,Defines the DFI tINIT_START timing parameter [in DFI clocks]  the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY. FC=0"
line.long 0x174 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_183,"
hexmask.long.tbyte 0x174 0.--23. 1. "TDFI_INIT_COMPLETE_F0,Defines the DFI tINIT_COMPLETE timing parameter [in DFI clocks]  the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY. FC=0"
line.long 0x178 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_184,"
hexmask.long.tbyte 0x178 0.--23. 1. "TDFI_INIT_START_F1,Defines the DFI tINIT_START timing parameter [in DFI clocks]  the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY. FC=1"
line.long 0x17C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_185,"
hexmask.long.tbyte 0x17C 0.--23. 1. "TDFI_INIT_COMPLETE_F1,Defines the DFI tINIT_COMPLETE timing parameter [in DFI clocks]  the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY. FC=1"
line.long 0x180 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_186,"
hexmask.long.tbyte 0x180 0.--23. 1. "TDFI_INIT_START_F2,Defines the DFI tINIT_START timing parameter [in DFI clocks]  the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY. FC=2"
line.long 0x184 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_187,"
hexmask.long.tbyte 0x184 0.--23. 1. "TDFI_INIT_COMPLETE_F2,Defines the DFI tINIT_COMPLETE timing parameter [in DFI clocks]  the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY. FC=2"
line.long 0x188 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_188,"
hexmask.long 0x188 0.--26. 1. "WRITE_MODEREG,Write memory mode register data to the DRAMs. Bits [7:0] define the memory mode register number if bit [23] is set  bits [15:8] define the chip select if bit [24] is clear  bits [23:16] define which memory mode register/s to write  bit [24].."
line.long 0x18C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_189,"
hexmask.long.tbyte 0x18C 8.--24. 1. "READ_MODEREG,Read the specified memory mode register from specified chip when start bit set. Bits [7:0] define the memory mode register and bits [15:8] define the chip select. Set bit [16] to 1 to trigger."
newline
hexmask.long.byte 0x18C 0.--7. 1. "MRW_STATUS,Write memory mode register status. Bit [0] set indicates a WRITE_MODEREG parameter programming error. Bit [1] set indicates a PASR error. Bit [2] is Reserved. Bit [3] set indicates a self-refresh or deep power-down error. Bit [4] set indicates.."
rgroup.long 0x2F8++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_190,"
hexmask.long.byte 0x0 24.--31. 1. "AUTO_TEMPCHK_VAL_0,MR4 data for all devices accessed by automatic MRR commands. Bits [3:0] correlate to the device on the lower byte  bits [7:4] correlate to the devices on the 2nd byte etc. Value indicates the OP7  OP2  OP1 and OP0 bits. READ-ONLY."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "PERIPHERAL_MRR_DATA,Data and chip returned from memory mode register read requested by the READ_MODEREG parameter. Bits [7:0] indicate the read data and bits [15:8] indicate the chip. READ-ONLY"
group.long 0x2FC++0x23B
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_191,"
bitfld.long 0x0 16.--17. "MRW_DFS_UPDATE_FRC,Defines the frequency register set to use when doing a software MRW with WRITE_MODEREG bit [26]." "0,1,2,3"
newline
bitfld.long 0x0 8. "DISABLE_UPDATE_TVRCG,Bypass changing for TVRCG during a DFS operation. Set to 1 to skip TVRCG." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "AUTO_TEMPCHK_VAL_1,MR4 data for all devices accessed by automatic MRR commands. Bits [3:0] correlate to the device on the lower byte  bits [7:4] correlate to the devices on the 2nd byte etc. Value indicates the OP7  OP2  OP1 and OP0 bits. READ-ONLY."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_192,"
hexmask.long.word 0x4 16.--25. 1. "TVRCG_DISABLE_F0,JEDEC TVRCG_DISABLE time. FC=0"
newline
hexmask.long.word 0x4 0.--9. 1. "TVRCG_ENABLE_F0,JEDEC TVRCG_ENABLE time. FC=0"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_193,"
hexmask.long.byte 0x8 24.--28. 1. "TCKFSPX_F0,JEDEC TCKFSPX  the frequency set point switching time. FC=0"
newline
hexmask.long.byte 0x8 16.--20. 1. "TCKFSPE_F0,JEDEC TCKFSPE  the frequency set point switching time. FC=0"
newline
hexmask.long.word 0x8 0.--9. 1. "TFC_F0,JEDEC TFC  the frequency set point switching time. FC=0"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_194,"
hexmask.long.tbyte 0xC 0.--19. 1. "TVREF_LONG_F0,JEDEC TVREF  design will always use the long value. FC=0"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_195,"
hexmask.long.word 0x10 16.--25. 1. "TVRCG_DISABLE_F1,JEDEC TVRCG_DISABLE time. FC=1"
newline
hexmask.long.word 0x10 0.--9. 1. "TVRCG_ENABLE_F1,JEDEC TVRCG_ENABLE time. FC=1"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_196,"
hexmask.long.byte 0x14 24.--28. 1. "TCKFSPX_F1,JEDEC TCKFSPX  the frequency set point switching time. FC=1"
newline
hexmask.long.byte 0x14 16.--20. 1. "TCKFSPE_F1,JEDEC TCKFSPE  the frequency set point switching time. FC=1"
newline
hexmask.long.word 0x14 0.--9. 1. "TFC_F1,JEDEC TFC  the frequency set point switching time. FC=1"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_197,"
hexmask.long.tbyte 0x18 0.--19. 1. "TVREF_LONG_F1,JEDEC TVREF  design will always use the long value. FC=1"
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_198,"
hexmask.long.word 0x1C 16.--25. 1. "TVRCG_DISABLE_F2,JEDEC TVRCG_DISABLE time. FC=2"
newline
hexmask.long.word 0x1C 0.--9. 1. "TVRCG_ENABLE_F2,JEDEC TVRCG_ENABLE time. FC=2"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_199,"
hexmask.long.byte 0x20 24.--28. 1. "TCKFSPX_F2,JEDEC TCKFSPX  the frequency set point switching time. FC=2"
newline
hexmask.long.byte 0x20 16.--20. 1. "TCKFSPE_F2,JEDEC TCKFSPE  the frequency set point switching time. FC=2"
newline
hexmask.long.word 0x20 0.--9. 1. "TFC_F2,JEDEC TFC  the frequency set point switching time. FC=2"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_200,"
hexmask.long.tbyte 0x24 0.--19. 1. "TVREF_LONG_F2,JEDEC TVREF  design will always use the long value. FC=2"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_201,"
hexmask.long.word 0x28 16.--31. 1. "MRR_PROMOTE_THRESHOLD_F1,MRR promotion number of long counts until the high priority request is asserted. Applies to SW MRR commands. FC=1"
newline
hexmask.long.word 0x28 0.--15. 1. "MRR_PROMOTE_THRESHOLD_F0,MRR promotion number of long counts until the high priority request is asserted. Applies to SW MRR commands. FC=0"
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_202,"
hexmask.long.word 0x2C 16.--31. 1. "MRW_PROMOTE_THRESHOLD_F0,MRW promotion number of long counts until the high priority request is asserted. Applies to SW MRW commands. FC=0"
newline
hexmask.long.word 0x2C 0.--15. 1. "MRR_PROMOTE_THRESHOLD_F2,MRR promotion number of long counts until the high priority request is asserted. Applies to SW MRR commands. FC=2"
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_203,"
hexmask.long.word 0x30 16.--31. 1. "MRW_PROMOTE_THRESHOLD_F2,MRW promotion number of long counts until the high priority request is asserted. Applies to SW MRW commands. FC=2"
newline
hexmask.long.word 0x30 0.--15. 1. "MRW_PROMOTE_THRESHOLD_F1,MRW promotion number of long counts until the high priority request is asserted. Applies to SW MRW commands. FC=1"
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_204,"
hexmask.long.tbyte 0x34 8.--24. 1. "MR0_DATA_F0_0,Data to program into memory mode register 0. FC=0"
newline
bitfld.long 0x34 0. "MR4_DLL_RST,Asserted if DRAM DLL Reset bit resides in MR4." "0,1"
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_205,"
hexmask.long.tbyte 0x38 0.--16. 1. "MR1_DATA_F0_0,Data to program into memory mode register 1. FC=0"
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_206,"
hexmask.long.tbyte 0x3C 0.--16. 1. "MR2_DATA_F0_0,Data to program into memory mode register 2. FC=0"
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_207,"
hexmask.long.tbyte 0x40 0.--16. 1. "MR0_DATA_F1_0,Data to program into memory mode register 0. FC=1"
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_208,"
hexmask.long.tbyte 0x44 0.--16. 1. "MR1_DATA_F1_0,Data to program into memory mode register 1. FC=1"
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_209,"
hexmask.long.tbyte 0x48 0.--16. 1. "MR2_DATA_F1_0,Data to program into memory mode register 2. FC=1"
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_210,"
hexmask.long.tbyte 0x4C 0.--16. 1. "MR0_DATA_F2_0,Data to program into memory mode register 0. FC=2"
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_211,"
hexmask.long.tbyte 0x50 0.--16. 1. "MR1_DATA_F2_0,Data to program into memory mode register 1. FC=2"
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_212,"
hexmask.long.tbyte 0x54 0.--16. 1. "MR2_DATA_F2_0,Data to program into memory mode register 2. FC=2"
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_213,"
hexmask.long.tbyte 0x58 0.--16. 1. "MR0_DATA_F0_1,Data to program into memory mode register 0. FC=0"
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_214,"
hexmask.long.tbyte 0x5C 0.--16. 1. "MR1_DATA_F0_1,Data to program into memory mode register 1. FC=0"
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_215,"
hexmask.long.tbyte 0x60 0.--16. 1. "MR2_DATA_F0_1,Data to program into memory mode register 2. FC=0"
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_216,"
hexmask.long.tbyte 0x64 0.--16. 1. "MR0_DATA_F1_1,Data to program into memory mode register 0. FC=1"
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_217,"
hexmask.long.tbyte 0x68 0.--16. 1. "MR1_DATA_F1_1,Data to program into memory mode register 1. FC=1"
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_218,"
hexmask.long.tbyte 0x6C 0.--16. 1. "MR2_DATA_F1_1,Data to program into memory mode register 2. FC=1"
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_219,"
hexmask.long.tbyte 0x70 0.--16. 1. "MR0_DATA_F2_1,Data to program into memory mode register 0. FC=2"
line.long 0x74 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_220,"
hexmask.long.tbyte 0x74 0.--16. 1. "MR1_DATA_F2_1,Data to program into memory mode register 1. FC=2"
line.long 0x78 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_221,"
hexmask.long.tbyte 0x78 0.--16. 1. "MR2_DATA_F2_1,Data to program into memory mode register 2. FC=2"
line.long 0x7C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_222,"
hexmask.long.tbyte 0x7C 0.--16. 1. "MRSINGLE_DATA_0,Data to program into memory mode register single write."
line.long 0x80 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_223,"
hexmask.long.tbyte 0x80 0.--16. 1. "MRSINGLE_DATA_1,Data to program into memory mode register single write."
line.long 0x84 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_224,"
hexmask.long.tbyte 0x84 0.--16. 1. "MR3_DATA_F0_0,Data to program into memory mode register 3. FC=0"
line.long 0x88 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_225,"
hexmask.long.tbyte 0x88 0.--16. 1. "MR3_DATA_F1_0,Data to program into memory mode register 3. FC=1"
line.long 0x8C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_226,"
hexmask.long.tbyte 0x8C 0.--16. 1. "MR3_DATA_F2_0,Data to program into memory mode register 3. FC=2"
line.long 0x90 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_227,"
hexmask.long.tbyte 0x90 0.--16. 1. "MR3_DATA_F0_1,Data to program into memory mode register 3. FC=0"
line.long 0x94 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_228,"
hexmask.long.tbyte 0x94 0.--16. 1. "MR3_DATA_F1_1,Data to program into memory mode register 3. FC=1"
line.long 0x98 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_229,"
hexmask.long.tbyte 0x98 0.--16. 1. "MR3_DATA_F2_1,Data to program into memory mode register 3. FC=2"
line.long 0x9C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_230,"
hexmask.long.tbyte 0x9C 0.--16. 1. "MR4_DATA_F0_0,Data to program into memory mode register 4. FC=0"
line.long 0xA0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_231,"
hexmask.long.tbyte 0xA0 0.--16. 1. "MR4_DATA_F1_0,Data to program into memory mode register 4. FC=1"
line.long 0xA4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_232,"
hexmask.long.tbyte 0xA4 0.--16. 1. "MR4_DATA_F2_0,Data to program into memory mode register 4. FC=2"
line.long 0xA8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_233,"
hexmask.long.tbyte 0xA8 0.--16. 1. "MR4_DATA_F0_1,Data to program into memory mode register 4. FC=0"
line.long 0xAC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_234,"
hexmask.long.tbyte 0xAC 0.--16. 1. "MR4_DATA_F1_1,Data to program into memory mode register 4. FC=1"
line.long 0xB0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_235,"
hexmask.long.tbyte 0xB0 0.--16. 1. "MR4_DATA_F2_1,Data to program into memory mode register 4. FC=2"
line.long 0xB4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_236,"
hexmask.long.tbyte 0xB4 0.--16. 1. "MR5_DATA_F0_0,Data to program into memory mode register 5. FC=0"
line.long 0xB8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_237,"
hexmask.long.tbyte 0xB8 0.--16. 1. "MR5_DATA_F1_0,Data to program into memory mode register 5. FC=1"
line.long 0xBC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_238,"
hexmask.long.tbyte 0xBC 0.--16. 1. "MR5_DATA_F2_0,Data to program into memory mode register 5. FC=2"
line.long 0xC0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_239,"
hexmask.long.tbyte 0xC0 0.--16. 1. "MR5_DATA_F0_1,Data to program into memory mode register 5. FC=0"
line.long 0xC4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_240,"
hexmask.long.tbyte 0xC4 0.--16. 1. "MR5_DATA_F1_1,Data to program into memory mode register 5. FC=1"
line.long 0xC8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_241,"
hexmask.long.tbyte 0xC8 0.--16. 1. "MR5_DATA_F2_1,Data to program into memory mode register 5. FC=2"
line.long 0xCC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_242,"
hexmask.long.tbyte 0xCC 0.--16. 1. "MR6_DATA_F0_0,Data to program into memory mode register 6. FC=0"
line.long 0xD0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_243,"
hexmask.long.tbyte 0xD0 0.--16. 1. "MR6_DATA_F1_0,Data to program into memory mode register 6. FC=1"
line.long 0xD4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_244,"
hexmask.long.tbyte 0xD4 0.--16. 1. "MR6_DATA_F2_0,Data to program into memory mode register 6. FC=2"
line.long 0xD8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_245,"
hexmask.long.tbyte 0xD8 0.--16. 1. "MR6_DATA_F0_1,Data to program into memory mode register 6. FC=0"
line.long 0xDC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_246,"
hexmask.long.tbyte 0xDC 0.--16. 1. "MR6_DATA_F1_1,Data to program into memory mode register 6. FC=1"
line.long 0xE0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_247,"
hexmask.long.byte 0xE0 24.--31. 1. "MR8_DATA_0,Data to program into memory mode register 8 for each chip select. READ-ONLY."
newline
hexmask.long.tbyte 0xE0 0.--16. 1. "MR6_DATA_F2_1,Data to program into memory mode register 6. FC=2"
line.long 0xE4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_248,"
hexmask.long.tbyte 0xE4 8.--24. 1. "MR10_DATA_F0_0,Data to program into memory mode register 10. FC=0"
newline
hexmask.long.byte 0xE4 0.--7. 1. "MR8_DATA_1,Data to program into memory mode register 8 for each chip select. READ-ONLY."
line.long 0xE8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_249,"
hexmask.long.tbyte 0xE8 0.--16. 1. "MR10_DATA_F1_0,Data to program into memory mode register 10. FC=1"
line.long 0xEC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_250,"
hexmask.long.tbyte 0xEC 0.--16. 1. "MR10_DATA_F2_0,Data to program into memory mode register 10. FC=2"
line.long 0xF0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_251,"
hexmask.long.tbyte 0xF0 0.--16. 1. "MR10_DATA_F0_1,Data to program into memory mode register 10. FC=0"
line.long 0xF4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_252,"
hexmask.long.tbyte 0xF4 0.--16. 1. "MR10_DATA_F1_1,Data to program into memory mode register 10. FC=1"
line.long 0xF8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_253,"
hexmask.long.byte 0xF8 24.--31. 1. "MR11_DATA_F0_0,Data to program into memory mode register 11. FC=0"
newline
hexmask.long.tbyte 0xF8 0.--16. 1. "MR10_DATA_F2_1,Data to program into memory mode register 10. FC=2"
line.long 0xFC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_254,"
hexmask.long.byte 0xFC 24.--31. 1. "MR11_DATA_F1_1,Data to program into memory mode register 11. FC=1"
newline
hexmask.long.byte 0xFC 16.--23. 1. "MR11_DATA_F0_1,Data to program into memory mode register 11. FC=0"
newline
hexmask.long.byte 0xFC 8.--15. 1. "MR11_DATA_F2_0,Data to program into memory mode register 11. FC=2"
newline
hexmask.long.byte 0xFC 0.--7. 1. "MR11_DATA_F1_0,Data to program into memory mode register 11. FC=1"
line.long 0x100 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_255,"
hexmask.long.tbyte 0x100 8.--24. 1. "MR12_DATA_F0_0,Data to program into memory mode register 12. FC=0"
newline
hexmask.long.byte 0x100 0.--7. 1. "MR11_DATA_F2_1,Data to program into memory mode register 11. FC=2"
line.long 0x104 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_256,"
hexmask.long.tbyte 0x104 0.--16. 1. "MR12_DATA_F1_0,Data to program into memory mode register 12. FC=1"
line.long 0x108 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_257,"
hexmask.long.tbyte 0x108 0.--16. 1. "MR12_DATA_F2_0,Data to program into memory mode register 12. FC=2"
line.long 0x10C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_258,"
hexmask.long.tbyte 0x10C 0.--16. 1. "MR12_DATA_F0_1,Data to program into memory mode register 12. FC=0"
line.long 0x110 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_259,"
hexmask.long.tbyte 0x110 0.--16. 1. "MR12_DATA_F1_1,Data to program into memory mode register 12. FC=1"
line.long 0x114 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_260,"
hexmask.long.tbyte 0x114 0.--16. 1. "MR12_DATA_F2_1,Data to program into memory mode register 12. FC=2"
line.long 0x118 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_261,"
hexmask.long.tbyte 0x118 0.--16. 1. "MR13_DATA_0,Data to program into memory mode register 13."
line.long 0x11C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_262,"
hexmask.long.tbyte 0x11C 0.--16. 1. "MR13_DATA_1,Data to program into memory mode register 13."
line.long 0x120 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_263,"
hexmask.long.tbyte 0x120 0.--16. 1. "MR14_DATA_F0_0,Data to program into memory mode register 14. FC=0"
line.long 0x124 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_264,"
hexmask.long.tbyte 0x124 0.--16. 1. "MR14_DATA_F1_0,Data to program into memory mode register 14. FC=1"
line.long 0x128 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_265,"
hexmask.long.tbyte 0x128 0.--16. 1. "MR14_DATA_F2_0,Data to program into memory mode register 14. FC=2"
line.long 0x12C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_266,"
hexmask.long.tbyte 0x12C 0.--16. 1. "MR14_DATA_F0_1,Data to program into memory mode register 14. FC=0"
line.long 0x130 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_267,"
hexmask.long.tbyte 0x130 0.--16. 1. "MR14_DATA_F1_1,Data to program into memory mode register 14. FC=1"
line.long 0x134 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_268,"
hexmask.long.byte 0x134 24.--31. 1. "MR16_DATA_0,Data to program into memory mode register 16."
newline
hexmask.long.tbyte 0x134 0.--16. 1. "MR14_DATA_F2_1,Data to program into memory mode register 14. FC=2"
line.long 0x138 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_269,"
hexmask.long.byte 0x138 24.--31. 1. "MR20_DATA_0,Data to program into memory mode register 20."
newline
hexmask.long.byte 0x138 16.--23. 1. "MR17_DATA_1,Data to program into memory mode register 17."
newline
hexmask.long.byte 0x138 8.--15. 1. "MR17_DATA_0,Data to program into memory mode register 17."
newline
hexmask.long.byte 0x138 0.--7. 1. "MR16_DATA_1,Data to program into memory mode register 16."
line.long 0x13C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_270,"
hexmask.long.tbyte 0x13C 8.--24. 1. "MR22_DATA_F0_0,Data to program into memory mode register 22. FC=0"
newline
hexmask.long.byte 0x13C 0.--7. 1. "MR20_DATA_1,Data to program into memory mode register 20."
line.long 0x140 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_271,"
hexmask.long.tbyte 0x140 0.--16. 1. "MR22_DATA_F1_0,Data to program into memory mode register 22. FC=1"
line.long 0x144 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_272,"
hexmask.long.tbyte 0x144 0.--16. 1. "MR22_DATA_F2_0,Data to program into memory mode register 22. FC=2"
line.long 0x148 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_273,"
hexmask.long.tbyte 0x148 0.--16. 1. "MR22_DATA_F0_1,Data to program into memory mode register 22. FC=0"
line.long 0x14C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_274,"
hexmask.long.tbyte 0x14C 0.--16. 1. "MR22_DATA_F1_1,Data to program into memory mode register 22. FC=1"
line.long 0x150 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_275,"
hexmask.long.tbyte 0x150 0.--16. 1. "MR22_DATA_F2_1,Data to program into memory mode register 22. FC=2"
line.long 0x154 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_276,"
bitfld.long 0x154 24. "MR_FSP_DATA_VALID_F0,Indicates that  at this frequency  memory was trained and the associated data has been loaded into the MRx_DATA parameter[s]. Value of 1 means memory was trained. FC=0" "0,1"
newline
hexmask.long.tbyte 0x154 0.--16. 1. "MR23_DATA,Data to program into memory mode register 23."
line.long 0x158 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_277,"
rbitfld.long 0x158 24. "DFS_FSP_INSYNC_INACTIVE,When cleared  this indicates that the contents in memcd_param is new that the values in memory's MRx FSP reg and if a dfs occurs  they need to be updated. READ-ONLY" "0,1"
newline
rbitfld.long 0x158 16. "DFS_FSP_INSYNC_ACTIVE,When cleared  this indicates that the contents in memcd_param is new that the values in memory's MRx FSP reg and if a dfs occurs  they need to be updated. READ-ONLY" "0,1"
newline
bitfld.long 0x158 8. "MR_FSP_DATA_VALID_F2,Indicates that  at this frequency  memory was trained and the associated data has been loaded into the MRx_DATA parameter[s]. Value of 1 means memory was trained. FC=2" "0,1"
newline
bitfld.long 0x158 0. "MR_FSP_DATA_VALID_F1,Indicates that  at this frequency  memory was trained and the associated data has been loaded into the MRx_DATA parameter[s]. Value of 1 means memory was trained. FC=1" "0,1"
line.long 0x15C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_278,"
bitfld.long 0x15C 24. "FSP_OP_CURRENT,Reports which FSP set the memory is currently using." "0,1"
newline
bitfld.long 0x15C 16. "FSP_STATUS,Indicates that a DFS event caused the FSP mode registers to be updated. Value of 1 means that the FSP mode registers were changed." "0,1"
newline
bitfld.long 0x15C 8. "DFS_ALWAYS_WRITE_FSP,Forces all FSP mode registers to be written by the controller during a DFS event. Set to 1 to force the write." "0,1"
newline
bitfld.long 0x15C 0. "FSP_PHY_UPDATE_MRW,Identifies the logic responsible for updating MR12 and MR14 in memory. Clear to 0 for the controller  or set to 1 for the PHY or PI." "0,1"
line.long 0x160 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_279,"
bitfld.long 0x160 24.--25. "FSP0_FRC,Identifies which of the controller's frequency copy is associated with FSP0." "0,1,2,3"
newline
bitfld.long 0x160 16. "FSP1_FRC_VALID,Specifies whether the FSP set defined in the FSP1_FRC parameter reflects the frequency used to program the FSP1 registers." "0,1"
newline
bitfld.long 0x160 8. "FSP0_FRC_VALID,Specifies whether the FSP set defined in the FSP0_FRC parameter reflects the frequency used to program the FSP0 registers." "0,1"
newline
bitfld.long 0x160 0. "FSP_WR_CURRENT,Reports which FSP set the memory will target with write commands." "0,1"
line.long 0x164 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_280,"
hexmask.long.byte 0x164 24.--29. 1. "ADDR_SPACE,Sets the number of address bits to check during BIST operation."
newline
rbitfld.long 0x164 16.--17. "BIST_RESULT,BIST operation status [pass/fail]. Bit [0] indicates data check status and bit [1] indicates address check status. Value of 1 is a passing result. READ-ONLY" "0,1,2,3"
newline
bitfld.long 0x164 8. "BIST_GO,Initiate a BIST operation. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x164 0.--1. "FSP1_FRC,Identifies which of the controller's frequency copy is associated with FSP1." "0,1,2,3"
line.long 0x168 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_281,"
bitfld.long 0x168 8. "BIST_ADDR_CHECK,Enable address checking with BIST operation. Set to 1 to enable." "0,1"
newline
bitfld.long 0x168 0. "BIST_DATA_CHECK,Enable data checking with BIST operation. Set to 1 to enable." "0,1"
line.long 0x16C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_282,"
hexmask.long 0x16C 0.--31. 1. "BIST_START_ADDRESS_0,Start BIST checking at this address."
line.long 0x170 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_283,"
bitfld.long 0x170 0. "BIST_START_ADDRESS_1,Start BIST checking at this address." "0,1"
line.long 0x174 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_284,"
hexmask.long 0x174 0.--31. 1. "BIST_DATA_MASK,Mask applied to data for BIST error checking. Bit [0] controls memory data path bit [0]  bit [1] controls memory data path bit [1]  etc. Set each bit to 1 to mask."
line.long 0x178 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_285,"
bitfld.long 0x178 0.--2. "BIST_TEST_MODE,Sets the BIST test mode. Value of 0 specifies standard BIST operation  value of 1 specifies a reduced BIST operation  value of 2 specifies a self-refresh retention test  value of 3 specifies an idle retention test  and value of 4 specifies.." "0,1,2,3,4,5,6,7"
line.long 0x17C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_286,"
hexmask.long 0x17C 0.--31. 1. "BIST_DATA_PATTERN_0,Data pattern to be used when the BIST_TEST_MODE parameter is programmed to 1  2  3 or 4. Only data corresponding to active portion of core word will be used while inactive portion will be ignored."
line.long 0x180 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_287,"
hexmask.long 0x180 0.--31. 1. "BIST_DATA_PATTERN_1,Data pattern to be used when the BIST_TEST_MODE parameter is programmed to 1  2  3 or 4. Only data corresponding to active portion of core word will be used while inactive portion will be ignored."
line.long 0x184 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_288,"
hexmask.long.word 0x184 8.--19. 1. "BIST_ERR_STOP,Defines the maximum number of error occurrences allowed prior to quitting when the BIST_TEST_MODE parameter is programmed to 1  2 or 3. A value of 0 will allow the test to run to completion."
newline
rbitfld.long 0x184 0. "BIST_RET_STATE,Indicates if BIST is in a retention wait state  used when the BIST_TEST_MODE parameter is programmed to 2 or 3. Value of 1 indicates BIST is waiting. READ-ONLY" "0,1"
line.long 0x188 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_289,"
hexmask.long.byte 0x188 24.--28. 1. "LONG_COUNT_MASK,Reduces the length of the long counter from 1024 cycles. The only supported values are 0x00 [1024 cycles]  0x10 [512 clocks]  0x18 [256 clocks]  0x1C [128 clocks]  0x1E [64 clocks] and 0x1F [32 clocks]."
newline
bitfld.long 0x188 16. "BIST_RET_STATE_EXIT,Exit self-refresh or idle retention state  used when the BIST_TEST_MODE parameter is programmed to 2 or 3. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
hexmask.long.word 0x188 0.--11. 1. "BIST_ERR_COUNT,Indicates the number of BIST errors found when the BIST_TEST_MODE parameter is programmed to 1  2 or 3. READ-ONLY"
line.long 0x18C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_290,"
hexmask.long.byte 0x18C 24.--28. 1. "AREF_MAX_CREDIT,AREF number of posted refreshes until the maximum number of refresh credits has been reached."
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hexmask.long.byte 0x18C 16.--20. 1. "AREF_MAX_DEFICIT,AREF number of pending refreshes until the maximum number of refreshes has been exceeded."
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hexmask.long.byte 0x18C 8.--12. 1. "AREF_HIGH_THRESHOLD,AREF number of pending refreshes until the high priority request is asserted."
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hexmask.long.byte 0x18C 0.--4. 1. "AREF_NORM_THRESHOLD,AREF number of pending refreshes until the normal priority request is asserted."
line.long 0x190 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_291,"
hexmask.long.word 0x190 16.--31. 1. "ZQ_CALSTART_NORM_THRESHOLD_F0,ZQ START number of long counts until the normal priority request is asserted. This value should be scaled based on the number of ranks [chip selects] the controller handles. The more chip selects there are  the more.."
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bitfld.long 0x190 8.--10. "ZQCS_OPT_THRESHOLD,Number of clocks before ZQCS expires when the ZQ task will deassert its request for optimal command to command turn-around timing." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x190 0.--3. 1. "AREF_CMD_MAX_PER_TREFI,Sets the maximum number of auto-refreshes that will be executed in a TREFI period - both normal and high priority. This does not prevent refreshes generated by sub-task requests such as a self-refresh exit and enter."
line.long 0x194 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_292,"
hexmask.long.word 0x194 16.--31. 1. "ZQ_CALLATCH_HIGH_THRESHOLD_F0,ZQ LATCH number of long counts until the high priority request is asserted. FC=0"
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hexmask.long.word 0x194 0.--15. 1. "ZQ_CALSTART_HIGH_THRESHOLD_F0,ZQ START number of long counts until the high priority request is asserted. FC=0"
line.long 0x198 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_293,"
hexmask.long.word 0x198 16.--31. 1. "ZQ_CS_HIGH_THRESHOLD_F0,ZQ CS number of long counts until the high priority request is asserted. FC=0"
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hexmask.long.word 0x198 0.--15. 1. "ZQ_CS_NORM_THRESHOLD_F0,ZQ CS number of long counts until the normal priority request is asserted. FC=0"
line.long 0x19C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_294,"
hexmask.long.word 0x19C 16.--31. 1. "ZQ_CALLATCH_TIMEOUT_F0,ZQ LATCH number of long counts until the timeout is asserted. FC=0"
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hexmask.long.word 0x19C 0.--15. 1. "ZQ_CALSTART_TIMEOUT_F0,ZQ START number of long counts until the timeout is asserted. FC=0"
line.long 0x1A0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_295,"
hexmask.long.word 0x1A0 16.--31. 1. "ZQ_PROMOTE_THRESHOLD_F0,ZQ SW promotion number of long counts until the high priority request is asserted. FC=0"
newline
hexmask.long.word 0x1A0 0.--15. 1. "ZQ_CS_TIMEOUT_F0,ZQ CS number of long counts until the timeout is asserted. FC=0"
line.long 0x1A4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_296,"
hexmask.long.word 0x1A4 16.--31. 1. "ZQ_CALSTART_HIGH_THRESHOLD_F1,ZQ START number of long counts until the high priority request is asserted. FC=1"
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hexmask.long.word 0x1A4 0.--15. 1. "ZQ_CALSTART_NORM_THRESHOLD_F1,ZQ START number of long counts until the normal priority request is asserted. This value should be scaled based on the number of ranks [chip selects] the controller handles. The more chip selects there are  the more.."
line.long 0x1A8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_297,"
hexmask.long.word 0x1A8 16.--31. 1. "ZQ_CS_NORM_THRESHOLD_F1,ZQ CS number of long counts until the normal priority request is asserted. FC=1"
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hexmask.long.word 0x1A8 0.--15. 1. "ZQ_CALLATCH_HIGH_THRESHOLD_F1,ZQ LATCH number of long counts until the high priority request is asserted. FC=1"
line.long 0x1AC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_298,"
hexmask.long.word 0x1AC 16.--31. 1. "ZQ_CALSTART_TIMEOUT_F1,ZQ START number of long counts until the timeout is asserted. FC=1"
newline
hexmask.long.word 0x1AC 0.--15. 1. "ZQ_CS_HIGH_THRESHOLD_F1,ZQ CS number of long counts until the high priority request is asserted. FC=1"
line.long 0x1B0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_299,"
hexmask.long.word 0x1B0 16.--31. 1. "ZQ_CS_TIMEOUT_F1,ZQ CS number of long counts until the timeout is asserted. FC=1"
newline
hexmask.long.word 0x1B0 0.--15. 1. "ZQ_CALLATCH_TIMEOUT_F1,ZQ LATCH number of long counts until the timeout is asserted. FC=1"
line.long 0x1B4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_300,"
hexmask.long.word 0x1B4 16.--31. 1. "ZQ_CALSTART_NORM_THRESHOLD_F2,ZQ START number of long counts until the normal priority request is asserted. This value should be scaled based on the number of ranks [chip selects] the controller handles. The more chip selects there are  the more.."
newline
hexmask.long.word 0x1B4 0.--15. 1. "ZQ_PROMOTE_THRESHOLD_F1,ZQ SW promotion number of long counts until the high priority request is asserted. FC=1"
line.long 0x1B8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_301,"
hexmask.long.word 0x1B8 16.--31. 1. "ZQ_CALLATCH_HIGH_THRESHOLD_F2,ZQ LATCH number of long counts until the high priority request is asserted. FC=2"
newline
hexmask.long.word 0x1B8 0.--15. 1. "ZQ_CALSTART_HIGH_THRESHOLD_F2,ZQ START number of long counts until the high priority request is asserted. FC=2"
line.long 0x1BC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_302,"
hexmask.long.word 0x1BC 16.--31. 1. "ZQ_CS_HIGH_THRESHOLD_F2,ZQ CS number of long counts until the high priority request is asserted. FC=2"
newline
hexmask.long.word 0x1BC 0.--15. 1. "ZQ_CS_NORM_THRESHOLD_F2,ZQ CS number of long counts until the normal priority request is asserted. FC=2"
line.long 0x1C0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_303,"
hexmask.long.word 0x1C0 16.--31. 1. "ZQ_CALLATCH_TIMEOUT_F2,ZQ LATCH number of long counts until the timeout is asserted. FC=2"
newline
hexmask.long.word 0x1C0 0.--15. 1. "ZQ_CALSTART_TIMEOUT_F2,ZQ START number of long counts until the timeout is asserted. FC=2"
line.long 0x1C4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_304,"
hexmask.long.word 0x1C4 16.--31. 1. "ZQ_PROMOTE_THRESHOLD_F2,ZQ SW promotion number of long counts until the high priority request is asserted. FC=2"
newline
hexmask.long.word 0x1C4 0.--15. 1. "ZQ_CS_TIMEOUT_F2,ZQ CS number of long counts until the timeout is asserted. FC=2"
line.long 0x1C8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_305,"
hexmask.long.word 0x1C8 8.--19. 1. "ZQINIT_F0,Number of cycles needed for a ZQINIT command. FC=0"
newline
hexmask.long.byte 0x1C8 0.--7. 1. "TIMEOUT_TIMER_LOG,Reflects which timers experienced a timeout error [or had an uncleared error] when the timeout interrupt fired. Bit [0] correlates to a ZQ cal init  cs  cl  or reset FM timeout. Bit [1] correlates to the ZQ calstart FM timeout. Bit.."
line.long 0x1CC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_306,"
hexmask.long.word 0x1CC 16.--27. 1. "ZQCS_F0,Number of cycles needed for a ZQCS command. FC=0"
newline
hexmask.long.word 0x1CC 0.--11. 1. "ZQCL_F0,Number of cycles needed for a ZQCL command. FC=0"
line.long 0x1D0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_307,"
hexmask.long.byte 0x1D0 16.--22. 1. "TZQLAT_F0,Holds the DRAM ZQLAT value in cycles. FC=0"
newline
hexmask.long.word 0x1D0 0.--11. 1. "TZQCAL_F0,Holds the DRAM ZQCAL value in cycles. FC=0"
line.long 0x1D4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_308,"
hexmask.long.word 0x1D4 16.--27. 1. "ZQCL_F1,Number of cycles needed for a ZQCL command. FC=1"
newline
hexmask.long.word 0x1D4 0.--11. 1. "ZQINIT_F1,Number of cycles needed for a ZQINIT command. FC=1"
line.long 0x1D8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_309,"
hexmask.long.word 0x1D8 16.--27. 1. "TZQCAL_F1,Holds the DRAM ZQCAL value in cycles. FC=1"
newline
hexmask.long.word 0x1D8 0.--11. 1. "ZQCS_F1,Number of cycles needed for a ZQCS command. FC=1"
line.long 0x1DC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_310,"
hexmask.long.word 0x1DC 8.--19. 1. "ZQINIT_F2,Number of cycles needed for a ZQINIT command. FC=2"
newline
hexmask.long.byte 0x1DC 0.--6. 1. "TZQLAT_F1,Holds the DRAM ZQLAT value in cycles. FC=1"
line.long 0x1E0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_311,"
hexmask.long.word 0x1E0 16.--27. 1. "ZQCS_F2,Number of cycles needed for a ZQCS command. FC=2"
newline
hexmask.long.word 0x1E0 0.--11. 1. "ZQCL_F2,Number of cycles needed for a ZQCL command. FC=2"
line.long 0x1E4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_312,"
bitfld.long 0x1E4 24.--25. "ZQ_SW_REQ_START_LATCH_MAP,Specifies which chip selects will simultaneously receive a ZQ start or latch command once the ZQ_REQ parameter is written with a ZQ Start or ZQ Latch command." "0,1,2,3"
newline
hexmask.long.byte 0x1E4 16.--22. 1. "TZQLAT_F2,Holds the DRAM ZQLAT value in cycles. FC=2"
newline
hexmask.long.word 0x1E4 0.--11. 1. "TZQCAL_F2,Holds the DRAM ZQCAL value in cycles. FC=2"
line.long 0x1E8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_313,"
hexmask.long.word 0x1E8 16.--27. 1. "ZQRESET_F0,Number of cycles needed for a ZQRESET command. FC=0"
newline
rbitfld.long 0x1E8 8. "ZQ_REQ_PENDING,Indicates that a ZQ command is currently in progress or waiting to run. Value of 1 indicates command in progress or waiting to run. When this is asserted  no writes to ZQ_REQ should occur. READ-ONLY" "0,1"
newline
hexmask.long.byte 0x1E8 0.--3. 1. "ZQ_REQ,User request to initiate a ZQ calibration. Program to 3 for ZQ Start  program to 4 for ZQ Initialization [ZQINIT]  program to 5 for ZQ Latch  or program to 8 for ZQ Reset. Clearing to 0 will not trigger any ZQ command. This parameter should only.."
line.long 0x1EC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_314,"
hexmask.long.word 0x1EC 16.--27. 1. "ZQRESET_F2,Number of cycles needed for a ZQRESET command. FC=2"
newline
hexmask.long.word 0x1EC 0.--11. 1. "ZQRESET_F1,Number of cycles needed for a ZQRESET command. FC=1"
line.long 0x1F0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_315,"
bitfld.long 0x1F0 24.--25. "ZQ_CAL_LATCH_MAP_0,Defines which chip select[s] will receive ZQ calibration latch commands simultaneously on iteration 0 of the ZQ LATCH initialization and periodic command sequences. Clear to all zeros for no ZQ LATCH commands. CS=0" "0,1,2,3"
newline
bitfld.long 0x1F0 16.--17. "ZQ_CAL_START_MAP_0,Defines which chip select[s] will receive ZQ calibration start commands simultaneously on iteration 0 of the ZQ START initialization and periodic command sequences. Clear to all zeros for no ZQ START commands. CS=0" "0,1,2,3"
newline
bitfld.long 0x1F0 8. "ZQCS_ROTATE,For memories that perform ZQ short commands [ZQCS]  selects whether a ZQCS command will calibrate just one chip select or all chip selects. When rotation is off  all chip selects will be calibrated  requiring a longer time frame  but ZQ.." "0,1"
newline
bitfld.long 0x1F0 0. "NO_ZQ_INIT,Disable ZQ operations during initialization. Set to 1 to disable." "0,1"
line.long 0x1F4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_316,"
bitfld.long 0x1F4 24.--25. "BANK_DIFF_1,Encoded number of banks on the DRAM[s]." "0,1,2,3"
newline
bitfld.long 0x1F4 16.--17. "BANK_DIFF_0,Encoded number of banks on the DRAM[s]." "0,1,2,3"
newline
bitfld.long 0x1F4 8.--9. "ZQ_CAL_LATCH_MAP_1,Defines which chip select[s] will receive ZQ calibration latch commands simultaneously on iteration 1 of the ZQ LATCH initialization and periodic command sequences. Clear to all zeros for no ZQ LATCH commands. CS=1" "0,1,2,3"
newline
bitfld.long 0x1F4 0.--1. "ZQ_CAL_START_MAP_1,Defines which chip select[s] will receive ZQ calibration start commands simultaneously on iteration 1 of the ZQ START initialization and periodic command sequences. Clear to all zeros for no ZQ START commands. CS=1" "0,1,2,3"
line.long 0x1F8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_317,"
hexmask.long.byte 0x1F8 24.--27. 1. "COL_DIFF_1,Difference between number of column pins available and number being used."
newline
hexmask.long.byte 0x1F8 16.--19. 1. "COL_DIFF_0,Difference between number of column pins available and number being used."
newline
bitfld.long 0x1F8 8.--10. "ROW_DIFF_1,Difference between number of address pins available and number being used." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1F8 0.--2. "ROW_DIFF_0,Difference between number of address pins available and number being used." "0,1,2,3,4,5,6,7"
line.long 0x1FC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_318,"
hexmask.long.word 0x1FC 16.--31. 1. "CS_VAL_UPPER_0,Upper bound address for chip select 0."
newline
hexmask.long.word 0x1FC 0.--15. 1. "CS_VAL_LOWER_0,Lower bound address for chip select 0."
line.long 0x200 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_319,"
hexmask.long.word 0x200 8.--23. 1. "CS_MSK_0,Mask applied to the address decode for chip select 0."
newline
bitfld.long 0x200 0.--1. "ROW_START_VAL_0,Row start value for chip select 0." "0,1,2,3"
line.long 0x204 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_320,"
hexmask.long.word 0x204 16.--31. 1. "CS_VAL_UPPER_1,Upper bound address for chip select 1."
newline
hexmask.long.word 0x204 0.--15. 1. "CS_VAL_LOWER_1,Lower bound address for chip select 1."
line.long 0x208 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_321,"
bitfld.long 0x208 24.--25. "CS_MAP_NON_POW2,Defines which chip selects are non-power-of-2 memory sizes." "0,1,2,3"
newline
hexmask.long.word 0x208 8.--23. 1. "CS_MSK_1,Mask applied to the address decode for chip select 1."
newline
bitfld.long 0x208 0.--1. "ROW_START_VAL_1,Row start value for chip select 1." "0,1,2,3"
line.long 0x20C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_322,"
hexmask.long.byte 0x20C 24.--28. 1. "APREBIT,Location of the auto pre-charge bit in the DRAM address."
newline
bitfld.long 0x20C 0. "CS_LOWER_ADDR_EN,Enables moving the CS field to lower in the address map. When set to 1  the memory address map will be changed to ROW__CS__BANK. Please refer to the limitations before setting this bit." "0,1"
line.long 0x210 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_323,"
bitfld.long 0x210 24. "ADDR_COLLISION_MPM_DIS,Disable address collision detection extension using micro page mask for command queue placement and selection. Set to 1 to disable." "0,1"
newline
bitfld.long 0x210 16. "ADDR_CMP_EN,Enable address collision detection as a rule for command queue placement. Set to 1 to enable." "0,1"
newline
hexmask.long.byte 0x210 8.--15. 1. "COMMAND_AGE_COUNT,Initial value of individual command aging counters for command aging."
newline
hexmask.long.byte 0x210 0.--7. 1. "AGE_COUNT,Initial value of master aging-rate counter for command aging."
line.long 0x214 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_324,"
bitfld.long 0x214 24. "RW_SAME_EN,Enable read/write grouping as a rule for command queue placement. Set to 1 to enable." "0,1"
newline
bitfld.long 0x214 16. "PRIORITY_EN,Enable priority as a rule for command queue placement. Set to 1 to enable." "0,1"
newline
bitfld.long 0x214 8. "PLACEMENT_EN,Enable placement logic for command queue. Set to 1 to enable." "0,1"
newline
bitfld.long 0x214 0. "BANK_SPLIT_EN,Enable bank splitting as a rule for command queue placement. Set to 1 to enable." "0,1"
line.long 0x218 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_325,"
bitfld.long 0x218 24.--25. "DISABLE_RW_GROUP_W_BNK_CONFLICT,Disables placement to read/write group when grouping creates a bank collision. Bit [0] controls placement next to bank conflict command and bit [1] controls placement 2 away from bank conflict command. Set each bit to 1 to.." "0,1,2,3"
newline
bitfld.long 0x218 16. "W2R_SPLIT_EN,Enable splitting of commands to the same chip select from a write to a read command as a rule for command queue placement." "0,1"
newline
bitfld.long 0x218 8. "CS_SAME_EN,Enable chip select grouping when read/write grouping as a rule for command queue placement. This is only valid when the RW_SAME_EN parameter is set. Set to 1 to enable." "0,1"
newline
bitfld.long 0x218 0. "RW_SAME_PAGE_EN,Enable page grouping when read/write grouping as a rule for command queue placement. This is only valid when the RW_SAME_EN parameter is set. Set to 1 to enable." "0,1"
line.long 0x21C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_326,"
bitfld.long 0x21C 24.--25. "INHIBIT_DRAM_CMD,Inhibit command types from being executed from the command queue. Clear to 0 to enable any command  program to 1 to inhibit read/write and bank commands  program to 2 to inhibit MRR and peripheral MRR commands  or program to 3 to inhibit.." "0,1,2,3"
newline
bitfld.long 0x21C 16. "DISABLE_RD_INTERLEAVE,Disable read data interleaving for commands from the same port  regardless of the requestor ID." "0,1"
newline
bitfld.long 0x21C 8. "SWAP_EN,Enable command swapping logic in execution unit. Set to 1 to enable." "0,1"
newline
hexmask.long.byte 0x21C 0.--4. 1. "NUM_Q_ENTRIES_ACT_DISABLE,Number of queue entries in which ACT requests will be disabled. Programming to X will disable ACT requests from the X entries lowest in the command queue."
line.long 0x220 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_327,"
bitfld.long 0x220 24.--26. "MEMDATA_RATIO_0,Defines the ratio of the DRAM device size on chip select 0 to the memory data width. Program with the log2 ratio of the memory data width to the device data width. CS=0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x220 16. "MEM_DP_REDUCTION,Enable the half datapath feature of the controller. Set to 1 to enable." "0,1"
newline
hexmask.long.byte 0x220 8.--11. 1. "BURST_ON_FLY_BIT,Identifies the burst-on-fly bit in the memory mode registers."
newline
bitfld.long 0x220 0.--1. "CS_MAP,Defines which chip selects are active." "0,1,2,3"
line.long 0x224 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_328,"
bitfld.long 0x224 24.--25. "DEVICE0_BYTE0_CS1,Defines the byte location of byte0 in the memory datapath for device 0 on chip 1. Used for MRRs to identify where data will be returned. DEV=0" "0,1,2,3"
newline
bitfld.long 0x224 16.--17. "DEVICE1_BYTE0_CS0,Defines the byte location of byte0 in the memory datapath for device 1 on chip 0. Used for MRRs to identify where data will be returned. DEV=1" "0,1,2,3"
newline
bitfld.long 0x224 8.--9. "DEVICE0_BYTE0_CS0,Defines the byte location of byte0 in the memory datapath for device 0 on chip 0. Used for MRRs to identify where data will be returned. DEV=0" "0,1,2,3"
newline
bitfld.long 0x224 0.--2. "MEMDATA_RATIO_1,Defines the ratio of the DRAM device size on chip select 1 to the memory data width. Program with the log2 ratio of the memory data width to the device data width. CS=1" "0,1,2,3,4,5,6,7"
line.long 0x228 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_329,"
bitfld.long 0x228 24.--25. "WR_ORDER_REQ,Determines if the controller can re-order write commands from the same source ID and/or the same port. Bit [0] controls source ID usage and bit [1] controls port ID usage. Set each bit to 1 to enable usage in placement logic." "0,1,2,3"
newline
bitfld.long 0x228 16. "IN_ORDER_ACCEPT,Forces the controller to accept commands in the order in which they are placed in the command queue." "0,1"
newline
hexmask.long.byte 0x228 8.--12. 1. "Q_FULLNESS,Quantity that determines when the command queue almost full signal will assert [q_almost_full]. When cleared to 0  the q_almost_full signal will be driven to 0 irrespective of number of entries in the command queue."
newline
bitfld.long 0x228 0.--1. "DEVICE1_BYTE0_CS1,Defines the byte location of byte0 in the memory datapath for device 1 on chip 1. Used for MRRs to identify where data will be returned. DEV=1" "0,1,2,3"
line.long 0x22C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_330,"
bitfld.long 0x22C 24. "CTRLUPD_AREF_HP_ENABLE,Enable an automatic controller-initiated update [dfi_ctrlupd_req] after every high priority refresh when executing as a subtask request. Set to 1 to enable." "0,1"
newline
bitfld.long 0x22C 16. "CTRLUPD_REQ_PER_AREF_EN,Enable an automatic controller-initiated update [dfi_ctrlupd_req] after every refresh. Set to 1 to enable." "0,1"
newline
bitfld.long 0x22C 8. "CTRLUPD_REQ,Assert the DFI controller-initiated update request signal dfi_ctrlupd_req. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
rbitfld.long 0x22C 0. "CONTROLLER_BUSY,Indicator that the controller is processing a command. Evaluates all ports for outstanding transactions. Value of 1 indicates controller busy. READ-ONLY" "0,1"
line.long 0x230 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_331,"
bitfld.long 0x230 24. "RD_PREAMBLE_TRAINING_EN,Enable read preamble training during gate training. Set to 1 to enable." "0,1"
newline
bitfld.long 0x230 16.--17. "PREAMBLE_SUPPORT_F2,Selection the preamble for read and write burst transfers. FC=2" "0,1,2,3"
newline
bitfld.long 0x230 8.--9. "PREAMBLE_SUPPORT_F1,Selection the preamble for read and write burst transfers. FC=1" "0,1,2,3"
newline
bitfld.long 0x230 0.--1. "PREAMBLE_SUPPORT_F0,Selection the preamble for read and write burst transfers. FC=0" "0,1,2,3"
line.long 0x234 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_332,"
rbitfld.long 0x234 16.--18. "DFI_ERROR,Indicates that the DFI error flag has been asserted. READ-ONLY" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x234 8. "RD_DBI_EN,Enables controller support of DRAM DBI feature for read data with DDR4 devices. Set to 1 to enable." "0,1"
newline
bitfld.long 0x234 0. "WR_DBI_EN,Enables controller support of DRAM DBI feature for write data with DDR4 devices. Set to 1 to enable." "0,1"
line.long 0x238 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_333,"
bitfld.long 0x238 16. "BG_ROTATE_EN,Enable bank group rotation. Set to 1 to enable." "0,1"
newline
hexmask.long.word 0x238 0.--11. 1. "DFI_ERROR_INFO,Holds the encoded DFI error type associated with the DFI_ERROR parameter assertion. READ-ONLY"
rgroup.long 0x538++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_334,"
hexmask.long 0x0 0.--31. 1. "INT_STATUS_MASTER,Master status reporting register for interrupt status groups. READ-ONLY"
group.long 0x53C++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_335,"
hexmask.long 0x0 0.--31. 1. "INT_MASK_MASTER,Master mask register for interrupt status groups. WRITE-ONLY"
rgroup.long 0x540++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_336,"
hexmask.long 0x0 0.--31. 1. "INT_STATUS_TIMEOUT,Status of interrupts in the controller related to Timeout monitors. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_337,"
hexmask.long.word 0x4 16.--31. 1. "INT_STATUS_LOWPOWER,Status of interrupts in the controller related to Low Power. READ-ONLY"
group.long 0x548++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_338,"
rgroup.long 0x54C++0x13
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_339,"
hexmask.long 0x0 0.--31. 1. "INT_STATUS_TRAINING,Status of interrupts in the controller related to Training/Calibration. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_340,"
hexmask.long 0x4 0.--31. 1. "INT_STATUS_USERIF,Status of interrupts in the controller related to ASIC to Controller Interface. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_341,"
hexmask.long.byte 0x8 16.--23. 1. "INT_STATUS_BIST,Status of interrupts in the controller related to BIST. READ-ONLY"
newline
hexmask.long.word 0x8 0.--15. 1. "INT_STATUS_MISC,Status of interrupts in the controller related to Miscellaneous features. READ-ONLY"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_342,"
hexmask.long.byte 0xC 24.--31. 1. "INT_STATUS_INIT,Status of interrupts in the controller related to Initialization. READ-ONLY"
newline
hexmask.long.byte 0xC 16.--23. 1. "INT_STATUS_FREQ,Status of interrupts in the controller related to Frequency Scaling. READ-ONLY"
newline
hexmask.long.byte 0xC 0.--7. 1. "INT_STATUS_DFI,Status of interrupts in the controller related to DFI. READ-ONLY"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_343,"
hexmask.long.byte 0x10 8.--15. 1. "INT_STATUS_PARITY,Status of interrupts in the controller related to Parity. READ-ONLY"
newline
hexmask.long.byte 0x10 0.--7. 1. "INT_STATUS_MODE,Status of interrupts in the controller related to Memory Mode Settings. READ-ONLY"
wgroup.long 0x560++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_344,"
hexmask.long 0x0 0.--31. 1. "INT_ACK_TIMEOUT,Clear status of the INT_STATUS_TIMEOUT parameter. WRITE-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_345,"
hexmask.long.word 0x4 16.--31. 1. "INT_ACK_LOWPOWER,Clear status of the INT_STATUS_LOWPOWER parameter. WRITE-ONLY"
group.long 0x568++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_346,"
wgroup.long 0x56C++0x13
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_347,"
hexmask.long 0x0 0.--31. 1. "INT_ACK_TRAINING,Clear status of the INT_STATUS_TRAINING parameter. WRITE-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_348,"
hexmask.long 0x4 0.--31. 1. "INT_ACK_USERIF,Clear status of the INT_STATUS_USERIF parameter. WRITE-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_349,"
hexmask.long.byte 0x8 16.--23. 1. "INT_ACK_BIST,Clear status of the INT_STATUS_BIST parameter. WRITE-ONLY"
newline
hexmask.long.word 0x8 0.--15. 1. "INT_ACK_MISC,Clear status of the INT_STATUS_MISC parameter. WRITE-ONLY"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_350,"
hexmask.long.byte 0xC 24.--31. 1. "INT_ACK_INIT,Clear status of the INT_STATUS_INIT parameter. WRITE-ONLY"
newline
hexmask.long.byte 0xC 16.--23. 1. "INT_ACK_FREQ,Clear status of the INT_STATUS_FREQ parameter. WRITE-ONLY"
newline
hexmask.long.byte 0xC 0.--7. 1. "INT_ACK_DFI,Clear status of the INT_STATUS_DFI parameter. WRITE-ONLY"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_351,"
hexmask.long.byte 0x10 8.--15. 1. "INT_ACK_PARITY,Clear status of the INT_STATUS_PARITY parameter. WRITE-ONLY"
newline
hexmask.long.byte 0x10 0.--7. 1. "INT_ACK_MODE,Clear status of the INT_STATUS_MODE parameter. WRITE-ONLY"
group.long 0x580++0x1F
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_352,"
hexmask.long 0x0 0.--31. 1. "INT_MASK_TIMEOUT,Mask for the controller_int signal from the INT_MASK_TIMEOUT parameter"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_353,"
hexmask.long.word 0x4 16.--31. 1. "INT_MASK_LOWPOWER,Mask for the controller_int signal from the INT_MASK_LOWPOWER parameter"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_354,"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_355,"
hexmask.long 0xC 0.--31. 1. "INT_MASK_TRAINING,Mask for the controller_int signal from the INT_MASK_TRAINING parameter"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_356,"
hexmask.long 0x10 0.--31. 1. "INT_MASK_USERIF,Mask for the controller_int signal from the INT_MASK_USERIF parameter"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_357,"
hexmask.long.byte 0x14 16.--23. 1. "INT_MASK_BIST,Mask for the controller_int signal from the INT_MASK_BIST parameter"
newline
hexmask.long.word 0x14 0.--15. 1. "INT_MASK_MISC,Mask for the controller_int signal from the INT_MASK_MISC parameter"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_358,"
hexmask.long.byte 0x18 24.--31. 1. "INT_MASK_INIT,Mask for the controller_int signal from the INT_MASK_INIT parameter"
newline
hexmask.long.byte 0x18 16.--23. 1. "INT_MASK_FREQ,Mask for the controller_int signal from the INT_MASK_FREQ parameter"
newline
hexmask.long.byte 0x18 0.--7. 1. "INT_MASK_DFI,Mask for the controller_int signal from the INT_MASK_DFI parameter"
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_359,"
hexmask.long.byte 0x1C 8.--15. 1. "INT_MASK_PARITY,Mask for the controller_int signal from the INT_MASK_PARITY parameter"
newline
hexmask.long.byte 0x1C 0.--7. 1. "INT_MASK_MODE,Mask for the controller_int signal from the INT_MASK_MODE parameter"
rgroup.long 0x5A0++0x27
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_360,"
hexmask.long 0x0 0.--31. 1. "OUT_OF_RANGE_ADDR_0,Address of command that caused an out-of-range interrupt. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_361,"
hexmask.long.byte 0x4 24.--30. 1. "OUT_OF_RANGE_TYPE,Type of command that caused an out-of-range interrupt. READ-ONLY"
newline
hexmask.long.word 0x4 8.--18. 1. "OUT_OF_RANGE_LENGTH,Length of command that caused an out-of-range interrupt. READ-ONLY"
newline
bitfld.long 0x4 0. "OUT_OF_RANGE_ADDR_1,Address of command that caused an out-of-range interrupt. READ-ONLY" "0,1"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_362,"
hexmask.long.byte 0x8 0.--5. 1. "OUT_OF_RANGE_SOURCE_ID,Source ID of command that caused an out-of-range interrupt. READ-ONLY"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_363,"
hexmask.long 0xC 0.--31. 1. "BIST_EXP_DATA_0,Expected data on BIST error. READ-ONLY"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_364,"
hexmask.long 0x10 0.--31. 1. "BIST_EXP_DATA_1,Expected data on BIST error. READ-ONLY"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_365,"
hexmask.long 0x14 0.--31. 1. "BIST_FAIL_DATA_0,Actual data on BIST error. READ-ONLY"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_366,"
hexmask.long 0x18 0.--31. 1. "BIST_FAIL_DATA_1,Actual data on BIST error. READ-ONLY"
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_367,"
hexmask.long 0x1C 0.--31. 1. "BIST_FAIL_ADDR_0,Address of BIST error. READ-ONLY"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_368,"
bitfld.long 0x20 0. "BIST_FAIL_ADDR_1,Address of BIST error. READ-ONLY" "0,1"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_369,"
hexmask.long 0x24 0.--31. 1. "PORT_CMD_ERROR_ADDR_0,Address of command that caused the PORT command error. READ-ONLY"
group.long 0x5C8++0xD3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_370,"
hexmask.long.byte 0x0 24.--31. 1. "TODTL_2CMD_F0,Defines the DRAM delay from an ODT de-assertion to the next non-write  non-read command. FC=0"
newline
rbitfld.long 0x0 16.--17. "PORT_CMD_ERROR_TYPE,Type of error and access type that caused the PORT command error. READ-ONLY" "0,1,2,3"
newline
hexmask.long.byte 0x0 8.--13. 1. "PORT_CMD_ERROR_ID,Source ID of command that caused the PORT command error. READ-ONLY"
newline
rbitfld.long 0x0 0. "PORT_CMD_ERROR_ADDR_1,Address of command that caused the PORT command error. READ-ONLY" "0,1"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_371,"
hexmask.long.byte 0x4 24.--27. 1. "TODTH_WR_F1,Defines the DRAM minimum ODT high time after an ODT assertion for a write command. FC=1"
newline
hexmask.long.byte 0x4 16.--23. 1. "TODTL_2CMD_F1,Defines the DRAM delay from an ODT de-assertion to the next non-write  non-read command. FC=1"
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hexmask.long.byte 0x4 8.--11. 1. "TODTH_RD_F0,Defines the DRAM minimum ODT high time after an ODT assertion for a read command. FC=0"
newline
hexmask.long.byte 0x4 0.--3. 1. "TODTH_WR_F0,Defines the DRAM minimum ODT high time after an ODT assertion for a write command. FC=0"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_372,"
hexmask.long.byte 0x8 24.--27. 1. "TODTH_RD_F2,Defines the DRAM minimum ODT high time after an ODT assertion for a read command. FC=2"
newline
hexmask.long.byte 0x8 16.--19. 1. "TODTH_WR_F2,Defines the DRAM minimum ODT high time after an ODT assertion for a write command. FC=2"
newline
hexmask.long.byte 0x8 8.--15. 1. "TODTL_2CMD_F2,Defines the DRAM delay from an ODT de-assertion to the next non-write  non-read command. FC=2"
newline
hexmask.long.byte 0x8 0.--3. 1. "TODTH_RD_F1,Defines the DRAM minimum ODT high time after an ODT assertion for a read command. FC=1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_373,"
bitfld.long 0xC 24. "EN_ODT_ASSERT_EXCEPT_RD,Enable controller to assert ODT at all times except during reads. Assumes single ODT pin connected. Set to 1 to enable." "0,1"
newline
bitfld.long 0xC 16. "ODT_EN_F2,Enable support of DRAM ODT. When enabled  controller will assert and de-assert ODT output to DRAM as needed. FC=2" "0,1"
newline
bitfld.long 0xC 8. "ODT_EN_F1,Enable support of DRAM ODT. When enabled  controller will assert and de-assert ODT output to DRAM as needed. FC=1" "0,1"
newline
bitfld.long 0xC 0. "ODT_EN_F0,Enable support of DRAM ODT. When enabled  controller will assert and de-assert ODT output to DRAM as needed. FC=0" "0,1"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_374,"
bitfld.long 0x10 24.--25. "ODT_RD_MAP_CS0,Determines which chip[s] will have termination when a read occurs. Set bit X to enable termination on csX when a read is performed. CS=0" "0,1,2,3"
newline
hexmask.long.byte 0x10 16.--21. 1. "WR_TO_ODTH_F2,Defines the delay from a write command to ODT assertion. FC=2"
newline
hexmask.long.byte 0x10 8.--13. 1. "WR_TO_ODTH_F1,Defines the delay from a write command to ODT assertion. FC=1"
newline
hexmask.long.byte 0x10 0.--5. 1. "WR_TO_ODTH_F0,Defines the delay from a write command to ODT assertion. FC=0"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_375,"
hexmask.long.byte 0x14 24.--29. 1. "RD_TO_ODTH_F0,Defines the delay from a read command to ODT assertion. FC=0"
newline
bitfld.long 0x14 16.--17. "ODT_WR_MAP_CS1,Determines which chip[s] will have termination when a write occurs. Set bit X to enable termination on csX when a write is performed. CS=1" "0,1,2,3"
newline
bitfld.long 0x14 8.--9. "ODT_RD_MAP_CS1,Determines which chip[s] will have termination when a read occurs. Set bit X to enable termination on csX when a read is performed. CS=1" "0,1,2,3"
newline
bitfld.long 0x14 0.--1. "ODT_WR_MAP_CS0,Determines which chip[s] will have termination when a write occurs. Set bit X to enable termination on csX when a write is performed. CS=0" "0,1,2,3"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_376,"
hexmask.long.byte 0x18 24.--28. 1. "RW2MRW_DLY_F1,Additional delay to insert between read or write and mode_reg_write. Allowed programming dependent on memory system. FC=1"
newline
hexmask.long.byte 0x18 16.--20. 1. "RW2MRW_DLY_F0,Additional delay to insert between read or write and mode_reg_write. Allowed programming dependent on memory system. FC=0"
newline
hexmask.long.byte 0x18 8.--13. 1. "RD_TO_ODTH_F2,Defines the delay from a read command to ODT assertion. FC=2"
newline
hexmask.long.byte 0x18 0.--5. 1. "RD_TO_ODTH_F1,Defines the delay from a read command to ODT assertion. FC=1"
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_377,"
hexmask.long.byte 0x1C 24.--28. 1. "W2R_DIFFCS_DLY_F0,Additional delay to insert between writes and reads to different chip selects. Allowed programming dependent on memory system. FC=0"
newline
hexmask.long.byte 0x1C 16.--20. 1. "R2W_DIFFCS_DLY_F0,Additional delay to insert between reads and writes to different chip selects. Program to a non-zero value. FC=0"
newline
hexmask.long.byte 0x1C 8.--12. 1. "R2R_DIFFCS_DLY_F0,Additional delay to insert between reads to different chip selects. Program to a non-zero value. FC=0"
newline
hexmask.long.byte 0x1C 0.--4. 1. "RW2MRW_DLY_F2,Additional delay to insert between read or write and mode_reg_write. Allowed programming dependent on memory system. FC=2"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_378,"
hexmask.long.byte 0x20 24.--28. 1. "W2R_DIFFCS_DLY_F1,Additional delay to insert between writes and reads to different chip selects. Allowed programming dependent on memory system. FC=1"
newline
hexmask.long.byte 0x20 16.--20. 1. "R2W_DIFFCS_DLY_F1,Additional delay to insert between reads and writes to different chip selects. Program to a non-zero value. FC=1"
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hexmask.long.byte 0x20 8.--12. 1. "R2R_DIFFCS_DLY_F1,Additional delay to insert between reads to different chip selects. Program to a non-zero value. FC=1"
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hexmask.long.byte 0x20 0.--4. 1. "W2W_DIFFCS_DLY_F0,Additional delay to insert between writes to different chip selects. Program to a non-zero value. FC=0"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_379,"
hexmask.long.byte 0x24 24.--28. 1. "W2R_DIFFCS_DLY_F2,Additional delay to insert between writes and reads to different chip selects. Allowed programming dependent on memory system. FC=2"
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hexmask.long.byte 0x24 16.--20. 1. "R2W_DIFFCS_DLY_F2,Additional delay to insert between reads and writes to different chip selects. Program to a non-zero value. FC=2"
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hexmask.long.byte 0x24 8.--12. 1. "R2R_DIFFCS_DLY_F2,Additional delay to insert between reads to different chip selects. Program to a non-zero value. FC=2"
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hexmask.long.byte 0x24 0.--4. 1. "W2W_DIFFCS_DLY_F1,Additional delay to insert between writes to different chip selects. Program to a non-zero value. FC=1"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_380,"
hexmask.long.byte 0x28 24.--28. 1. "R2W_SAMECS_DLY_F2,Additional delay to insert between reads and writes to the same chip select. Program to a non-zero value. FC=2"
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hexmask.long.byte 0x28 16.--20. 1. "R2W_SAMECS_DLY_F1,Additional delay to insert between reads and writes to the same chip select. Program to a non-zero value. FC=1"
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hexmask.long.byte 0x28 8.--12. 1. "R2W_SAMECS_DLY_F0,Additional delay to insert between reads and writes to the same chip select. Program to a non-zero value. FC=0"
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hexmask.long.byte 0x28 0.--4. 1. "W2W_DIFFCS_DLY_F2,Additional delay to insert between writes to different chip selects. Program to a non-zero value. FC=2"
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_381,"
hexmask.long.byte 0x2C 24.--27. 1. "TDQSCK_MAX_F0,Additional delay needed for tDQSCK. FC=0"
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hexmask.long.byte 0x2C 16.--20. 1. "W2W_SAMECS_DLY,Additional delay to insert between two writes to the same chip select. Any value including 0 supported."
newline
hexmask.long.byte 0x2C 8.--12. 1. "W2R_SAMECS_DLY,Additional delay to insert between writes and reads to the same chip select."
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hexmask.long.byte 0x2C 0.--4. 1. "R2R_SAMECS_DLY,Additional delay to insert between two reads to the same chip select. Any value including 0 supported."
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_382,"
hexmask.long.byte 0x30 24.--27. 1. "TDQSCK_MAX_F2,Additional delay needed for tDQSCK. FC=2"
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bitfld.long 0x30 16.--18. "TDQSCK_MIN_F1,Additional delay needed for tDQSCK. FC=1" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x30 8.--11. 1. "TDQSCK_MAX_F1,Additional delay needed for tDQSCK. FC=1"
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bitfld.long 0x30 0.--2. "TDQSCK_MIN_F0,Additional delay needed for tDQSCK. FC=0" "0,1,2,3,4,5,6,7"
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_383,"
bitfld.long 0x34 24.--26. "AXI0_R_PRIORITY,Priority of read commands from AXI port 0. 0 is the highest priority. This may only be changed before initialization begins or when the controller is quiescent  there is no data in the port FIFOs  and the AXI0_FIXED_PORT_PRIORITY_ENABLE.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 16. "AXI0_FIXED_PORT_PRIORITY_ENABLE,Defines the priority control for AXI port 0 as per-port or per-command. Set to 1 for per-port with priority defined through the AXI.0._R_PRIORITY and AXI.0._W_PRIORITY parameters. Clear to 0 for per-command." "0,1"
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bitfld.long 0x34 8. "AXI0_ALL_STROBES_USED_ENABLE,Enables use of the AWALLSTRB signal for AXI port 0. Set to 1 to enable." "0,1"
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bitfld.long 0x34 0.--2. "TDQSCK_MIN_F2,Additional delay needed for tDQSCK. FC=2" "0,1,2,3,4,5,6,7"
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_384,"
hexmask.long.byte 0x38 24.--31. 1. "TDFI_PHY_RDLAT_F0,Defines the DFI tPHY_RDLAT timing parameter [in DFI PHY clocks]  the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion. FC=0"
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rbitfld.long 0x38 16. "MEM_RST_VALID,Register access to mem_rst_valid signal. READ-ONLY" "0,1"
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rbitfld.long 0x38 8.--9. "CKE_STATUS,Register access to cke_status signal. READ-ONLY" "0,1,2,3"
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bitfld.long 0x38 0.--2. "AXI0_W_PRIORITY,Priority of write commands from AXI port 0. 0 is the highest priority. This may only be changed before initialization begins or when the controller is quiescent  there is no data in the port FIFOs  and the AXI0_FIXED_PORT_PRIORITY_ENABLE.." "0,1,2,3,4,5,6,7"
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_385,"
hexmask.long.tbyte 0x3C 0.--20. 1. "TDFI_CTRLUPD_MAX_F0,Defines the DFI tCTRLUPD_MAX timing parameter [in DFI clocks]  the maximum cycles that dfi_ctrlupd_req can be asserted. If programmed to a non-zero  a timing violation will cause an interrupt and bit [0] set in the UPDATE_ERROR_STATUS.."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_386,"
hexmask.long 0x40 0.--31. 1. "TDFI_PHYUPD_TYPE0_F0,Defines the DFI tPHYUPD_TYPE0 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 0. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_387,"
hexmask.long 0x44 0.--31. 1. "TDFI_PHYUPD_TYPE1_F0,Defines the DFI tPHYUPD_TYPE1 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 1. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_388,"
hexmask.long 0x48 0.--31. 1. "TDFI_PHYUPD_TYPE2_F0,Defines the DFI tPHYUPD_TYPE2 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 2. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_389,"
hexmask.long 0x4C 0.--31. 1. "TDFI_PHYUPD_TYPE3_F0,Defines the DFI tPHYUPD_TYPE3 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 3. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_390,"
hexmask.long.tbyte 0x50 0.--22. 1. "TDFI_PHYUPD_RESP_F0,Defines the DFI tPHYUPD_RESP timing parameter [in DFI clocks]  the maximum cycles between a dfi_phyupd_req assertion and a dfi_phyupd_ack assertion. If programmed to a non-zero  a timing violation will cause an interrupt and bit [5].."
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_391,"
hexmask.long 0x54 0.--31. 1. "TDFI_CTRLUPD_INTERVAL_F0,Defines the DFI tCTRLUPD_INTERVAL timing parameter [in DFI clocks]  the maximum cycles between dfi_ctrlupd_req assertions. If programmed to a non-zero  a timing violation will cause an interrupt and bit [6] set in the.."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_392,"
hexmask.long.byte 0x58 24.--31. 1. "TDFI_RDDATA_EN_F0,DFI tRDDATA_EN timing parameter. This is the number of DFI data phases between a read command and the first assertion of dfi_rddata_en_pN. FC=0"
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hexmask.long.byte 0x58 16.--23. 1. "TDFI_RDCSLAT_F0,Defines the DFI tPHY_RDCSLAT timing parameter [in DFI PHY clocks]  the maximum cycles between a read command and a dfi_rddata_cs_n assertion. FC=0"
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bitfld.long 0x58 8.--10. "TDFI_PHY_WRDATA_F0,Defines the DFI tPHY_WRDATA timing parameter [in DFI PHY clocks]  the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal. FC=0" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x58 0.--3. 1. "TDFI_CTRL_DELAY_F0,Defines the DFI tCTRL_DELAY timing parameter [in DFI clocks]  the delay between a DFI command change and a memory command. FC=0"
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_393,"
hexmask.long.byte 0x5C 16.--23. 1. "TDFI_PHY_RDLAT_F1,Defines the DFI tPHY_RDLAT timing parameter [in DFI PHY clocks]  the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion. FC=1"
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hexmask.long.byte 0x5C 8.--15. 1. "TDFI_PHY_WRLAT_F0,DFI tPHY_WRLAT timing parameter. This is the number of DFI data phases between a write command and the first assertion of dfi_wrdata_en_pN. FC=0"
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hexmask.long.byte 0x5C 0.--7. 1. "TDFI_WRCSLAT_F0,Defines the DFI tPHY_WRCSLAT timing parameter [in DFI PHY clocks]  the maximum cycles between a write command and a dfi_wrdata_cs_n assertion. FC=0"
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_394,"
hexmask.long.tbyte 0x60 0.--20. 1. "TDFI_CTRLUPD_MAX_F1,Defines the DFI tCTRLUPD_MAX timing parameter [in DFI clocks]  the maximum cycles that dfi_ctrlupd_req can be asserted. If programmed to a non-zero  a timing violation will cause an interrupt and bit [0] set in the UPDATE_ERROR_STATUS.."
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_395,"
hexmask.long 0x64 0.--31. 1. "TDFI_PHYUPD_TYPE0_F1,Defines the DFI tPHYUPD_TYPE0 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 0. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_396,"
hexmask.long 0x68 0.--31. 1. "TDFI_PHYUPD_TYPE1_F1,Defines the DFI tPHYUPD_TYPE1 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 1. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_397,"
hexmask.long 0x6C 0.--31. 1. "TDFI_PHYUPD_TYPE2_F1,Defines the DFI tPHYUPD_TYPE2 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 2. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_398,"
hexmask.long 0x70 0.--31. 1. "TDFI_PHYUPD_TYPE3_F1,Defines the DFI tPHYUPD_TYPE3 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 3. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x74 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_399,"
hexmask.long.tbyte 0x74 0.--22. 1. "TDFI_PHYUPD_RESP_F1,Defines the DFI tPHYUPD_RESP timing parameter [in DFI clocks]  the maximum cycles between a dfi_phyupd_req assertion and a dfi_phyupd_ack assertion. If programmed to a non-zero  a timing violation will cause an interrupt and bit [5].."
line.long 0x78 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_400,"
hexmask.long 0x78 0.--31. 1. "TDFI_CTRLUPD_INTERVAL_F1,Defines the DFI tCTRLUPD_INTERVAL timing parameter [in DFI clocks]  the maximum cycles between dfi_ctrlupd_req assertions. If programmed to a non-zero  a timing violation will cause an interrupt and bit [6] set in the.."
line.long 0x7C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_401,"
hexmask.long.byte 0x7C 24.--31. 1. "TDFI_RDDATA_EN_F1,DFI tRDDATA_EN timing parameter. This is the number of DFI data phases between a read command and the first assertion of dfi_rddata_en_pN. FC=1"
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hexmask.long.byte 0x7C 16.--23. 1. "TDFI_RDCSLAT_F1,Defines the DFI tPHY_RDCSLAT timing parameter [in DFI PHY clocks]  the maximum cycles between a read command and a dfi_rddata_cs_n assertion. FC=1"
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bitfld.long 0x7C 8.--10. "TDFI_PHY_WRDATA_F1,Defines the DFI tPHY_WRDATA timing parameter [in DFI PHY clocks]  the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal. FC=1" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x7C 0.--3. 1. "TDFI_CTRL_DELAY_F1,Defines the DFI tCTRL_DELAY timing parameter [in DFI clocks]  the delay between a DFI command change and a memory command. FC=1"
line.long 0x80 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_402,"
hexmask.long.byte 0x80 16.--23. 1. "TDFI_PHY_RDLAT_F2,Defines the DFI tPHY_RDLAT timing parameter [in DFI PHY clocks]  the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion. FC=2"
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hexmask.long.byte 0x80 8.--15. 1. "TDFI_PHY_WRLAT_F1,DFI tPHY_WRLAT timing parameter. This is the number of DFI data phases between a write command and the first assertion of dfi_wrdata_en_pN. FC=1"
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hexmask.long.byte 0x80 0.--7. 1. "TDFI_WRCSLAT_F1,Defines the DFI tPHY_WRCSLAT timing parameter [in DFI PHY clocks]  the maximum cycles between a write command and a dfi_wrdata_cs_n assertion. FC=1"
line.long 0x84 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_403,"
hexmask.long.tbyte 0x84 0.--20. 1. "TDFI_CTRLUPD_MAX_F2,Defines the DFI tCTRLUPD_MAX timing parameter [in DFI clocks]  the maximum cycles that dfi_ctrlupd_req can be asserted. If programmed to a non-zero  a timing violation will cause an interrupt and bit [0] set in the UPDATE_ERROR_STATUS.."
line.long 0x88 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_404,"
hexmask.long 0x88 0.--31. 1. "TDFI_PHYUPD_TYPE0_F2,Defines the DFI tPHYUPD_TYPE0 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 0. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x8C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_405,"
hexmask.long 0x8C 0.--31. 1. "TDFI_PHYUPD_TYPE1_F2,Defines the DFI tPHYUPD_TYPE1 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 1. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x90 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_406,"
hexmask.long 0x90 0.--31. 1. "TDFI_PHYUPD_TYPE2_F2,Defines the DFI tPHYUPD_TYPE2 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 2. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x94 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_407,"
hexmask.long 0x94 0.--31. 1. "TDFI_PHYUPD_TYPE3_F2,Defines the DFI tPHYUPD_TYPE3 timing parameter [in DFI clocks]  the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 3. If programmed to a non-zero  a timing violation will cause an interrupt and.."
line.long 0x98 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_408,"
hexmask.long.tbyte 0x98 0.--22. 1. "TDFI_PHYUPD_RESP_F2,Defines the DFI tPHYUPD_RESP timing parameter [in DFI clocks]  the maximum cycles between a dfi_phyupd_req assertion and a dfi_phyupd_ack assertion. If programmed to a non-zero  a timing violation will cause an interrupt and bit [5].."
line.long 0x9C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_409,"
hexmask.long 0x9C 0.--31. 1. "TDFI_CTRLUPD_INTERVAL_F2,Defines the DFI tCTRLUPD_INTERVAL timing parameter [in DFI clocks]  the maximum cycles between dfi_ctrlupd_req assertions. If programmed to a non-zero  a timing violation will cause an interrupt and bit [6] set in the.."
line.long 0xA0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_410,"
hexmask.long.byte 0xA0 24.--31. 1. "TDFI_RDDATA_EN_F2,DFI tRDDATA_EN timing parameter. This is the number of DFI data phases between a read command and the first assertion of dfi_rddata_en_pN. FC=2"
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hexmask.long.byte 0xA0 16.--23. 1. "TDFI_RDCSLAT_F2,Defines the DFI tPHY_RDCSLAT timing parameter [in DFI PHY clocks]  the maximum cycles between a read command and a dfi_rddata_cs_n assertion. FC=2"
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bitfld.long 0xA0 8.--10. "TDFI_PHY_WRDATA_F2,Defines the DFI tPHY_WRDATA timing parameter [in DFI PHY clocks]  the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal. FC=2" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xA0 0.--3. 1. "TDFI_CTRL_DELAY_F2,Defines the DFI tCTRL_DELAY timing parameter [in DFI clocks]  the delay between a DFI command change and a memory command. FC=2"
line.long 0xA4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_411,"
hexmask.long.word 0xA4 16.--31. 1. "DLL_RST_DELAY,Minimum cycles required for DLL reset signal dll_rst_n to be held. If this signal is not being used by the PHY  this parameter may be ignored."
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hexmask.long.byte 0xA4 8.--15. 1. "TDFI_PHY_WRLAT_F2,DFI tPHY_WRLAT timing parameter. This is the number of DFI data phases between a write command and the first assertion of dfi_wrdata_en_pN. FC=2"
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hexmask.long.byte 0xA4 0.--7. 1. "TDFI_WRCSLAT_F2,Defines the DFI tPHY_WRCSLAT timing parameter [in DFI PHY clocks]  the maximum cycles between a write command and a dfi_wrdata_cs_n assertion. FC=2"
line.long 0xA8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_412,"
bitfld.long 0xA8 16.--17. "DRAM_CLK_DISABLE,Set value for the dfi_dram_clk_disable signal. Bit [0] controls cs0  bit [1] controls cs1  etc. Set each bit to 1 to disable." "0,1,2,3"
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hexmask.long.byte 0xA8 8.--14. 1. "UPDATE_ERROR_STATUS,Identifies the source of any DFI MC-initiated or PHY-initiated update errors. Value of 1 indicates a timing violation of the associated timing parameter. READ-ONLY"
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hexmask.long.byte 0xA8 0.--7. 1. "DLL_RST_ADJ_DLY,Minimum cycles after setting master delay in DLL until the DLL reset signal dll_rst_n may be asserted. If this signal is not being used by the PHY  this parameter may be ignored."
line.long 0xAC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_413,"
hexmask.long.byte 0xAC 24.--27. 1. "TDFI_DRAM_CLK_ENABLE,Defines the DFI tDRAM_CLK_ENABLE timing parameter [in DFI clocks]  the delay between a dfi_dram_clk_disable de-assertion and the memory clock enable."
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hexmask.long.byte 0xAC 16.--19. 1. "TDFI_DRAM_CLK_DISABLE,Defines the DFI tDRAM_CLK_DISABLE timing parameter [in DFI clocks]  the delay between a dfi_dram_clock_disable assertion and the memory clock disable."
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hexmask.long.word 0xAC 0.--15. 1. "TDFI_CTRLUPD_MIN,Defines the DFI tCTRLUPD_MIN timing parameter [in DFI clocks]  the minimum cycles that dfi_ctrlupd_req must be asserted."
line.long 0xB0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_414,"
bitfld.long 0xB0 24.--26. "STRATEGY_2TICK_COUNT,NEED TO FiLL IN ." "0,1,2,3,4,5,6,7"
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bitfld.long 0xB0 16. "DISABLE_MEMORY_MASKED_WRITE,Restricts the controller from masked write commands. Set to 1 to not issue these commands. Only used if connected to an LPDDR4 device." "0,1"
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hexmask.long.byte 0xB0 8.--15. 1. "TDFI_WRDATA_DELAY,Defines the tWRDATA_DELAY timing parameter [in DFI PHY clocks]  the maximum cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus."
newline
bitfld.long 0xB0 0.--2. "TDFI_PARIN_LAT,Defines the DFI tPARIN_LAT timing parameter [in DFI PHY clocks]  the maximum cycles between a DFI command and a dfi_parity_in signal assertion." "0,1,2,3,4,5,6,7"
line.long 0xB4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_415,"
bitfld.long 0xB4 24.--26. "BANK_ACTIVATE_4TICK_COUNT,NEED TO FiLL IN ." "0,1,2,3,4,5,6,7"
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bitfld.long 0xB4 16.--18. "STRATEGY_4TICK_COUNT,NEED TO FiLL IN ." "0,1,2,3,4,5,6,7"
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bitfld.long 0xB4 8.--10. "PRE_2TICK_COUNT,NEED TO FiLL IN ." "0,1,2,3,4,5,6,7"
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bitfld.long 0xB4 0.--2. "BANK_ACTIVATE_2TICK_COUNT,NEED TO FiLL IN ." "0,1,2,3,4,5,6,7"
line.long 0xB8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_416,"
hexmask.long.byte 0xB8 24.--27. 1. "TMP_NXN_TICK_PLUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xB8 16.--19. 1. "TMP_2X4_TICK_MINUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xB8 8.--11. 1. "TMP_2X4_TICK_PLUS_ADJ,NEED TO FiLL IN ."
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bitfld.long 0xB8 0.--2. "PRE_4TICK_COUNT,NEED TO FiLL IN ." "0,1,2,3,4,5,6,7"
line.long 0xBC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_417,"
hexmask.long.byte 0xBC 24.--27. 1. "TRAS_TICK_PLUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xBC 16.--19. 1. "ODT_TICK_MINUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xBC 8.--11. 1. "ODT_TICK_PLUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xBC 0.--3. 1. "TMP_NXN_TICK_MINUS_ADJ,NEED TO FiLL IN ."
line.long 0xC0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_418,"
hexmask.long.byte 0xC0 24.--27. 1. "TWR_TICK_PLUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xC0 16.--19. 1. "TRP_TICK_MINUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xC0 8.--11. 1. "TRP_TICK_PLUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xC0 0.--3. 1. "TRAS_TICK_MINUS_ADJ,NEED TO FiLL IN ."
line.long 0xC4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_419,"
hexmask.long.byte 0xC4 24.--27. 1. "TRFC_TICK_PLUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xC4 16.--19. 1. "TMP_4X2_TICK_MINUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xC4 8.--11. 1. "TMP_4X2_TICK_PLUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xC4 0.--3. 1. "TWR_TICK_MINUS_ADJ,NEED TO FiLL IN ."
line.long 0xC8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_420,"
hexmask.long.byte 0xC8 24.--27. 1. "WL_TICK_PLUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xC8 16.--19. 1. "RL_TICK_MINUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xC8 8.--11. 1. "RL_TICK_PLUS_ADJ,NEED TO FiLL IN ."
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hexmask.long.byte 0xC8 0.--3. 1. "TRFC_TICK_MINUS_ADJ,NEED TO FiLL IN ."
line.long 0xCC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_421,"
hexmask.long.byte 0xCC 24.--31. 1. "NWR_F2,DRAM NWR value in cycles. FC=2"
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hexmask.long.byte 0xCC 16.--23. 1. "NWR_F1,DRAM NWR value in cycles. FC=1"
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hexmask.long.byte 0xCC 8.--15. 1. "NWR_F0,DRAM NWR value in cycles. FC=0"
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hexmask.long.byte 0xCC 0.--3. 1. "WL_TICK_MINUS_ADJ,NEED TO FiLL IN ."
line.long 0xD0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_CTL_422,"
hexmask.long.byte 0xD0 16.--22. 1. "TDFI_CTRLMSG_RESP_F2,Defines the DFI tCTRLMSG_RESP timing parameter [in DFI clocks]  the maximum number of DFI clocks allowed for dfi_ctrlmsg_ack to assert after dfi_ctrlmsg_req goes high. FC=2"
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hexmask.long.byte 0xD0 8.--14. 1. "TDFI_CTRLMSG_RESP_F1,Defines the DFI tCTRLMSG_RESP timing parameter [in DFI clocks]  the maximum number of DFI clocks allowed for dfi_ctrlmsg_ack to assert after dfi_ctrlmsg_req goes high. FC=1"
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hexmask.long.byte 0xD0 0.--6. 1. "TDFI_CTRLMSG_RESP_F0,Defines the DFI tCTRLMSG_RESP timing parameter [in DFI clocks]  the maximum number of DFI clocks allowed for dfi_ctrlmsg_ack to assert after dfi_ctrlmsg_req goes high. FC=0"
group.long 0x2000++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_0,"
hexmask.long.byte 0x0 8.--11. 1. "PI_DRAM_CLASS,Defines the memory class for the PI."
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bitfld.long 0x0 0. "PI_START,Initiate command processing in the PI. Set to 1 to initiate." "0,1"
rgroup.long 0x2004++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_1,"
hexmask.long 0x0 0.--31. 1. "PI_VERSION_0,Holds the PI version number. This is a unique number for each PHY IP delivery. This will help in identifying different version of the PHY IP. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_2,"
hexmask.long 0x4 0.--31. 1. "PI_VERSION_1,Holds the PI version number. This is a unique number for each PHY IP delivery. This will help in identifying different version of the PHY IP. READ-ONLY"
group.long 0x200C++0xF
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_3,"
bitfld.long 0x0 24. "PI_NORMAL_LVL_SEQ,Enable the PI to finish all the pending leveling before releasing the DFI bus." "0,1"
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rbitfld.long 0x0 16. "PI_RELEASE_DFI,This is a status whether PI has release DFI. READ-ONLY." "0,1"
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hexmask.long.word 0x0 0.--15. 1. "PI_ID,Holds the PI ID number. This is a Cadence DDR PHY IP identifier. It is set to 0x1387. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_4,"
hexmask.long.word 0x4 16.--31. 1. "PI_TCMD_GAP,Specifies the minimum gap in DFI clocks between two commands. Used to guard the timing from the last command of MC and the first command of PI when MC hand over the control of DFI to PI."
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bitfld.long 0x4 8.--9. "PI_NOTCARE_PHYUPD,Allow the PI to issue a master request to the controller if a phyupd_req from the PHY has been detected.bit[1] represents supports in normal state;bit[0] represents supports in initialization state. Set to 1 to issue the master request." "0,1,2,3"
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bitfld.long 0x4 0. "PI_INIT_LVL_EN,Enables the initial leveling sequence after PI initialization procedure. Set to 1 to enable." "0,1"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_5,"
bitfld.long 0x8 24.--25. "PI_DFI_PHYMSTR_TYPE,DFI Master Request Type used for dfi 4.1 verision: This signal indicates the required state of DRAM when PHY becomes the master. Each memory rank uses one bit. 1'b0: IDLE. The MC should close all the pages. 1'b1: IDLE or Self Refresh." "0: IDLE,1: IDLE or Self Refresh,?,?"
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bitfld.long 0x8 16. "PI_DFI_VERSION,Define the DFI master version  set 1 for DFI4.1  set 0 for DFI4.0" "0,1"
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bitfld.long 0x8 8. "PI_TRAIN_ALL_FREQ_REQ,Triggers training for all supported frequencies in PI_FREQ_MAP. Applies to LPDDR4 devices onlyh. Set to 1 to trigger. Only applicable after memory initialization has been completed. Can be used to train new frequencies that were not.." "0,1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_6,"
bitfld.long 0xC 8. "PI_DFI_PHYMSTR_STATE_SEL_R,DFI PHY Master State Select: Indication from the PHY to the MC whether the requested memory state is IDLE or Self refresh. 'b0: indicates that the corresponding CS must be put into the IDLE state. 'b1: indicates that the.." "0: indicates that the corresponding CS must be put..,1: indicates that the corresponding CS must be put.."
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bitfld.long 0xC 0. "PI_DFI_PHYMSTR_CS_STATE_R,This signal indicates the state of the DRAM when the PHY becomes the master. 'b0: The PHY specifies the required state  using the dfi_phymstr_state_sel signal. 'b1: is reserved." "0: The PHY specifies the required state,1: is reserved"
rgroup.long 0x201C++0xF
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_7,"
hexmask.long 0x0 0.--31. 1. "PI_TDFI_PHYMSTR_MAX,Indicates the maximum number of DFI clock cycles registered while the dfi_phymstr_req signal is asserted and the dfi_phymstr_ack signal is asserted. READ-ONLY."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_8,"
hexmask.long.tbyte 0x4 0.--19. 1. "PI_TDFI_PHYMSTR_RESP,Indicates the maximum number of DFI clock cycles registered between a dfi_phymstr_req signal assertion and a dfi_phymstr_ack signal assertion. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_9,"
hexmask.long.tbyte 0x8 0.--19. 1. "PI_TDFI_PHYUPD_RESP,Indicates the maximum number of DFI clock cycles registered between a dfi_phyupd_req signal assertion and a dfi_phyupd_ack signal assertion. READ-ONLY."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_10,"
hexmask.long 0xC 0.--31. 1. "PI_TDFI_PHYUPD_MAX,Indicates the maximum number of DFI clock cycles registered while the dfi_phyupd_req signal is asserted and the dfi_phy_ack signal is asserted. READ-ONLY."
group.long 0x202C++0x1B
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_11,"
bitfld.long 0x0 8. "PI_INIT_DFS_CALVL_ONLY,Enables frequency training for CA leveling only. Other trainings are not performed." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "PI_INIT_WORK_FREQ,Indicates the initial work frequency after initialization and initial leveling sequence."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_12,"
hexmask.long 0x4 0.--31. 1. "PI_FREQ_MAP,Frequency map for supported working frequencies. Each bit represents one supported frequency."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_13,"
bitfld.long 0x8 24. "PI_SWLVL_CS_SEL,Defines which chip selects are active in swlvl  0 for binary  1 for one-hot." "0,1"
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bitfld.long 0x8 16.--17. "PI_CS_MAP,Defines which chip selects are active." "0,1,2,3"
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bitfld.long 0x8 0. "PI_SW_RST_N,User request to reset the whole PI except the parameter modules. Set 0 to reset  set to 1 to release." "0,1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_14,"
hexmask.long.byte 0xC 24.--27. 1. "PI_TMRR,DRAM tMRR value in memory clock cycles."
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bitfld.long 0xC 16. "PI_SRX_LVL_TARGET_CS_EN,Defines self refresh exit trigger target rank/ranks training or all ranks training. 1: The rank/ranks exit from self refresh will trigger the corresponding rank/ranks training. Note: If multiple ranks exit from self refresh .." "0: Any rank/ranks exit from self refresh will..,1: The rank/ranks exit from self refresh will.."
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hexmask.long.byte 0xC 8.--12. 1. "PI_RANK_NUM_PER_CKE,Defines the number of chip selects share one cke"
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bitfld.long 0xC 0.--1. "PI_CS_MASK,Defines which chip selects are active." "0,1,2,3"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_15,"
bitfld.long 0x10 16. "PI_MCAREF_FORWARD_ONLY,Controls the generation of AREF from the PI module or forward the MC received value." "0,1"
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bitfld.long 0x10 8.--10. "PI_VRCG_EN,Whether enable VRCG mode in two cases: bit0 - when DFS. bit1-when setting DQ Vref. bit2-when setting CBT." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 0.--3. 1. "PI_TMPRR,DRAM tMPRR value in memory clock cycles."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_16,"
rbitfld.long 0x14 24. "PI_ON_DFIBUS,Monitors the state of the PI controlling the DFI bus. 1 means PI is in control. READ-ONLY." "0,1"
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hexmask.long.tbyte 0x14 0.--19. 1. "PI_TREF_INTERVAL,Defines the cycles between refreshes to different chip selects."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_17,"
rbitfld.long 0x18 24. "PI_SW_WRLVL_RESP_0,Write leveling response for data slice 0. READ-ONLY" "0,1"
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rbitfld.long 0x18 16. "PI_SWLVL_OP_DONE,Reports the status of the software leveling operation. Value of 1 indicates operation complete. READ-ONLY" "0,1"
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bitfld.long 0x18 8. "PI_SWLVL_LOAD,User request to load delays and execute software leveling. Set to 1 to trigger. WRITE-ONLY" "0,1"
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rbitfld.long 0x18 0. "PI_DATA_RETENTION,Monitors the readiness for the PHY to be put into data retention mode after pi_sref_entry req parameter has been written. 1 means ready for data retention. READ-ONLY." "0,1"
rgroup.long 0x2048++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_18,"
bitfld.long 0x0 24.--25. "PI_SW_CALVL_RESP_0,CA leveling response for address slice 0. READ-ONLY" "0,1,2,3"
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bitfld.long 0x0 16.--17. "PI_SW_RDLVL_RESP_1,Read leveling response for data slice 1. READ-ONLY" "0,1,2,3"
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bitfld.long 0x0 8.--9. "PI_SW_RDLVL_RESP_0,Read leveling response for data slice 0. READ-ONLY" "0,1,2,3"
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bitfld.long 0x0 0. "PI_SW_WRLVL_RESP_1,Write leveling response for data slice 1. READ-ONLY" "0,1"
group.long 0x204C++0x37
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_19,"
bitfld.long 0x0 24. "PI_SWLVL_WR_SLICE_0,SW leveling write command in WDQ training. WRITE-ONLY" "0,1"
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bitfld.long 0x0 16. "PI_SWLVL_EXIT,User request to exit software leveling. Set to 1 to exit. WRITE-ONLY" "0,1"
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bitfld.long 0x0 8. "PI_SWLVL_START,User request to initiate software leveling of type in the SW_LEVELING_MODE parameter. Set to 1 to trigger. WRITE-ONLY" "0,1"
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bitfld.long 0x0 0.--2. "PI_SW_LEVELING_MODE,Defines the leveling operation for software leveling. Set to 'b111 for DDR4 VREF training  set to b001 for write leveling  set to b010 for read data eye training  or set to b011 for read gate training  set to b100 for ca training  set.." "0,1,2,3,4,5,6,7"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_20,"
bitfld.long 0x4 24. "PI_SWLVL_WR_SLICE_1,SW leveling write command in WDQ training. WRITE-ONLY" "0,1"
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rbitfld.long 0x4 16.--17. "PI_SW_WDQLVL_RESP_0,Leveling response for data slice 0. READ-ONLY" "0,1,2,3"
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bitfld.long 0x4 8. "PI_SWLVL_VREF_UPDATE_SLICE_0,SW leveling vref update command in WDQ training. WRITE-ONLY" "0,1"
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bitfld.long 0x4 0. "PI_SWLVL_RD_SLICE_0,SW leveling read command in WDQ training. WRITE-ONLY" "0,1"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_21,"
bitfld.long 0x8 24. "PI_SWLVL_SM2_START,SW leveling start command for stage 2. WRITE-ONLY" "0,1"
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rbitfld.long 0x8 16.--17. "PI_SW_WDQLVL_RESP_1,Leveling response for data slice 1. READ-ONLY" "0,1,2,3"
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bitfld.long 0x8 8. "PI_SWLVL_VREF_UPDATE_SLICE_1,SW leveling vref update command in WDQ training. WRITE-ONLY" "0,1"
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bitfld.long 0x8 0. "PI_SWLVL_RD_SLICE_1,SW leveling read command in WDQ training. WRITE-ONLY" "0,1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_22,"
bitfld.long 0xC 24. "PI_DFS_PERIOD_EN,Enable the DFS triggered periodic leveling." "0,1"
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bitfld.long 0xC 16. "PI_SEQUENTIAL_LVL_REQ,User request to initiate all possible leveling sequences. Set to 1 to trigger. WRITE-ONLY" "0,1"
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bitfld.long 0xC 8. "PI_SWLVL_SM2_RD,SW leveling read command for stage 2. WRITE-ONLY" "0,1"
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bitfld.long 0xC 0. "PI_SWLVL_SM2_WR,SW leveling write command for stage 2. WRITE-ONLY" "0,1"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_23,"
bitfld.long 0x10 24. "PI_WRLVL_REQ,User request to initiate write leveling. Set to 1 to trigger. WRITE-ONLY" "0,1"
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bitfld.long 0x10 16. "PI_DFI40_POLARITY,Defines the polarity of the dfi_wrdata_cs_n/dfi_rddata_cs_n signals." "0,1"
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bitfld.long 0x10 8. "PI_MPD_PERIOD_EN,Enable the max power saving mode exit triggered periodic leveling." "0,1"
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bitfld.long 0x10 0. "PI_SRE_PERIOD_EN,Enable the self refresh exit triggered periodic leveling." "0,1"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_24,"
hexmask.long.byte 0x14 24.--29. 1. "PI_WLMRD,Delay from issuing MRS to first write leveling strobe."
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hexmask.long.byte 0x14 16.--21. 1. "PI_WLDQSEN,Delay from issuing MRS to first DQS strobe for write leveling."
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bitfld.long 0x14 8. "PI_WRLVL_CS,Specifies the target chip select for the write leveling operation initiated through the WRLVL_REQ parameter." "0,1"
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bitfld.long 0x14 0.--1. "PI_WRLVL_CS_SW,Specifies the target chip select for the write leveling operation initiated through the WRLVL_REQ parameter." "0,1,2,3"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_25,"
bitfld.long 0x18 24. "PI_WRLVL_DISABLE_DFS,Disable automatic write leveling on freq change. Set to 1 to disable wrlvl on dfs set 0 enable wrlvl on dfs." "0,1"
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bitfld.long 0x18 16. "PI_WRLVL_ON_SREF_EXIT,Enables automatic write leveling on a self-refresh exit. Set to 1 to enable." "0,1"
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hexmask.long.word 0x18 0.--15. 1. "PI_WRLVL_INTERVAL,Number of long count sequences counted between automatic write leveling commands."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_26,"
bitfld.long 0x1C 24. "PI_WRLVL_ON_MPD_EXIT,Enables automatic write leveling on a maximum power down mode exit. Set to 1 to enable." "0,1"
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bitfld.long 0x1C 16.--17. "PI_WRLVL_CS_MAP,Defines the chip select map for write leveling operations. Bit [0] controls cs0  bit [1] controls cs1  etc. Set each bit to 1 to enable chip for write leveling." "0,1,2,3"
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bitfld.long 0x1C 8. "PI_WRLVL_ROTATE,Enables rotational CS for counter triggered automatic write leveling. Set to 1  only one rank's write levling will process  the rank number is rotational for each time that write leveling been triggered by counter expiring. Set to 0 or.." "0,1"
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bitfld.long 0x1C 0.--1. "PI_WRLVL_RESP_MASK,Mask for the dfi_wrlvl_resp signal during write leveling." "0,1,2,3"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_27,"
hexmask.long.byte 0x20 8.--15. 1. "PI_TDFI_WRLVL_EN,Defines the DFI tWRLVL_EN timing parameter [in DFI clocks]  the minimum cycles from a dfi_wrlvl_en assertion to the first dfi_wrlvl_strobe assertion."
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rbitfld.long 0x20 0. "PI_WRLVL_ERROR_STATUS,Holds the error associated with the write level error interrupt. Bit [0] set indicates a TDFI_WRLVL_MAX parameter violation and bit [1] set indicates a TDFI_WRLVL_RESP parameter violation. READ-ONLY" "0,1"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_28,"
hexmask.long 0x24 0.--31. 1. "PI_TDFI_WRLVL_RESP,Defines the DFI tWRLVL_RESP timing parameter [in DFI clocks]  the maximum cycles between a dfi_wrlvl_req assertion and a dfi_wrlvl_en assertion."
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_29,"
hexmask.long 0x28 0.--31. 1. "PI_TDFI_WRLVL_MAX,Defines the DFI tWRLVL_MAX timing parameter [in DFI clocks]  the maximum cycles between a dfi_wrlvl_en assertion and a valid dfi_wrlvl_resp."
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_30,"
bitfld.long 0x2C 24.--25. "PI_ODT_VALUE,When using LPDDR4  this value will be driven out on the dfi_odt signal." "0,1,2,3"
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hexmask.long.byte 0x2C 16.--19. 1. "PI_TODTH_RD,Defines the minimum DRAM cycles of ODT high time for a read command  in memory clocks."
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hexmask.long.byte 0x2C 8.--11. 1. "PI_TODTH_WR,Defines the minimum DRAM cycles of ODT high time for a write command  in memory clocks."
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hexmask.long.byte 0x2C 0.--4. 1. "PI_WRLVL_STROBE_NUM,Defines the number of write leveling strobes generated."
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_31,"
bitfld.long 0x30 0.--1. "PI_ADDRESS_MIRRORING,Indicates which chip selects support address mirroring. Bit [0] controls cs0  bit [1] controls cs1  etc. Set each bit to 1 to enable." "0,1,2,3"
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_32,"
hexmask.long 0x34 0.--25. 1. "PI_CA_PARITY_ERROR_INJECT,Selects bit to corrupt on the CA bus for CA parity error injection."
wgroup.long 0x2084++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_33,"
bitfld.long 0x0 24. "PI_RDLVL_GATE_REQ,User request to initiate gate training. Set to 1 to trigger. WRITE-ONLY" "0,1"
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bitfld.long 0x0 16. "PI_RDLVL_REQ,User request to initiate data eye training. Set to 1 to trigger. WRITE-ONLY" "0,1"
group.long 0x2088++0xC3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_34,"
bitfld.long 0x0 8. "PI_RDLVL_CS,Specifies the target chip select for the data eye training operation initiated through the RDLVL_REQ parameter or the gate training operation initiated through the RDLVL_GATE_REQ parameter." "0,1"
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bitfld.long 0x0 0.--1. "PI_RDLVL_CS_SW,Specifies the target chip select for the data eye training operation initiated through the RDLVL_REQ parameter or the gate training operation initiated through the RDLVL_GATE_REQ parameter." "0,1,2,3"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_35,"
hexmask.long 0x4 0.--31. 1. "PI_RDLVL_PAT_0,Non-default pattern 0 used for read data eye training of DDR4 or LPDDR4  and read dbi training of DDR4."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_36,"
hexmask.long 0x8 0.--31. 1. "PI_RDLVL_PAT_1,Non-default pattern 1 used for read data eye training of DDR4 or LPDDR4  and read dbi training of DDR4."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_37,"
hexmask.long 0xC 0.--31. 1. "PI_RDLVL_PAT_2,Non-default pattern 2 used for read data eye training of DDR4 or LPDDR4  and read dbi training of DDR4."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_38,"
hexmask.long 0x10 0.--31. 1. "PI_RDLVL_PAT_3,Non-default pattern 3 used for read data eye training of DDR4 or LPDDR4  and read dbi training of DDR4."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_39,"
hexmask.long 0x14 0.--31. 1. "PI_RDLVL_PAT_4,Non-default pattern 4 used for read data eye training of DDR4 or LPDDR4  and read dbi training of DDR4."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_40,"
hexmask.long 0x18 0.--31. 1. "PI_RDLVL_PAT_5,Non-default pattern 5 used for read data eye training of DDR4 or LPDDR4  and read dbi training of DDR4."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_41,"
hexmask.long 0x1C 0.--31. 1. "PI_RDLVL_PAT_6,Non-default pattern 6 used for read data eye training of DDR4 or LPDDR4  and read dbi training of DDR4."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_42,"
hexmask.long 0x20 0.--31. 1. "PI_RDLVL_PAT_7,Non-default pattern 7 used for read data eye training of DDR4 or LPDDR4  and read dbi training of DDR4."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_43,"
bitfld.long 0x24 24. "PI_RDLVL_GATE_ON_SREF_EXIT,Enables automatic gate training on a self-refresh exit. Set to 1 to enable." "0,1"
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bitfld.long 0x24 16. "PI_RDLVL_DISABLE_DFS,Disables automatic data eye training on freq change. Set to 1 to disable rdlvl on dfs Set to 0 to enable rdlvl on dfs." "0,1"
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bitfld.long 0x24 8. "PI_RDLVL_ON_SREF_EXIT,Enables automatic data eye training on a self-refresh exit. Set to 1 to enable." "0,1"
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hexmask.long.byte 0x24 0.--3. 1. "PI_RDLVL_SEQ_EN,Specifies the pattern  format and MPR for data eye training."
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_44,"
bitfld.long 0x28 24. "PI_RDLVL_ROTATE,Enables rotational CS for interval data eye training. Set to 1 for rotating CS." "0,1"
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bitfld.long 0x28 16. "PI_RDLVL_GATE_ON_MPD_EXIT,Enables automatic gate training on a maximum power down mode exit. Set to 1 to enable." "0,1"
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bitfld.long 0x28 8. "PI_RDLVL_ON_MPD_EXIT,Enables automatic data eye training on a maximum power down mode exit. Set to 1 to enable." "0,1"
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bitfld.long 0x28 0. "PI_RDLVL_GATE_DISABLE_DFS,Disables automatic gate training on freq change. Set to 1 to disable rdlvl_gate on dfs Set to 0 to enable rdlvl_gate on dfs." "0,1"
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_45,"
bitfld.long 0x2C 16.--17. "PI_RDLVL_GATE_CS_MAP,Defines the chip select map for gate training operations. Bit [0] controls cs0  bit [1] controls cs1  etc. Set each bit to 1 to enable chip for gate training." "0,1,2,3"
newline
bitfld.long 0x2C 8.--9. "PI_RDLVL_CS_MAP,Defines the chip select map for data eye training operations. Bit [0] controls cs0  bit [1] controls cs1  etc. Set each bit to 1 to enable chip for data eye training." "0,1,2,3"
newline
bitfld.long 0x2C 0. "PI_RDLVL_GATE_ROTATE,Enables rotational CS for interval gate training. Set to 1 for rotating CS." "0,1"
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_46,"
hexmask.long.word 0x30 0.--9. 1. "PI_TDFI_RDLVL_RR,Defines the DFI tRDLVL_RR timing parameter [in DFI clocks]  the minimum cycles between read commands."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_47,"
hexmask.long 0x34 0.--31. 1. "PI_TDFI_RDLVL_RESP,Defines the DFI tRDLVL_RESP timing parameter [in DFI clocks]  the maximum cycles between a dfi_rdlvl_req or dfi_rdlvl_gate_req assertion and a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_48,"
hexmask.long.byte 0x38 8.--15. 1. "PI_TDFI_RDLVL_EN,Defines the DFI tRDLVL_EN timing parameter [in DFI clocks]  the minimum cycles from a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion to the first read or MRR. Set to 1 means the minium value[1 cycle]  set to 0 means the maxium value"
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bitfld.long 0x38 0.--1. "PI_RDLVL_RESP_MASK,Mask for the dfi_rdlvl_resp signal during data eye training." "0,1,2,3"
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_49,"
hexmask.long 0x3C 0.--31. 1. "PI_TDFI_RDLVL_MAX,Defines the DFI tRDLVL_MAX timing parameter [in DFI clocks]  the maximum cycles between a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion and a valid dfi_rdlvl_resp."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_50,"
hexmask.long.word 0x40 8.--23. 1. "PI_RDLVL_INTERVAL,Number of long count sequences counted between automatic data eye training commands."
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rbitfld.long 0x40 0. "PI_RDLVL_ERROR_STATUS,Holds the error associated with the data eye training error or gate training error interrupt. Uppermost bit set indicates a TDFI_RDLVL_RESP parameter violation. Next uppermost bit set indicates a TDFI_RDLVL_MAX parameter violation." "0,1"
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_51,"
hexmask.long.byte 0x44 24.--27. 1. "PI_RDLVL_PATTERN_NUM,Defines the number of pattern supported in read leveling."
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hexmask.long.byte 0x44 16.--19. 1. "PI_RDLVL_PATTERN_START,Defines the start pattern in read leveling."
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hexmask.long.word 0x44 0.--15. 1. "PI_RDLVL_GATE_INTERVAL,Number of long count sequences counted between automatic gate training commands."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_52,"
bitfld.long 0x48 24. "PI_REG_DIMM_ENABLE,Enable registered DIMM operation. Set to 1 to enable." "0,1"
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bitfld.long 0x48 16. "PI_RD_PREAMBLE_TRAINING_EN,Enable read preamble training during gate training. Set to 1 to enable." "0,1"
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hexmask.long.byte 0x48 8.--12. 1. "PI_RDLVL_GATE_STROBE_NUM,Defines the number of back to back MPC command in one read process in read gate training."
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hexmask.long.byte 0x48 0.--4. 1. "PI_RDLVL_STROBE_NUM,Defines the number of back to back MPC command in one read process in read eye training."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_53,"
bitfld.long 0x4C 24.--25. "PI_CALVL_CS_SW,Specifies the target chip select for the CA training operation initiated through the CALVL_REQ parameter." "0,1,2,3"
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bitfld.long 0x4C 16. "PI_CALVL_REQ,User request to initiate CA training. Set to 1 to trigger. WRITE-ONLY" "0,1"
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hexmask.long.byte 0x4C 8.--15. 1. "PI_TDFI_PHY_WRLAT,Holds the calculated DFI tPHY_WRLAT timing parameter [in DFI PHY clocks]  the maximum cycles between a write command and a dfi_wrdata_en assertion. READ-ONLY"
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hexmask.long.byte 0x4C 0.--7. 1. "PI_TDFI_RDDATA_EN,Holds the calculated DFI tRDDATA_EN timing parameter [in DFI PHY clocks]  the maximum cycles between a read command and a dfi_rddata_en assertion. READ-ONLY"
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_54,"
bitfld.long 0x50 24.--25. "PI_CALVL_SEQ_EN,Specifies which CA training patterns will be used. Set to 0 for pattern 0 only  set to 1 for patterns 0 and 1  set to 2 for patterns 0  1 and 2  or set to 3 for all patterns." "0,1,2,3"
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bitfld.long 0x50 0. "PI_CALVL_CS,Specifies the target chip select for the CA training operation initiated through the CALVL_REQ parameter." "0,1"
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_55,"
bitfld.long 0x54 24. "PI_CALVL_ROTATE,Enables rotational CS for interval CA training. Set to 1 for rotating CS." "0,1"
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bitfld.long 0x54 16. "PI_CALVL_DISABLE_DFS,Disables automatic CA training on freq change. Set to 1 to disable CA training on dfs  Set to 0 to enable CA training ." "0,1"
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bitfld.long 0x54 8. "PI_CALVL_ON_SREF_EXIT,Enables automatic CA training on a self-refresh exit. Set to 1 to enable." "0,1"
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bitfld.long 0x54 0. "PI_CALVL_PERIODIC,Enables the use of the dfi_lvl_periodic signal during CA training. Set to 1 to enable." "0,1"
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_56,"
hexmask.long.byte 0x58 8.--15. 1. "PI_TDFI_CALVL_EN,Defines the DFI tCALVL_EN timing parameter [in DFI clocks]  the minimum cycles between a dfi_calvl_en assertion and a dfi_cke de-assertion."
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bitfld.long 0x58 0.--1. "PI_CALVL_CS_MAP,Defines the chip select map for CA training operations. Bit [0] controls cs0  bit [1] controls cs1  etc. Set each bit to 1 to enable chip for CA training." "0,1,2,3"
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_57,"
hexmask.long 0x5C 0.--31. 1. "PI_TDFI_CALVL_RESP,Defines the DFI tCALVL_RESP timing parameter [in DFI clocks]  the maximum cycles between a dfi_calvl_req assertion and a dfi_calvl_en assertion."
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_58,"
hexmask.long 0x60 0.--31. 1. "PI_TDFI_CALVL_MAX,Defines the DFI tCALVL_MAX timing parameter [in DFI clocks]  the maximum cycles between a dfi_calvl_en assertion and a valid dfi_calvl_resp."
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_59,"
hexmask.long.word 0x64 16.--31. 1. "PI_CALVL_INTERVAL,Number of long count sequences counted between automatic CA training commands."
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rbitfld.long 0x64 8.--9. "PI_CALVL_ERROR_STATUS,Holds the error associated with the CA training error interrupt. Bit [0] set indicates a TDFI_CALVL_RESP parameter violation and bit [1] set indicates a TDFI_CALVL_MAX parameter violation. READ-ONLY" "0,1,2,3"
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bitfld.long 0x64 0. "PI_CALVL_RESP_MASK,Mask for the dfi_calvl_resp signal during CA training." "0,1"
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_60,"
hexmask.long.byte 0x68 24.--28. 1. "PI_TCAEXT,DRAM tCAEXT value in memory cycles."
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hexmask.long.byte 0x68 16.--20. 1. "PI_TCACKEH,DRAM tCACKEH value in memory cycles."
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hexmask.long.byte 0x68 8.--13. 1. "PI_TCAMRD,DRAM tCAMRD value in memory cycles."
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hexmask.long.byte 0x68 0.--4. 1. "PI_TCACKEL,DRAM tCACKEL value in memory cycles."
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_61,"
hexmask.long.byte 0x6C 24.--31. 1. "PI_TDFI_INIT_START_MIN,Minimum number of DFI clocks before dfi_init_start can be driven after a previous command/training event."
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hexmask.long.byte 0x6C 16.--19. 1. "PI_CALVL_VREF_NORMAL_STEPSIZE,The adjust step for the post-initial Vref[ca] training."
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hexmask.long.byte 0x6C 8.--11. 1. "PI_CALVL_VREF_INITIAL_STEPSIZE,The adjust step for the initial Vref[ca] training."
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bitfld.long 0x6C 0. "PI_CA_TRAIN_VREF_EN,Control for VREF training during CA training post power-on initialization. Set to enable VREF training." "0,1"
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_62,"
bitfld.long 0x70 24. "PI_REFRESH_BETWEEN_SEGMENT_DISABLE,Disable the refresh between CA first and second segment training. Set to 1 to disable." "0,1"
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hexmask.long.byte 0x70 16.--22. 1. "PI_SW_CA_TRAIN_VREF,The Vref value which is set for SW step by step CA training."
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hexmask.long.byte 0x70 8.--12. 1. "PI_CALVL_STROBE_NUM,The consecutive dfi_calvl_strobe number when updating the CA vref data."
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hexmask.long.byte 0x70 0.--7. 1. "PI_TCKCKEH,DRAM tCKELCK Clock and command valid before CKE HIGH."
line.long 0x74 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_63,"
hexmask.long.byte 0x74 24.--31. 1. "PI_TDFI_INIT_COMPLETE_MIN,Minimum number of DFI clocks from dfi_init_complete to a command/training event."
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bitfld.long 0x74 16. "PI_DRAM_CLK_DISABLE_DEASSERT_SEL,Indicate dfi_dram_clk_disable deassert following dfi_init_start deassert or dfi_init_complete assert. Set to 0: dfi_dram_clk_disable deassert following dfi_init_start deassert. Set to 1: dfi_dram_clk_disable deassert.." "0: dfi_dram_clk_disable deassert following..,1: dfi_dram_clk_disable deassert following.."
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hexmask.long.byte 0x74 8.--15. 1. "PI_INIT_STARTORCOMPLETE_2_CLKDISABLE,Defines the delay from deasserting of dfi_init_start or asserting of dfi_init_complete to deasserting of dfi_dram_clk_disable in DFI clock."
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hexmask.long.byte 0x74 0.--7. 1. "PI_CLKDISABLE_2_INIT_START,Defines the delay from the asserting of dfi_dram_clk_disable to the asserting of dfi_init_start in DFI clock."
line.long 0x78 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_64,"
bitfld.long 0x78 24. "PI_MC_DFS_PI_SET_VREF_ENABLE,Enable the PI to set VREF value after DFS issued by MC. MR12 and MR14 for LPDDR4. MR6 for DDR4. 1 means disable." "0,1"
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bitfld.long 0x78 16. "PI_VREFLVL_DISABLE_DFS,Disables automatic VREF training on freq change. Set to 1 to disable." "0,1"
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bitfld.long 0x78 8. "PI_VREF_PDA_EN,Enable per-DRAM addressability during VREF training. Set to 1 to enable." "0,1"
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bitfld.long 0x78 0. "PI_VREF_CS,Specifies the target chip select for the VREF training operation." "0,1"
line.long 0x7C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_65,"
bitfld.long 0x7C 24.--25. "PI_WDQLVL_RESP_MASK,Write DQ training response mask. When set to 1  the dfi_wdqlvl_en of the slice is not asserted." "0,1,2,3"
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bitfld.long 0x7C 16.--18. "PI_WDQLVL_BST_NUM,Defines the number of write/read bursts issued at each step in write DQ training." "0,1,2,3,4,5,6,7"
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bitfld.long 0x7C 8. "PI_WDQLVL_VREF_EN,Control for VREF training as part of non-initialization write DQ training." "0,1"
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hexmask.long.byte 0x7C 0.--7. 1. "PI_INIT_COMPLETE_TO_MC_DELAY_COUNT,It controls the time PI bypass CKE at the beginning of PI mask dfi_init_complete to controller."
line.long 0x80 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_66,"
hexmask.long.byte 0x80 24.--28. 1. "PI_WDQLVL_VREF_NORMAL_STEPSIZE,Write DQ training vref step size for post_initial training."
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hexmask.long.byte 0x80 16.--20. 1. "PI_WDQLVL_VREF_INITIAL_STEPSIZE,Write DQ training vref step size for initial training."
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bitfld.long 0x80 8.--9. "PI_WDQLVL_CS_MAP,Map of CS's included in write DQ training sequence." "0,1,2,3"
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bitfld.long 0x80 0. "PI_WDQLVL_ROTATE,Enables write DQ training rotate for interval training." "0,1"
line.long 0x84 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_67,"
bitfld.long 0x84 24. "PI_WDQLVL_CS,Write DQ training target chip select." "0,1"
newline
bitfld.long 0x84 16.--17. "PI_WDQLVL_CS_SW,Write DQ training target chip select." "0,1,2,3"
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bitfld.long 0x84 8. "PI_WDQLVL_REQ,SW write to initiate Write DQ training request. WRITE-ONLY" "0,1"
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bitfld.long 0x84 0. "PI_WDQLVL_PERIODIC,Enables periodic write DQ training." "0,1"
line.long 0x88 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_68,"
hexmask.long.byte 0x88 0.--7. 1. "PI_TDFI_WDQLVL_EN,DFI timing param tWDQLVL_EN. Minimum number of DFI clocks required after the write DQ training enable signal is asserted until the first write command may be asserted."
line.long 0x8C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_69,"
hexmask.long 0x8C 0.--31. 1. "PI_TDFI_WDQLVL_RESP,DFI timing param tWDQLVL_RESP. Maximum number of DFI clocks that may occur between a write DQ training request and the associated mode enable."
line.long 0x90 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_70,"
hexmask.long 0x90 0.--31. 1. "PI_TDFI_WDQLVL_MAX,DFI timing param tWDQLVL_MAX. Maximum number of DFI clocks that the PI will wait for a response from the PHY."
line.long 0x94 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_71,"
bitfld.long 0x94 24. "PI_WDQLVL_ON_MPD_EXIT,Issue a write DQ training command on maximum power saving mode exit." "0,1"
newline
bitfld.long 0x94 16. "PI_WDQLVL_ON_SREF_EXIT,Issue a write DQ training command on self-refresh exit." "0,1"
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hexmask.long.word 0x94 0.--15. 1. "PI_WDQLVL_INTERVAL,Sets the maximum number of long count sequences allowed between automatic write DQ training operations."
line.long 0x98 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_72,"
bitfld.long 0x98 16.--17. "PI_WDQLVL_NEED_SAVE_RESTORE,Enables the use of functional DRAM address space for write DQ training  1 = enable  not for LPDDR4." "?,1: enable,?,?"
newline
rbitfld.long 0x98 8.--9. "PI_WDQLVL_ERROR_STATUS,Holds the error associated with the write dq level error interrupt. Bit [0] set indicates a PI_TDFI_WDQLVL_MAX parameter violation and bit [1] set indicates a PI_TDFI_WDQLVL_RESP parameter violation. READ-ONLY." "0,1,2,3"
newline
bitfld.long 0x98 0. "PI_WDQLVL_DISABLE_DFS,Disable automatic write DQ training on freq change. Set to 1 to disable." "0,1"
line.long 0x9C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_73,"
hexmask.long 0x9C 0.--31. 1. "PI_WDQLVL_DRAM_LVL_START_ADDR_0,Start address of WDQ leveling  not for LPDDR4."
line.long 0xA0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_74,"
bitfld.long 0xA0 16. "PI_NO_MEMORY_DM,Defines if the attached memory supports the Data Mask function  1 = not supported." "?,1: not supported"
newline
bitfld.long 0xA0 8. "PI_WDQLVL_DM_LEVEL_EN,Enable for write DM training as part of the write DQ training  not for LPDDR4." "0,1"
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bitfld.long 0xA0 0. "PI_WDQLVL_DRAM_LVL_START_ADDR_1,Start address of WDQ leveling  not for LPDDR4." "0,1"
line.long 0xA4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_75,"
bitfld.long 0xA4 24. "PI_WDQLVL_NIBBLE_MODE,WDQ Training Nibble mode indication. When set to 1  nibble mode is enabled  and the training timing is doubled." "0,1"
newline
bitfld.long 0xA4 16. "PI_SWLVL_SM2_DM_NIBBLE_START,Start command for stage 2  when in the process of DM leveling or nibble mode. WRITE-ONLY" "0,1"
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hexmask.long.word 0xA4 0.--9. 1. "PI_TDFI_WDQLVL_WW,Minimum number of DFI clocks to be inserted between write commands during the DM portion of write DQ training."
line.long 0xA8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_76,"
bitfld.long 0xA8 24. "PI_WDQLVL_PDA_VREF_TRAIN,Enable for the use of PDA to set the VREF during write DQ training  1 = enabled." "?,1: enabled"
newline
bitfld.long 0xA8 16. "PI_WDQLVL_PDA_EN,Enable for the use of write DQ training for PDA mode  1 = enabled." "?,1: enabled"
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bitfld.long 0xA8 8. "PI_DQS_OSC_PERIOD_EN,Enable for DQS oscillator triggered periodic write DQ training  1 = enabled." "?,1: enabled"
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bitfld.long 0xA8 0. "PI_WDQLVL_OSC_EN,Enable for DQS oscillator triggered write DQ training  1 = enabled." "?,1: enabled"
line.long 0xAC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_77,"
hexmask.long.byte 0xAC 24.--28. 1. "PI_TCCD,DRAM CAS-to-CAS value in cycles."
newline
bitfld.long 0xAC 16.--18. "PI_ROW_DIFF,Difference between number of address pins available and number being used." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xAC 8.--9. "PI_BANK_DIFF,Difference between number of bank pins available and number being used." "0,1,2,3"
newline
bitfld.long 0xAC 0.--1. "PI_DBILVL_RESP_MASK,Mask for the dfi_rdlvl_resp signal during read dbi training." "0,1,2,3"
line.long 0xB0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_78,"
line.long 0xB4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_79,"
line.long 0xB8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_80,"
line.long 0xBC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_81,"
line.long 0xC0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_82,"
rgroup.long 0x214C++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_83,"
hexmask.long 0x0 0.--29. 1. "PI_INT_STATUS,Status of interrupt features in the PI. READ-ONLY"
wgroup.long 0x2150++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_84,"
hexmask.long 0x0 0.--28. 1. "PI_INT_ACK,Clear the corresponding interrupt bit of the PI_INT_STATUS parameter. WRITE-ONLY"
group.long 0x2154++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_85,"
hexmask.long 0x0 0.--29. 1. "PI_INT_MASK,Mask for PI_int signals from the PI_INT_STATUS parameter."
rgroup.long 0x2158++0x13
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_86,"
hexmask.long 0x0 0.--31. 1. "PI_BIST_EXP_DATA_0,Expected data on BIST error. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_87,"
hexmask.long 0x4 0.--31. 1. "PI_BIST_EXP_DATA_1,Expected data on BIST error. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_88,"
hexmask.long 0x8 0.--31. 1. "PI_BIST_FAIL_DATA_0,Actual data on BIST error. READ-ONLY"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_89,"
hexmask.long 0xC 0.--31. 1. "PI_BIST_FAIL_DATA_1,Actual data on BIST error. READ-ONLY"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_90,"
hexmask.long 0x10 0.--31. 1. "PI_BIST_FAIL_ADDR_0,The burst aligned address of BIST error. READ-ONLY"
group.long 0x216C++0xC7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_91,"
bitfld.long 0x0 24. "PI_CMD_SWAP_EN,Command pin swap function enable" "0,1"
newline
hexmask.long.byte 0x0 16.--20. 1. "PI_LONG_COUNT_MASK,Reduces the length of the long counter from 1024 cycles."
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hexmask.long.byte 0x0 8.--13. 1. "PI_BSTLEN,Encoded burst length sent to DRAMs during initialization."
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rbitfld.long 0x0 0. "PI_BIST_FAIL_ADDR_1,The burst aligned address of BIST error. READ-ONLY" "0,1"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_92,"
hexmask.long.byte 0x4 24.--28. 1. "PI_BG_MUX_1,Command pin BG_1 mux selector"
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hexmask.long.byte 0x4 16.--20. 1. "PI_BG_MUX_0,Command pin BG_0 mux selector"
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hexmask.long.byte 0x4 8.--12. 1. "PI_ACT_N_MUX,Command pin ACT_N mux selector"
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hexmask.long.byte 0x4 0.--4. 1. "PI_PARITY_IN_MUX,Command pin parity mux selector"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_93,"
hexmask.long.byte 0x8 24.--28. 1. "PI_BANK_MUX_0,Command pin BANK_0 mux selector"
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hexmask.long.byte 0x8 16.--20. 1. "PI_WE_N_MUX,Command pin WE_N mux selector"
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hexmask.long.byte 0x8 8.--12. 1. "PI_CAS_N_MUX,Command pin CAS_N mux selector"
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hexmask.long.byte 0x8 0.--4. 1. "PI_RAS_N_MUX,Command pin RAS_N mux selector"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_94,"
bitfld.long 0xC 24. "PI_DATA_BYTE_SWAP_SLICE1,DATA pin 1 mux selector" "0,1"
newline
bitfld.long 0xC 16. "PI_DATA_BYTE_SWAP_SLICE0,DATA pin 0 mux selector" "0,1"
newline
bitfld.long 0xC 8. "PI_DATA_BYTE_SWAP_EN,DATA pin swap function enable" "0,1"
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hexmask.long.byte 0xC 0.--4. 1. "PI_BANK_MUX_1,Command pin BANK_1 mux selector"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_95,"
rbitfld.long 0x10 24.--25. "PI_UPDATE_ERROR_STATUS,Identifies the source of any DFI PI-initiated update errors. Value of 1 indicates a timing violation of the associated timing parameter. Bit 1-0: ctrlupd_max_error  ctrlupd_interval_error. Bit 6-2: reserved. READ-ONLY" "0,1,2,3"
newline
hexmask.long.word 0x10 8.--23. 1. "PI_TDFI_CTRLUPD_MIN,Reports the DFI tCTRLUPD_MIN timing parameter [in DFI clocks]  the minimum cycles that dfi_ctrlupd_req must be asserted."
newline
bitfld.long 0x10 0. "PI_CTRLUPD_REQ_PER_AREF_EN,Enable an automatic PI initiated update [dfi_ctrlupd_req] after every refresh. Set to 1 to enable." "0,1"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_96,"
rbitfld.long 0x14 24. "PI_BIST_LFSR_PATTERN_DONE,BIST operation lfsr pattern  data pattern 1'b0 means the data is useful 1'b1 means next pattern sequence can ingore. READ-ONLY" "0,1"
newline
rbitfld.long 0x14 16.--17. "PI_BIST_RESULT,BIST operation status [pass/fail]. Bit [0] indicates data check status and bit [1] indicates address check status. Value of 1 is a passing result. READ-ONLY" "0,1,2,3"
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bitfld.long 0x14 8. "PI_BIST_GO,Initiate a BIST operation. Set to 1 to trigger." "0,1"
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bitfld.long 0x14 0.--2. "PI_TDFI_PARIN_LAT,Defines the DFI tPARIN_LAT timing parameter [in DFI PHY clocks]  the maximum cycles between a DFI command and a dfi_parity_in signal assertion." "0,1,2,3,4,5,6,7"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_97,"
bitfld.long 0x18 16. "PI_BIST_ADDR_CHECK,Enable address checking with BIST operation. Set to 1 to enable." "0,1"
newline
bitfld.long 0x18 8. "PI_BIST_DATA_CHECK,Enable data checking with BIST operation. Set to 1 to enable." "0,1"
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hexmask.long.byte 0x18 0.--7. 1. "PI_ADDR_SPACE,Sets the number of address bits to check during BIST operation. The end address of BIST is start_address+[1 shifted up by PI_ADDR_SPACE]-1. The end address should not beyond the actual memory address range."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_98,"
hexmask.long 0x1C 0.--31. 1. "PI_BIST_START_ADDRESS_0,Start BIST checking at this address."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_99,"
hexmask.long.byte 0x20 8.--15. 1. "PI_MBIST_INIT_PATTERN,PI mbist data check  random lfsr pattern mode init pattern seed."
newline
bitfld.long 0x20 0. "PI_BIST_START_ADDRESS_1,Start BIST checking at this address." "0,1"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_100,"
hexmask.long 0x24 0.--31. 1. "PI_BIST_DATA_MASK,Mask applied to data for BIST error checking. Bit [0] controls memory data path bit [0]  bit [1] controls memory data path bit [1]  etc. The mask range is the data transfer size in each memory clock cycle [The data on a rising edge and.."
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_101,"
hexmask.long.word 0x28 16.--27. 1. "PI_BIST_ERR_STOP,Defines the maximum number of error occurrences allowed prior to quitting when the BIST_TEST_MODE parameter is set to 1  2 or 3. A value of 0 will allow the test to run to completion."
newline
hexmask.long.word 0x28 0.--11. 1. "PI_BIST_ERR_COUNT,Indicates the number of BIST errors found when the BIST_TEST_MODE parameter is set to 1  2 or 3. READ-ONLY"
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_102,"
hexmask.long 0x2C 0.--31. 1. "PI_BIST_ADDR_MASK_0_0,Defines an address to be masked during the BIST operation.."
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_103,"
bitfld.long 0x30 0.--1. "PI_BIST_ADDR_MASK_0_1,Defines an address to be masked during the BIST operation.." "0,1,2,3"
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_104,"
hexmask.long 0x34 0.--31. 1. "PI_BIST_ADDR_MASK_1_0,Defines an address to be masked during the BIST operation.."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_105,"
bitfld.long 0x38 0.--1. "PI_BIST_ADDR_MASK_1_1,Defines an address to be masked during the BIST operation.." "0,1,2,3"
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_106,"
hexmask.long 0x3C 0.--31. 1. "PI_BIST_ADDR_MASK_2_0,Defines an address to be masked during the BIST operation.."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_107,"
bitfld.long 0x40 0.--1. "PI_BIST_ADDR_MASK_2_1,Defines an address to be masked during the BIST operation.." "0,1,2,3"
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_108,"
hexmask.long 0x44 0.--31. 1. "PI_BIST_ADDR_MASK_3_0,Defines an address to be masked during the BIST operation.."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_109,"
bitfld.long 0x48 0.--1. "PI_BIST_ADDR_MASK_3_1,Defines an address to be masked during the BIST operation.." "0,1,2,3"
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_110,"
hexmask.long 0x4C 0.--31. 1. "PI_BIST_ADDR_MASK_4_0,Defines an address to be masked during the BIST operation.."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_111,"
bitfld.long 0x50 0.--1. "PI_BIST_ADDR_MASK_4_1,Defines an address to be masked during the BIST operation.." "0,1,2,3"
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_112,"
hexmask.long 0x54 0.--31. 1. "PI_BIST_ADDR_MASK_5_0,Defines an address to be masked during the BIST operation.."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_113,"
bitfld.long 0x58 0.--1. "PI_BIST_ADDR_MASK_5_1,Defines an address to be masked during the BIST operation.." "0,1,2,3"
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_114,"
hexmask.long 0x5C 0.--31. 1. "PI_BIST_ADDR_MASK_6_0,Defines an address to be masked during the BIST operation.."
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_115,"
bitfld.long 0x60 0.--1. "PI_BIST_ADDR_MASK_6_1,Defines an address to be masked during the BIST operation.." "0,1,2,3"
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_116,"
hexmask.long 0x64 0.--31. 1. "PI_BIST_ADDR_MASK_7_0,Defines an address to be masked during the BIST operation.."
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_117,"
bitfld.long 0x68 0.--1. "PI_BIST_ADDR_MASK_7_1,Defines an address to be masked during the BIST operation.." "0,1,2,3"
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_118,"
hexmask.long 0x6C 0.--31. 1. "PI_BIST_ADDR_MASK_8_0,Defines an address to be masked during the BIST operation.."
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_119,"
bitfld.long 0x70 0.--1. "PI_BIST_ADDR_MASK_8_1,Defines an address to be masked during the BIST operation.." "0,1,2,3"
line.long 0x74 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_120,"
hexmask.long 0x74 0.--31. 1. "PI_BIST_ADDR_MASK_9_0,Defines an address to be masked during the BIST operation.."
line.long 0x78 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_121,"
bitfld.long 0x78 24.--25. "PI_BIST_PAT_MODE,Sets the pattern mode of BIST. 'b00 indicates using built-in pattern. 'b01 indicates checkerboard pattern  each data transfer inverts the last data transfer based on the built-in pattern. 'b10 indicates using both user pattern and.." "0,1,2,3"
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bitfld.long 0x78 16.--17. "PI_BIST_ADDR_MODE,Sets the address traversing order of BIST. 'b00 indicates fast column order [burst-column-bank-row-rank]. 'b01 indicates fast row order [burst-row-column-bank-rank]. 'b10 indicates fast bank order [burst-bank-column-row-rank]." "0,1,2,3"
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bitfld.long 0x78 8.--10. "PI_BIST_MODE,Sets the BIST data checking mode. 'b00 indicates MOVI13N mode. 'b01 indicates March C mode. 'b10 indicates GALPAT mode. 'b11 indicates PRBS mode. 'b100 indicates programmable March data check mode." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x78 0.--1. "PI_BIST_ADDR_MASK_9_1,Defines an address to be masked during the BIST operation.." "0,1,2,3"
line.long 0x7C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_122,"
hexmask.long 0x7C 0.--31. 1. "PI_BIST_USER_PAT_0,Sets the user-specified pattern of BIST."
line.long 0x80 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_123,"
hexmask.long 0x80 0.--31. 1. "PI_BIST_USER_PAT_1,Sets the user-specified pattern of BIST."
line.long 0x84 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_124,"
hexmask.long.byte 0x84 0.--5. 1. "PI_BIST_PAT_NUM,Sets the max used pattern number of BIST from a total of 8 built-in patterns. Ex. set to 3  The BIST would use pattern 1  2 and 3."
line.long 0x88 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_125,"
hexmask.long 0x88 0.--29. 1. "PI_BIST_STAGE_0,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4."
line.long 0x8C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_126,"
hexmask.long 0x8C 0.--29. 1. "PI_BIST_STAGE_1,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4."
line.long 0x90 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_127,"
hexmask.long 0x90 0.--29. 1. "PI_BIST_STAGE_2,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4."
line.long 0x94 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_128,"
hexmask.long 0x94 0.--29. 1. "PI_BIST_STAGE_3,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4."
line.long 0x98 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_129,"
hexmask.long 0x98 0.--29. 1. "PI_BIST_STAGE_4,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4."
line.long 0x9C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_130,"
hexmask.long 0x9C 0.--29. 1. "PI_BIST_STAGE_5,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4."
line.long 0xA0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_131,"
hexmask.long 0xA0 0.--29. 1. "PI_BIST_STAGE_6,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4."
line.long 0xA4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_132,"
hexmask.long 0xA4 0.--29. 1. "PI_BIST_STAGE_7,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4."
line.long 0xA8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_133,"
bitfld.long 0xA8 24. "PI_SELF_REFRESH_EN,Control for PI to enable self refresh mode. Set to 1 to enable." "0,1"
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bitfld.long 0xA8 16. "PI_CRC_CALC,Defines where CRC is performed; set to 1 for PI responsibility or clear to 0 for PHY responsibility." "0,1"
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bitfld.long 0xA8 8. "PI_BG_ROTATE_EN,Enable bank group rotation. Set to 1 to enable." "0,1"
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hexmask.long.byte 0xA8 0.--3. 1. "PI_COL_DIFF,Difference between number of column pins available and number being used."
line.long 0xAC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_134,"
bitfld.long 0xAC 24. "PI_SREF_ENTRY_REQ,In PI power up data retention  PI can issued sref entry command. WRITE-ONLY" "0,1"
newline
bitfld.long 0xAC 16. "PI_SREFRESH_EXIT_NO_REFRESH,Disables the automatic refresh request associated with self-refresh exit. Set to 1 to disable." "0,1"
newline
bitfld.long 0xAC 8. "PI_PWRUP_SREFRESH_EXIT,PI control powerup via self-refresh instead of full memory initialization. Set to 1 to enable." "0,1"
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bitfld.long 0xAC 0. "PI_MC_PWRUP_SREFRESH_EXIT,It indicates MC control powerup via self-refresh instead of full memory initialization. Set to 1 to enable." "0,1"
line.long 0xB0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_135,"
bitfld.long 0xB0 24. "PI_NO_AUTO_MRR_INIT,Disable MRR commands during initialization. Set to 1 to disable." "0,1"
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bitfld.long 0xB0 16. "PI_NO_PHY_IND_TRAIN_INIT,Disable PHY Independent Training during initialization. Set to 1 to disable." "0,1"
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bitfld.long 0xB0 8. "PI_NO_MRW_INIT,Disable MRW commands after training during initialization. Set to 1 to disable." "0,1"
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bitfld.long 0xB0 0. "PI_NO_MRW_BT_INIT,Disable MRW commands before training during initialization. Set to 1 to disable." "0,1"
line.long 0xB4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_136,"
hexmask.long 0xB4 0.--31. 1. "PI_TRST_PWRON,Duration of memory reset during power-on initialization."
line.long 0xB8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_137,"
hexmask.long 0xB8 0.--31. 1. "PI_CKE_INACTIVE,Number of cycles after reset before CKE will be active."
line.long 0xBC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_138,"
hexmask.long.word 0xBC 16.--31. 1. "PI_DLL_RST_DELAY,Minimum cycles required for DLL reset signal dll_rst_n to be held."
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bitfld.long 0xBC 8. "PI_DRAM_INIT_EN,Control for the initialization of DRAM by the PI." "0,1"
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bitfld.long 0xBC 0. "PI_DLL_RST,Enables use of the DLL reset [dll_rst_n]." "0,1"
line.long 0xC0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_139,"
hexmask.long.byte 0xC0 0.--7. 1. "PI_DLL_RST_ADJ_DLY,Minimum cycles after setting master delay in DLL until the DLL reset signal dll_rst_n may be asserted."
line.long 0xC4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_140,"
hexmask.long 0xC4 0.--25. 1. "PI_WRITE_MODEREG,Write memory mode register data to the DRAMs. Bits [7:0] define the memory mode register number if bit [23] is set  bits [15:8] define the chip select if bit [24] is clear  bits [23:16] define which memory mode register/s to write  bit.."
rgroup.long 0x2234++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_141,"
hexmask.long.byte 0x0 0.--7. 1. "PI_MRW_STATUS,Write memory mode register status. Bit [0] set indicates a WRITE_MODEREG parameter programming error. Bit [1] set indicates a PASR error. Bit [2] is Reserved. Bit [3] set indicates a self refresh or deep power down error. Bit [4] set.."
group.long 0x2238++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_142,"
hexmask.long.tbyte 0x0 0.--16. 1. "PI_READ_MODEREG,Read the specified memory mode register from specified chip when start bit set. Bits [7:0] define the memory mode register and bits [15:8] define the chip select. Set bit [16] to 1 to trigger."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_143,"
bitfld.long 0x4 24. "PI_NO_ZQ_INIT,Disable ZQ operations during initialization. Set to 1 to disable." "0,1"
newline
hexmask.long.tbyte 0x4 0.--23. 1. "PI_PERIPHERAL_MRR_DATA_0,Data and chip returned from memory mode register read requested by the READ_MODEREG parameter  Bits [15:0] define MRR data  [23:16] define the chip select. READ-ONLY"
rgroup.long 0x2240++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_144,"
bitfld.long 0x0 16. "PI_ZQ_REQ_PENDING,Indicates that a ZQ command is currently in progress or waiting to run. When this is asserted  no writes to ZQ_REQ should occur. READ-ONLY" "0,1"
group.long 0x2244++0x17
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_145,"
hexmask.long.byte 0x0 24.--31. 1. "PI_MONITOR_0,Monitor register 0. READ-ONLY."
newline
bitfld.long 0x0 16. "PI_MONITOR_CAP_SEL_0,Selection of captures for pi_monitor_0." "0,1"
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hexmask.long.byte 0x0 8.--11. 1. "PI_MONITOR_SRC_SEL_0,Selection of sources for pi_monitor_0."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_146,"
hexmask.long.byte 0x4 24.--27. 1. "PI_MONITOR_SRC_SEL_2,Selection of sources for pi_monitor_2."
newline
hexmask.long.byte 0x4 16.--23. 1. "PI_MONITOR_1,Monitor register 1. READ-ONLY."
newline
bitfld.long 0x4 8. "PI_MONITOR_CAP_SEL_1,Selection of captures for pi_monitor_1." "0,1"
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hexmask.long.byte 0x4 0.--3. 1. "PI_MONITOR_SRC_SEL_1,Selection of sources for pi_monitor_1."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_147,"
bitfld.long 0x8 24. "PI_MONITOR_CAP_SEL_3,Selection of captures for pi_monitor_3." "0,1"
newline
hexmask.long.byte 0x8 16.--19. 1. "PI_MONITOR_SRC_SEL_3,Selection of sources for pi_monitor_3."
newline
hexmask.long.byte 0x8 8.--15. 1. "PI_MONITOR_2,Monitor register 2. READ-ONLY."
newline
bitfld.long 0x8 0. "PI_MONITOR_CAP_SEL_2,Selection of captures for pi_monitor_2." "0,1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_148,"
hexmask.long.byte 0xC 24.--31. 1. "PI_MONITOR_4,Monitor register 4. READ-ONLY."
newline
bitfld.long 0xC 16. "PI_MONITOR_CAP_SEL_4,Selection of captures for pi_monitor_4." "0,1"
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hexmask.long.byte 0xC 8.--11. 1. "PI_MONITOR_SRC_SEL_4,Selection of sources for pi_monitor_4."
newline
hexmask.long.byte 0xC 0.--7. 1. "PI_MONITOR_3,Monitor register 3. READ-ONLY."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_149,"
hexmask.long.byte 0x10 24.--27. 1. "PI_MONITOR_SRC_SEL_6,Selection of sources for pi_monitor_6."
newline
hexmask.long.byte 0x10 16.--23. 1. "PI_MONITOR_5,Monitor register 5. READ-ONLY."
newline
bitfld.long 0x10 8. "PI_MONITOR_CAP_SEL_5,Selection of captures for pi_monitor_5." "0,1"
newline
hexmask.long.byte 0x10 0.--3. 1. "PI_MONITOR_SRC_SEL_5,Selection of sources for pi_monitor_5."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_150,"
bitfld.long 0x14 24. "PI_MONITOR_CAP_SEL_7,Selection of captures for pi_monitor_7." "0,1"
newline
hexmask.long.byte 0x14 16.--19. 1. "PI_MONITOR_SRC_SEL_7,Selection of sources for pi_monitor_7."
newline
hexmask.long.byte 0x14 8.--15. 1. "PI_MONITOR_6,Monitor register 6. READ-ONLY."
newline
bitfld.long 0x14 0. "PI_MONITOR_CAP_SEL_6,Selection of captures for pi_monitor_6." "0,1"
rgroup.long 0x225C++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_151,"
hexmask.long.byte 0x0 0.--7. 1. "PI_MONITOR_7,Monitor register 7. READ-ONLY."
wgroup.long 0x2260++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_152,"
hexmask.long.byte 0x0 0.--7. 1. "PI_MONITOR_STROBE,Strobe the pi_monitor once. Every bit corresponds respectively with a pi_monitor. WRITE-ONLY"
group.long 0x2264++0x2FF
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_153,"
hexmask.long.byte 0x0 16.--20. 1. "PI_FREQ_RETENTION_NUM,Monitor active freq number in PI for data_retention"
newline
hexmask.long.byte 0x0 8.--12. 1. "PI_FREQ_NUMBER_STATUS,Monitor active freq number in PI. READ-ONLY."
newline
rbitfld.long 0x0 0. "PI_DLL_LOCK,Monitor dfi_init_complete from PHY. READ-ONLY." "0,1"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_154,"
bitfld.long 0x4 16. "PI_POWER_REDUC_EN,PI Power reduction enable  1 = enabled." "?,1: enabled"
newline
bitfld.long 0x4 0.--1. "PI_PHYMSTR_TYPE,Defines how the controller should set the state of DRAM before turning control of the DFI bus over to the PI." "0,1,2,3"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_155,"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_156,"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_157,"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_158,"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_159,"
hexmask.long.byte 0x18 16.--23. 1. "PI_WRLVL_MAX_STROBE_PEND,Defines the maximum number of wrlvl_strobes that be accumulated before an AREF is prevented from being generated."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_160,"
hexmask.long.word 0x1C 0.--8. 1. "PI_TREFBW_THR,Threshold value to control the AREF command interval. When the number of pending AREF is over this value  the interval is expanded to be tREF/8."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_161,"
hexmask.long.byte 0x20 0.--4. 1. "PI_FREQ_CHANGE_REG_COPY,In non-DFI 4.0 mode  contains the frequency copy value."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_162,"
bitfld.long 0x24 24. "PI_NO_CATR_READ,Defines how the LPDDR4 termination status is determined. 1: PI use PI_CATR to get DRAM CA Termination status. 0: PI reads DRAM MR0.OP7 to get DRAM CA Termination status." "0: PI reads DRAM MR0,1: PI use PI_CATR to get DRAM CA Termination status"
newline
bitfld.long 0x24 16.--17. "PI_CATR,It indicates LP4 DRAM CA terminition ON/OFF state. Each bit corresponds to each chip select. 1:ON 0:OFF. This parameter is active when PI_NO_CATR_READ==1. When PI_NO_CATR_READ==0  this param is inactive" "0: OFF,1: ON,?,?"
newline
bitfld.long 0x24 0. "PI_FREQ_SEL_FROM_REGIF,In non-DFI 4.0 mode  user select the frequency copies from pi_freq_change_reg_copy." "0,1"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_163,"
bitfld.long 0x28 24. "PI_NOTCARE_MC_INIT_START,Defines whether PI waits for the controller to initiate dfi_init_start before PI memory initialization  1: wait for dfi_init_start" "?,1: wait for dfi_init_start"
newline
bitfld.long 0x28 16. "PI_DISABLE_PHYMSTR_REQ,PI mask dfi_phymstr_req to the controller and get dfi bus without dfi_phymstr_ack  1: disconnect" "?,1: disconnect"
newline
bitfld.long 0x28 8. "PI_DISCONNECT_MC,PI disconnects the controller from the PHY  1: disconnect" "?,1: disconnect"
newline
bitfld.long 0x28 0. "PI_MASK_INIT_COMPLETE,Enable the masking of the dfi_init_complete signal back to the controller  1: mask." "?,1: mask"
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_164,"
hexmask.long.word 0x2C 8.--23. 1. "PI_TVREF_F0,Defines the number of cycles that the PI should wait before issuing the next command after a VREF training MRW command for frequency set 0."
newline
bitfld.long 0x2C 0.--2. "PI_PHYMSTR_REQ_ACK_LOOP_DELAY,The delay between phymstr_req and inner phymstr_ack when PI_DISABLE_PHYMSTR_REQ set 1" "0,1,2,3,4,5,6,7"
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_165,"
hexmask.long.word 0x30 16.--31. 1. "PI_TVREF_F2,Defines the number of cycles that the PI should wait before issuing the next command after a VREF training MRW command for frequency set 2."
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hexmask.long.word 0x30 0.--15. 1. "PI_TVREF_F1,Defines the number of cycles that the PI should wait before issuing the next command after a VREF training MRW command for frequency set 1."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_166,"
hexmask.long.byte 0x34 16.--23. 1. "PI_TSDO_F2,The delay from the read preamble training MRS command to the data strobe drive out for frequency set 2  in PI clocks"
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hexmask.long.byte 0x34 8.--15. 1. "PI_TSDO_F1,The delay from the read preamble training MRS command to the data strobe drive out for frequency set 1  in PI clocks"
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hexmask.long.byte 0x34 0.--7. 1. "PI_TSDO_F0,The delay from the read preamble training MRS command to the data strobe drive out for frequency set 0  in PI clocks"
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_167,"
hexmask.long.byte 0x38 0.--7. 1. "PI_TDELAY_RDWR_2_BUS_IDLE_F0,The delay from read or write to bus idle for frequency set 0. Recommend setting is: delay time from read command issued to last read data received."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_168,"
hexmask.long.byte 0x3C 0.--7. 1. "PI_TDELAY_RDWR_2_BUS_IDLE_F1,The delay from read or write to bus idle for frequency set 1. Recommend setting is: delay time from read command issued to last read data received."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_169,"
hexmask.long.word 0x40 8.--19. 1. "PI_ZQINIT_F0,Number of cycles needed for a ZQINIT command for frequency set 0."
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hexmask.long.byte 0x40 0.--7. 1. "PI_TDELAY_RDWR_2_BUS_IDLE_F2,The delay from read or write to bus idle for frequency set 2. Recommend setting is: delay time from read command issued to last read data received."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_170,"
hexmask.long.word 0x44 16.--27. 1. "PI_ZQINIT_F2,Number of cycles needed for a ZQINIT command for frequency set 2."
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hexmask.long.word 0x44 0.--11. 1. "PI_ZQINIT_F1,Number of cycles needed for a ZQINIT command for frequency set 1."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_171,"
hexmask.long.byte 0x48 24.--31. 1. "PI_TPARITY_ERROR_CMD_INHIBIT_F0,Defines the window after the PI receives a parity error during which DRAM commands will not execute for frequency set 0."
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hexmask.long.byte 0x48 16.--19. 1. "PI_CA_PARITY_LAT_F0,DRAM CA parity latency value in cycles for frequency set 0."
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hexmask.long.byte 0x48 8.--13. 1. "PI_ADDITIVE_LAT_F0,DRAM additive latency value in cycles for frequency set 0."
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hexmask.long.byte 0x48 0.--6. 1. "PI_WRLAT_F0,DRAM WRLAT value in cycles for frequency set 0."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_172,"
hexmask.long.byte 0x4C 24.--27. 1. "PI_CA_PARITY_LAT_F1,DRAM CA parity latency value in cycles for frequency set 1."
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hexmask.long.byte 0x4C 16.--21. 1. "PI_ADDITIVE_LAT_F1,DRAM additive latency value in cycles for frequency set 1."
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hexmask.long.byte 0x4C 8.--14. 1. "PI_WRLAT_F1,DRAM WRLAT value in cycles for frequency set 1."
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hexmask.long.byte 0x4C 0.--6. 1. "PI_CASLAT_LIN_F0,Sets latency from read command sent to data received from/to controller for frequency set 0. Bit [0] is half-cycle increment and the upper bits define memory CAS latency for the controller."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_173,"
hexmask.long.byte 0x50 24.--29. 1. "PI_ADDITIVE_LAT_F2,DRAM additive latency value in cycles for frequency set 2."
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hexmask.long.byte 0x50 16.--22. 1. "PI_WRLAT_F2,DRAM WRLAT value in cycles for frequency set 2."
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hexmask.long.byte 0x50 8.--14. 1. "PI_CASLAT_LIN_F1,Sets latency from read command sent to data received from/to controller for frequency set 1. Bit [0] is half-cycle increment and the upper bits define memory CAS latency for the controller."
newline
hexmask.long.byte 0x50 0.--7. 1. "PI_TPARITY_ERROR_CMD_INHIBIT_F1,Defines the window after the PI receives a parity error during which DRAM commands will not execute for frequency set 1."
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_174,"
hexmask.long.byte 0x54 16.--22. 1. "PI_CASLAT_LIN_F2,Sets latency from read command sent to data received from/to controller for frequency set 2. Bit [0] is half-cycle increment and the upper bits define memory CAS latency for the controller."
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hexmask.long.byte 0x54 8.--15. 1. "PI_TPARITY_ERROR_CMD_INHIBIT_F2,Defines the window after the PI receives a parity error during which DRAM commands will not execute for frequency set 2."
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hexmask.long.byte 0x54 0.--3. 1. "PI_CA_PARITY_LAT_F2,DRAM CA parity latency value in cycles for frequency set 2."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_175,"
hexmask.long.word 0x58 0.--9. 1. "PI_TRFC_F0,DRAM tRFC value in memory clocks for frequency set 0."
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_176,"
hexmask.long.tbyte 0x5C 0.--19. 1. "PI_TREF_F0,DRAM tREF value in memory clocks for frequency set 0."
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_177,"
hexmask.long.word 0x60 0.--9. 1. "PI_TRFC_F1,DRAM tRFC value in memory clocks for frequency set 1."
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_178,"
hexmask.long.tbyte 0x64 0.--19. 1. "PI_TREF_F1,DRAM tREF value in memory clocks for frequency set 1."
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_179,"
hexmask.long.word 0x68 0.--9. 1. "PI_TRFC_F2,DRAM tRFC value in memory clocks for frequency set 2."
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_180,"
hexmask.long.byte 0x6C 24.--27. 1. "PI_TDFI_CTRL_DELAY_F0,Defines the DFI tCTRL_DELAY timing parameter [in DFI clocks] for frequency set 0  the delay between a DFI command change and a memory command."
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hexmask.long.tbyte 0x6C 0.--19. 1. "PI_TREF_F2,DRAM tREF value in memory clocks for frequency set 2."
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_181,"
bitfld.long 0x70 24.--25. "PI_WRLVL_EN_F1,Enable the PI write leveling module for frequency set 1. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
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bitfld.long 0x70 16.--17. "PI_WRLVL_EN_F0,Enable the PI write leveling module for frequency set 0. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
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hexmask.long.byte 0x70 8.--11. 1. "PI_TDFI_CTRL_DELAY_F2,Defines the DFI tCTRL_DELAY timing parameter [in DFI clocks] for frequency set 2  the delay between a DFI command change and a memory command."
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hexmask.long.byte 0x70 0.--3. 1. "PI_TDFI_CTRL_DELAY_F1,Defines the DFI tCTRL_DELAY timing parameter [in DFI clocks] for frequency set 1  the delay between a DFI command change and a memory command."
line.long 0x74 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_182,"
hexmask.long.word 0x74 8.--17. 1. "PI_TDFI_WRLVL_WW_F0,Defines the DFI tWRLVL_WW timing parameter [in DFI clocks] for frequency set 0  the minimum cycles between dfi_wrlvl_strobe assertions."
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bitfld.long 0x74 0.--1. "PI_WRLVL_EN_F2,Enable the PI write leveling module for frequency set 2. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
line.long 0x78 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_183,"
hexmask.long.word 0x78 16.--25. 1. "PI_TDFI_WRLVL_WW_F2,Defines the DFI tWRLVL_WW timing parameter [in DFI clocks] for frequency set 2  the minimum cycles between dfi_wrlvl_strobe assertions."
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hexmask.long.word 0x78 0.--9. 1. "PI_TDFI_WRLVL_WW_F1,Defines the DFI tWRLVL_WW timing parameter [in DFI clocks] for frequency set 1  the minimum cycles between dfi_wrlvl_strobe assertions."
line.long 0x7C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_184,"
bitfld.long 0x7C 24. "PI_ODT_EN_F1,Enable support of DRAM ODT. When enabled  PI will assert and de-assert ODT output to DRAM as needed for frequency set 1." "0,1"
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hexmask.long.byte 0x7C 16.--23. 1. "PI_TODTL_2CMD_F1,Defines the DRAM delay from an ODT de-assertion to the next non-write  non-read command for frequency set 1."
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bitfld.long 0x7C 8. "PI_ODT_EN_F0,Enable support of DRAM ODT. When enabled  PI will assert and de-assert ODT output to DRAM as needed for frequency set 0." "0,1"
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hexmask.long.byte 0x7C 0.--7. 1. "PI_TODTL_2CMD_F0,Defines the DRAM delay from an ODT de-assertion to the next non-write  non-read command for frequency set 0."
line.long 0x80 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_185,"
hexmask.long.byte 0x80 24.--27. 1. "PI_TODTON_MIN_F0,Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 0."
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hexmask.long.byte 0x80 16.--19. 1. "PI_ODTLON_F0,Defines the latency from a CAS-2 command to the tODTon reference for frequency set 0."
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bitfld.long 0x80 8. "PI_ODT_EN_F2,Enable support of DRAM ODT. When enabled  PI will assert and de-assert ODT output to DRAM as needed for frequency set 2." "0,1"
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hexmask.long.byte 0x80 0.--7. 1. "PI_TODTL_2CMD_F2,Defines the DRAM delay from an ODT de-assertion to the next non-write  non-read command for frequency set 2."
line.long 0x84 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_186,"
hexmask.long.byte 0x84 24.--27. 1. "PI_TODTON_MIN_F2,Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 2."
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hexmask.long.byte 0x84 16.--19. 1. "PI_ODTLON_F2,Defines the latency from a CAS-2 command to the tODTon reference for frequency set 2."
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hexmask.long.byte 0x84 8.--11. 1. "PI_TODTON_MIN_F1,Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 1."
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hexmask.long.byte 0x84 0.--3. 1. "PI_ODTLON_F1,Defines the latency from a CAS-2 command to the tODTon reference for frequency set 1."
line.long 0x88 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_187,"
hexmask.long.byte 0x88 24.--29. 1. "PI_RD_TO_ODTH_F0,Defines the delay from a read command to ODT assertion for frequency set 0."
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hexmask.long.byte 0x88 16.--21. 1. "PI_WR_TO_ODTH_F2,Defines the delay from a write command to ODT assertion for frequency set 2."
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hexmask.long.byte 0x88 8.--13. 1. "PI_WR_TO_ODTH_F1,Defines the delay from a write command to ODT assertion for frequency set 1."
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hexmask.long.byte 0x88 0.--5. 1. "PI_WR_TO_ODTH_F0,Defines the delay from a write command to ODT assertion for frequency set 0."
line.long 0x8C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_188,"
bitfld.long 0x8C 24.--25. "PI_RDLVL_GATE_EN_F0,Enable the PI gate training module for frequency set 0. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
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bitfld.long 0x8C 16.--17. "PI_RDLVL_EN_F0,Enable the PI data eye training module for frequency set 0. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
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hexmask.long.byte 0x8C 8.--13. 1. "PI_RD_TO_ODTH_F2,Defines the delay from a read command to ODT assertion for frequency set 2."
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hexmask.long.byte 0x8C 0.--5. 1. "PI_RD_TO_ODTH_F1,Defines the delay from a read command to ODT assertion for frequency set 1."
line.long 0x90 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_189,"
bitfld.long 0x90 24.--25. "PI_RDLVL_GATE_EN_F2,Enable the PI gate training module for frequency set 2. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
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bitfld.long 0x90 16.--17. "PI_RDLVL_EN_F2,Enable the PI data eye training module for frequency set 2. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
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bitfld.long 0x90 8.--9. "PI_RDLVL_GATE_EN_F1,Enable the PI gate training module for frequency set 1. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
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bitfld.long 0x90 0.--1. "PI_RDLVL_EN_F1,Enable the PI data eye training module for frequency set 1. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
line.long 0x94 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_190,"
bitfld.long 0x94 24.--25. "PI_RDLVL_PAT0_EN_F0,Enable PATTERN-0 for read training for frequency set 0. bit1 for normal; bit0 for initialization." "0,1,2,3"
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hexmask.long.byte 0x94 16.--23. 1. "PI_TWR_MPR_F2,Number of cycles after MPR write command and before any other command for frequency set 2."
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hexmask.long.byte 0x94 8.--15. 1. "PI_TWR_MPR_F1,Number of cycles after MPR write command and before any other command for frequency set 1."
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hexmask.long.byte 0x94 0.--7. 1. "PI_TWR_MPR_F0,Number of cycles after MPR write command and before any other command for frequency set 0."
line.long 0x98 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_191,"
bitfld.long 0x98 24.--25. "PI_RDLVL_PAT0_EN_F1,Enable PATTERN-0 for read training for frequency set 1. bit1 for normal; bit0 for initialization." "0,1,2,3"
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bitfld.long 0x98 16.--17. "PI_RDLVL_MULTI_EN_F0,Enable Multi-pattern [from PI_RDLVL_PATTERN_START  total PI_RDLVL_PATTERN_NUM] for read training for frequency set 0. bit1 for normal; bit0 for initialization." "0,1,2,3"
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bitfld.long 0x98 8.--9. "PI_RDLVL_DFE_EN_F0,Enable DFE [PATTERN 8 9] for read training for frequency set 0. bit1 for normal; bit0 for initialization." "0,1,2,3"
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bitfld.long 0x98 0.--1. "PI_RDLVL_RXCAL_EN_F0,Enable RX Offset calibration [PATTERN 14 15] for read training for frequency set 0. bit1 for normal; bit0 for initialization." "0,1,2,3"
line.long 0x9C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_192,"
bitfld.long 0x9C 24.--25. "PI_RDLVL_PAT0_EN_F2,Enable PATTERN-0 for read training for frequency set 2. bit1 for normal; bit0 for initialization." "0,1,2,3"
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bitfld.long 0x9C 16.--17. "PI_RDLVL_MULTI_EN_F1,Enable Multi-pattern [from PI_RDLVL_PATTERN_START  total PI_RDLVL_PATTERN_NUM] for read training for frequency set 1. bit1 for normal; bit0 for initialization." "0,1,2,3"
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bitfld.long 0x9C 8.--9. "PI_RDLVL_DFE_EN_F1,Enable DFE [PATTERN 8 9] for read training for frequency set 1. bit1 for normal; bit0 for initialization." "0,1,2,3"
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bitfld.long 0x9C 0.--1. "PI_RDLVL_RXCAL_EN_F1,Enable RX Offset calibration [PATTERN 14 15] for read training for frequency set 1. bit1 for normal; bit0 for initialization." "0,1,2,3"
line.long 0xA0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_193,"
hexmask.long.byte 0xA0 24.--31. 1. "PI_RDLAT_ADJ_F0,Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 0."
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bitfld.long 0xA0 16.--17. "PI_RDLVL_MULTI_EN_F2,Enable Multi-pattern [from PI_RDLVL_PATTERN_START  total PI_RDLVL_PATTERN_NUM] for read training for frequency set 2. bit1 for normal; bit0 for initialization." "0,1,2,3"
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bitfld.long 0xA0 8.--9. "PI_RDLVL_DFE_EN_F2,Enable DFE [PATTERN 8 9] for read training for frequency set 2. bit1 for normal; bit0 for initialization." "0,1,2,3"
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bitfld.long 0xA0 0.--1. "PI_RDLVL_RXCAL_EN_F2,Enable RX Offset calibration [PATTERN 14 15] for read training for frequency set 2. bit1 for normal; bit0 for initialization." "0,1,2,3"
line.long 0xA4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_194,"
hexmask.long.byte 0xA4 24.--31. 1. "PI_WRLAT_ADJ_F1,Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 1."
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hexmask.long.byte 0xA4 16.--23. 1. "PI_WRLAT_ADJ_F0,Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 0."
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hexmask.long.byte 0xA4 8.--15. 1. "PI_RDLAT_ADJ_F2,Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 2."
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hexmask.long.byte 0xA4 0.--7. 1. "PI_RDLAT_ADJ_F1,Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 1."
line.long 0xA8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_195,"
bitfld.long 0xA8 24.--26. "PI_TDFI_PHY_WRDATA_F2,Defines the DFI tPHY_WRDATA timing parameter [in DFI PHY clocks] for frequency set 2  the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal." "0,1,2,3,4,5,6,7"
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bitfld.long 0xA8 16.--18. "PI_TDFI_PHY_WRDATA_F1,Defines the DFI tPHY_WRDATA timing parameter [in DFI PHY clocks] for frequency set 1  the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal." "0,1,2,3,4,5,6,7"
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bitfld.long 0xA8 8.--10. "PI_TDFI_PHY_WRDATA_F0,Defines the DFI tPHY_WRDATA timing parameter [in DFI PHY clocks] for frequency set 0  the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xA8 0.--7. 1. "PI_WRLAT_ADJ_F2,Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 2."
line.long 0xAC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_196,"
hexmask.long.word 0xAC 16.--25. 1. "PI_TDFI_CALVL_CAPTURE_F0,Defines the DFI tCALVL_CAPTURE timing parameter [in DFI clocks] for frequency set 0  the minimum cycles between a calibration command and a dfi_calvl_capture pulse."
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hexmask.long.word 0xAC 0.--9. 1. "PI_TDFI_CALVL_CC_F0,Defines the DFI tCALVL_CC timing parameter [in DFI clocks] for frequency set 0  the minimum cycles between calibration commands."
line.long 0xB0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_197,"
hexmask.long.word 0xB0 16.--25. 1. "PI_TDFI_CALVL_CAPTURE_F1,Defines the DFI tCALVL_CAPTURE timing parameter [in DFI clocks] for frequency set 1  the minimum cycles between a calibration command and a dfi_calvl_capture pulse."
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hexmask.long.word 0xB0 0.--9. 1. "PI_TDFI_CALVL_CC_F1,Defines the DFI tCALVL_CC timing parameter [in DFI clocks] for frequency set 1  the minimum cycles between calibration commands."
line.long 0xB4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_198,"
hexmask.long.word 0xB4 16.--25. 1. "PI_TDFI_CALVL_CAPTURE_F2,Defines the DFI tCALVL_CAPTURE timing parameter [in DFI clocks] for frequency set 2  the minimum cycles between a calibration command and a dfi_calvl_capture pulse."
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hexmask.long.word 0xB4 0.--9. 1. "PI_TDFI_CALVL_CC_F2,Defines the DFI tCALVL_CC timing parameter [in DFI clocks] for frequency set 2  the minimum cycles between calibration commands."
line.long 0xB8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_199,"
hexmask.long.byte 0xB8 24.--28. 1. "PI_TMRZ_F0,Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 0."
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bitfld.long 0xB8 16.--17. "PI_CALVL_EN_F2,Enable the PI CA training module. Bit[1] represents the support when non-initialization for frequency set 2. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
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bitfld.long 0xB8 8.--9. "PI_CALVL_EN_F1,Enable the PI CA training module. Bit[1] represents the support when non-initialization for frequency set 1. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
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bitfld.long 0xB8 0.--1. "PI_CALVL_EN_F0,Enable the PI CA training module. Bit[1] represents the support when non-initialization for frequency set 0. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
line.long 0xBC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_200,"
hexmask.long.byte 0xBC 16.--20. 1. "PI_TMRZ_F1,Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 1."
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hexmask.long.word 0xBC 0.--13. 1. "PI_TCAENT_F0,Defines the DRAM tCAENT term  in memory clocks for frequency set 0."
line.long 0xC0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_201,"
hexmask.long.byte 0xC0 16.--20. 1. "PI_TMRZ_F2,Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 2."
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hexmask.long.word 0xC0 0.--13. 1. "PI_TCAENT_F1,Defines the DRAM tCAENT term  in memory clocks for frequency set 1."
line.long 0xC4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_202,"
hexmask.long.byte 0xC4 24.--28. 1. "PI_TDFI_CASEL_F0,Defines the DFI tcalvl_ca_sel timing parameter  the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 0."
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hexmask.long.byte 0xC4 16.--20. 1. "PI_TDFI_CACSCA_F0,Defines the DFI tcalvl_cs_ca timing parameter  the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 0."
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hexmask.long.word 0xC4 0.--13. 1. "PI_TCAENT_F2,Defines the DRAM tCAENT term  in memory clocks for frequency set 2."
line.long 0xC8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_203,"
hexmask.long.word 0xC8 16.--25. 1. "PI_TVREF_LONG_F0,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 0."
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hexmask.long.word 0xC8 0.--9. 1. "PI_TVREF_SHORT_F0,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 0."
line.long 0xCC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_204,"
hexmask.long.word 0xCC 16.--25. 1. "PI_TVREF_SHORT_F1,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 1."
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hexmask.long.byte 0xCC 8.--12. 1. "PI_TDFI_CASEL_F1,Defines the DFI tcalvl_ca_sel timing parameter  the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 1."
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hexmask.long.byte 0xCC 0.--4. 1. "PI_TDFI_CACSCA_F1,Defines the DFI tcalvl_cs_ca timing parameter  the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 1."
line.long 0xD0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_205,"
hexmask.long.byte 0xD0 24.--28. 1. "PI_TDFI_CASEL_F2,Defines the DFI tcalvl_ca_sel timing parameter  the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 2."
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hexmask.long.byte 0xD0 16.--20. 1. "PI_TDFI_CACSCA_F2,Defines the DFI tcalvl_cs_ca timing parameter  the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 2."
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hexmask.long.word 0xD0 0.--9. 1. "PI_TVREF_LONG_F1,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 1."
line.long 0xD4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_206,"
hexmask.long.word 0xD4 16.--25. 1. "PI_TVREF_LONG_F2,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 2."
newline
hexmask.long.word 0xD4 0.--9. 1. "PI_TVREF_SHORT_F2,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 2."
line.long 0xD8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_207,"
hexmask.long.byte 0xD8 24.--30. 1. "PI_CALVL_VREF_INITIAL_STOP_POINT_F1,The end point of initial training for the Vref[ca] training for frequency set 1 { vrefca_range  vref_ca_setting[5:0]}."
newline
hexmask.long.byte 0xD8 16.--22. 1. "PI_CALVL_VREF_INITIAL_START_POINT_F1,The start point of initial training for the Vref[ca] training for frequency set 1 { vrefca_range  vref_ca_setting[5:0]}."
newline
hexmask.long.byte 0xD8 8.--14. 1. "PI_CALVL_VREF_INITIAL_STOP_POINT_F0,The end point of initial training for the Vref[ca] training for frequency set 0 { vrefca_range  vref_ca_setting[5:0]}."
newline
hexmask.long.byte 0xD8 0.--6. 1. "PI_CALVL_VREF_INITIAL_START_POINT_F0,The start point of initial training for the Vref[ca] training for frequency set 0 { vrefca_range  vref_ca_setting[5:0]}."
line.long 0xDC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_208,"
hexmask.long.byte 0xDC 24.--27. 1. "PI_CALVL_VREF_DELTA_F1,The delta fro the current CA vref for non-initial CA training for frequency set 1."
newline
hexmask.long.byte 0xDC 16.--19. 1. "PI_CALVL_VREF_DELTA_F0,The delta fro the current CA vref for non-initial CA training for frequency set 0."
newline
hexmask.long.byte 0xDC 8.--14. 1. "PI_CALVL_VREF_INITIAL_STOP_POINT_F2,The end point of initial training for the Vref[ca] training for frequency set 2 { vrefca_range  vref_ca_setting[5:0]}."
newline
hexmask.long.byte 0xDC 0.--6. 1. "PI_CALVL_VREF_INITIAL_START_POINT_F2,The start point of initial training for the Vref[ca] training for frequency set 2 { vrefca_range  vref_ca_setting[5:0]}."
line.long 0xE0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_209,"
hexmask.long.byte 0xE0 24.--31. 1. "PI_TMRWCKEL_F0,Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 0."
newline
hexmask.long.byte 0xE0 16.--20. 1. "PI_TXP_F0,CKE assert to next valid command delay for frequency set 0."
newline
hexmask.long.byte 0xE0 8.--11. 1. "PI_TDFI_CALVL_STROBE_F0,Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 0."
newline
hexmask.long.byte 0xE0 0.--3. 1. "PI_CALVL_VREF_DELTA_F2,The delta fro the current CA vref for non-initial CA training for frequency set 2."
line.long 0xE4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_210,"
hexmask.long.byte 0xE4 24.--31. 1. "PI_TMRWCKEL_F1,Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 1."
newline
hexmask.long.byte 0xE4 16.--20. 1. "PI_TXP_F1,CKE assert to next valid command delay for frequency set 1."
newline
hexmask.long.byte 0xE4 8.--11. 1. "PI_TDFI_CALVL_STROBE_F1,Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 1."
newline
hexmask.long.byte 0xE4 0.--4. 1. "PI_TCKELCK_F0,Valid Clock Requirement after CKE deassert for frequency set 0."
line.long 0xE8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_211,"
hexmask.long.byte 0xE8 24.--31. 1. "PI_TMRWCKEL_F2,Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 2."
newline
hexmask.long.byte 0xE8 16.--20. 1. "PI_TXP_F2,CKE assert to next valid command delay for frequency set 2."
newline
hexmask.long.byte 0xE8 8.--11. 1. "PI_TDFI_CALVL_STROBE_F2,Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 2."
newline
hexmask.long.byte 0xE8 0.--4. 1. "PI_TCKELCK_F1,Valid Clock Requirement after CKE deassert for frequency set 1."
line.long 0xEC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_212,"
hexmask.long.tbyte 0xEC 8.--31. 1. "PI_TDFI_INIT_START_F0,Defines the DFI tINIT_START timing parameter [in DFI clocks] for frequency set 0  the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY."
newline
hexmask.long.byte 0xEC 0.--4. 1. "PI_TCKELCK_F2,Valid Clock Requirement after CKE deassert for frequency set 2."
line.long 0xF0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_213,"
hexmask.long.tbyte 0xF0 0.--23. 1. "PI_TDFI_INIT_COMPLETE_F0,Defines the DFI tINIT_COMPLETE timing parameter [in DFI clocks] for frequency set 0  the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY."
line.long 0xF4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_214,"
hexmask.long.tbyte 0xF4 0.--23. 1. "PI_TDFI_INIT_START_F1,Defines the DFI tINIT_START timing parameter [in DFI clocks] for frequency set 1  the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY."
line.long 0xF8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_215,"
hexmask.long.tbyte 0xF8 0.--23. 1. "PI_TDFI_INIT_COMPLETE_F1,Defines the DFI tINIT_COMPLETE timing parameter [in DFI clocks] for frequency set 1  the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY."
line.long 0xFC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_216,"
hexmask.long.tbyte 0xFC 0.--23. 1. "PI_TDFI_INIT_START_F2,Defines the DFI tINIT_START timing parameter [in DFI clocks] for frequency set 2  the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY."
line.long 0x100 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_217,"
hexmask.long.byte 0x100 24.--29. 1. "PI_TCKEHDQS_F0,The DRAM timing tCKEHDQS  minimum delay from CKE high to strobe high impedance for frequency set 0."
newline
hexmask.long.tbyte 0x100 0.--23. 1. "PI_TDFI_INIT_COMPLETE_F2,Defines the DFI tINIT_COMPLETE timing parameter [in DFI clocks] for frequency set 2  the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY."
line.long 0x104 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_218,"
hexmask.long.byte 0x104 16.--21. 1. "PI_TCKEHDQS_F1,The DRAM timing tCKEHDQS  minimum delay from CKE high to strobe high impedance for frequency set 1."
newline
hexmask.long.word 0x104 0.--9. 1. "PI_TFC_F0,The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 0."
line.long 0x108 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_219,"
hexmask.long.byte 0x108 16.--21. 1. "PI_TCKEHDQS_F2,The DRAM timing tCKEHDQS  minimum delay from CKE high to strobe high impedance for frequency set 2."
newline
hexmask.long.word 0x108 0.--9. 1. "PI_TFC_F1,The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 1."
line.long 0x10C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_220,"
bitfld.long 0x10C 24.--25. "PI_VREF_EN_F1,Enable VREF training during power-up initialization for frequency set 1. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
newline
bitfld.long 0x10C 16.--17. "PI_VREF_EN_F0,Enable VREF training during power-up initialization for frequency set 0. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
newline
hexmask.long.word 0x10C 0.--9. 1. "PI_TFC_F2,The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 2."
line.long 0x110 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_221,"
hexmask.long.word 0x110 8.--17. 1. "PI_TDFI_WDQLVL_WR_F0,Switch time from write to read for frequency set 0."
newline
bitfld.long 0x110 0.--1. "PI_VREF_EN_F2,Enable VREF training during power-up initialization for frequency set 2. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Set to 1 to enable." "0,1,2,3"
line.long 0x114 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_222,"
hexmask.long.byte 0x114 24.--30. 1. "PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0,Write DQ training vref initial training stop value for frequency set 0."
newline
hexmask.long.byte 0x114 16.--22. 1. "PI_WDQLVL_VREF_INITIAL_START_POINT_F0,Write DQ training vref initial training start value for frequency set 0."
newline
hexmask.long.word 0x114 0.--9. 1. "PI_TDFI_WDQLVL_RW_F0,Switch time from read to write for frequency set 0."
line.long 0x118 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_223,"
hexmask.long.byte 0x118 24.--28. 1. "PI_WDQLVL_CL_F0,CL when the Read DBI disabled while doing WDQ training for frequency set 0."
newline
bitfld.long 0x118 16.--17. "PI_NTP_TRAIN_EN_F0,Indicates whether the no topology WDQ training is enabled. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization." "0,1,2,3"
newline
bitfld.long 0x118 8.--9. "PI_WDQLVL_EN_F0,Indicates if Write DQ leveling is enabled for frequency set 0. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization." "0,1,2,3"
newline
hexmask.long.byte 0x118 0.--3. 1. "PI_WDQLVL_VREF_DELTA_F0,The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 0."
line.long 0x11C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_224,"
hexmask.long.word 0x11C 16.--25. 1. "PI_TDFI_WDQLVL_WR_F1,Switch time from write to read for frequency set 1."
newline
hexmask.long.byte 0x11C 8.--15. 1. "PI_WDQLVL_WRLAT_ADJ_F0,Adjusted Tdfi_wrdata_en value for PHY read timing when read dbi disabled for frequency set 0  used for WDQ training."
newline
hexmask.long.byte 0x11C 0.--7. 1. "PI_WDQLVL_RDLAT_ADJ_F0,Adjusted Tdfi_rddata_en value for PHY read timing when read dbi disabled for frequency set 0  used for WDQ training."
line.long 0x120 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_225,"
hexmask.long.byte 0x120 24.--30. 1. "PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1,Write DQ training vref initial training stop value for frequency set 1."
newline
hexmask.long.byte 0x120 16.--22. 1. "PI_WDQLVL_VREF_INITIAL_START_POINT_F1,Write DQ training vref initial training start value for frequency set 1."
newline
hexmask.long.word 0x120 0.--9. 1. "PI_TDFI_WDQLVL_RW_F1,Switch time from read to write for frequency set 1."
line.long 0x124 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_226,"
hexmask.long.byte 0x124 24.--28. 1. "PI_WDQLVL_CL_F1,CL when the Read DBI disabled while doing WDQ training for frequency set 1."
newline
bitfld.long 0x124 16.--17. "PI_NTP_TRAIN_EN_F1,Indicates whether the no topology WDQ training is enabled. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization." "0,1,2,3"
newline
bitfld.long 0x124 8.--9. "PI_WDQLVL_EN_F1,Indicates if Write DQ leveling is enabled for frequency set 1. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization." "0,1,2,3"
newline
hexmask.long.byte 0x124 0.--3. 1. "PI_WDQLVL_VREF_DELTA_F1,The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 1."
line.long 0x128 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_227,"
hexmask.long.word 0x128 16.--25. 1. "PI_TDFI_WDQLVL_WR_F2,Switch time from write to read for frequency set 2."
newline
hexmask.long.byte 0x128 8.--15. 1. "PI_WDQLVL_WRLAT_ADJ_F1,Adjusted Tdfi_wrdata_en value for PHY read timing when read dbi disabled for frequency set 1  used for WDQ training."
newline
hexmask.long.byte 0x128 0.--7. 1. "PI_WDQLVL_RDLAT_ADJ_F1,Adjusted Tdfi_rddata_en value for PHY read timing when read dbi disabled for frequency set 1  used for WDQ training."
line.long 0x12C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_228,"
hexmask.long.byte 0x12C 24.--30. 1. "PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2,Write DQ training vref initial training stop value for frequency set 2."
newline
hexmask.long.byte 0x12C 16.--22. 1. "PI_WDQLVL_VREF_INITIAL_START_POINT_F2,Write DQ training vref initial training start value for frequency set 2."
newline
hexmask.long.word 0x12C 0.--9. 1. "PI_TDFI_WDQLVL_RW_F2,Switch time from read to write for frequency set 2."
line.long 0x130 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_229,"
hexmask.long.byte 0x130 24.--28. 1. "PI_WDQLVL_CL_F2,CL when the Read DBI disabled while doing WDQ training for frequency set 2."
newline
bitfld.long 0x130 16.--17. "PI_NTP_TRAIN_EN_F2,Indicates whether the no topology WDQ training is enabled. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization." "0,1,2,3"
newline
bitfld.long 0x130 8.--9. "PI_WDQLVL_EN_F2,Indicates if Write DQ leveling is enabled for frequency set 2. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization." "0,1,2,3"
newline
hexmask.long.byte 0x130 0.--3. 1. "PI_WDQLVL_VREF_DELTA_F2,The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 2."
line.long 0x134 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_230,"
bitfld.long 0x134 24.--25. "PI_RD_DBI_LEVEL_EN_F1,Read DBI leveling enable  only can be enabled when READ DBI supported for DDR4  and PI_WDQLVL_EN or PI_RDLVL_EN configured by 1 for frequency set 1. Bit[1] represents the support when non-initialization. Bit[0]represents the support.." "0,1,2,3"
newline
bitfld.long 0x134 16.--17. "PI_RD_DBI_LEVEL_EN_F0,Read DBI leveling enable  only can be enabled when READ DBI supported for DDR4  and PI_WDQLVL_EN or PI_RDLVL_EN configured by 1 for frequency set 0. Bit[1] represents the support when non-initialization. Bit[0]represents the support.." "0,1,2,3"
newline
hexmask.long.byte 0x134 8.--15. 1. "PI_WDQLVL_WRLAT_ADJ_F2,Adjusted Tdfi_wrdata_en value for PHY read timing when read dbi disabled for frequency set 2  used for WDQ training."
newline
hexmask.long.byte 0x134 0.--7. 1. "PI_WDQLVL_RDLAT_ADJ_F2,Adjusted Tdfi_rddata_en value for PHY read timing when read dbi disabled for frequency set 2  used for WDQ training."
line.long 0x138 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_231,"
hexmask.long.byte 0x138 24.--31. 1. "PI_TRCD_F0,DRAM tRCD value in cycles for frequency set 0."
newline
hexmask.long.byte 0x138 16.--23. 1. "PI_TRP_F0,DRAM tRP value in cycles for frequency set 0."
newline
hexmask.long.byte 0x138 8.--15. 1. "PI_TRTP_F0,DRAM tRTP value in cycles for frequency set 0."
newline
bitfld.long 0x138 0.--1. "PI_RD_DBI_LEVEL_EN_F2,Read DBI leveling enable  only can be enabled when READ DBI supported for DDR4  and PI_WDQLVL_EN or PI_RDLVL_EN configured by 1 for frequency set 2. Bit[1] represents the support when non-initialization. Bit[0]represents the support.." "0,1,2,3"
line.long 0x13C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_232,"
hexmask.long.byte 0x13C 16.--23. 1. "PI_TWR_F0,DRAM tWR value in cycles for frequency set 0."
newline
hexmask.long.byte 0x13C 8.--13. 1. "PI_TWTR_F0,DRAM tWTR value in cycles for frequency set 0."
newline
hexmask.long.byte 0x13C 0.--4. 1. "PI_TCCD_L_F0,DRAM CAS-to_CAS value within the same bank group in cycles for frequency set 0."
line.long 0x140 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_233,"
hexmask.long.tbyte 0x140 0.--19. 1. "PI_TRAS_MAX_F0,DRAM tRAS_MAX value in cycles for frequency set 0."
line.long 0x144 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_234,"
hexmask.long.byte 0x144 24.--29. 1. "PI_TCCDMW_F0,LPDDR4 DRAM tCCDMW in cycles for frequency set 0."
newline
hexmask.long.byte 0x144 16.--19. 1. "PI_TDQSCK_MAX_F0,Additional delay needed for tDQSCK for frequency set 0."
newline
hexmask.long.word 0x144 0.--8. 1. "PI_TRAS_MIN_F0,DRAM tRAS_MIN value in cycles for frequency set 0."
line.long 0x148 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_235,"
hexmask.long.byte 0x148 24.--31. 1. "PI_TMOD_F0,DRAM tMOD value in cycles for frequency set 0."
newline
hexmask.long.byte 0x148 16.--23. 1. "PI_TMRW_F0,DRAM tMRW value in cycles for frequency set 0."
newline
hexmask.long.byte 0x148 8.--15. 1. "PI_TMRD_F0,DRAM tMRD value in cycles for frequency set 0."
newline
hexmask.long.byte 0x148 0.--7. 1. "PI_TSR_F0,Min cycles from sref entry to sref exit for frequency set 0."
line.long 0x14C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_236,"
hexmask.long.byte 0x14C 24.--31. 1. "PI_TRP_F1,DRAM tRP value in cycles for frequency set 1."
newline
hexmask.long.byte 0x14C 16.--23. 1. "PI_TRTP_F1,DRAM tRTP value in cycles for frequency set 1."
newline
hexmask.long.byte 0x14C 8.--15. 1. "PI_TMRD_PAR_F0,DRAM tMRD value when CA parity is enabled in cycles for frequency set 0."
newline
hexmask.long.byte 0x14C 0.--7. 1. "PI_TMOD_PAR_F0,DRAM tMOD value when CA parity is enabled in cycles for frequency set 0."
line.long 0x150 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_237,"
hexmask.long.byte 0x150 24.--31. 1. "PI_TWR_F1,DRAM tWR value in cycles for frequency set 1."
newline
hexmask.long.byte 0x150 16.--21. 1. "PI_TWTR_F1,DRAM tWTR value in cycles for frequency set 1."
newline
hexmask.long.byte 0x150 8.--12. 1. "PI_TCCD_L_F1,DRAM CAS-to_CAS value within the same bank group in cycles for frequency set 1."
newline
hexmask.long.byte 0x150 0.--7. 1. "PI_TRCD_F1,DRAM tRCD value in cycles for frequency set 1."
line.long 0x154 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_238,"
hexmask.long.tbyte 0x154 0.--19. 1. "PI_TRAS_MAX_F1,DRAM tRAS_MAX value in cycles for frequency set 1."
line.long 0x158 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_239,"
hexmask.long.byte 0x158 24.--29. 1. "PI_TCCDMW_F1,LPDDR4 DRAM tCCDMW in cycles for frequency set 1."
newline
hexmask.long.byte 0x158 16.--19. 1. "PI_TDQSCK_MAX_F1,Additional delay needed for tDQSCK for frequency set 1."
newline
hexmask.long.word 0x158 0.--8. 1. "PI_TRAS_MIN_F1,DRAM tRAS_MIN value in cycles for frequency set 1."
line.long 0x15C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_240,"
hexmask.long.byte 0x15C 24.--31. 1. "PI_TMOD_F1,DRAM tMOD value in cycles for frequency set 1."
newline
hexmask.long.byte 0x15C 16.--23. 1. "PI_TMRW_F1,DRAM tMRW value in cycles for frequency set 1."
newline
hexmask.long.byte 0x15C 8.--15. 1. "PI_TMRD_F1,DRAM tMRD value in cycles for frequency set 1."
newline
hexmask.long.byte 0x15C 0.--7. 1. "PI_TSR_F1,Min cycles from sref entry to sref exit for frequency set 1."
line.long 0x160 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_241,"
hexmask.long.byte 0x160 24.--31. 1. "PI_TRP_F2,DRAM tRP value in cycles for frequency set 2."
newline
hexmask.long.byte 0x160 16.--23. 1. "PI_TRTP_F2,DRAM tRTP value in cycles for frequency set 2."
newline
hexmask.long.byte 0x160 8.--15. 1. "PI_TMRD_PAR_F1,DRAM tMRD value when CA parity is enabled in cycles for frequency set 1."
newline
hexmask.long.byte 0x160 0.--7. 1. "PI_TMOD_PAR_F1,DRAM tMOD value when CA parity is enabled in cycles for frequency set 1."
line.long 0x164 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_242,"
hexmask.long.byte 0x164 24.--31. 1. "PI_TWR_F2,DRAM tWR value in cycles for frequency set 2."
newline
hexmask.long.byte 0x164 16.--21. 1. "PI_TWTR_F2,DRAM tWTR value in cycles for frequency set 2."
newline
hexmask.long.byte 0x164 8.--12. 1. "PI_TCCD_L_F2,DRAM CAS-to_CAS value within the same bank group in cycles for frequency set 2."
newline
hexmask.long.byte 0x164 0.--7. 1. "PI_TRCD_F2,DRAM tRCD value in cycles for frequency set 2."
line.long 0x168 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_243,"
hexmask.long.tbyte 0x168 0.--19. 1. "PI_TRAS_MAX_F2,DRAM tRAS_MAX value in cycles for frequency set 2."
line.long 0x16C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_244,"
hexmask.long.byte 0x16C 24.--29. 1. "PI_TCCDMW_F2,LPDDR4 DRAM tCCDMW in cycles for frequency set 2."
newline
hexmask.long.byte 0x16C 16.--19. 1. "PI_TDQSCK_MAX_F2,Additional delay needed for tDQSCK for frequency set 2."
newline
hexmask.long.word 0x16C 0.--8. 1. "PI_TRAS_MIN_F2,DRAM tRAS_MIN value in cycles for frequency set 2."
line.long 0x170 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_245,"
hexmask.long.byte 0x170 24.--31. 1. "PI_TMOD_F2,DRAM tMOD value in cycles for frequency set 2."
newline
hexmask.long.byte 0x170 16.--23. 1. "PI_TMRW_F2,DRAM tMRW value in cycles for frequency set 2."
newline
hexmask.long.byte 0x170 8.--15. 1. "PI_TMRD_F2,DRAM tMRD value in cycles for frequency set 2."
newline
hexmask.long.byte 0x170 0.--7. 1. "PI_TSR_F2,Min cycles from sref entry to sref exit for frequency set 2."
line.long 0x174 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_246,"
hexmask.long.byte 0x174 8.--15. 1. "PI_TMRD_PAR_F2,DRAM tMRD value when CA parity is enabled in cycles for frequency set 2."
newline
hexmask.long.byte 0x174 0.--7. 1. "PI_TMOD_PAR_F2,DRAM tMOD value when CA parity is enabled in cycles for frequency set 2."
line.long 0x178 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_247,"
hexmask.long.tbyte 0x178 0.--20. 1. "PI_TDFI_CTRLUPD_MAX_F0,Defines the DFI tCTRLUPD_MAX timing parameter [in DFI clocks] for frequency set 0  the maximum cycles that dfi_ctrlupd_req can be asserted. If programmed to a non-zero  a timing violation will cause an interrupt and bit [1] set in.."
line.long 0x17C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_248,"
hexmask.long 0x17C 0.--31. 1. "PI_TDFI_CTRLUPD_INTERVAL_F0,Defines the DFI tCTRLUPD_INTERVAL timing parameter [in DFI clocks] for frequency set 0  the maximum cycles between dfi_ctrlupd_req assertions. If programmed to a non-zero  a timing violation will cause an interrupt and bit [0].."
line.long 0x180 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_249,"
hexmask.long.tbyte 0x180 0.--20. 1. "PI_TDFI_CTRLUPD_MAX_F1,Defines the DFI tCTRLUPD_MAX timing parameter [in DFI clocks] for frequency set 1  the maximum cycles that dfi_ctrlupd_req can be asserted. If programmed to a non-zero  a timing violation will cause an interrupt and bit [1] set in.."
line.long 0x184 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_250,"
hexmask.long 0x184 0.--31. 1. "PI_TDFI_CTRLUPD_INTERVAL_F1,Defines the DFI tCTRLUPD_INTERVAL timing parameter [in DFI clocks] for frequency set 1  the maximum cycles between dfi_ctrlupd_req assertions. If programmed to a non-zero  a timing violation will cause an interrupt and bit [0].."
line.long 0x188 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_251,"
hexmask.long.tbyte 0x188 0.--20. 1. "PI_TDFI_CTRLUPD_MAX_F2,Defines the DFI tCTRLUPD_MAX timing parameter [in DFI clocks] for frequency set 2  the maximum cycles that dfi_ctrlupd_req can be asserted. If programmed to a non-zero  a timing violation will cause an interrupt and bit [1] set in.."
line.long 0x18C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_252,"
hexmask.long 0x18C 0.--31. 1. "PI_TDFI_CTRLUPD_INTERVAL_F2,Defines the DFI tCTRLUPD_INTERVAL timing parameter [in DFI clocks] for frequency set 2  the maximum cycles between dfi_ctrlupd_req assertions. If programmed to a non-zero  a timing violation will cause an interrupt and bit [0].."
line.long 0x190 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_253,"
hexmask.long.word 0x190 16.--31. 1. "PI_TXSR_F1,DRAM TXSR value for frequency set 1 in cycles."
newline
hexmask.long.word 0x190 0.--15. 1. "PI_TXSR_F0,DRAM TXSR value for frequency set 0 in cycles."
line.long 0x194 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_254,"
hexmask.long.byte 0x194 24.--29. 1. "PI_TEXCKE_F1,DRAM CKE low after SREF command timing for frequency set 1."
newline
hexmask.long.byte 0x194 16.--21. 1. "PI_TEXCKE_F0,DRAM CKE low after SREF command timing for frequency set 0."
newline
hexmask.long.word 0x194 0.--15. 1. "PI_TXSR_F2,DRAM TXSR value for frequency set 2 in cycles."
line.long 0x198 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_255,"
hexmask.long.word 0x198 8.--23. 1. "PI_TDLL_F0,DRAM tDLL value for frequency set 0 in cycles."
newline
hexmask.long.byte 0x198 0.--5. 1. "PI_TEXCKE_F2,DRAM CKE low after SREF command timing for frequency set 2."
line.long 0x19C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_256,"
hexmask.long.word 0x19C 16.--31. 1. "PI_TDLL_F2,DRAM tDLL value for frequency set 2 in cycles."
newline
hexmask.long.word 0x19C 0.--15. 1. "PI_TDLL_F1,DRAM tDLL value for frequency set 1 in cycles."
line.long 0x1A0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_257,"
hexmask.long.byte 0x1A0 24.--31. 1. "PI_TCKSRE_F1,DRAM tCKSRE value."
newline
hexmask.long.byte 0x1A0 16.--23. 1. "PI_TCKSRX_F1,DRAM tCKSRX value."
newline
hexmask.long.byte 0x1A0 8.--15. 1. "PI_TCKSRE_F0,DRAM tCKSRE value."
newline
hexmask.long.byte 0x1A0 0.--7. 1. "PI_TCKSRX_F0,DRAM tCKSRX value."
line.long 0x1A4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_258,"
hexmask.long.byte 0x1A4 8.--15. 1. "PI_TCKSRE_F2,DRAM tCKSRE value."
newline
hexmask.long.byte 0x1A4 0.--7. 1. "PI_TCKSRX_F2,DRAM tCKSRX value."
line.long 0x1A8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_259,"
hexmask.long.tbyte 0x1A8 0.--23. 1. "PI_TINIT_F0,DRAM tINIT value for frequency set 0 in cycles."
line.long 0x1AC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_260,"
hexmask.long.tbyte 0x1AC 0.--23. 1. "PI_TINIT3_F0,DRAM tINIT3 value for frequency set 0 in cycles."
line.long 0x1B0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_261,"
hexmask.long.tbyte 0x1B0 0.--23. 1. "PI_TINIT4_F0,DRAM tINIT4 value for frequency set 0 in cycles."
line.long 0x1B4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_262,"
hexmask.long.tbyte 0x1B4 0.--23. 1. "PI_TINIT5_F0,DRAM tINIT5 value for frequency set 0 in cycles."
line.long 0x1B8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_263,"
hexmask.long.word 0x1B8 0.--15. 1. "PI_TXSNR_F0,DRAM tXSNR value for frequency set 0 in cycles."
line.long 0x1BC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_264,"
hexmask.long.tbyte 0x1BC 0.--23. 1. "PI_TINIT_F1,DRAM tINIT value for frequency set 1 in cycles."
line.long 0x1C0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_265,"
hexmask.long.tbyte 0x1C0 0.--23. 1. "PI_TINIT3_F1,DRAM tINIT3 value for frequency set 1 in cycles."
line.long 0x1C4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_266,"
hexmask.long.tbyte 0x1C4 0.--23. 1. "PI_TINIT4_F1,DRAM tINIT4 value for frequency set 1 in cycles."
line.long 0x1C8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_267,"
hexmask.long.tbyte 0x1C8 0.--23. 1. "PI_TINIT5_F1,DRAM tINIT5 value for frequency set 1 in cycles."
line.long 0x1CC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_268,"
hexmask.long.word 0x1CC 0.--15. 1. "PI_TXSNR_F1,DRAM tXSNR value for frequency set 1 in cycles."
line.long 0x1D0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_269,"
hexmask.long.tbyte 0x1D0 0.--23. 1. "PI_TINIT_F2,DRAM tINIT value for frequency set 2 in cycles."
line.long 0x1D4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_270,"
hexmask.long.tbyte 0x1D4 0.--23. 1. "PI_TINIT3_F2,DRAM tINIT3 value for frequency set 2 in cycles."
line.long 0x1D8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_271,"
hexmask.long.tbyte 0x1D8 0.--23. 1. "PI_TINIT4_F2,DRAM tINIT4 value for frequency set 2 in cycles."
line.long 0x1DC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_272,"
hexmask.long.tbyte 0x1DC 0.--23. 1. "PI_TINIT5_F2,DRAM tINIT5 value for frequency set 2 in cycles."
line.long 0x1E0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_273,"
hexmask.long.word 0x1E0 0.--15. 1. "PI_TXSNR_F2,DRAM tXSNR value for frequency set 2 in cycles."
line.long 0x1E4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_274,"
hexmask.long.word 0x1E4 16.--27. 1. "PI_TZQCAL_F0,Holds the DRAM ZQCAL value for frequency set 0 in cycles."
line.long 0x1E8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_275,"
hexmask.long.byte 0x1E8 0.--6. 1. "PI_TZQLAT_F0,Holds the DRAM ZQLAT value for frequency set 0 in cycles."
line.long 0x1EC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_276,"
hexmask.long.word 0x1EC 16.--27. 1. "PI_TZQCAL_F1,Holds the DRAM ZQCAL value for frequency set 1 in cycles."
line.long 0x1F0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_277,"
hexmask.long.byte 0x1F0 0.--6. 1. "PI_TZQLAT_F1,Holds the DRAM ZQLAT value for frequency set 1 in cycles."
line.long 0x1F4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_278,"
hexmask.long.word 0x1F4 16.--27. 1. "PI_TZQCAL_F2,Holds the DRAM ZQCAL value for frequency set 2 in cycles."
line.long 0x1F8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_279,"
hexmask.long.byte 0x1F8 0.--6. 1. "PI_TZQLAT_F2,Holds the DRAM ZQLAT value for frequency set 2 in cycles."
line.long 0x1FC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_280,"
line.long 0x200 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_281,"
bitfld.long 0x200 24.--25. "PI_PREAMBLE_SUPPORT_F0,bit0: Selection of one or two cycle preamble for read burst transfers. bit1: Selection of one or two cycles write burst transfers for NON-DDR5 one or multi[up to four] cycles write burst transfers for DDR5." "0,1,2,3"
newline
hexmask.long.byte 0x200 16.--19. 1. "PI_WDQ_OSC_DELTA_INDEX_F2,WDQ DQS delay delta index for OSC triggered periodic training for frequency set 2. If the value is n  the delay is 2^n/512 cycle."
newline
hexmask.long.byte 0x200 8.--11. 1. "PI_WDQ_OSC_DELTA_INDEX_F1,WDQ DQS delay delta index for OSC triggered periodic training for frequency set 1. If the value is n  the delay is 2^n/512 cycle."
newline
hexmask.long.byte 0x200 0.--3. 1. "PI_WDQ_OSC_DELTA_INDEX_F0,WDQ DQS delay delta index for OSC triggered periodic training for frequency set 0. If the value is n  the delay is 2^n/512 cycle."
line.long 0x204 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_282,"
bitfld.long 0x204 24.--26. "PI_MEMDATA_RATIO_1,Defines the ratio of the DRAM device size on chip select 1 to the memory data width. Program with the log2 ratio of the memory data width to the device data width." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x204 16.--18. "PI_MEMDATA_RATIO_0,Defines the ratio of the DRAM device size on chip select 0 to the memory data width. Program with the log2 ratio of the memory data width to the device data width." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x204 8.--9. "PI_PREAMBLE_SUPPORT_F2,bit0: Selection of one or two cycle preamble for read burst transfers. bit1: Selection of one or two cycles write burst transfers for NON-DDR5 one or multi[up to four] cycles write burst transfers for DDR5." "0,1,2,3"
newline
bitfld.long 0x204 0.--1. "PI_PREAMBLE_SUPPORT_F1,bit0: Selection of one or two cycle preamble for read burst transfers. bit1: Selection of one or two cycles write burst transfers for NON-DDR5 one or multi[up to four] cycles write burst transfers for DDR5." "0,1,2,3"
line.long 0x208 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_283,"
bitfld.long 0x208 24.--25. "PI_ODT_WR_MAP_CS1,Determines which chip[s] will have termination when a write occurs on chip select 1. Set bit X to enable termination on csX when cs1 is performing a write." "0,1,2,3"
newline
bitfld.long 0x208 16.--17. "PI_ODT_RD_MAP_CS1,Determines which chip[s] will have termination when a read occurs on chip select 1. Set bit X to enable termination on csX when cs1 is performing a read." "0,1,2,3"
newline
bitfld.long 0x208 8.--9. "PI_ODT_WR_MAP_CS0,Determines which chip[s] will have termination when a write occurs on chip select 0. Set bit X to enable termination on csX when cs0 is performing a write." "0,1,2,3"
newline
bitfld.long 0x208 0.--1. "PI_ODT_RD_MAP_CS0,Determines which chip[s] will have termination when a read occurs on chip select 0. Set bit X to enable termination on csX when cs0 is performing a read." "0,1,2,3"
line.long 0x20C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_284,"
hexmask.long.byte 0x20C 24.--30. 1. "PI_VREF_VAL_DEV1_1,Defines the range and value for VREF training for DRAM 1 for CS 1. If the PI_VREF_PDA_EN parameter is not set  device 0 values are used for all devices."
newline
hexmask.long.byte 0x20C 16.--22. 1. "PI_VREF_VAL_DEV1_0,Defines the range and value for VREF training for DRAM 1 for CS 0. If the PI_VREF_PDA_EN parameter is not set  device 0 values are used for all devices."
newline
hexmask.long.byte 0x20C 8.--14. 1. "PI_VREF_VAL_DEV0_1,Defines the range and value for VREF training for DRAM 0 for CS 1. If the PI_VREF_PDA_EN parameter is not set  device 0 values are used for all devices."
newline
hexmask.long.byte 0x20C 0.--6. 1. "PI_VREF_VAL_DEV0_0,Defines the range and value for VREF training for DRAM 0 for CS 0. If the PI_VREF_PDA_EN parameter is not set  device 0 values are used for all devices."
line.long 0x210 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_285,"
hexmask.long.byte 0x210 24.--29. 1. "PI_MR6_VREF_0_1,The parameter stores the vref value of every devices of the same CS. It is updated after WDQLVL PDA mode completed. READ-ONLY."
newline
hexmask.long.byte 0x210 16.--21. 1. "PI_MR6_VREF_0_0,The parameter stores the vref value of every devices of the same CS. It is updated after WDQLVL PDA mode completed. READ-ONLY."
newline
bitfld.long 0x210 8.--9. "PI_SLICE_PER_DEV_1,Indicates the number of data slices per memory device. The device width divided by 8." "0,1,2,3"
newline
bitfld.long 0x210 0.--1. "PI_SLICE_PER_DEV_0,Indicates the number of data slices per memory device. The device width divided by 8." "0,1,2,3"
line.long 0x214 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_286,"
hexmask.long.byte 0x214 24.--31. 1. "PI_MR15_DATA_0,Data to program into memory mode register 15 for chip select 0."
newline
hexmask.long.byte 0x214 16.--23. 1. "PI_MR13_DATA_0,Data to program into memory mode register 13 for chip select 0."
newline
hexmask.long.byte 0x214 8.--13. 1. "PI_MR6_VREF_1_1,The parameter stores the vref value of every devices of the same CS. It is updated after WDQLVL PDA mode completed. READ-ONLY."
newline
hexmask.long.byte 0x214 0.--5. 1. "PI_MR6_VREF_1_0,The parameter stores the vref value of every devices of the same CS. It is updated after WDQLVL PDA mode completed. READ-ONLY."
line.long 0x218 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_287,"
hexmask.long.byte 0x218 16.--23. 1. "PI_MR20_DATA_0,Data to program into memory mode register 20 for chip select 0."
newline
hexmask.long.byte 0x218 8.--15. 1. "PI_MR17_DATA_0,Data to program into memory mode register 17 for chip select 0."
newline
hexmask.long.byte 0x218 0.--7. 1. "PI_MR16_DATA_0,Data to program into memory mode register 16 for chip select 0."
line.long 0x21C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_288,"
hexmask.long.byte 0x21C 24.--31. 1. "PI_MR40_DATA_0,Data to program into memory mode register 40 for chip select 0."
newline
hexmask.long.tbyte 0x21C 0.--16. 1. "PI_MR32_DATA_0,Data to program into memory mode register 32 for chip select 0."
line.long 0x220 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_289,"
hexmask.long.byte 0x220 24.--31. 1. "PI_MR17_DATA_1,Data to program into memory mode register 17 for chip select 1."
newline
hexmask.long.byte 0x220 16.--23. 1. "PI_MR16_DATA_1,Data to program into memory mode register 16 for chip select 1."
newline
hexmask.long.byte 0x220 8.--15. 1. "PI_MR15_DATA_1,Data to program into memory mode register 15 for chip select 1."
newline
hexmask.long.byte 0x220 0.--7. 1. "PI_MR13_DATA_1,Data to program into memory mode register 13 for chip select 1."
line.long 0x224 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_290,"
hexmask.long.tbyte 0x224 8.--24. 1. "PI_MR32_DATA_1,Data to program into memory mode register 32 for chip select 1."
newline
hexmask.long.byte 0x224 0.--7. 1. "PI_MR20_DATA_1,Data to program into memory mode register 20 for chip select 1."
line.long 0x228 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_291,"
hexmask.long.byte 0x228 24.--28. 1. "PI_CS_MUX_0,Command pin CS_0 mux selector"
newline
hexmask.long.byte 0x228 16.--20. 1. "PI_CKE_MUX_1,Command pin CKE_1 mux selector"
newline
hexmask.long.byte 0x228 8.--12. 1. "PI_CKE_MUX_0,Command pin CKE_0 mux selector"
newline
hexmask.long.byte 0x228 0.--7. 1. "PI_MR40_DATA_1,Data to program into memory mode register 40 for chip select 1."
line.long 0x22C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_292,"
hexmask.long.byte 0x22C 24.--28. 1. "PI_RESET_N_MUX_0,Command pin RESET_N_0 mux selector"
newline
hexmask.long.byte 0x22C 16.--20. 1. "PI_ODT_MUX_1,Command pin ODT_1 mux selector"
newline
hexmask.long.byte 0x22C 8.--12. 1. "PI_ODT_MUX_0,Command pin ODT_0 mux selector"
newline
hexmask.long.byte 0x22C 0.--4. 1. "PI_CS_MUX_1,Command pin CS_1 mux selector"
line.long 0x230 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_293,"
hexmask.long.tbyte 0x230 8.--24. 1. "PI_MRSINGLE_DATA_0,Data to program into memory mode register single write to chip select 0."
newline
hexmask.long.byte 0x230 0.--4. 1. "PI_RESET_N_MUX_1,Command pin RESET_N_1 mux selector"
line.long 0x234 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_294,"
bitfld.long 0x234 24.--25. "PI_ZQ_CAL_START_MAP_0,Defines which chip select[s] will receive ZQ calibration start commands simultaneously on iteration 0 of the ZQ START initialization and periodic command sequences. Clear to all zeros for no ZQ START commands." "0,1,2,3"
newline
hexmask.long.tbyte 0x234 0.--16. 1. "PI_MRSINGLE_DATA_1,Data to program into memory mode register single write to chip select 1."
line.long 0x238 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_295,"
bitfld.long 0x238 16.--17. "PI_ZQ_CAL_LATCH_MAP_1,Defines which chip select[s] will receive ZQ calibration latch commands simultaneously on iteration 1 of the ZQ LATCH initialization and periodic command sequences. Clear to all zeros for no ZQ LATCH commands." "0,1,2,3"
newline
bitfld.long 0x238 8.--9. "PI_ZQ_CAL_START_MAP_1,Defines which chip select[s] will receive ZQ calibration start commands simultaneously on iteration 1 of the ZQ START initialization and periodic command sequences. Clear to all zeros for no ZQ START commands." "0,1,2,3"
newline
bitfld.long 0x238 0.--1. "PI_ZQ_CAL_LATCH_MAP_0,Defines which chip select[s] will receive ZQ calibration latch commands simultaneously on iteration 0 of the ZQ LATCH initialization and periodic command sequences. Clear to all zeros for no ZQ LATCH commands." "0,1,2,3"
line.long 0x23C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_296,"
hexmask.long.word 0x23C 16.--31. 1. "PI_DQS_OSC_BASE_VALUE_0_1,Base value for comparison of oscillator measurement for device 0 of rank 1"
newline
hexmask.long.word 0x23C 0.--15. 1. "PI_DQS_OSC_BASE_VALUE_0_0,Base value for comparison of oscillator measurement for device 0 of rank 0"
line.long 0x240 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_297,"
hexmask.long.tbyte 0x240 0.--16. 1. "PI_MR0_DATA_F0_0,Data to program into memory mode register 0 for chip select 0 for frequency set 0."
line.long 0x244 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_298,"
hexmask.long.tbyte 0x244 0.--16. 1. "PI_MR1_DATA_F0_0,Data to program into memory mode register 1 for chip select 0 for frequency set 0."
line.long 0x248 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_299,"
hexmask.long.tbyte 0x248 0.--16. 1. "PI_MR2_DATA_F0_0,Data to program into memory mode register 2 for chip select 0 for frequency set 0."
line.long 0x24C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_300,"
hexmask.long.tbyte 0x24C 0.--16. 1. "PI_MR3_DATA_F0_0,Data to program into memory mode register 3 for chip select 0 for frequency set 0."
line.long 0x250 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_301,"
hexmask.long.tbyte 0x250 0.--16. 1. "PI_MR4_DATA_F0_0,Data to program into memory mode register 4 for chip select 0 for frequency set 0."
line.long 0x254 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_302,"
hexmask.long.tbyte 0x254 0.--16. 1. "PI_MR5_DATA_F0_0,Data to program into memory mode register 5 for chip select 0 for frequency set 0."
line.long 0x258 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_303,"
hexmask.long.byte 0x258 24.--31. 1. "PI_MR11_DATA_F0_0,Data to program into memory mode register 11 for chip select 0 for frequency set 0."
newline
hexmask.long.tbyte 0x258 0.--16. 1. "PI_MR6_DATA_F0_0,Data to program into memory mode register 6 for chip select 0 for frequency set 0."
line.long 0x25C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_304,"
hexmask.long.byte 0x25C 24.--31. 1. "PI_MR23_DATA_F0_0,Data to program into memory mode register 23 for chip select 0 for frequency set 0."
newline
hexmask.long.byte 0x25C 16.--23. 1. "PI_MR22_DATA_F0_0,Data to program into memory mode register 22 for chip select 0 for frequency set 0."
newline
hexmask.long.byte 0x25C 8.--15. 1. "PI_MR14_DATA_F0_0,Data to program into memory mode register 14 for chip select 0 for frequency set 0."
newline
hexmask.long.byte 0x25C 0.--7. 1. "PI_MR12_DATA_F0_0,Data to program into memory mode register 12 for chip select 0 for frequency set 0."
line.long 0x260 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_305,"
hexmask.long.tbyte 0x260 0.--16. 1. "PI_MR0_DATA_F1_0,Data to program into memory mode register 0 for chip select 0 for frequency set 1."
line.long 0x264 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_306,"
hexmask.long.tbyte 0x264 0.--16. 1. "PI_MR1_DATA_F1_0,Data to program into memory mode register 1 for chip select 0 for frequency set 1."
line.long 0x268 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_307,"
hexmask.long.tbyte 0x268 0.--16. 1. "PI_MR2_DATA_F1_0,Data to program into memory mode register 2 for chip select 0 for frequency set 1."
line.long 0x26C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_308,"
hexmask.long.tbyte 0x26C 0.--16. 1. "PI_MR3_DATA_F1_0,Data to program into memory mode register 3 for chip select 0 for frequency set 1."
line.long 0x270 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_309,"
hexmask.long.tbyte 0x270 0.--16. 1. "PI_MR4_DATA_F1_0,Data to program into memory mode register 4 for chip select 0 for frequency set 1."
line.long 0x274 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_310,"
hexmask.long.tbyte 0x274 0.--16. 1. "PI_MR5_DATA_F1_0,Data to program into memory mode register 5 for chip select 0 for frequency set 1."
line.long 0x278 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_311,"
hexmask.long.byte 0x278 24.--31. 1. "PI_MR11_DATA_F1_0,Data to program into memory mode register 11 for chip select 0 for frequency set 1."
newline
hexmask.long.tbyte 0x278 0.--16. 1. "PI_MR6_DATA_F1_0,Data to program into memory mode register 6 for chip select 0 for frequency set 1."
line.long 0x27C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_312,"
hexmask.long.byte 0x27C 24.--31. 1. "PI_MR23_DATA_F1_0,Data to program into memory mode register 23 for chip select 0 for frequency set 1."
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hexmask.long.byte 0x27C 16.--23. 1. "PI_MR22_DATA_F1_0,Data to program into memory mode register 22 for chip select 0 for frequency set 1."
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hexmask.long.byte 0x27C 8.--15. 1. "PI_MR14_DATA_F1_0,Data to program into memory mode register 14 for chip select 0 for frequency set 1."
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hexmask.long.byte 0x27C 0.--7. 1. "PI_MR12_DATA_F1_0,Data to program into memory mode register 12 for chip select 0 for frequency set 1."
line.long 0x280 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_313,"
hexmask.long.tbyte 0x280 0.--16. 1. "PI_MR0_DATA_F2_0,Data to program into memory mode register 0 for chip select 0 for frequency set 2."
line.long 0x284 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_314,"
hexmask.long.tbyte 0x284 0.--16. 1. "PI_MR1_DATA_F2_0,Data to program into memory mode register 1 for chip select 0 for frequency set 2."
line.long 0x288 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_315,"
hexmask.long.tbyte 0x288 0.--16. 1. "PI_MR2_DATA_F2_0,Data to program into memory mode register 2 for chip select 0 for frequency set 2."
line.long 0x28C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_316,"
hexmask.long.tbyte 0x28C 0.--16. 1. "PI_MR3_DATA_F2_0,Data to program into memory mode register 3 for chip select 0 for frequency set 2."
line.long 0x290 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_317,"
hexmask.long.tbyte 0x290 0.--16. 1. "PI_MR4_DATA_F2_0,Data to program into memory mode register 4 for chip select 0 for frequency set 2."
line.long 0x294 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_318,"
hexmask.long.tbyte 0x294 0.--16. 1. "PI_MR5_DATA_F2_0,Data to program into memory mode register 5 for chip select 0 for frequency set 2."
line.long 0x298 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_319,"
hexmask.long.byte 0x298 24.--31. 1. "PI_MR11_DATA_F2_0,Data to program into memory mode register 11 for chip select 0 for frequency set 2."
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hexmask.long.tbyte 0x298 0.--16. 1. "PI_MR6_DATA_F2_0,Data to program into memory mode register 6 for chip select 0 for frequency set 2."
line.long 0x29C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_320,"
hexmask.long.byte 0x29C 24.--31. 1. "PI_MR23_DATA_F2_0,Data to program into memory mode register 23 for chip select 0 for frequency set 2."
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hexmask.long.byte 0x29C 16.--23. 1. "PI_MR22_DATA_F2_0,Data to program into memory mode register 22 for chip select 0 for frequency set 2."
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hexmask.long.byte 0x29C 8.--15. 1. "PI_MR14_DATA_F2_0,Data to program into memory mode register 14 for chip select 0 for frequency set 2."
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hexmask.long.byte 0x29C 0.--7. 1. "PI_MR12_DATA_F2_0,Data to program into memory mode register 12 for chip select 0 for frequency set 2."
line.long 0x2A0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_321,"
hexmask.long.tbyte 0x2A0 0.--16. 1. "PI_MR0_DATA_F0_1,Data to program into memory mode register 0 for chip select 1 for frequency set 0."
line.long 0x2A4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_322,"
hexmask.long.tbyte 0x2A4 0.--16. 1. "PI_MR1_DATA_F0_1,Data to program into memory mode register 1 for chip select 1 for frequency set 0."
line.long 0x2A8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_323,"
hexmask.long.tbyte 0x2A8 0.--16. 1. "PI_MR2_DATA_F0_1,Data to program into memory mode register 2 for chip select 1 for frequency set 0."
line.long 0x2AC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_324,"
hexmask.long.tbyte 0x2AC 0.--16. 1. "PI_MR3_DATA_F0_1,Data to program into memory mode register 3 for chip select 1 for frequency set 0."
line.long 0x2B0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_325,"
hexmask.long.tbyte 0x2B0 0.--16. 1. "PI_MR4_DATA_F0_1,Data to program into memory mode register 4 for chip select 1 for frequency set 0."
line.long 0x2B4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_326,"
hexmask.long.tbyte 0x2B4 0.--16. 1. "PI_MR5_DATA_F0_1,Data to program into memory mode register 5 for chip select 1 for frequency set 0."
line.long 0x2B8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_327,"
hexmask.long.byte 0x2B8 24.--31. 1. "PI_MR11_DATA_F0_1,Data to program into memory mode register 11 for chip select 1 for frequency set 0."
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hexmask.long.tbyte 0x2B8 0.--16. 1. "PI_MR6_DATA_F0_1,Data to program into memory mode register 6 for chip select 1 for frequency set 0."
line.long 0x2BC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_328,"
hexmask.long.byte 0x2BC 24.--31. 1. "PI_MR23_DATA_F0_1,Data to program into memory mode register 23 for chip select 1 for frequency set 0."
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hexmask.long.byte 0x2BC 16.--23. 1. "PI_MR22_DATA_F0_1,Data to program into memory mode register 22 for chip select 1 for frequency set 0."
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hexmask.long.byte 0x2BC 8.--15. 1. "PI_MR14_DATA_F0_1,Data to program into memory mode register 14 for chip select 1 for frequency set 0."
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hexmask.long.byte 0x2BC 0.--7. 1. "PI_MR12_DATA_F0_1,Data to program into memory mode register 12 for chip select 1 for frequency set 0."
line.long 0x2C0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_329,"
hexmask.long.tbyte 0x2C0 0.--16. 1. "PI_MR0_DATA_F1_1,Data to program into memory mode register 0 for chip select 1 for frequency set 1."
line.long 0x2C4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_330,"
hexmask.long.tbyte 0x2C4 0.--16. 1. "PI_MR1_DATA_F1_1,Data to program into memory mode register 1 for chip select 1 for frequency set 1."
line.long 0x2C8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_331,"
hexmask.long.tbyte 0x2C8 0.--16. 1. "PI_MR2_DATA_F1_1,Data to program into memory mode register 2 for chip select 1 for frequency set 1."
line.long 0x2CC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_332,"
hexmask.long.tbyte 0x2CC 0.--16. 1. "PI_MR3_DATA_F1_1,Data to program into memory mode register 3 for chip select 1 for frequency set 1."
line.long 0x2D0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_333,"
hexmask.long.tbyte 0x2D0 0.--16. 1. "PI_MR4_DATA_F1_1,Data to program into memory mode register 4 for chip select 1 for frequency set 1."
line.long 0x2D4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_334,"
hexmask.long.tbyte 0x2D4 0.--16. 1. "PI_MR5_DATA_F1_1,Data to program into memory mode register 5 for chip select 1 for frequency set 1."
line.long 0x2D8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_335,"
hexmask.long.byte 0x2D8 24.--31. 1. "PI_MR11_DATA_F1_1,Data to program into memory mode register 11 for chip select 1 for frequency set 1."
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hexmask.long.tbyte 0x2D8 0.--16. 1. "PI_MR6_DATA_F1_1,Data to program into memory mode register 6 for chip select 1 for frequency set 1."
line.long 0x2DC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_336,"
hexmask.long.byte 0x2DC 24.--31. 1. "PI_MR23_DATA_F1_1,Data to program into memory mode register 23 for chip select 1 for frequency set 1."
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hexmask.long.byte 0x2DC 16.--23. 1. "PI_MR22_DATA_F1_1,Data to program into memory mode register 22 for chip select 1 for frequency set 1."
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hexmask.long.byte 0x2DC 8.--15. 1. "PI_MR14_DATA_F1_1,Data to program into memory mode register 14 for chip select 1 for frequency set 1."
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hexmask.long.byte 0x2DC 0.--7. 1. "PI_MR12_DATA_F1_1,Data to program into memory mode register 12 for chip select 1 for frequency set 1."
line.long 0x2E0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_337,"
hexmask.long.tbyte 0x2E0 0.--16. 1. "PI_MR0_DATA_F2_1,Data to program into memory mode register 0 for chip select 1 for frequency set 2."
line.long 0x2E4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_338,"
hexmask.long.tbyte 0x2E4 0.--16. 1. "PI_MR1_DATA_F2_1,Data to program into memory mode register 1 for chip select 1 for frequency set 2."
line.long 0x2E8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_339,"
hexmask.long.tbyte 0x2E8 0.--16. 1. "PI_MR2_DATA_F2_1,Data to program into memory mode register 2 for chip select 1 for frequency set 2."
line.long 0x2EC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_340,"
hexmask.long.tbyte 0x2EC 0.--16. 1. "PI_MR3_DATA_F2_1,Data to program into memory mode register 3 for chip select 1 for frequency set 2."
line.long 0x2F0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_341,"
hexmask.long.tbyte 0x2F0 0.--16. 1. "PI_MR4_DATA_F2_1,Data to program into memory mode register 4 for chip select 1 for frequency set 2."
line.long 0x2F4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_342,"
hexmask.long.tbyte 0x2F4 0.--16. 1. "PI_MR5_DATA_F2_1,Data to program into memory mode register 5 for chip select 1 for frequency set 2."
line.long 0x2F8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_343,"
hexmask.long.byte 0x2F8 24.--31. 1. "PI_MR11_DATA_F2_1,Data to program into memory mode register 11 for chip select 1 for frequency set 2."
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hexmask.long.tbyte 0x2F8 0.--16. 1. "PI_MR6_DATA_F2_1,Data to program into memory mode register 6 for chip select 1 for frequency set 2."
line.long 0x2FC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PI_344,"
hexmask.long.byte 0x2FC 24.--31. 1. "PI_MR23_DATA_F2_1,Data to program into memory mode register 23 for chip select 1 for frequency set 2."
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hexmask.long.byte 0x2FC 16.--23. 1. "PI_MR22_DATA_F2_1,Data to program into memory mode register 22 for chip select 1 for frequency set 2."
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hexmask.long.byte 0x2FC 8.--15. 1. "PI_MR14_DATA_F2_1,Data to program into memory mode register 14 for chip select 1 for frequency set 2."
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hexmask.long.byte 0x2FC 0.--7. 1. "PI_MR12_DATA_F2_1,Data to program into memory mode register 12 for chip select 1 for frequency set 2."
group.long 0x4000++0x27
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_0,"
hexmask.long.word 0x0 16.--26. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_0,Write data clock bypass mode slave delay setting for slice 0."
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hexmask.long.byte 0x0 8.--14. 1. "PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0,Controls PCLK/PARK pin for pad for slice 0 with boot frequency."
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bitfld.long 0x0 0.--2. "PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0,RX_PCLK boot clock frequency selection for slice 0." "0,1,2,3,4,5,6,7"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1,"
bitfld.long 0x4 24.--26. "PHY_WRITE_PATH_LAT_ADD_BYPASS_0,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 0." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x4 8.--17. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0,Write DQS bypass mode slave delay setting for slice 0."
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hexmask.long.byte 0x4 0.--3. 1. "PHY_IO_PAD_DELAY_TIMING_BYPASS_0,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 0."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_2,"
bitfld.long 0x8 24. "PHY_CLK_BYPASS_OVERRIDE_0,Bypass mode override setting for slice 0." "0,1"
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bitfld.long 0x8 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_0,Two_cycle_preamble for bypass mode for slice 0." "0,1,2,3"
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hexmask.long.word 0x8 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0,Read DQS bypass mode slave delay setting for slice 0."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_3,"
hexmask.long.byte 0xC 24.--29. 1. "PHY_SW_WRDQ3_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
newline
hexmask.long.byte 0xC 16.--21. 1. "PHY_SW_WRDQ2_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
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hexmask.long.byte 0xC 8.--13. 1. "PHY_SW_WRDQ1_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
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hexmask.long.byte 0xC 0.--5. 1. "PHY_SW_WRDQ0_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_4,"
hexmask.long.byte 0x10 24.--29. 1. "PHY_SW_WRDQ7_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
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hexmask.long.byte 0x10 16.--21. 1. "PHY_SW_WRDQ6_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
newline
hexmask.long.byte 0x10 8.--13. 1. "PHY_SW_WRDQ5_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
newline
hexmask.long.byte 0x10 0.--5. 1. "PHY_SW_WRDQ4_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_5,"
hexmask.long.byte 0x14 24.--28. 1. "PHY_LP4_BOOT_RDDATA_EN_DLY_0,For LPDDR4 boot frequency  the number of cycles that the dfi_rddata_en signal is early for slice 0."
newline
bitfld.long 0x14 16.--17. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0,For LPDDR4 boot frequency  the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0." "0,1,2,3"
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hexmask.long.byte 0x14 8.--11. 1. "PHY_SW_WRDQS_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bit [3] is the.."
newline
hexmask.long.byte 0x14 0.--5. 1. "PHY_SW_WRDM_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_6,"
bitfld.long 0x18 24.--25. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0,For LPDDR4 boot frequency  write path clock gating disable for slice 0. Bit [0]: disable pull in wrdata_en; Bit [1]: disable write path clock gating  clock always on" "0,1,2,3"
newline
hexmask.long.byte 0x18 16.--19. 1. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0,For LPDDR4 boot frequency  the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0."
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hexmask.long.byte 0x18 8.--11. 1. "PHY_LP4_BOOT_RPTR_UPDATE_0,For LPDDR4 boot frequency  the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 0."
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hexmask.long.byte 0x18 0.--4. 1. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0,For LPDDR4 boot frequency  the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_7,"
hexmask.long.word 0x1C 16.--24. 1. "PHY_LPBK_CONTROL_0,Loopback control bits for slice 0."
newline
bitfld.long 0x1C 8.--9. "PHY_CTRL_LPBK_EN_0,Loopback control en for slice 0." "0,1,2,3"
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hexmask.long.byte 0x1C 0.--4. 1. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0,For LPDDR4 boot frequency  the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 0."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_8,"
bitfld.long 0x20 8. "PHY_GATE_DELAY_COMP_DISABLE_0,use the control whether to compensate half_cycle when gate_slave_delay is larger than half_cycle for the gate close for slice 0." "0,1"
newline
bitfld.long 0x20 0. "PHY_LPBK_DFX_TIMEOUT_EN_0,Loopback read only test timeout mechanism enable for slice 0." "0,1"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_9,"
hexmask.long 0x24 0.--31. 1. "PHY_AUTO_TIMING_MARGIN_CONTROL_0,Auto timing marging control bits for slice 0."
rgroup.long 0x4028++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_10,"
hexmask.long 0x0 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_0,Observation register for the auto_timing_margin for slice 0. READ-ONLY"
group.long 0x402C++0x17
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_11,"
hexmask.long.byte 0x0 24.--30. 1. "PHY_PRBS_PATTERN_START_0,PRBS7 start pattern for slice 0."
newline
bitfld.long 0x0 16. "PHY_PDA_MODE_EN_0,When set to 1  the invalid DQs will be driven by the dfi_wrdata to make sure the tpda_s and tpda_h's timing is meet for slice 0." "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "PHY_DQ_IDLE_0,When set to 1  the inavlid DQ will be driven to high  when set to 0  the invalid DQ will be driven to low for slice 0."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_12,"
bitfld.long 0x4 24. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_0,Read Leveling read level windows disable reset for slice 0." "0,1"
newline
bitfld.long 0x4 16. "PHY_RDLVL_MULTI_PATT_ENABLE_0,Read Leveling Multi-pattern enable for slice 0." "0,1"
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hexmask.long.word 0x4 0.--8. 1. "PHY_PRBS_PATTERN_MASK_0,PRBS7 mask signal for slice 0."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_13,"
hexmask.long.word 0x8 16.--25. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0,Read DQS data clock bypass mode slave delay setting for slice 0."
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hexmask.long.byte 0x8 8.--14. 1. "PHY_VREF_TRAIN_OBS_0,Observation register for best vref value for slice 0. READ-ONLY"
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hexmask.long.byte 0x8 0.--5. 1. "PHY_VREF_INITIAL_STEPSIZE_0,Data slice initial VREF training step size for slice 0."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_14,"
hexmask.long.word 0xC 16.--24. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_0,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 0."
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bitfld.long 0xC 8. "SC_PHY_SNAP_OBS_REGS_0,Initiates a snapshot of the internal observation registers for slice 0. Set to 1 to trigger. WRITE-ONLY" "0,1"
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hexmask.long.byte 0xC 0.--3. 1. "PHY_GATE_ERROR_DELAY_SELECT_0,Number of cycles to wait for the DQS gate to close before flagging an error for slice 0."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_15,"
hexmask.long.word 0x10 16.--24. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_0,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 0."
newline
bitfld.long 0x10 8.--10. "PHY_MEM_CLASS_0,Indicates the type of DRAM for slice 0. 0 for DDR3  1 for DDR4  2 for DDR5  4 for LPDDR2  5 for LPDDR3. 6 for LPDDR4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "PHY_LPDDR_0,Adds a cycle of delay for the slice 0 to match the address slice. Set to 1 to add a cycle" "0,1"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_16,"
bitfld.long 0x14 0.--1. "ON_FLY_GATE_ADJUST_EN_0,Control the on-the-fly gate adjustment for slice 0." "0,1,2,3"
rgroup.long 0x4044++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_17,"
hexmask.long 0x0 0.--31. 1. "PHY_GATE_TRACKING_OBS_0,Report the on-the-fly gate measurement result for slice 0. READ-ONLY"
group.long 0x4048++0x6B
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_18,"
bitfld.long 0x0 0.--1. "PHY_LP4_PST_AMBLE_0,Controls the read postamble extension for LPDDR4 for slice 0." "0,1,2,3"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_19,"
hexmask.long 0x4 0.--31. 1. "PHY_RDLVL_PATT8_0,Read leveling pattern 8 data for slice 0."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_20,"
hexmask.long 0x8 0.--31. 1. "PHY_RDLVL_PATT9_0,Read leveling pattern 9 data for slice 0."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_21,"
hexmask.long 0xC 0.--31. 1. "PHY_RDLVL_PATT10_0,Read leveling pattern 10 data for slice 0."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_22,"
hexmask.long 0x10 0.--31. 1. "PHY_RDLVL_PATT11_0,Read leveling pattern 11 data for slice 0."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_23,"
hexmask.long 0x14 0.--31. 1. "PHY_RDLVL_PATT12_0,Read leveling pattern 12 data for slice 0."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_24,"
hexmask.long 0x18 0.--31. 1. "PHY_RDLVL_PATT13_0,Read leveling pattern 13 data for slice 0."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_25,"
hexmask.long 0x1C 0.--31. 1. "PHY_RDLVL_PATT14_0,Read leveling pattern 14 data for slice 0."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_26,"
hexmask.long 0x20 0.--31. 1. "PHY_RDLVL_PATT15_0,Read leveling pattern 15 data for slice 0."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_27,"
bitfld.long 0x24 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_0,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 0." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x24 16.--19. 1. "PHY_MASTER_DLY_LOCK_OBS_SELECT_0,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 0."
newline
bitfld.long 0x24 8. "PHY_SW_FIFO_PTR_RST_DISABLE_0,Disables automatic reset of the read entry FIFO pointers for slice 0. Set to 1 to disable automatic resets." "0,1"
newline
bitfld.long 0x24 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_0,Reserved for future use for slice 0." "0,1,2,3,4,5,6,7"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_28,"
hexmask.long.byte 0x28 24.--27. 1. "PHY_FIFO_PTR_OBS_SELECT_0,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 0."
newline
hexmask.long.byte 0x28 16.--19. 1. "PHY_WR_SHIFT_OBS_SELECT_0,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 0."
newline
hexmask.long.byte 0x28 8.--11. 1. "PHY_WR_ENC_OBS_SELECT_0,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 0."
newline
hexmask.long.byte 0x28 0.--3. 1. "PHY_RDDQS_DQ_ENC_OBS_SELECT_0,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 0."
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_29,"
hexmask.long.byte 0x2C 24.--29. 1. "PHY_WRLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during write leveling for slice 0."
newline
bitfld.long 0x2C 16.--17. "PHY_WRLVL_ALGO_0,Write leveling algorithm selection for slice 0." "0,1,2,3"
newline
bitfld.long 0x2C 8. "SC_PHY_LVL_DEBUG_CONT_0,Allows the leveling state machine to advance [when in debug mode] for slice 0. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x2C 0. "PHY_LVL_DEBUG_MODE_0,Enables leveling debug mode for slice 0. Set to 1 to enable." "0,1"
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_30,"
hexmask.long.byte 0x30 24.--27. 1. "PHY_GTLVL_UPDT_WAIT_CNT_0,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 0. The valid range is 0x0 to 0xB."
newline
hexmask.long.byte 0x30 16.--21. 1. "PHY_GTLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during gate training for slice 0."
newline
hexmask.long.byte 0x30 8.--15. 1. "PHY_DQ_MASK_0,For ECC slice  should set this register to do DQ bit mask for slice 0."
newline
hexmask.long.byte 0x30 0.--3. 1. "PHY_WRLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 0."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_31,"
hexmask.long.byte 0x34 24.--28. 1. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 0."
newline
bitfld.long 0x34 16.--17. "PHY_RDLVL_OP_MODE_0,Read leveling algorithm select for slice 0. Clear to 0 to move linearly from left to right. Set to 1 to start inside the window  move left and then move right." "0,1,2,3"
newline
hexmask.long.byte 0x34 8.--11. 1. "PHY_RDLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 0."
newline
hexmask.long.byte 0x34 0.--5. 1. "PHY_RDLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during read leveling for slice 0."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_32,"
hexmask.long.tbyte 0x38 8.--25. 1. "PHY_RDLVL_DATA_SWIZZLE_0,Read level bit swizzling for DDR4 operation for slice 0."
newline
hexmask.long.byte 0x38 0.--7. 1. "PHY_RDLVL_DATA_MASK_0,Per-bit mask for read leveling for slice 0. If all bits are not used  only 1 bit should be cleared to 0."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_33,"
bitfld.long 0x3C 16.--18. "PHY_WDQLVL_PATT_0,Defines the training patterns to be used during the write data leveling sequence for slice 0. Bit [0] corresponds to the LFSR data training pattern. Bit [1] corresponds to the CLK data training pattern. Bit [2] corresponds to.." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x3C 8.--13. 1. "PHY_WDQLVL_BURST_CNT_0,Defines the write/read burst length in bytes during the write data leveling sequence for slice 0."
newline
hexmask.long.byte 0x3C 0.--7. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_0,Defines the minimum gap requirment for the LE and TE window for slice 0."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_34,"
hexmask.long.byte 0x40 24.--27. 1. "PHY_WDQLVL_DQDM_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 0."
newline
hexmask.long.byte 0x40 16.--19. 1. "PHY_WDQLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 0."
newline
hexmask.long.word 0x40 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0,Defines the slave delay jump value when the TE window is found and begin to serch TE window for slice 0."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_35,"
bitfld.long 0x44 24. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_0,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 0. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
hexmask.long.byte 0x44 16.--19. 1. "PHY_WDQLVL_DM_DLY_STEP_0,The slave delay line step for DM training for slice 0."
newline
hexmask.long.byte 0x44 8.--15. 1. "PHY_WDQLVL_DQ_SLV_DELTA_0,The margin for DQ0-7's LE and TE dealy to make sure the DQ bits can work during DM training for slice 0."
newline
hexmask.long.byte 0x44 0.--7. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_0,Select value to map specific information during or post periodic write data leveling for slice 0."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_36,"
hexmask.long.word 0x48 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_0,Per-bit mask for write data leveling for slice 0. Set to 1 to mask any bit from the leveling process."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_37,"
hexmask.long 0x4C 0.--31. 1. "PHY_USER_PATT0_0,User-defined pattern to be used during write data leveling for slice 0. This register holds the bytes 3 to 0 written/read from device."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_38,"
hexmask.long 0x50 0.--31. 1. "PHY_USER_PATT1_0,User-defined pattern to be used during write data leveling for slice 0. This register holds the bytes 7 to 4 written/read from device."
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_39,"
hexmask.long 0x54 0.--31. 1. "PHY_USER_PATT2_0,User-defined pattern to be used during write data leveling for slice 0. This register holds the bytes 11 to 8 written/read from device."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_40,"
hexmask.long 0x58 0.--31. 1. "PHY_USER_PATT3_0,User-defined pattern to be used during write data leveling for slice 0. This register holds the bytes 15 to 12 written/read from device."
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_41,"
bitfld.long 0x5C 16. "PHY_NTP_MULT_TRAIN_0,Control for single pass only No-Topology training for slice 0." "0,1"
newline
hexmask.long.word 0x5C 0.--15. 1. "PHY_USER_PATT4_0,User-defined pattern to be used during write data leveling for slice 0. This register holds the DM bit for the 15 to 0 DQ written/read from device."
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_42,"
hexmask.long.word 0x60 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_0,Threshold Criteria of period threshold after No-Topology training is completed for slice 0."
newline
hexmask.long.word 0x60 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_0,Threshold Criteria of early threshold after No-Topology training is completed for slice 0."
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_43,"
hexmask.long.word 0x64 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_0,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary  to set period threshold/early threshold after No-Topology training is completed for slice 0."
newline
hexmask.long.word 0x64 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_0,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary  to set period threshold/early threshold after No-Topology training is completed for slice 0."
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_44,"
hexmask.long.byte 0x68 16.--23. 1. "PHY_FIFO_PTR_OBS_0,Observation register containing read entry FIFO pointers for slice 0. READ-ONLY"
newline
hexmask.long.byte 0x68 8.--13. 1. "SC_PHY_MANUAL_CLEAR_0,Manual reset/clear of internal logic for slice 0. Bit [0] initiates manual setup of the read DQS gate. Bit [1] is reset of read entry FIFO pointers. Bit [2] is reset of master delay min/max lock values. Bit [3] is manual reset of.."
newline
bitfld.long 0x68 0. "PHY_CALVL_VREF_DRIVING_SLICE_0,Indicates if slice 0 is used to drive the VREF value to the device during CA training." "0,1"
rgroup.long 0x40B4++0x3F
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_45,"
hexmask.long 0x0 0.--31. 1. "PHY_LPBK_RESULT_OBS_0,Observation register containing loopback status/results for slice 0. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_46,"
hexmask.long.word 0x4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_0,Observation register containing master delay results for slice 0. READ-ONLY"
newline
hexmask.long.word 0x4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_0,Observation register containing total number of loopback error data for slice 0. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_47,"
hexmask.long.byte 0x8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 0. READ-ONLY"
newline
hexmask.long.byte 0x8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_0,Observation register containing fraction of the cycle in 1 delay element  numerator with demominator of 512  for slice 0. READ-ONLY"
newline
hexmask.long.byte 0x8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0,Observation register containing read DQS base slave delay encoded value for slice 0. READ-ONLY"
newline
hexmask.long.byte 0x8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_0,Observation register containing read DQ slave delay encoded values for slice 0. READ-ONLY"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_48,"
hexmask.long.byte 0xC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0,Observation register containing write DQS base slave delay encoded value for slice 0. READ-ONLY"
newline
hexmask.long.word 0xC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0,Observation register containing read DQS gate slave delay encoded value for slice 0. READ-ONLY"
newline
hexmask.long.byte 0xC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 0. READ-ONLY"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_49,"
bitfld.long 0x10 16.--18. "PHY_WR_SHIFT_OBS_0,Observation register containing automatic half cycle and cycle shift values for slice 0. READ-ONLY" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing write adder slave delay encoded value for slice 0. READ-ONLY"
newline
hexmask.long.byte 0x10 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0,Observation register containing write DQ base slave delay encoded value for slice 0. READ-ONLY"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_50,"
hexmask.long.word 0x14 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_0,Observation register containing write leveling first hard 1 DQS slave delay for slice 0. READ-ONLY"
newline
hexmask.long.word 0x14 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_0,Observation register containing write leveling last hard 0 DQS slave delay for slice 0. READ-ONLY"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_51,"
hexmask.long.tbyte 0x18 0.--20. 1. "PHY_WRLVL_STATUS_OBS_0,Observation register containing write leveling status for slice 0. READ-ONLY"
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_52,"
hexmask.long.word 0x1C 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0,Observation register containing gate sample2 slave delay encoded values for slice 0. READ-ONLY"
newline
hexmask.long.word 0x1C 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0,Observation register containing gate sample1 slave delay encoded values for slice 0. READ-ONLY"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_53,"
hexmask.long.word 0x20 16.--29. 1. "PHY_GTLVL_HARD1_DELAY_OBS_0,Observation register containing gate training last hard 1 DQS slave delay for slice 0. READ-ONLY"
newline
hexmask.long.word 0x20 0.--13. 1. "PHY_GTLVL_HARD0_DELAY_OBS_0,Observation register containing gate training first hard 0 DQS slave delay for slice 0. READ-ONLY"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_54,"
hexmask.long.tbyte 0x24 0.--17. 1. "PHY_GTLVL_STATUS_OBS_0,Observation register containing gate training status for slice 0. READ-ONLY"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_55,"
hexmask.long.word 0x28 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0,Observation register containing read leveling data window trailing edge slave delay setting for slice 0. READ-ONLY"
newline
hexmask.long.word 0x28 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0,Observation register containing read leveling data window leading edge slave delay setting for slice 0. READ-ONLY"
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_56,"
bitfld.long 0x2C 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0,Observation register containing read leveling number of windows found for slice 0. READ-ONLY" "0,1,2,3"
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_57,"
hexmask.long 0x30 0.--31. 1. "PHY_RDLVL_STATUS_OBS_0,Observation register containing read leveling status for slice 0. READ-ONLY"
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_58,"
hexmask.long.word 0x34 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_0,Observation register containing write data leveling data window trailing edge slave delay setting for slice 0. READ-ONLY"
newline
hexmask.long.word 0x34 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_0,Observation register containing write data leveling data window leading edge slave delay setting for slice 0. READ-ONLY"
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_59,"
hexmask.long 0x38 0.--31. 1. "PHY_WDQLVL_STATUS_OBS_0,Observation register containing write data leveling status for slice 0. READ-ONLY"
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_60,"
hexmask.long 0x3C 0.--31. 1. "PHY_WDQLVL_PERIODIC_OBS_0,Observation register containing periodic write data leveling status for slice 0. READ-ONLY"
group.long 0x40F4++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_61,"
hexmask.long 0x0 0.--30. 1. "PHY_DDL_MODE_0,DDL mode for slice 0."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_62,"
hexmask.long.byte 0x4 0.--5. 1. "PHY_DDL_MASK_0,DDL mask for slice 0."
rgroup.long 0x40FC++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_63,"
hexmask.long 0x0 0.--31. 1. "PHY_DDL_TEST_OBS_0,DDL test observation for slice 0. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_64,"
hexmask.long 0x4 0.--31. 1. "PHY_DDL_TEST_MSTR_DLY_OBS_0,DDL test observation delays for slice 0 master DDL. READ-ONLY"
group.long 0x4104++0xF3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_65,"
hexmask.long.word 0x0 16.--24. 1. "PHY_RX_CAL_DQ0_0,RX Calibration codes for DQ0 for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
newline
bitfld.long 0x0 8. "PHY_LP4_WDQS_OE_EXTEND_0,LPDDR4 write preamble extension enable for slice 0." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_0,Specify threshold value for PHY init update tracking for slice 0."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_66,"
hexmask.long.word 0x4 16.--24. 1. "PHY_RX_CAL_DQ2_0,RX Calibration codes for DQ2 for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
newline
hexmask.long.word 0x4 0.--8. 1. "PHY_RX_CAL_DQ1_0,RX Calibration codes for DQ1 for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_67,"
hexmask.long.word 0x8 16.--24. 1. "PHY_RX_CAL_DQ4_0,RX Calibration codes for DQ4 for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
newline
hexmask.long.word 0x8 0.--8. 1. "PHY_RX_CAL_DQ3_0,RX Calibration codes for DQ3 for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_68,"
hexmask.long.word 0xC 16.--24. 1. "PHY_RX_CAL_DQ6_0,RX Calibration codes for DQ6 for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
newline
hexmask.long.word 0xC 0.--8. 1. "PHY_RX_CAL_DQ5_0,RX Calibration codes for DQ5 for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_69,"
hexmask.long.word 0x10 0.--8. 1. "PHY_RX_CAL_DQ7_0,RX Calibration codes for DQ7 for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_70,"
hexmask.long.tbyte 0x14 0.--17. 1. "PHY_RX_CAL_DM_0,RX Calibration codes for DM for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_71,"
hexmask.long.word 0x18 16.--24. 1. "PHY_RX_CAL_FDBK_0,RX Calibration codes for FDBK for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
newline
hexmask.long.word 0x18 0.--8. 1. "PHY_RX_CAL_DQS_0,RX Calibration codes for DQS for slice 0. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_72,"
bitfld.long 0x1C 24.--26. "PHY_FDBK_PWR_CTRL_0,Shutoff gate feedback IO to reduce power for slice 0." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x1C 16.--20. 1. "PHY_STATIC_TOG_DISABLE_0,Control to disable toggle during static activity for slice 0. bit0: Write path delay line disable; bit1: Read path delay line disable; bit2: Read data path disable; bit3: clk_phy disable; bit4: master delay line disable."
newline
hexmask.long.word 0x1C 0.--10. 1. "PHY_PAD_RX_BIAS_EN_0,Controls RX_BIAS_EN pin for each pad for slice 0."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_73,"
bitfld.long 0x20 24. "PHY_SLICE_PWR_RDC_DISABLE_0,Data slice power reduction disable for slice 0." "0,1"
newline
bitfld.long 0x20 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0,Data slice RX_CAL block power reduction disable for slice 0." "0,1"
newline
bitfld.long 0x20 8. "PHY_RDPATH_GATE_DISABLE_0,Data slice read path power reduction disable for slice 0." "0,1"
newline
bitfld.long 0x20 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_0,Data slice slv_dly_control block power reduction disable for slice 0." "0,1"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_74,"
bitfld.long 0x24 24.--26. "PHY_DQS_TSEL_ENABLE_0,Operation type tsel enables for DQS signals for slice 0. Bit [0] enables tsel_en during read cycles. Bit [1] enables tsel_en during write cycles. Bit [2] enables tsel_en during idle cycles. Set each bit to 1 to enable." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 8.--23. 1. "PHY_DQ_TSEL_SELECT_0,Operation type tsel select values for DQ/DM signals for slice 0."
newline
bitfld.long 0x24 0.--2. "PHY_DQ_TSEL_ENABLE_0,Operation type tsel enables for DQ/DM signals for slice 0. Bit [0] enables tsel_en during read cycles. Bit [1] enables tsel_en during write cycles. Bit [2] enables tsel_en during idle cycles. Set each bit to 1 to enable." "0,1,2,3,4,5,6,7"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_75,"
hexmask.long.byte 0x28 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_0,Data slice initial VREF training start value for slice 0."
newline
bitfld.long 0x28 16.--17. "PHY_TWO_CYC_PREAMBLE_0,2 cycle preamble support for slice 0. Bit [0] controls the 2 cycle read preamble. Bit [1] controls the 2 cycle write preamble. Set each bit to 1 to enable." "0,1,2,3"
newline
hexmask.long.word 0x28 0.--15. 1. "PHY_DQS_TSEL_SELECT_0,Operation type tsel select values for DQS signals for slice 0."
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_76,"
hexmask.long.byte 0x2C 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_0,Step size of WR DQ slave delay during No-Topology training for slice 0."
newline
bitfld.long 0x2C 16. "PHY_NTP_TRAIN_EN_0,Enable for No-Topology training for slice 0." "0,1"
newline
bitfld.long 0x2C 8.--9. "PHY_VREF_TRAINING_CTRL_0,Data slice vref training enable control for slice 0." "0,1,2,3"
newline
hexmask.long.byte 0x2C 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_0,Data slice initial VREF training stop value for slice 0."
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_77,"
hexmask.long.word 0x30 16.--26. 1. "PHY_NTP_WDQ_STOP_0,End of WR DQ slave delay in No-Topology training for slice 0."
newline
hexmask.long.word 0x30 0.--10. 1. "PHY_NTP_WDQ_START_0,Starting WR DQ slave delay in No-Topology training for slice 0."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_78,"
bitfld.long 0x34 24. "PHY_SW_WDQLVL_DVW_MIN_EN_0,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 0." "0,1"
newline
hexmask.long.word 0x34 8.--17. 1. "PHY_WDQLVL_DVW_MIN_0,Minimum data valid window across DQs and ranks for slice 0."
newline
hexmask.long.byte 0x34 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_0,Enable Bit for WR DQ during No-Topology training for slice 0."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_79,"
hexmask.long.byte 0x38 24.--28. 1. "PHY_PAD_RX_DCD_0_0,Controls RX_DCD pin for each pad for slice 0."
newline
hexmask.long.byte 0x38 16.--20. 1. "PHY_PAD_TX_DCD_0,Controls TX_DCD pin for each pad for slice 0."
newline
hexmask.long.byte 0x38 8.--11. 1. "PHY_FAST_LVL_EN_0,Enable for fast multi-pattern window search for slice 0."
newline
hexmask.long.byte 0x38 0.--5. 1. "PHY_WDQLVL_PER_START_OFFSET_0,Peridic training start point offset for slice 0."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_80,"
hexmask.long.byte 0x3C 24.--28. 1. "PHY_PAD_RX_DCD_4_0,Controls RX_DCD pin for each pad for slice 0."
newline
hexmask.long.byte 0x3C 16.--20. 1. "PHY_PAD_RX_DCD_3_0,Controls RX_DCD pin for each pad for slice 0."
newline
hexmask.long.byte 0x3C 8.--12. 1. "PHY_PAD_RX_DCD_2_0,Controls RX_DCD pin for each pad for slice 0."
newline
hexmask.long.byte 0x3C 0.--4. 1. "PHY_PAD_RX_DCD_1_0,Controls RX_DCD pin for each pad for slice 0."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_81,"
hexmask.long.byte 0x40 24.--28. 1. "PHY_PAD_DM_RX_DCD_0,Controls RX_DCD pin for dm pad for slice 0."
newline
hexmask.long.byte 0x40 16.--20. 1. "PHY_PAD_RX_DCD_7_0,Controls RX_DCD pin for each pad for slice 0."
newline
hexmask.long.byte 0x40 8.--12. 1. "PHY_PAD_RX_DCD_6_0,Controls RX_DCD pin for each pad for slice 0."
newline
hexmask.long.byte 0x40 0.--4. 1. "PHY_PAD_RX_DCD_5_0,Controls RX_DCD pin for each pad for slice 0."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_82,"
hexmask.long.byte 0x44 16.--22. 1. "PHY_PAD_DSLICE_IO_CFG_0,Controls PCLK/PARK pin for pad for slice 0."
newline
hexmask.long.byte 0x44 8.--12. 1. "PHY_PAD_FDBK_RX_DCD_0,Controls RX_DCD pin for fdbk pad for slice 0."
newline
hexmask.long.byte 0x44 0.--4. 1. "PHY_PAD_DQS_RX_DCD_0,Controls RX_DCD pin for dqs pad for slice 0."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_83,"
hexmask.long.word 0x48 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_0,Read DQ1 slave delay setting for slice 0."
newline
hexmask.long.word 0x48 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_0,Read DQ0 slave delay setting for slice 0."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_84,"
hexmask.long.word 0x4C 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_0,Read DQ3 slave delay setting for slice 0."
newline
hexmask.long.word 0x4C 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_0,Read DQ2 slave delay setting for slice 0."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_85,"
hexmask.long.word 0x50 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_0,Read DQ5 slave delay setting for slice 0."
newline
hexmask.long.word 0x50 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_0,Read DQ4 slave delay setting for slice 0."
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_86,"
hexmask.long.word 0x54 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_0,Read DQ7 slave delay setting for slice 0."
newline
hexmask.long.word 0x54 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_0,Read DQ6 slave delay setting for slice 0."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_87,"
hexmask.long.byte 0x58 24.--28. 1. "PHY_RX_CAL_ALL_DLY_0,Defines the number of cycles/half cycles that the rx_cal_all_opad signal should be asserted for. There is a phy_rx_cal_all_dly_X parameter for each of the slices of data sent on the DFI data bus for slice 0."
newline
bitfld.long 0x58 16.--18. "PHY_RX_PCLK_CLK_SEL_0,RX_PCLK clock frequency selection for slice 0." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x58 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_0,Read DM/DBI slave delay setting for slice 0. May be used for data swap."
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_88,"
hexmask.long.byte 0x5C 24.--31. 1. "PHY_DQS_OE_TIMING_0,Start/end timing values for DQS output enable signals for slice 0."
newline
hexmask.long.byte 0x5C 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_0,Start/end timing values for DQ/DM write based termination enable and select signals for slice 0."
newline
hexmask.long.byte 0x5C 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_0,Start/end timing values for DQ/DM read based termination enable and select signals for slice 0."
newline
hexmask.long.byte 0x5C 0.--7. 1. "PHY_DQ_OE_TIMING_0,Start/end timing values for DQ/DM output enable signals for slice 0."
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_89,"
hexmask.long.byte 0x60 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_0,Start/end timing values for DQS write based termination enable and select signals for slice 0."
newline
hexmask.long.byte 0x60 16.--23. 1. "PHY_DQS_OE_RD_TIMING_0,Start/end timing values for DQS read based OE extension for slice 0."
newline
hexmask.long.byte 0x60 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_0,Start/end timing values for DQS read based termination enable and select signals for slice 0."
newline
hexmask.long.byte 0x60 0.--3. 1. "PHY_IO_PAD_DELAY_TIMING_0,Feedback pad's OPAD and IPAD delay timing for slice 0."
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_90,"
hexmask.long.word 0x64 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_0,Pad VREF control settings for DQ slice 0."
newline
hexmask.long.word 0x64 0.--15. 1. "PHY_VREF_SETTING_TIME_0,Number of cycles for vref settle after setting is changed for slice 0."
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_91,"
bitfld.long 0x68 24.--25. "PHY_IE_MODE_0,Input enable mode bits for slice 0. Bit [0] enables the mode where the input enables are always on; set to 1 to enable. Bit [1] disables the input enable on the DM signal; set to 1 to disable." "0,1,2,3"
newline
bitfld.long 0x68 16.--17. "PHY_RDDATA_EN_IE_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0." "0,1,2,3"
newline
hexmask.long.byte 0x68 8.--15. 1. "PHY_DQS_IE_TIMING_0,Start/end timing values for DQS input enable signals for slice 0."
newline
hexmask.long.byte 0x68 0.--7. 1. "PHY_DQ_IE_TIMING_0,Start/end timing values for DQ/DM input enable signals for slice 0."
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_92,"
hexmask.long.byte 0x6C 24.--28. 1. "PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0,For WR DQ training  the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0."
newline
hexmask.long.byte 0x6C 16.--20. 1. "PHY_WDQLVL_RDDATA_EN_DLY_0,For WR DQ training  the number of cycles that the dfi_rddata_en signal is early for slice 0."
newline
bitfld.long 0x6C 8. "PHY_WDQLVL_IE_ON_0,IE control  1 meams IE is always on during WR DQ training for slice 0." "0,1"
newline
bitfld.long 0x6C 0.--1. "PHY_DBI_MODE_0,DBI mode for slice 0. Bit [0] enables return of DBI read data." "0,1,2,3"
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_93,"
hexmask.long.byte 0x70 16.--19. 1. "PHY_SW_MASTER_MODE_0,Master delay line override settings for slice 0. Bit [0] enables software half clock mode. Bit [1] is the software half clock mode value. Bit [2] enables software bypass mode. Bit [3] is the software bypass mode value."
newline
hexmask.long.byte 0x70 8.--12. 1. "PHY_RDDATA_EN_OE_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 0."
newline
hexmask.long.byte 0x70 0.--4. 1. "PHY_RDDATA_EN_TSEL_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0."
line.long 0x74 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_94,"
hexmask.long.byte 0x74 24.--31. 1. "PHY_MASTER_DELAY_WAIT_0,Wait cycles for master delay line locking algorithm for slice 0. Bits [3:0] are the cycle wait count after a calibration clock setting change. Bits [7:4] are the cycle wait count after a master delay setting change."
newline
hexmask.long.byte 0x74 16.--21. 1. "PHY_MASTER_DELAY_STEP_0,Incremental step size for master delay line locking algorithm for slice 0."
newline
hexmask.long.word 0x74 0.--10. 1. "PHY_MASTER_DELAY_START_0,Start value for master delay line locking algorithm for slice 0."
line.long 0x78 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_95,"
hexmask.long.byte 0x78 24.--27. 1. "PHY_WRLVL_DLY_FINE_STEP_0,DQS slave delay fine step size during write leveling for slice 0."
newline
hexmask.long.byte 0x78 16.--23. 1. "PHY_WRLVL_DLY_STEP_0,DQS slave delay step size during write leveling for slice 0."
newline
hexmask.long.byte 0x78 8.--11. 1. "PHY_RPTR_UPDATE_0,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 0."
newline
hexmask.long.byte 0x78 0.--7. 1. "PHY_MASTER_DELAY_HALF_MEASURE_0,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 0."
line.long 0x7C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_96,"
hexmask.long.byte 0x7C 16.--20. 1. "PHY_GTLVL_RESP_WAIT_CNT_0,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 0. The valid range is 0x0 to 0xB."
newline
hexmask.long.byte 0x7C 8.--11. 1. "PHY_GTLVL_DLY_STEP_0,DQS slave delay step size during gate training for slice 0."
newline
hexmask.long.byte 0x7C 0.--5. 1. "PHY_WRLVL_RESP_WAIT_CNT_0,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 0."
line.long 0x80 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_97,"
hexmask.long.word 0x80 16.--25. 1. "PHY_GTLVL_FINAL_STEP_0,Final backup step delay used in gate training algorithm for slice 0."
newline
hexmask.long.word 0x80 0.--9. 1. "PHY_GTLVL_BACK_STEP_0,Interim backup step delay used in gate training algorithm for slice 0."
line.long 0x84 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_98,"
hexmask.long.word 0x84 16.--24. 1. "PHY_WDQLVL_DM_SEARCH_RANGE_0,The dm slave delay search range for non-lpddr4 DM training for slice 0."
newline
hexmask.long.byte 0x84 8.--11. 1. "PHY_WDQLVL_QTR_DLY_STEP_0,Defines the step granularity for the logic to use once an edge is found for slice 0. When this occurs  the logic jumps back to the previous invalid value and uses this step size to determine a more accurate delay value."
newline
hexmask.long.byte 0x84 0.--7. 1. "PHY_WDQLVL_DLY_STEP_0,DQ slave delay step size during write data leveling for slice 0."
line.long 0x88 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_99,"
hexmask.long.byte 0x88 8.--11. 1. "PHY_RDLVL_DLY_STEP_0,DQS slave delay step size during read leveling for slice 0."
newline
bitfld.long 0x88 0. "PHY_TOGGLE_PRE_SUPPORT_0,Support the toggle read preamble for LPDDR4 for slice 0." "0,1"
line.long 0x8C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_100,"
hexmask.long.word 0x8C 0.--9. 1. "PHY_RDLVL_MAX_EDGE_0,The maximun rdlvl slave delay search window for read eye training for slice 0."
line.long 0x90 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_101,"
hexmask.long.byte 0x90 24.--30. 1. "PHY_MEAS_DLY_STEP_ENABLE_0,Data slice training step definition using phy_meas_dly_step_value for slice 0."
newline
hexmask.long.byte 0x90 16.--22. 1. "PHY_WDQ_OSC_DELTA_0,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 0."
newline
bitfld.long 0x90 8.--10. "PHY_WRPATH_GATE_TIMING_0,Write path clock gating timing for slice 0. it means additional clock number to write path clock gate" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x90 0.--1. "PHY_WRPATH_GATE_DISABLE_0,Write path clock gating disable for slice 0. [0]: disable pull in wrdata_en; [1]: disable write path clock gating  clock always on" "0,1,2,3"
line.long 0x94 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_102,"
hexmask.long.byte 0x94 0.--4. 1. "PHY_RDDATA_EN_DLY_0,Number of cycles that the dfi_rddata_en signal is early for slice 0."
line.long 0x98 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_103,"
hexmask.long 0x98 0.--31. 1. "PHY_DQ_DM_SWIZZLE0_0,DQ/DM bit swizzling 0 for slice 0. Bits [3:0] inform the PHY which bit in {DM DQ]} map to DQ0  Bits [7:4] inform the PHY which bit in {DM DQ} map to DQ1  etc."
line.long 0x9C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_104,"
hexmask.long.byte 0x9C 0.--3. 1. "PHY_DQ_DM_SWIZZLE1_0,DQ/DM bit swizzling 1 for slice 0. Bits [3:0] inform the PHY which bit in {DM DQ]} map to DM."
line.long 0xA0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_105,"
hexmask.long.word 0xA0 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_0,Write clock slave delay setting for DQ1 for slice 0."
newline
hexmask.long.word 0xA0 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_0,Write clock slave delay setting for DQ0 for slice 0."
line.long 0xA4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_106,"
hexmask.long.word 0xA4 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_0,Write clock slave delay setting for DQ3 for slice 0."
newline
hexmask.long.word 0xA4 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_0,Write clock slave delay setting for DQ2 for slice 0."
line.long 0xA8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_107,"
hexmask.long.word 0xA8 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_0,Write clock slave delay setting for DQ5 for slice 0."
newline
hexmask.long.word 0xA8 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_0,Write clock slave delay setting for DQ4 for slice 0."
line.long 0xAC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_108,"
hexmask.long.word 0xAC 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_0,Write clock slave delay setting for DQ7 for slice 0."
newline
hexmask.long.word 0xAC 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_0,Write clock slave delay setting for DQ6 for slice 0."
line.long 0xB0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_109,"
hexmask.long.word 0xB0 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_0,Write clock slave delay setting for DQS for slice 0."
newline
hexmask.long.word 0xB0 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_0,Write clock slave delay setting for DM for slice 0."
line.long 0xB4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_110,"
hexmask.long.word 0xB4 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ0 for slice 0."
newline
bitfld.long 0xB4 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_0,Write level threshold adjust value based on those thresholds for DQS for slice 0." "0,1,2,3"
line.long 0xB8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_111,"
hexmask.long.word 0xB8 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ1 for slice 0."
newline
hexmask.long.word 0xB8 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ0 for slice 0."
line.long 0xBC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_112,"
hexmask.long.word 0xBC 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ2 for slice 0."
newline
hexmask.long.word 0xBC 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ1 for slice 0."
line.long 0xC0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_113,"
hexmask.long.word 0xC0 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ3 for slice 0."
newline
hexmask.long.word 0xC0 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ2 for slice 0."
line.long 0xC4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_114,"
hexmask.long.word 0xC4 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ4 for slice 0."
newline
hexmask.long.word 0xC4 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ3 for slice 0."
line.long 0xC8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_115,"
hexmask.long.word 0xC8 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ5 for slice 0."
newline
hexmask.long.word 0xC8 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ4 for slice 0."
line.long 0xCC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_116,"
hexmask.long.word 0xCC 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ6 for slice 0."
newline
hexmask.long.word 0xCC 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ5 for slice 0."
line.long 0xD0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_117,"
hexmask.long.word 0xD0 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ7 for slice 0."
newline
hexmask.long.word 0xD0 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ6 for slice 0."
line.long 0xD4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_118,"
hexmask.long.word 0xD4 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DM for slice 0."
newline
hexmask.long.word 0xD4 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ7 for slice 0."
line.long 0xD8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_119,"
hexmask.long.word 0xD8 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_0,Read DQS slave delay setting for slice 0."
newline
hexmask.long.word 0xD8 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DM for slice 0."
line.long 0xDC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_120,"
hexmask.long.word 0xDC 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_0,Write level delay threshold above which will be considered in previous cycle for slice 0."
newline
bitfld.long 0xDC 8.--10. "PHY_WRITE_PATH_LAT_ADD_0,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 0." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xDC 0.--3. 1. "PHY_RDDQS_LATENCY_ADJUST_0,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0."
line.long 0xE0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_121,"
bitfld.long 0xE0 16. "PHY_WRLVL_EARLY_FORCE_ZERO_0,Force the final write level delay value [that meets the early threshold] to 0 for slice 0." "0,1"
newline
hexmask.long.word 0xE0 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0,Write level delay threshold below which will add a cycle of write path latency for slice 0."
line.long 0xE4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_122,"
hexmask.long.byte 0xE4 16.--19. 1. "PHY_GTLVL_LAT_ADJ_START_0,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 0."
newline
hexmask.long.word 0xE4 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_0,Initial read DQS gate slave delay setting during gate training for slice 0."
line.long 0xE8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_123,"
bitfld.long 0xE8 24. "PHY_NTP_PASS_0,Indicates if No-topology training found a passing result for slice 0." "0,1"
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hexmask.long.byte 0xE8 16.--19. 1. "PHY_NTP_WRLAT_START_0,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 0."
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hexmask.long.word 0xE8 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_0,Initial DQ/DM slave delay setting during write data leveling for slice 0."
line.long 0xEC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_124,"
hexmask.long.word 0xEC 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0,Read leveling starting value for the DQS/DQ slave delay settings for slice 0."
line.long 0xF0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_125,"
hexmask.long.byte 0xF0 16.--21. 1. "PHY_DSLICE_PAD_RX_CTLE_SETTING_0,Setting for RX ctle P/N of pad for slice 0."
newline
hexmask.long.word 0xF0 0.--15. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_0,Setting for boost P/N of pad for slice 0."
group.long 0x4400++0x27
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_256,"
hexmask.long.word 0x0 16.--26. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_1,Write data clock bypass mode slave delay setting for slice 1."
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hexmask.long.byte 0x0 8.--14. 1. "PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1,Controls PCLK/PARK pin for pad for slice 1 with boot frequency."
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bitfld.long 0x0 0.--2. "PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1,RX_PCLK boot clock frequency selection for slice 1." "0,1,2,3,4,5,6,7"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_257,"
bitfld.long 0x4 24.--26. "PHY_WRITE_PATH_LAT_ADD_BYPASS_1,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 1." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x4 8.--17. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1,Write DQS bypass mode slave delay setting for slice 1."
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hexmask.long.byte 0x4 0.--3. 1. "PHY_IO_PAD_DELAY_TIMING_BYPASS_1,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 1."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_258,"
bitfld.long 0x8 24. "PHY_CLK_BYPASS_OVERRIDE_1,Bypass mode override setting for slice 1." "0,1"
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bitfld.long 0x8 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_1,Two_cycle_preamble for bypass mode for slice 1." "0,1,2,3"
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hexmask.long.word 0x8 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1,Read DQS bypass mode slave delay setting for slice 1."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_259,"
hexmask.long.byte 0xC 24.--29. 1. "PHY_SW_WRDQ3_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
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hexmask.long.byte 0xC 16.--21. 1. "PHY_SW_WRDQ2_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
newline
hexmask.long.byte 0xC 8.--13. 1. "PHY_SW_WRDQ1_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
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hexmask.long.byte 0xC 0.--5. 1. "PHY_SW_WRDQ0_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_260,"
hexmask.long.byte 0x10 24.--29. 1. "PHY_SW_WRDQ7_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
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hexmask.long.byte 0x10 16.--21. 1. "PHY_SW_WRDQ6_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
newline
hexmask.long.byte 0x10 8.--13. 1. "PHY_SW_WRDQ5_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
newline
hexmask.long.byte 0x10 0.--5. 1. "PHY_SW_WRDQ4_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_261,"
hexmask.long.byte 0x14 24.--28. 1. "PHY_LP4_BOOT_RDDATA_EN_DLY_1,For LPDDR4 boot frequency  the number of cycles that the dfi_rddata_en signal is early for slice 1."
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bitfld.long 0x14 16.--17. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1,For LPDDR4 boot frequency  the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 1." "0,1,2,3"
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hexmask.long.byte 0x14 8.--11. 1. "PHY_SW_WRDQS_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bit [3] is the.."
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hexmask.long.byte 0x14 0.--5. 1. "PHY_SW_WRDM_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3] are the.."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_262,"
bitfld.long 0x18 24.--25. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1,For LPDDR4 boot frequency  write path clock gating disable for slice 1. Bit [0]: disable pull in wrdata_en; Bit [1]: disable write path clock gating  clock always on" "0,1,2,3"
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hexmask.long.byte 0x18 16.--19. 1. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1,For LPDDR4 boot frequency  the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 1."
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hexmask.long.byte 0x18 8.--11. 1. "PHY_LP4_BOOT_RPTR_UPDATE_1,For LPDDR4 boot frequency  the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 1."
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hexmask.long.byte 0x18 0.--4. 1. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1,For LPDDR4 boot frequency  the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_263,"
hexmask.long.word 0x1C 16.--24. 1. "PHY_LPBK_CONTROL_1,Loopback control bits for slice 1."
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bitfld.long 0x1C 8.--9. "PHY_CTRL_LPBK_EN_1,Loopback control en for slice 1." "0,1,2,3"
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hexmask.long.byte 0x1C 0.--4. 1. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1,For LPDDR4 boot frequency  the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 1."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_264,"
bitfld.long 0x20 8. "PHY_GATE_DELAY_COMP_DISABLE_1,use the control whether to compensate half_cycle when gate_slave_delay is larger than half_cycle for the gate close for slice 1." "0,1"
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bitfld.long 0x20 0. "PHY_LPBK_DFX_TIMEOUT_EN_1,Loopback read only test timeout mechanism enable for slice 1." "0,1"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_265,"
hexmask.long 0x24 0.--31. 1. "PHY_AUTO_TIMING_MARGIN_CONTROL_1,Auto timing marging control bits for slice 1."
rgroup.long 0x4428++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_266,"
hexmask.long 0x0 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_1,Observation register for the auto_timing_margin for slice 1. READ-ONLY"
group.long 0x442C++0x17
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_267,"
hexmask.long.byte 0x0 24.--30. 1. "PHY_PRBS_PATTERN_START_1,PRBS7 start pattern for slice 1."
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bitfld.long 0x0 16. "PHY_PDA_MODE_EN_1,When set to 1  the invalid DQs will be driven by the dfi_wrdata to make sure the tpda_s and tpda_h's timing is meet for slice 1." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "PHY_DQ_IDLE_1,When set to 1  the inavlid DQ will be driven to high  when set to 0  the invalid DQ will be driven to low for slice 1."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_268,"
bitfld.long 0x4 24. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_1,Read Leveling read level windows disable reset for slice 1." "0,1"
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bitfld.long 0x4 16. "PHY_RDLVL_MULTI_PATT_ENABLE_1,Read Leveling Multi-pattern enable for slice 1." "0,1"
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hexmask.long.word 0x4 0.--8. 1. "PHY_PRBS_PATTERN_MASK_1,PRBS7 mask signal for slice 1."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_269,"
hexmask.long.word 0x8 16.--25. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1,Read DQS data clock bypass mode slave delay setting for slice 1."
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hexmask.long.byte 0x8 8.--14. 1. "PHY_VREF_TRAIN_OBS_1,Observation register for best vref value for slice 1. READ-ONLY"
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hexmask.long.byte 0x8 0.--5. 1. "PHY_VREF_INITIAL_STEPSIZE_1,Data slice initial VREF training step size for slice 1."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_270,"
hexmask.long.word 0xC 16.--24. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_1,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 1."
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bitfld.long 0xC 8. "SC_PHY_SNAP_OBS_REGS_1,Initiates a snapshot of the internal observation registers for slice 1. Set to 1 to trigger. WRITE-ONLY" "0,1"
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hexmask.long.byte 0xC 0.--3. 1. "PHY_GATE_ERROR_DELAY_SELECT_1,Number of cycles to wait for the DQS gate to close before flagging an error for slice 1."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_271,"
hexmask.long.word 0x10 16.--24. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_1,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 1."
newline
bitfld.long 0x10 8.--10. "PHY_MEM_CLASS_1,Indicates the type of DRAM for slice 1. 0 for DDR3  1 for DDR4  2 for DDR5  4 for LPDDR2  5 for LPDDR3. 6 for LPDDR4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "PHY_LPDDR_1,Adds a cycle of delay for the slice 1 to match the address slice. Set to 1 to add a cycle" "0,1"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_272,"
bitfld.long 0x14 0.--1. "ON_FLY_GATE_ADJUST_EN_1,Control the on-the-fly gate adjustment for slice 1." "0,1,2,3"
rgroup.long 0x4444++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_273,"
hexmask.long 0x0 0.--31. 1. "PHY_GATE_TRACKING_OBS_1,Report the on-the-fly gate measurement result for slice 1. READ-ONLY"
group.long 0x4448++0x6B
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_274,"
bitfld.long 0x0 0.--1. "PHY_LP4_PST_AMBLE_1,Controls the read postamble extension for LPDDR4 for slice 1." "0,1,2,3"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_275,"
hexmask.long 0x4 0.--31. 1. "PHY_RDLVL_PATT8_1,Read leveling pattern 8 data for slice 1."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_276,"
hexmask.long 0x8 0.--31. 1. "PHY_RDLVL_PATT9_1,Read leveling pattern 9 data for slice 1."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_277,"
hexmask.long 0xC 0.--31. 1. "PHY_RDLVL_PATT10_1,Read leveling pattern 10 data for slice 1."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_278,"
hexmask.long 0x10 0.--31. 1. "PHY_RDLVL_PATT11_1,Read leveling pattern 11 data for slice 1."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_279,"
hexmask.long 0x14 0.--31. 1. "PHY_RDLVL_PATT12_1,Read leveling pattern 12 data for slice 1."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_280,"
hexmask.long 0x18 0.--31. 1. "PHY_RDLVL_PATT13_1,Read leveling pattern 13 data for slice 1."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_281,"
hexmask.long 0x1C 0.--31. 1. "PHY_RDLVL_PATT14_1,Read leveling pattern 14 data for slice 1."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_282,"
hexmask.long 0x20 0.--31. 1. "PHY_RDLVL_PATT15_1,Read leveling pattern 15 data for slice 1."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_283,"
bitfld.long 0x24 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_1,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 1." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x24 16.--19. 1. "PHY_MASTER_DLY_LOCK_OBS_SELECT_1,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 1."
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bitfld.long 0x24 8. "PHY_SW_FIFO_PTR_RST_DISABLE_1,Disables automatic reset of the read entry FIFO pointers for slice 1. Set to 1 to disable automatic resets." "0,1"
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bitfld.long 0x24 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_1,Reserved for future use for slice 1." "0,1,2,3,4,5,6,7"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_284,"
hexmask.long.byte 0x28 24.--27. 1. "PHY_FIFO_PTR_OBS_SELECT_1,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 1."
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hexmask.long.byte 0x28 16.--19. 1. "PHY_WR_SHIFT_OBS_SELECT_1,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 1."
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hexmask.long.byte 0x28 8.--11. 1. "PHY_WR_ENC_OBS_SELECT_1,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 1."
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hexmask.long.byte 0x28 0.--3. 1. "PHY_RDDQS_DQ_ENC_OBS_SELECT_1,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 1."
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_285,"
hexmask.long.byte 0x2C 24.--29. 1. "PHY_WRLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during write leveling for slice 1."
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bitfld.long 0x2C 16.--17. "PHY_WRLVL_ALGO_1,Write leveling algorithm selection for slice 1." "0,1,2,3"
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bitfld.long 0x2C 8. "SC_PHY_LVL_DEBUG_CONT_1,Allows the leveling state machine to advance [when in debug mode] for slice 1. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x2C 0. "PHY_LVL_DEBUG_MODE_1,Enables leveling debug mode for slice 1. Set to 1 to enable." "0,1"
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_286,"
hexmask.long.byte 0x30 24.--27. 1. "PHY_GTLVL_UPDT_WAIT_CNT_1,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 1. The valid range is 0x0 to 0xB."
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hexmask.long.byte 0x30 16.--21. 1. "PHY_GTLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during gate training for slice 1."
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hexmask.long.byte 0x30 8.--15. 1. "PHY_DQ_MASK_1,For ECC slice  should set this register to do DQ bit mask for slice 1."
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hexmask.long.byte 0x30 0.--3. 1. "PHY_WRLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 1."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_287,"
hexmask.long.byte 0x34 24.--28. 1. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 1."
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bitfld.long 0x34 16.--17. "PHY_RDLVL_OP_MODE_1,Read leveling algorithm select for slice 1. Clear to 0 to move linearly from left to right. Set to 1 to start inside the window  move left and then move right." "0,1,2,3"
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hexmask.long.byte 0x34 8.--11. 1. "PHY_RDLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 1."
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hexmask.long.byte 0x34 0.--5. 1. "PHY_RDLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during read leveling for slice 1."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_288,"
hexmask.long.tbyte 0x38 8.--25. 1. "PHY_RDLVL_DATA_SWIZZLE_1,Read level bit swizzling for DDR4 operation for slice 1."
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hexmask.long.byte 0x38 0.--7. 1. "PHY_RDLVL_DATA_MASK_1,Per-bit mask for read leveling for slice 1. If all bits are not used  only 1 bit should be cleared to 0."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_289,"
bitfld.long 0x3C 16.--18. "PHY_WDQLVL_PATT_1,Defines the training patterns to be used during the write data leveling sequence for slice 1. Bit [0] corresponds to the LFSR data training pattern. Bit [1] corresponds to the CLK data training pattern. Bit [2] corresponds to.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x3C 8.--13. 1. "PHY_WDQLVL_BURST_CNT_1,Defines the write/read burst length in bytes during the write data leveling sequence for slice 1."
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hexmask.long.byte 0x3C 0.--7. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_1,Defines the minimum gap requirment for the LE and TE window for slice 1."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_290,"
hexmask.long.byte 0x40 24.--27. 1. "PHY_WDQLVL_DQDM_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 1."
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hexmask.long.byte 0x40 16.--19. 1. "PHY_WDQLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 1."
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hexmask.long.word 0x40 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1,Defines the slave delay jump value when the TE window is found and begin to serch TE window for slice 1."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_291,"
bitfld.long 0x44 24. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_1,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 1. Set to 1 to trigger. WRITE-ONLY" "0,1"
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hexmask.long.byte 0x44 16.--19. 1. "PHY_WDQLVL_DM_DLY_STEP_1,The slave delay line step for DM training for slice 1."
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hexmask.long.byte 0x44 8.--15. 1. "PHY_WDQLVL_DQ_SLV_DELTA_1,The margin for DQ0-7's LE and TE dealy to make sure the DQ bits can work during DM training for slice 1."
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hexmask.long.byte 0x44 0.--7. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_1,Select value to map specific information during or post periodic write data leveling for slice 1."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_292,"
hexmask.long.word 0x48 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_1,Per-bit mask for write data leveling for slice 1. Set to 1 to mask any bit from the leveling process."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_293,"
hexmask.long 0x4C 0.--31. 1. "PHY_USER_PATT0_1,User-defined pattern to be used during write data leveling for slice 1. This register holds the bytes 3 to 0 written/read from device."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_294,"
hexmask.long 0x50 0.--31. 1. "PHY_USER_PATT1_1,User-defined pattern to be used during write data leveling for slice 1. This register holds the bytes 7 to 4 written/read from device."
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_295,"
hexmask.long 0x54 0.--31. 1. "PHY_USER_PATT2_1,User-defined pattern to be used during write data leveling for slice 1. This register holds the bytes 11 to 8 written/read from device."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_296,"
hexmask.long 0x58 0.--31. 1. "PHY_USER_PATT3_1,User-defined pattern to be used during write data leveling for slice 1. This register holds the bytes 15 to 12 written/read from device."
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_297,"
bitfld.long 0x5C 16. "PHY_NTP_MULT_TRAIN_1,Control for single pass only No-Topology training for slice 1." "0,1"
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hexmask.long.word 0x5C 0.--15. 1. "PHY_USER_PATT4_1,User-defined pattern to be used during write data leveling for slice 1. This register holds the DM bit for the 15 to 0 DQ written/read from device."
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_298,"
hexmask.long.word 0x60 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_1,Threshold Criteria of period threshold after No-Topology training is completed for slice 1."
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hexmask.long.word 0x60 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_1,Threshold Criteria of early threshold after No-Topology training is completed for slice 1."
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_299,"
hexmask.long.word 0x64 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_1,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary  to set period threshold/early threshold after No-Topology training is completed for slice 1."
newline
hexmask.long.word 0x64 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_1,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary  to set period threshold/early threshold after No-Topology training is completed for slice 1."
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_300,"
hexmask.long.byte 0x68 16.--23. 1. "PHY_FIFO_PTR_OBS_1,Observation register containing read entry FIFO pointers for slice 1. READ-ONLY"
newline
hexmask.long.byte 0x68 8.--13. 1. "SC_PHY_MANUAL_CLEAR_1,Manual reset/clear of internal logic for slice 1. Bit [0] initiates manual setup of the read DQS gate. Bit [1] is reset of read entry FIFO pointers. Bit [2] is reset of master delay min/max lock values. Bit [3] is manual reset of.."
newline
bitfld.long 0x68 0. "PHY_CALVL_VREF_DRIVING_SLICE_1,Indicates if slice 1 is used to drive the VREF value to the device during CA training." "0,1"
rgroup.long 0x44B4++0x3F
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_301,"
hexmask.long 0x0 0.--31. 1. "PHY_LPBK_RESULT_OBS_1,Observation register containing loopback status/results for slice 1. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_302,"
hexmask.long.word 0x4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_1,Observation register containing master delay results for slice 1. READ-ONLY"
newline
hexmask.long.word 0x4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_1,Observation register containing total number of loopback error data for slice 1. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_303,"
hexmask.long.byte 0x8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 1. READ-ONLY"
newline
hexmask.long.byte 0x8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_1,Observation register containing fraction of the cycle in 1 delay element  numerator with demominator of 512  for slice 1. READ-ONLY"
newline
hexmask.long.byte 0x8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1,Observation register containing read DQS base slave delay encoded value for slice 1. READ-ONLY"
newline
hexmask.long.byte 0x8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_1,Observation register containing read DQ slave delay encoded values for slice 1. READ-ONLY"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_304,"
hexmask.long.byte 0xC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1,Observation register containing write DQS base slave delay encoded value for slice 1. READ-ONLY"
newline
hexmask.long.word 0xC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1,Observation register containing read DQS gate slave delay encoded value for slice 1. READ-ONLY"
newline
hexmask.long.byte 0xC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 1. READ-ONLY"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_305,"
bitfld.long 0x10 16.--18. "PHY_WR_SHIFT_OBS_1,Observation register containing automatic half cycle and cycle shift values for slice 1. READ-ONLY" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing write adder slave delay encoded value for slice 1. READ-ONLY"
newline
hexmask.long.byte 0x10 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1,Observation register containing write DQ base slave delay encoded value for slice 1. READ-ONLY"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_306,"
hexmask.long.word 0x14 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_1,Observation register containing write leveling first hard 1 DQS slave delay for slice 1. READ-ONLY"
newline
hexmask.long.word 0x14 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_1,Observation register containing write leveling last hard 0 DQS slave delay for slice 1. READ-ONLY"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_307,"
hexmask.long.tbyte 0x18 0.--20. 1. "PHY_WRLVL_STATUS_OBS_1,Observation register containing write leveling status for slice 1. READ-ONLY"
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_308,"
hexmask.long.word 0x1C 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1,Observation register containing gate sample2 slave delay encoded values for slice 1. READ-ONLY"
newline
hexmask.long.word 0x1C 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1,Observation register containing gate sample1 slave delay encoded values for slice 1. READ-ONLY"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_309,"
hexmask.long.word 0x20 16.--29. 1. "PHY_GTLVL_HARD1_DELAY_OBS_1,Observation register containing gate training last hard 1 DQS slave delay for slice 1. READ-ONLY"
newline
hexmask.long.word 0x20 0.--13. 1. "PHY_GTLVL_HARD0_DELAY_OBS_1,Observation register containing gate training first hard 0 DQS slave delay for slice 1. READ-ONLY"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_310,"
hexmask.long.tbyte 0x24 0.--17. 1. "PHY_GTLVL_STATUS_OBS_1,Observation register containing gate training status for slice 1. READ-ONLY"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_311,"
hexmask.long.word 0x28 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1,Observation register containing read leveling data window trailing edge slave delay setting for slice 1. READ-ONLY"
newline
hexmask.long.word 0x28 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1,Observation register containing read leveling data window leading edge slave delay setting for slice 1. READ-ONLY"
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_312,"
bitfld.long 0x2C 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1,Observation register containing read leveling number of windows found for slice 1. READ-ONLY" "0,1,2,3"
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_313,"
hexmask.long 0x30 0.--31. 1. "PHY_RDLVL_STATUS_OBS_1,Observation register containing read leveling status for slice 1. READ-ONLY"
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_314,"
hexmask.long.word 0x34 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_1,Observation register containing write data leveling data window trailing edge slave delay setting for slice 1. READ-ONLY"
newline
hexmask.long.word 0x34 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_1,Observation register containing write data leveling data window leading edge slave delay setting for slice 1. READ-ONLY"
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_315,"
hexmask.long 0x38 0.--31. 1. "PHY_WDQLVL_STATUS_OBS_1,Observation register containing write data leveling status for slice 1. READ-ONLY"
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_316,"
hexmask.long 0x3C 0.--31. 1. "PHY_WDQLVL_PERIODIC_OBS_1,Observation register containing periodic write data leveling status for slice 1. READ-ONLY"
group.long 0x44F4++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_317,"
hexmask.long 0x0 0.--30. 1. "PHY_DDL_MODE_1,DDL mode for slice 1."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_318,"
hexmask.long.byte 0x4 0.--5. 1. "PHY_DDL_MASK_1,DDL mask for slice 1."
rgroup.long 0x44FC++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_319,"
hexmask.long 0x0 0.--31. 1. "PHY_DDL_TEST_OBS_1,DDL test observation for slice 1. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_320,"
hexmask.long 0x4 0.--31. 1. "PHY_DDL_TEST_MSTR_DLY_OBS_1,DDL test observation delays for slice 1 master DDL. READ-ONLY"
group.long 0x4504++0xF3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_321,"
hexmask.long.word 0x0 16.--24. 1. "PHY_RX_CAL_DQ0_1,RX Calibration codes for DQ0 for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
newline
bitfld.long 0x0 8. "PHY_LP4_WDQS_OE_EXTEND_1,LPDDR4 write preamble extension enable for slice 1." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_1,Specify threshold value for PHY init update tracking for slice 1."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_322,"
hexmask.long.word 0x4 16.--24. 1. "PHY_RX_CAL_DQ2_1,RX Calibration codes for DQ2 for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
newline
hexmask.long.word 0x4 0.--8. 1. "PHY_RX_CAL_DQ1_1,RX Calibration codes for DQ1 for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_323,"
hexmask.long.word 0x8 16.--24. 1. "PHY_RX_CAL_DQ4_1,RX Calibration codes for DQ4 for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
newline
hexmask.long.word 0x8 0.--8. 1. "PHY_RX_CAL_DQ3_1,RX Calibration codes for DQ3 for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_324,"
hexmask.long.word 0xC 16.--24. 1. "PHY_RX_CAL_DQ6_1,RX Calibration codes for DQ6 for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
newline
hexmask.long.word 0xC 0.--8. 1. "PHY_RX_CAL_DQ5_1,RX Calibration codes for DQ5 for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_325,"
hexmask.long.word 0x10 0.--8. 1. "PHY_RX_CAL_DQ7_1,RX Calibration codes for DQ7 for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_326,"
hexmask.long.tbyte 0x14 0.--17. 1. "PHY_RX_CAL_DM_1,RX Calibration codes for DM for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_327,"
hexmask.long.word 0x18 16.--24. 1. "PHY_RX_CAL_FDBK_1,RX Calibration codes for FDBK for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
newline
hexmask.long.word 0x18 0.--8. 1. "PHY_RX_CAL_DQS_1,RX Calibration codes for DQS for slice 1. Bits [5:0] contain rx_cal_code_down. Bits [11:6] contain rx_cal_code_up. Bits [17:12] contain rx_cal_code2_down. Bits [23:18] contain rx_cal_code2_up."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_328,"
bitfld.long 0x1C 24.--26. "PHY_FDBK_PWR_CTRL_1,Shutoff gate feedback IO to reduce power for slice 1." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x1C 16.--20. 1. "PHY_STATIC_TOG_DISABLE_1,Control to disable toggle during static activity for slice 1. bit0: Write path delay line disable; bit1: Read path delay line disable; bit2: Read data path disable; bit3: clk_phy disable; bit4: master delay line disable."
newline
hexmask.long.word 0x1C 0.--10. 1. "PHY_PAD_RX_BIAS_EN_1,Controls RX_BIAS_EN pin for each pad for slice 1."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_329,"
bitfld.long 0x20 24. "PHY_SLICE_PWR_RDC_DISABLE_1,Data slice power reduction disable for slice 1." "0,1"
newline
bitfld.long 0x20 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1,Data slice RX_CAL block power reduction disable for slice 1." "0,1"
newline
bitfld.long 0x20 8. "PHY_RDPATH_GATE_DISABLE_1,Data slice read path power reduction disable for slice 1." "0,1"
newline
bitfld.long 0x20 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_1,Data slice slv_dly_control block power reduction disable for slice 1." "0,1"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_330,"
bitfld.long 0x24 24.--26. "PHY_DQS_TSEL_ENABLE_1,Operation type tsel enables for DQS signals for slice 1. Bit [0] enables tsel_en during read cycles. Bit [1] enables tsel_en during write cycles. Bit [2] enables tsel_en during idle cycles. Set each bit to 1 to enable." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 8.--23. 1. "PHY_DQ_TSEL_SELECT_1,Operation type tsel select values for DQ/DM signals for slice 1."
newline
bitfld.long 0x24 0.--2. "PHY_DQ_TSEL_ENABLE_1,Operation type tsel enables for DQ/DM signals for slice 1. Bit [0] enables tsel_en during read cycles. Bit [1] enables tsel_en during write cycles. Bit [2] enables tsel_en during idle cycles. Set each bit to 1 to enable." "0,1,2,3,4,5,6,7"
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_331,"
hexmask.long.byte 0x28 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_1,Data slice initial VREF training start value for slice 1."
newline
bitfld.long 0x28 16.--17. "PHY_TWO_CYC_PREAMBLE_1,2 cycle preamble support for slice 1. Bit [0] controls the 2 cycle read preamble. Bit [1] controls the 2 cycle write preamble. Set each bit to 1 to enable." "0,1,2,3"
newline
hexmask.long.word 0x28 0.--15. 1. "PHY_DQS_TSEL_SELECT_1,Operation type tsel select values for DQS signals for slice 1."
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_332,"
hexmask.long.byte 0x2C 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_1,Step size of WR DQ slave delay during No-Topology training for slice 1."
newline
bitfld.long 0x2C 16. "PHY_NTP_TRAIN_EN_1,Enable for No-Topology training for slice 1." "0,1"
newline
bitfld.long 0x2C 8.--9. "PHY_VREF_TRAINING_CTRL_1,Data slice vref training enable control for slice 1." "0,1,2,3"
newline
hexmask.long.byte 0x2C 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_1,Data slice initial VREF training stop value for slice 1."
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_333,"
hexmask.long.word 0x30 16.--26. 1. "PHY_NTP_WDQ_STOP_1,End of WR DQ slave delay in No-Topology training for slice 1."
newline
hexmask.long.word 0x30 0.--10. 1. "PHY_NTP_WDQ_START_1,Starting WR DQ slave delay in No-Topology training for slice 1."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_334,"
bitfld.long 0x34 24. "PHY_SW_WDQLVL_DVW_MIN_EN_1,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 1." "0,1"
newline
hexmask.long.word 0x34 8.--17. 1. "PHY_WDQLVL_DVW_MIN_1,Minimum data valid window across DQs and ranks for slice 1."
newline
hexmask.long.byte 0x34 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_1,Enable Bit for WR DQ during No-Topology training for slice 1."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_335,"
hexmask.long.byte 0x38 24.--28. 1. "PHY_PAD_RX_DCD_0_1,Controls RX_DCD pin for each pad for slice 1."
newline
hexmask.long.byte 0x38 16.--20. 1. "PHY_PAD_TX_DCD_1,Controls TX_DCD pin for each pad for slice 1."
newline
hexmask.long.byte 0x38 8.--11. 1. "PHY_FAST_LVL_EN_1,Enable for fast multi-pattern window search for slice 1."
newline
hexmask.long.byte 0x38 0.--5. 1. "PHY_WDQLVL_PER_START_OFFSET_1,Peridic training start point offset for slice 1."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_336,"
hexmask.long.byte 0x3C 24.--28. 1. "PHY_PAD_RX_DCD_4_1,Controls RX_DCD pin for each pad for slice 1."
newline
hexmask.long.byte 0x3C 16.--20. 1. "PHY_PAD_RX_DCD_3_1,Controls RX_DCD pin for each pad for slice 1."
newline
hexmask.long.byte 0x3C 8.--12. 1. "PHY_PAD_RX_DCD_2_1,Controls RX_DCD pin for each pad for slice 1."
newline
hexmask.long.byte 0x3C 0.--4. 1. "PHY_PAD_RX_DCD_1_1,Controls RX_DCD pin for each pad for slice 1."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_337,"
hexmask.long.byte 0x40 24.--28. 1. "PHY_PAD_DM_RX_DCD_1,Controls RX_DCD pin for dm pad for slice 1."
newline
hexmask.long.byte 0x40 16.--20. 1. "PHY_PAD_RX_DCD_7_1,Controls RX_DCD pin for each pad for slice 1."
newline
hexmask.long.byte 0x40 8.--12. 1. "PHY_PAD_RX_DCD_6_1,Controls RX_DCD pin for each pad for slice 1."
newline
hexmask.long.byte 0x40 0.--4. 1. "PHY_PAD_RX_DCD_5_1,Controls RX_DCD pin for each pad for slice 1."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_338,"
hexmask.long.byte 0x44 16.--22. 1. "PHY_PAD_DSLICE_IO_CFG_1,Controls PCLK/PARK pin for pad for slice 1."
newline
hexmask.long.byte 0x44 8.--12. 1. "PHY_PAD_FDBK_RX_DCD_1,Controls RX_DCD pin for fdbk pad for slice 1."
newline
hexmask.long.byte 0x44 0.--4. 1. "PHY_PAD_DQS_RX_DCD_1,Controls RX_DCD pin for dqs pad for slice 1."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_339,"
hexmask.long.word 0x48 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_1,Read DQ1 slave delay setting for slice 1."
newline
hexmask.long.word 0x48 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_1,Read DQ0 slave delay setting for slice 1."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_340,"
hexmask.long.word 0x4C 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_1,Read DQ3 slave delay setting for slice 1."
newline
hexmask.long.word 0x4C 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_1,Read DQ2 slave delay setting for slice 1."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_341,"
hexmask.long.word 0x50 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_1,Read DQ5 slave delay setting for slice 1."
newline
hexmask.long.word 0x50 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_1,Read DQ4 slave delay setting for slice 1."
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_342,"
hexmask.long.word 0x54 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_1,Read DQ7 slave delay setting for slice 1."
newline
hexmask.long.word 0x54 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_1,Read DQ6 slave delay setting for slice 1."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_343,"
hexmask.long.byte 0x58 24.--28. 1. "PHY_RX_CAL_ALL_DLY_1,Defines the number of cycles/half cycles that the rx_cal_all_opad signal should be asserted for. There is a phy_rx_cal_all_dly_X parameter for each of the slices of data sent on the DFI data bus for slice 1."
newline
bitfld.long 0x58 16.--18. "PHY_RX_PCLK_CLK_SEL_1,RX_PCLK clock frequency selection for slice 1." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x58 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_1,Read DM/DBI slave delay setting for slice 1. May be used for data swap."
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_344,"
hexmask.long.byte 0x5C 24.--31. 1. "PHY_DQS_OE_TIMING_1,Start/end timing values for DQS output enable signals for slice 1."
newline
hexmask.long.byte 0x5C 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_1,Start/end timing values for DQ/DM write based termination enable and select signals for slice 1."
newline
hexmask.long.byte 0x5C 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_1,Start/end timing values for DQ/DM read based termination enable and select signals for slice 1."
newline
hexmask.long.byte 0x5C 0.--7. 1. "PHY_DQ_OE_TIMING_1,Start/end timing values for DQ/DM output enable signals for slice 1."
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_345,"
hexmask.long.byte 0x60 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_1,Start/end timing values for DQS write based termination enable and select signals for slice 1."
newline
hexmask.long.byte 0x60 16.--23. 1. "PHY_DQS_OE_RD_TIMING_1,Start/end timing values for DQS read based OE extension for slice 1."
newline
hexmask.long.byte 0x60 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_1,Start/end timing values for DQS read based termination enable and select signals for slice 1."
newline
hexmask.long.byte 0x60 0.--3. 1. "PHY_IO_PAD_DELAY_TIMING_1,Feedback pad's OPAD and IPAD delay timing for slice 1."
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_346,"
hexmask.long.word 0x64 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_1,Pad VREF control settings for DQ slice 1."
newline
hexmask.long.word 0x64 0.--15. 1. "PHY_VREF_SETTING_TIME_1,Number of cycles for vref settle after setting is changed for slice 1."
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_347,"
bitfld.long 0x68 24.--25. "PHY_IE_MODE_1,Input enable mode bits for slice 1. Bit [0] enables the mode where the input enables are always on; set to 1 to enable. Bit [1] disables the input enable on the DM signal; set to 1 to disable." "0,1,2,3"
newline
bitfld.long 0x68 16.--17. "PHY_RDDATA_EN_IE_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 1." "0,1,2,3"
newline
hexmask.long.byte 0x68 8.--15. 1. "PHY_DQS_IE_TIMING_1,Start/end timing values for DQS input enable signals for slice 1."
newline
hexmask.long.byte 0x68 0.--7. 1. "PHY_DQ_IE_TIMING_1,Start/end timing values for DQ/DM input enable signals for slice 1."
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_348,"
hexmask.long.byte 0x6C 24.--28. 1. "PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1,For WR DQ training  the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1."
newline
hexmask.long.byte 0x6C 16.--20. 1. "PHY_WDQLVL_RDDATA_EN_DLY_1,For WR DQ training  the number of cycles that the dfi_rddata_en signal is early for slice 1."
newline
bitfld.long 0x6C 8. "PHY_WDQLVL_IE_ON_1,IE control  1 meams IE is always on during WR DQ training for slice 1." "0,1"
newline
bitfld.long 0x6C 0.--1. "PHY_DBI_MODE_1,DBI mode for slice 1. Bit [0] enables return of DBI read data." "0,1,2,3"
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_349,"
hexmask.long.byte 0x70 16.--19. 1. "PHY_SW_MASTER_MODE_1,Master delay line override settings for slice 1. Bit [0] enables software half clock mode. Bit [1] is the software half clock mode value. Bit [2] enables software bypass mode. Bit [3] is the software bypass mode value."
newline
hexmask.long.byte 0x70 8.--12. 1. "PHY_RDDATA_EN_OE_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 1."
newline
hexmask.long.byte 0x70 0.--4. 1. "PHY_RDDATA_EN_TSEL_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1."
line.long 0x74 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_350,"
hexmask.long.byte 0x74 24.--31. 1. "PHY_MASTER_DELAY_WAIT_1,Wait cycles for master delay line locking algorithm for slice 1. Bits [3:0] are the cycle wait count after a calibration clock setting change. Bits [7:4] are the cycle wait count after a master delay setting change."
newline
hexmask.long.byte 0x74 16.--21. 1. "PHY_MASTER_DELAY_STEP_1,Incremental step size for master delay line locking algorithm for slice 1."
newline
hexmask.long.word 0x74 0.--10. 1. "PHY_MASTER_DELAY_START_1,Start value for master delay line locking algorithm for slice 1."
line.long 0x78 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_351,"
hexmask.long.byte 0x78 24.--27. 1. "PHY_WRLVL_DLY_FINE_STEP_1,DQS slave delay fine step size during write leveling for slice 1."
newline
hexmask.long.byte 0x78 16.--23. 1. "PHY_WRLVL_DLY_STEP_1,DQS slave delay step size during write leveling for slice 1."
newline
hexmask.long.byte 0x78 8.--11. 1. "PHY_RPTR_UPDATE_1,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 1."
newline
hexmask.long.byte 0x78 0.--7. 1. "PHY_MASTER_DELAY_HALF_MEASURE_1,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 1."
line.long 0x7C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_352,"
hexmask.long.byte 0x7C 16.--20. 1. "PHY_GTLVL_RESP_WAIT_CNT_1,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 1. The valid range is 0x0 to 0xB."
newline
hexmask.long.byte 0x7C 8.--11. 1. "PHY_GTLVL_DLY_STEP_1,DQS slave delay step size during gate training for slice 1."
newline
hexmask.long.byte 0x7C 0.--5. 1. "PHY_WRLVL_RESP_WAIT_CNT_1,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 1."
line.long 0x80 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_353,"
hexmask.long.word 0x80 16.--25. 1. "PHY_GTLVL_FINAL_STEP_1,Final backup step delay used in gate training algorithm for slice 1."
newline
hexmask.long.word 0x80 0.--9. 1. "PHY_GTLVL_BACK_STEP_1,Interim backup step delay used in gate training algorithm for slice 1."
line.long 0x84 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_354,"
hexmask.long.word 0x84 16.--24. 1. "PHY_WDQLVL_DM_SEARCH_RANGE_1,The dm slave delay search range for non-lpddr4 DM training for slice 1."
newline
hexmask.long.byte 0x84 8.--11. 1. "PHY_WDQLVL_QTR_DLY_STEP_1,Defines the step granularity for the logic to use once an edge is found for slice 1. When this occurs  the logic jumps back to the previous invalid value and uses this step size to determine a more accurate delay value."
newline
hexmask.long.byte 0x84 0.--7. 1. "PHY_WDQLVL_DLY_STEP_1,DQ slave delay step size during write data leveling for slice 1."
line.long 0x88 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_355,"
hexmask.long.byte 0x88 8.--11. 1. "PHY_RDLVL_DLY_STEP_1,DQS slave delay step size during read leveling for slice 1."
newline
bitfld.long 0x88 0. "PHY_TOGGLE_PRE_SUPPORT_1,Support the toggle read preamble for LPDDR4 for slice 1." "0,1"
line.long 0x8C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_356,"
hexmask.long.word 0x8C 0.--9. 1. "PHY_RDLVL_MAX_EDGE_1,The maximun rdlvl slave delay search window for read eye training for slice 1."
line.long 0x90 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_357,"
hexmask.long.byte 0x90 24.--30. 1. "PHY_MEAS_DLY_STEP_ENABLE_1,Data slice training step definition using phy_meas_dly_step_value for slice 1."
newline
hexmask.long.byte 0x90 16.--22. 1. "PHY_WDQ_OSC_DELTA_1,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 1."
newline
bitfld.long 0x90 8.--10. "PHY_WRPATH_GATE_TIMING_1,Write path clock gating timing for slice 1. it means additional clock number to write path clock gate" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x90 0.--1. "PHY_WRPATH_GATE_DISABLE_1,Write path clock gating disable for slice 1. [0]: disable pull in wrdata_en; [1]: disable write path clock gating  clock always on" "0,1,2,3"
line.long 0x94 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_358,"
hexmask.long.byte 0x94 0.--4. 1. "PHY_RDDATA_EN_DLY_1,Number of cycles that the dfi_rddata_en signal is early for slice 1."
line.long 0x98 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_359,"
hexmask.long 0x98 0.--31. 1. "PHY_DQ_DM_SWIZZLE0_1,DQ/DM bit swizzling 0 for slice 1. Bits [3:0] inform the PHY which bit in {DM DQ]} map to DQ0  Bits [7:4] inform the PHY which bit in {DM DQ} map to DQ1  etc."
line.long 0x9C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_360,"
hexmask.long.byte 0x9C 0.--3. 1. "PHY_DQ_DM_SWIZZLE1_1,DQ/DM bit swizzling 1 for slice 1. Bits [3:0] inform the PHY which bit in {DM DQ]} map to DM."
line.long 0xA0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_361,"
hexmask.long.word 0xA0 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_1,Write clock slave delay setting for DQ1 for slice 1."
newline
hexmask.long.word 0xA0 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_1,Write clock slave delay setting for DQ0 for slice 1."
line.long 0xA4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_362,"
hexmask.long.word 0xA4 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_1,Write clock slave delay setting for DQ3 for slice 1."
newline
hexmask.long.word 0xA4 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_1,Write clock slave delay setting for DQ2 for slice 1."
line.long 0xA8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_363,"
hexmask.long.word 0xA8 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_1,Write clock slave delay setting for DQ5 for slice 1."
newline
hexmask.long.word 0xA8 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_1,Write clock slave delay setting for DQ4 for slice 1."
line.long 0xAC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_364,"
hexmask.long.word 0xAC 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_1,Write clock slave delay setting for DQ7 for slice 1."
newline
hexmask.long.word 0xAC 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_1,Write clock slave delay setting for DQ6 for slice 1."
line.long 0xB0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_365,"
hexmask.long.word 0xB0 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_1,Write clock slave delay setting for DQS for slice 1."
newline
hexmask.long.word 0xB0 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_1,Write clock slave delay setting for DM for slice 1."
line.long 0xB4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_366,"
hexmask.long.word 0xB4 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ0 for slice 1."
newline
bitfld.long 0xB4 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_1,Write level threshold adjust value based on those thresholds for DQS for slice 1." "0,1,2,3"
line.long 0xB8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_367,"
hexmask.long.word 0xB8 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ1 for slice 1."
newline
hexmask.long.word 0xB8 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ0 for slice 1."
line.long 0xBC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_368,"
hexmask.long.word 0xBC 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ2 for slice 1."
newline
hexmask.long.word 0xBC 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ1 for slice 1."
line.long 0xC0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_369,"
hexmask.long.word 0xC0 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ3 for slice 1."
newline
hexmask.long.word 0xC0 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ2 for slice 1."
line.long 0xC4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_370,"
hexmask.long.word 0xC4 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ4 for slice 1."
newline
hexmask.long.word 0xC4 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ3 for slice 1."
line.long 0xC8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_371,"
hexmask.long.word 0xC8 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ5 for slice 1."
newline
hexmask.long.word 0xC8 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ4 for slice 1."
line.long 0xCC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_372,"
hexmask.long.word 0xCC 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ6 for slice 1."
newline
hexmask.long.word 0xCC 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ5 for slice 1."
line.long 0xD0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_373,"
hexmask.long.word 0xD0 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ7 for slice 1."
newline
hexmask.long.word 0xD0 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ6 for slice 1."
line.long 0xD4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_374,"
hexmask.long.word 0xD4 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DM for slice 1."
newline
hexmask.long.word 0xD4 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ7 for slice 1."
line.long 0xD8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_375,"
hexmask.long.word 0xD8 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_1,Read DQS slave delay setting for slice 1."
newline
hexmask.long.word 0xD8 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DM for slice 1."
line.long 0xDC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_376,"
hexmask.long.word 0xDC 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_1,Write level delay threshold above which will be considered in previous cycle for slice 1."
newline
bitfld.long 0xDC 8.--10. "PHY_WRITE_PATH_LAT_ADD_1,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 1." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xDC 0.--3. 1. "PHY_RDDQS_LATENCY_ADJUST_1,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 1."
line.long 0xE0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_377,"
bitfld.long 0xE0 16. "PHY_WRLVL_EARLY_FORCE_ZERO_1,Force the final write level delay value [that meets the early threshold] to 0 for slice 1." "0,1"
newline
hexmask.long.word 0xE0 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1,Write level delay threshold below which will add a cycle of write path latency for slice 1."
line.long 0xE4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_378,"
hexmask.long.byte 0xE4 16.--19. 1. "PHY_GTLVL_LAT_ADJ_START_1,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 1."
newline
hexmask.long.word 0xE4 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_1,Initial read DQS gate slave delay setting during gate training for slice 1."
line.long 0xE8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_379,"
bitfld.long 0xE8 24. "PHY_NTP_PASS_1,Indicates if No-topology training found a passing result for slice 1." "0,1"
newline
hexmask.long.byte 0xE8 16.--19. 1. "PHY_NTP_WRLAT_START_1,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 1."
newline
hexmask.long.word 0xE8 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_1,Initial DQ/DM slave delay setting during write data leveling for slice 1."
line.long 0xEC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_380,"
hexmask.long.word 0xEC 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1,Read leveling starting value for the DQS/DQ slave delay settings for slice 1."
line.long 0xF0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_381,"
hexmask.long.byte 0xF0 16.--21. 1. "PHY_DSLICE_PAD_RX_CTLE_SETTING_1,Setting for RX ctle P/N of pad for slice 1."
newline
hexmask.long.word 0xF0 0.--15. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_1,Setting for boost P/N of pad for slice 1."
group.long 0x4800++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_512,"
bitfld.long 0x0 24.--26. "SC_PHY_ADR_MANUAL_CLEAR_0,Manual reset/clear of internal logic for address slice 0. Bit [0] is reset of master delay min/max lock values. Bit [1] is manual reset of master delay unlock counter. Bit [2] clears the loopback error/results registers. Set.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "PHY_ADR_CLK_BYPASS_OVERRIDE_0,Bypass mode override setting for address slice 0. Set to 1 to enable." "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0,Command/Address clock bypass mode slave delay setting for address slice 0."
rgroup.long 0x4804++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_513,"
hexmask.long 0x0 0.--31. 1. "PHY_ADR_LPBK_RESULT_OBS_0,Observation register containing loopback status/results for address slice 0. READ-ONLY"
group.long 0x4808++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_514,"
hexmask.long.byte 0x0 24.--27. 1. "PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0,Select value to map the internal master delay observation registers to the accessible master delay observation register for address slice 0."
newline
hexmask.long.byte 0x0 16.--23. 1. "PHY_ADR_MEAS_DLY_STEP_VALUE_0,Contains the fraction of a cycle in 1 delay element numerator with demominator of 512  for address slice 0. READ-ONLY"
newline
hexmask.long.word 0x0 0.--15. 1. "PHY_ADR_LPBK_ERROR_COUNT_OBS_0,Observation register containing total number of loopback error data for address slice 0. READ-ONLY"
rgroup.long 0x480C++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_515,"
hexmask.long.byte 0x0 24.--31. 1. "PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing addr slave delay for address slice 0. READ-ONLY"
newline
hexmask.long.byte 0x0 16.--22. 1. "PHY_ADR_BASE_SLV_DLY_ENC_OBS_0,Observation register containing base slave delay for address slice 0. READ-ONLY"
newline
hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_MASTER_DLY_LOCK_OBS_0,Observation register containing master delay results for address slice 0. READ-ONLY"
group.long 0x4810++0x13
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_516,"
bitfld.long 0x0 24. "PHY_ADR_TSEL_ENABLE_0,Enables tsel_en for address slice 0." "0,1"
newline
bitfld.long 0x0 16. "SC_PHY_ADR_SNAP_OBS_REGS_0,Initiates a snapshot of the internal observation registers for address slice 0. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x0 8.--10. "PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0,Select value to map the addr bits delay observation registers to the accessible delay observation register for address slice 0." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0,Reserved for address slice 0." "0,1,2,3,4,5,6,7"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_517,"
bitfld.long 0x4 24. "PHY_ADR_PWR_RDC_DISABLE_0,Power reduction disable for address slice 0." "0,1"
newline
hexmask.long.byte 0x4 16.--20. 1. "PHY_ADR_PRBS_PATTERN_MASK_0,PRBS7 mask signal for address slice 0."
newline
hexmask.long.byte 0x4 8.--14. 1. "PHY_ADR_PRBS_PATTERN_START_0,PRBS7 start pattern for address slice 0."
newline
hexmask.long.byte 0x4 0.--6. 1. "PHY_ADR_LPBK_CONTROL_0,Loopback control bits for address slice 0."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_518,"
bitfld.long 0x8 24. "PHY_ADR_IE_MODE_0,Input enable control for address slice 0." "0,1"
newline
rbitfld.long 0x8 16.--18. "PHY_ADR_WRADDR_SHIFT_OBS_0,Observation register containing automatic half cycle and cycle shift values for address slice 0. READ-ONLY" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 8.--9. "PHY_ADR_TYPE_0,DRAM type for address slice 0." "0,1,2,3"
newline
bitfld.long 0x8 0. "PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0,Power reduction slv_dly_control block gate disable for address slice 0." "0,1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_519,"
hexmask.long 0xC 0.--26. 1. "PHY_ADR_DDL_MODE_0,DDL mode for address slice 0."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_520,"
hexmask.long.byte 0x10 0.--5. 1. "PHY_ADR_DDL_MASK_0,DDL mask for address slice 0."
rgroup.long 0x4824++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_521,"
hexmask.long 0x0 0.--31. 1. "PHY_ADR_DDL_TEST_OBS_0,Observation register containing DDL test bits for address slice 0. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_522,"
hexmask.long 0x4 0.--31. 1. "PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0,Observation register containing master DDL bits for address slice 0. READ-ONLY"
group.long 0x482C++0x17
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_523,"
hexmask.long.word 0x0 16.--26. 1. "PHY_ADR_CALVL_COARSE_DLY_0,Coarse CA training DDL increment value for address slice 0."
newline
hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_CALVL_START_0,CA training DDL start value for address slice 0."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_524,"
hexmask.long.word 0x4 0.--10. 1. "PHY_ADR_CALVL_QTR_0,CA training DDL quarter cycle delay value for address slice 0."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_525,"
hexmask.long.tbyte 0x8 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE0_0,CA training RD DQ bit swizzle map 0 for address slice 0."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_526,"
bitfld.long 0xC 24.--25. "PHY_ADR_CALVL_RANK_CTRL_0,CA training rank aggregation control bits for address slice 0." "0,1,2,3"
newline
hexmask.long.tbyte 0xC 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE1_0,CA training RD DQ bit swizzle map 1 for address slice 0."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_527,"
hexmask.long.word 0x10 16.--24. 1. "PHY_ADR_CALVL_PERIODIC_START_OFFSET_0,Relative offset to start periodic CALVL from previous result"
newline
hexmask.long.byte 0x10 8.--11. 1. "PHY_ADR_CALVL_RESP_WAIT_CNT_0,Number of samples to wait before sampling response during CA training for address slice 0."
newline
bitfld.long 0x10 0.--1. "PHY_ADR_CALVL_NUM_PATTERNS_0,Number of patterns to use during CA training for address slice 0." "0,1,2,3"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_528,"
bitfld.long 0x14 24.--26. "PHY_ADR_CALVL_OBS_SELECT_0,CA bit lane to observe result from OBS0 during CA training for address slice 0." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 16. "SC_PHY_ADR_CALVL_ERROR_CLR_0,Clears the CA training state machine error status for address slice 0. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x14 8. "SC_PHY_ADR_CALVL_DEBUG_CONT_0,Allows the CA training state machine to advance [when in debug mode] for address slice 0. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x14 0. "PHY_ADR_CALVL_DEBUG_MODE_0,Enables CA training debug mode for address slice 0. Set to 1 to enable." "0,1"
rgroup.long 0x4844++0xB
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_529,"
hexmask.long 0x0 0.--31. 1. "PHY_ADR_CALVL_OBS0_0,Observation register contains lane specific CA training bits for slice 0. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_530,"
hexmask.long 0x4 0.--31. 1. "PHY_ADR_CALVL_OBS1_0,Observation register contains general CA training bits for slice 0. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_531,"
hexmask.long 0x8 0.--31. 1. "PHY_ADR_CALVL_OBS2_0,Observation register contains periodic CA training bits for slice 0. READ-ONLY"
group.long 0x4850++0x5B
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_532,"
hexmask.long.tbyte 0x0 0.--19. 1. "PHY_ADR_CALVL_FG_0_0,CA training foreground pattern 0 for address slice 0."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_533,"
hexmask.long.tbyte 0x4 0.--19. 1. "PHY_ADR_CALVL_BG_0_0,CA training background pattern 0 for address slice 0."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_534,"
hexmask.long.tbyte 0x8 0.--19. 1. "PHY_ADR_CALVL_FG_1_0,CA training foreground pattern 1 for address slice 0."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_535,"
hexmask.long.tbyte 0xC 0.--19. 1. "PHY_ADR_CALVL_BG_1_0,CA training background pattern 1 for address slice 0."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_536,"
hexmask.long.tbyte 0x10 0.--19. 1. "PHY_ADR_CALVL_FG_2_0,CA training foreground pattern 2 for address slice 0."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_537,"
hexmask.long.tbyte 0x14 0.--19. 1. "PHY_ADR_CALVL_BG_2_0,CA training background pattern 2 for address slice 0."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_538,"
hexmask.long.tbyte 0x18 0.--19. 1. "PHY_ADR_CALVL_FG_3_0,CA training foreground pattern 3 for address slice 0."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_539,"
hexmask.long.tbyte 0x1C 0.--19. 1. "PHY_ADR_CALVL_BG_3_0,CA training background pattern 3 for address slice 0."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_540,"
hexmask.long 0x20 0.--29. 1. "PHY_ADR_ADDR_SEL_0,Selects which DFI address pins connect to which CA pins for LPDDR3/4 for address slice 0."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_541,"
hexmask.long.byte 0x24 24.--29. 1. "PHY_ADR_SEG_MASK_0,Segment mask bit for address slice 0. Set to 1 to indicate that the bit is either CA 4 or CA 9."
newline
hexmask.long.byte 0x24 16.--21. 1. "PHY_ADR_BIT_MASK_0,Mask bit for address slice 0. Set to 1 to indicate that the bit is used."
newline
hexmask.long.word 0x24 0.--9. 1. "PHY_ADR_LP4_BOOT_SLV_DELAY_0,Address slave delay setting during the LPDDR4 boot frequency operation for address slice 0."
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_542,"
hexmask.long.byte 0x28 24.--29. 1. "PHY_ADR_SW_TXIO_CTRL_0,Controls address pad output enable for address slice 0. Set to 1 to disable output enable."
newline
hexmask.long.byte 0x28 16.--19. 1. "PHY_ADR_STATIC_TOG_DISABLE_0,Toggle control during static activity for address slice 0. Set bit to dsiable toggling  bit0: Write path delay line  bit1: Read path delay line  bit2: Read data path  bit3: clk_phy  bit4: master delay line."
newline
hexmask.long.byte 0x28 8.--13. 1. "PHY_ADR_CSLVL_TRAIN_MASK_0,Mask bit for CS training participation for address slice 0. Set to 1 to indicate that the bit is participating in CS training."
newline
hexmask.long.byte 0x28 0.--5. 1. "PHY_ADR_CALVL_TRAIN_MASK_0,Mask bit for CA training participation for address slice 0. Set to 1 to indicate that the bit is participating in CA training."
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_543,"
hexmask.long.byte 0x2C 0.--5. 1. "PHY_ADR_SW_TXPWR_CTRL_0,Disable address output enables in deep sleep mode for address slice 0."
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_544,"
bitfld.long 0x30 24.--26. "PHY_PAD_ADR_RX_PCLK_CLK_SEL_0,Reserved for address slice 0." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 8.--18. 1. "PHY_PAD_ADR_IO_CFG_0,Controls I/O pads for address pad for address slice 0. Bits [10:5] = Park value  bits [4] park override  bits [2:0] clk divider."
newline
hexmask.long.byte 0x30 0.--7. 1. "PHY_ADR_TSEL_SELECT_0,Tsel select values for address slice 0."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_545,"
hexmask.long.byte 0x34 24.--28. 1. "PHY_ADR1_SW_WRADDR_SHIFT_0,Manual override of CA bit 1 of automatic half_cycle_shift/cycle_shift for address slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x34 8.--18. 1. "PHY_ADR0_CLK_WR_SLAVE_DELAY_0,CA bit 0 slave delay setting for address slice 0."
newline
hexmask.long.byte 0x34 0.--4. 1. "PHY_ADR0_SW_WRADDR_SHIFT_0,Manual override of CA bit 0 of automatic half_cycle_shift/cycle_shift for address slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_546,"
hexmask.long.byte 0x38 16.--20. 1. "PHY_ADR2_SW_WRADDR_SHIFT_0,Manual override of CA bit 2 of automatic half_cycle_shift/cycle_shift for address slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x38 0.--10. 1. "PHY_ADR1_CLK_WR_SLAVE_DELAY_0,CA bit 1 slave delay setting for address slice 0."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_547,"
hexmask.long.byte 0x3C 16.--20. 1. "PHY_ADR3_SW_WRADDR_SHIFT_0,Manual override of CA bit 3 of automatic half_cycle_shift/cycle_shift for address slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x3C 0.--10. 1. "PHY_ADR2_CLK_WR_SLAVE_DELAY_0,CA bit 2 slave delay setting for address slice 0."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_548,"
hexmask.long.byte 0x40 16.--20. 1. "PHY_ADR4_SW_WRADDR_SHIFT_0,Manual override of CA bit 4 of automatic half_cycle_shift/cycle_shift for address slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x40 0.--10. 1. "PHY_ADR3_CLK_WR_SLAVE_DELAY_0,CA bit 3 slave delay setting for address slice 0."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_549,"
hexmask.long.byte 0x44 16.--20. 1. "PHY_ADR5_SW_WRADDR_SHIFT_0,Manual override of CA bit 5 of automatic half_cycle_shift/cycle_shift for address slice 0. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x44 0.--10. 1. "PHY_ADR4_CLK_WR_SLAVE_DELAY_0,CA bit 4 slave delay setting for address slice 0."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_550,"
hexmask.long.byte 0x48 16.--19. 1. "PHY_ADR_SW_MASTER_MODE_0,Master delay line override settings for address slice 0. Bit [0] enables software half clock mode. Bit [1] is the software half clock mode value. Bit [2] enables software bypass mode. Bit [3] is the software bypass mode value."
newline
hexmask.long.word 0x48 0.--10. 1. "PHY_ADR5_CLK_WR_SLAVE_DELAY_0,CA bit 5 slave delay setting for address slice 0."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_551,"
hexmask.long.byte 0x4C 24.--31. 1. "PHY_ADR_MASTER_DELAY_WAIT_0,Wait cycles for master delay line locking algorithm for address slice 0. Bits [3:0] is the cycle wait count after a calibration clock setting change. Bits [7:4] is the cycle wait count after a master delay setting change."
newline
hexmask.long.byte 0x4C 16.--21. 1. "PHY_ADR_MASTER_DELAY_STEP_0,Incremental step size for master delay line locking algorithm for address slice 0."
newline
hexmask.long.word 0x4C 0.--10. 1. "PHY_ADR_MASTER_DELAY_START_0,Start value for master delay line locking algorithm for address slice 0."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_552,"
bitfld.long 0x50 24. "PHY_ADR_SW_CALVL_DVW_MIN_EN_0,Enables the software override data valid window size during CA training for address slice 0." "0,1"
newline
hexmask.long.word 0x50 8.--17. 1. "PHY_ADR_SW_CALVL_DVW_MIN_0,Sets the software override data valid window size during CA training for address slice 0."
newline
hexmask.long.byte 0x50 0.--7. 1. "PHY_ADR_MASTER_DELAY_HALF_MEASURE_0,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle for the master in address slice 0"
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_553,"
hexmask.long.byte 0x54 0.--3. 1. "PHY_ADR_CALVL_DLY_STEP_0,Sets the delay step size plus 1 during CA training for address slice 0."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_554,"
bitfld.long 0x58 8. "PHY_ADR_MEAS_DLY_STEP_ENABLE_0,Enables delay parameter setting using phy_adr_meas_dly_step_value for address slice 0." "0,1"
newline
hexmask.long.byte 0x58 0.--3. 1. "PHY_ADR_CALVL_CAPTURE_CNT_0,Number of samples to take at each ADDR slave delay setting during CA training for address slice 0."
group.long 0x4C00++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_768,"
bitfld.long 0x0 24.--26. "SC_PHY_ADR_MANUAL_CLEAR_1,Manual reset/clear of internal logic for address slice 1. Bit [0] is reset of master delay min/max lock values. Bit [1] is manual reset of master delay unlock counter. Bit [2] clears the loopback error/results registers. Set.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "PHY_ADR_CLK_BYPASS_OVERRIDE_1,Bypass mode override setting for address slice 1. Set to 1 to enable." "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1,Command/Address clock bypass mode slave delay setting for address slice 1."
rgroup.long 0x4C04++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_769,"
hexmask.long 0x0 0.--31. 1. "PHY_ADR_LPBK_RESULT_OBS_1,Observation register containing loopback status/results for address slice 1. READ-ONLY"
group.long 0x4C08++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_770,"
hexmask.long.byte 0x0 24.--27. 1. "PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1,Select value to map the internal master delay observation registers to the accessible master delay observation register for address slice 1."
newline
hexmask.long.byte 0x0 16.--23. 1. "PHY_ADR_MEAS_DLY_STEP_VALUE_1,Contains the fraction of a cycle in 1 delay element numerator with demominator of 512  for address slice 1. READ-ONLY"
newline
hexmask.long.word 0x0 0.--15. 1. "PHY_ADR_LPBK_ERROR_COUNT_OBS_1,Observation register containing total number of loopback error data for address slice 1. READ-ONLY"
rgroup.long 0x4C0C++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_771,"
hexmask.long.byte 0x0 24.--31. 1. "PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing addr slave delay for address slice 1. READ-ONLY"
newline
hexmask.long.byte 0x0 16.--22. 1. "PHY_ADR_BASE_SLV_DLY_ENC_OBS_1,Observation register containing base slave delay for address slice 1. READ-ONLY"
newline
hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_MASTER_DLY_LOCK_OBS_1,Observation register containing master delay results for address slice 1. READ-ONLY"
group.long 0x4C10++0x13
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_772,"
bitfld.long 0x0 24. "PHY_ADR_TSEL_ENABLE_1,Enables tsel_en for address slice 1." "0,1"
newline
bitfld.long 0x0 16. "SC_PHY_ADR_SNAP_OBS_REGS_1,Initiates a snapshot of the internal observation registers for address slice 1. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x0 8.--10. "PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1,Select value to map the addr bits delay observation registers to the accessible delay observation register for address slice 1." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1,Reserved for address slice 1." "0,1,2,3,4,5,6,7"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_773,"
bitfld.long 0x4 24. "PHY_ADR_PWR_RDC_DISABLE_1,Power reduction disable for address slice 1." "0,1"
newline
hexmask.long.byte 0x4 16.--20. 1. "PHY_ADR_PRBS_PATTERN_MASK_1,PRBS7 mask signal for address slice 1."
newline
hexmask.long.byte 0x4 8.--14. 1. "PHY_ADR_PRBS_PATTERN_START_1,PRBS7 start pattern for address slice 1."
newline
hexmask.long.byte 0x4 0.--6. 1. "PHY_ADR_LPBK_CONTROL_1,Loopback control bits for address slice 1."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_774,"
bitfld.long 0x8 24. "PHY_ADR_IE_MODE_1,Input enable control for address slice 1." "0,1"
newline
rbitfld.long 0x8 16.--18. "PHY_ADR_WRADDR_SHIFT_OBS_1,Observation register containing automatic half cycle and cycle shift values for address slice 1. READ-ONLY" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 8.--9. "PHY_ADR_TYPE_1,DRAM type for address slice 1." "0,1,2,3"
newline
bitfld.long 0x8 0. "PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1,Power reduction slv_dly_control block gate disable for address slice 1." "0,1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_775,"
hexmask.long 0xC 0.--26. 1. "PHY_ADR_DDL_MODE_1,DDL mode for address slice 1."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_776,"
hexmask.long.byte 0x10 0.--5. 1. "PHY_ADR_DDL_MASK_1,DDL mask for address slice 1."
rgroup.long 0x4C24++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_777,"
hexmask.long 0x0 0.--31. 1. "PHY_ADR_DDL_TEST_OBS_1,Observation register containing DDL test bits for address slice 1. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_778,"
hexmask.long 0x4 0.--31. 1. "PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1,Observation register containing master DDL bits for address slice 1. READ-ONLY"
group.long 0x4C2C++0x17
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_779,"
hexmask.long.word 0x0 16.--26. 1. "PHY_ADR_CALVL_COARSE_DLY_1,Coarse CA training DDL increment value for address slice 1."
newline
hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_CALVL_START_1,CA training DDL start value for address slice 1."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_780,"
hexmask.long.word 0x4 0.--10. 1. "PHY_ADR_CALVL_QTR_1,CA training DDL quarter cycle delay value for address slice 1."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_781,"
hexmask.long.tbyte 0x8 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE0_1,CA training RD DQ bit swizzle map 0 for address slice 1."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_782,"
bitfld.long 0xC 24.--25. "PHY_ADR_CALVL_RANK_CTRL_1,CA training rank aggregation control bits for address slice 1." "0,1,2,3"
newline
hexmask.long.tbyte 0xC 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE1_1,CA training RD DQ bit swizzle map 1 for address slice 1."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_783,"
hexmask.long.word 0x10 16.--24. 1. "PHY_ADR_CALVL_PERIODIC_START_OFFSET_1,Relative offset to start periodic CALVL from previous result"
newline
hexmask.long.byte 0x10 8.--11. 1. "PHY_ADR_CALVL_RESP_WAIT_CNT_1,Number of samples to wait before sampling response during CA training for address slice 1."
newline
bitfld.long 0x10 0.--1. "PHY_ADR_CALVL_NUM_PATTERNS_1,Number of patterns to use during CA training for address slice 1." "0,1,2,3"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_784,"
bitfld.long 0x14 24.--26. "PHY_ADR_CALVL_OBS_SELECT_1,CA bit lane to observe result from OBS0 during CA training for address slice 1." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 16. "SC_PHY_ADR_CALVL_ERROR_CLR_1,Clears the CA training state machine error status for address slice 1. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x14 8. "SC_PHY_ADR_CALVL_DEBUG_CONT_1,Allows the CA training state machine to advance [when in debug mode] for address slice 1. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x14 0. "PHY_ADR_CALVL_DEBUG_MODE_1,Enables CA training debug mode for address slice 1. Set to 1 to enable." "0,1"
rgroup.long 0x4C44++0xB
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_785,"
hexmask.long 0x0 0.--31. 1. "PHY_ADR_CALVL_OBS0_1,Observation register contains lane specific CA training bits for slice 1. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_786,"
hexmask.long 0x4 0.--31. 1. "PHY_ADR_CALVL_OBS1_1,Observation register contains general CA training bits for slice 1. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_787,"
hexmask.long 0x8 0.--31. 1. "PHY_ADR_CALVL_OBS2_1,Observation register contains periodic CA training bits for slice 1. READ-ONLY"
group.long 0x4C50++0x5B
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_788,"
hexmask.long.tbyte 0x0 0.--19. 1. "PHY_ADR_CALVL_FG_0_1,CA training foreground pattern 0 for address slice 1."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_789,"
hexmask.long.tbyte 0x4 0.--19. 1. "PHY_ADR_CALVL_BG_0_1,CA training background pattern 0 for address slice 1."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_790,"
hexmask.long.tbyte 0x8 0.--19. 1. "PHY_ADR_CALVL_FG_1_1,CA training foreground pattern 1 for address slice 1."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_791,"
hexmask.long.tbyte 0xC 0.--19. 1. "PHY_ADR_CALVL_BG_1_1,CA training background pattern 1 for address slice 1."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_792,"
hexmask.long.tbyte 0x10 0.--19. 1. "PHY_ADR_CALVL_FG_2_1,CA training foreground pattern 2 for address slice 1."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_793,"
hexmask.long.tbyte 0x14 0.--19. 1. "PHY_ADR_CALVL_BG_2_1,CA training background pattern 2 for address slice 1."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_794,"
hexmask.long.tbyte 0x18 0.--19. 1. "PHY_ADR_CALVL_FG_3_1,CA training foreground pattern 3 for address slice 1."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_795,"
hexmask.long.tbyte 0x1C 0.--19. 1. "PHY_ADR_CALVL_BG_3_1,CA training background pattern 3 for address slice 1."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_796,"
hexmask.long 0x20 0.--29. 1. "PHY_ADR_ADDR_SEL_1,Selects which DFI address pins connect to which CA pins for LPDDR3/4 for address slice 1."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_797,"
hexmask.long.byte 0x24 24.--29. 1. "PHY_ADR_SEG_MASK_1,Segment mask bit for address slice 1. Set to 1 to indicate that the bit is either CA 4 or CA 9."
newline
hexmask.long.byte 0x24 16.--21. 1. "PHY_ADR_BIT_MASK_1,Mask bit for address slice 1. Set to 1 to indicate that the bit is used."
newline
hexmask.long.word 0x24 0.--9. 1. "PHY_ADR_LP4_BOOT_SLV_DELAY_1,Address slave delay setting during the LPDDR4 boot frequency operation for address slice 1."
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_798,"
hexmask.long.byte 0x28 24.--29. 1. "PHY_ADR_SW_TXIO_CTRL_1,Controls address pad output enable for address slice 1. Set to 1 to disable output enable."
newline
hexmask.long.byte 0x28 16.--19. 1. "PHY_ADR_STATIC_TOG_DISABLE_1,Toggle control during static activity for address slice 1. Set bit to dsiable toggling  bit0: Write path delay line  bit1: Read path delay line  bit2: Read data path  bit3: clk_phy  bit4: master delay line."
newline
hexmask.long.byte 0x28 8.--13. 1. "PHY_ADR_CSLVL_TRAIN_MASK_1,Mask bit for CS training participation for address slice 1. Set to 1 to indicate that the bit is participating in CS training."
newline
hexmask.long.byte 0x28 0.--5. 1. "PHY_ADR_CALVL_TRAIN_MASK_1,Mask bit for CA training participation for address slice 1. Set to 1 to indicate that the bit is participating in CA training."
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_799,"
hexmask.long.byte 0x2C 0.--5. 1. "PHY_ADR_SW_TXPWR_CTRL_1,Disable address output enables in deep sleep mode for address slice 1."
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_800,"
bitfld.long 0x30 24.--26. "PHY_PAD_ADR_RX_PCLK_CLK_SEL_1,Reserved for address slice 1." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 8.--18. 1. "PHY_PAD_ADR_IO_CFG_1,Controls I/O pads for address pad for address slice 1. Bits [10:5] = Park value  bits [4] park override  bits [2:0] clk divider."
newline
hexmask.long.byte 0x30 0.--7. 1. "PHY_ADR_TSEL_SELECT_1,Tsel select values for address slice 1."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_801,"
hexmask.long.byte 0x34 24.--28. 1. "PHY_ADR1_SW_WRADDR_SHIFT_1,Manual override of CA bit 1 of automatic half_cycle_shift/cycle_shift for address slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x34 8.--18. 1. "PHY_ADR0_CLK_WR_SLAVE_DELAY_1,CA bit 0 slave delay setting for address slice 1."
newline
hexmask.long.byte 0x34 0.--4. 1. "PHY_ADR0_SW_WRADDR_SHIFT_1,Manual override of CA bit 0 of automatic half_cycle_shift/cycle_shift for address slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_802,"
hexmask.long.byte 0x38 16.--20. 1. "PHY_ADR2_SW_WRADDR_SHIFT_1,Manual override of CA bit 2 of automatic half_cycle_shift/cycle_shift for address slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x38 0.--10. 1. "PHY_ADR1_CLK_WR_SLAVE_DELAY_1,CA bit 1 slave delay setting for address slice 1."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_803,"
hexmask.long.byte 0x3C 16.--20. 1. "PHY_ADR3_SW_WRADDR_SHIFT_1,Manual override of CA bit 3 of automatic half_cycle_shift/cycle_shift for address slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x3C 0.--10. 1. "PHY_ADR2_CLK_WR_SLAVE_DELAY_1,CA bit 2 slave delay setting for address slice 1."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_804,"
hexmask.long.byte 0x40 16.--20. 1. "PHY_ADR4_SW_WRADDR_SHIFT_1,Manual override of CA bit 4 of automatic half_cycle_shift/cycle_shift for address slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x40 0.--10. 1. "PHY_ADR3_CLK_WR_SLAVE_DELAY_1,CA bit 3 slave delay setting for address slice 1."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_805,"
hexmask.long.byte 0x44 16.--20. 1. "PHY_ADR5_SW_WRADDR_SHIFT_1,Manual override of CA bit 5 of automatic half_cycle_shift/cycle_shift for address slice 1. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x44 0.--10. 1. "PHY_ADR4_CLK_WR_SLAVE_DELAY_1,CA bit 4 slave delay setting for address slice 1."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_806,"
hexmask.long.byte 0x48 16.--19. 1. "PHY_ADR_SW_MASTER_MODE_1,Master delay line override settings for address slice 1. Bit [0] enables software half clock mode. Bit [1] is the software half clock mode value. Bit [2] enables software bypass mode. Bit [3] is the software bypass mode value."
newline
hexmask.long.word 0x48 0.--10. 1. "PHY_ADR5_CLK_WR_SLAVE_DELAY_1,CA bit 5 slave delay setting for address slice 1."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_807,"
hexmask.long.byte 0x4C 24.--31. 1. "PHY_ADR_MASTER_DELAY_WAIT_1,Wait cycles for master delay line locking algorithm for address slice 1. Bits [3:0] is the cycle wait count after a calibration clock setting change. Bits [7:4] is the cycle wait count after a master delay setting change."
newline
hexmask.long.byte 0x4C 16.--21. 1. "PHY_ADR_MASTER_DELAY_STEP_1,Incremental step size for master delay line locking algorithm for address slice 1."
newline
hexmask.long.word 0x4C 0.--10. 1. "PHY_ADR_MASTER_DELAY_START_1,Start value for master delay line locking algorithm for address slice 1."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_808,"
bitfld.long 0x50 24. "PHY_ADR_SW_CALVL_DVW_MIN_EN_1,Enables the software override data valid window size during CA training for address slice 1." "0,1"
newline
hexmask.long.word 0x50 8.--17. 1. "PHY_ADR_SW_CALVL_DVW_MIN_1,Sets the software override data valid window size during CA training for address slice 1."
newline
hexmask.long.byte 0x50 0.--7. 1. "PHY_ADR_MASTER_DELAY_HALF_MEASURE_1,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle for the master in address slice 1"
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_809,"
hexmask.long.byte 0x54 0.--3. 1. "PHY_ADR_CALVL_DLY_STEP_1,Sets the delay step size plus 1 during CA training for address slice 1."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_810,"
bitfld.long 0x58 8. "PHY_ADR_MEAS_DLY_STEP_ENABLE_1,Enables delay parameter setting using phy_adr_meas_dly_step_value for address slice 1." "0,1"
newline
hexmask.long.byte 0x58 0.--3. 1. "PHY_ADR_CALVL_CAPTURE_CNT_1,Number of samples to take at each ADDR slave delay setting during CA training for address slice 1."
group.long 0x5000++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1024,"
bitfld.long 0x0 24.--26. "SC_PHY_ADR_MANUAL_CLEAR_2,Manual reset/clear of internal logic for address slice 2. Bit [0] is reset of master delay min/max lock values. Bit [1] is manual reset of master delay unlock counter. Bit [2] clears the loopback error/results registers. Set.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "PHY_ADR_CLK_BYPASS_OVERRIDE_2,Bypass mode override setting for address slice 2. Set to 1 to enable." "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2,Command/Address clock bypass mode slave delay setting for address slice 2."
rgroup.long 0x5004++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1025,"
hexmask.long 0x0 0.--31. 1. "PHY_ADR_LPBK_RESULT_OBS_2,Observation register containing loopback status/results for address slice 2. READ-ONLY"
group.long 0x5008++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1026,"
hexmask.long.byte 0x0 24.--27. 1. "PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2,Select value to map the internal master delay observation registers to the accessible master delay observation register for address slice 2."
newline
hexmask.long.byte 0x0 16.--23. 1. "PHY_ADR_MEAS_DLY_STEP_VALUE_2,Contains the fraction of a cycle in 1 delay element numerator with demominator of 512  for address slice 2. READ-ONLY"
newline
hexmask.long.word 0x0 0.--15. 1. "PHY_ADR_LPBK_ERROR_COUNT_OBS_2,Observation register containing total number of loopback error data for address slice 2. READ-ONLY"
rgroup.long 0x500C++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1027,"
hexmask.long.byte 0x0 24.--31. 1. "PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2,Observation register containing addr slave delay for address slice 2. READ-ONLY"
newline
hexmask.long.byte 0x0 16.--22. 1. "PHY_ADR_BASE_SLV_DLY_ENC_OBS_2,Observation register containing base slave delay for address slice 2. READ-ONLY"
newline
hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_MASTER_DLY_LOCK_OBS_2,Observation register containing master delay results for address slice 2. READ-ONLY"
group.long 0x5010++0x13
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1028,"
bitfld.long 0x0 24. "PHY_ADR_TSEL_ENABLE_2,Enables tsel_en for address slice 2." "0,1"
newline
bitfld.long 0x0 16. "SC_PHY_ADR_SNAP_OBS_REGS_2,Initiates a snapshot of the internal observation registers for address slice 2. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x0 8.--10. "PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2,Select value to map the addr bits delay observation registers to the accessible delay observation register for address slice 2." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2,Reserved for address slice 2." "0,1,2,3,4,5,6,7"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1029,"
bitfld.long 0x4 24. "PHY_ADR_PWR_RDC_DISABLE_2,Power reduction disable for address slice 2." "0,1"
newline
hexmask.long.byte 0x4 16.--20. 1. "PHY_ADR_PRBS_PATTERN_MASK_2,PRBS7 mask signal for address slice 2."
newline
hexmask.long.byte 0x4 8.--14. 1. "PHY_ADR_PRBS_PATTERN_START_2,PRBS7 start pattern for address slice 2."
newline
hexmask.long.byte 0x4 0.--6. 1. "PHY_ADR_LPBK_CONTROL_2,Loopback control bits for address slice 2."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1030,"
bitfld.long 0x8 24. "PHY_ADR_IE_MODE_2,Input enable control for address slice 2." "0,1"
newline
rbitfld.long 0x8 16.--18. "PHY_ADR_WRADDR_SHIFT_OBS_2,Observation register containing automatic half cycle and cycle shift values for address slice 2. READ-ONLY" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 8.--9. "PHY_ADR_TYPE_2,DRAM type for address slice 2." "0,1,2,3"
newline
bitfld.long 0x8 0. "PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2,Power reduction slv_dly_control block gate disable for address slice 2." "0,1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1031,"
hexmask.long 0xC 0.--26. 1. "PHY_ADR_DDL_MODE_2,DDL mode for address slice 2."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1032,"
hexmask.long.byte 0x10 0.--5. 1. "PHY_ADR_DDL_MASK_2,DDL mask for address slice 2."
rgroup.long 0x5024++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1033,"
hexmask.long 0x0 0.--31. 1. "PHY_ADR_DDL_TEST_OBS_2,Observation register containing DDL test bits for address slice 2. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1034,"
hexmask.long 0x4 0.--31. 1. "PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2,Observation register containing master DDL bits for address slice 2. READ-ONLY"
group.long 0x502C++0x17
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1035,"
hexmask.long.word 0x0 16.--26. 1. "PHY_ADR_CALVL_COARSE_DLY_2,Coarse CA training DDL increment value for address slice 2."
newline
hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_CALVL_START_2,CA training DDL start value for address slice 2."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1036,"
hexmask.long.word 0x4 0.--10. 1. "PHY_ADR_CALVL_QTR_2,CA training DDL quarter cycle delay value for address slice 2."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1037,"
hexmask.long.tbyte 0x8 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE0_2,CA training RD DQ bit swizzle map 0 for address slice 2."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1038,"
bitfld.long 0xC 24.--25. "PHY_ADR_CALVL_RANK_CTRL_2,CA training rank aggregation control bits for address slice 2." "0,1,2,3"
newline
hexmask.long.tbyte 0xC 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE1_2,CA training RD DQ bit swizzle map 1 for address slice 2."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1039,"
hexmask.long.word 0x10 16.--24. 1. "PHY_ADR_CALVL_PERIODIC_START_OFFSET_2,Relative offset to start periodic CALVL from previous result"
newline
hexmask.long.byte 0x10 8.--11. 1. "PHY_ADR_CALVL_RESP_WAIT_CNT_2,Number of samples to wait before sampling response during CA training for address slice 2."
newline
bitfld.long 0x10 0.--1. "PHY_ADR_CALVL_NUM_PATTERNS_2,Number of patterns to use during CA training for address slice 2." "0,1,2,3"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1040,"
bitfld.long 0x14 24.--26. "PHY_ADR_CALVL_OBS_SELECT_2,CA bit lane to observe result from OBS0 during CA training for address slice 2." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 16. "SC_PHY_ADR_CALVL_ERROR_CLR_2,Clears the CA training state machine error status for address slice 2. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x14 8. "SC_PHY_ADR_CALVL_DEBUG_CONT_2,Allows the CA training state machine to advance [when in debug mode] for address slice 2. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x14 0. "PHY_ADR_CALVL_DEBUG_MODE_2,Enables CA training debug mode for address slice 2. Set to 1 to enable." "0,1"
rgroup.long 0x5044++0xB
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1041,"
hexmask.long 0x0 0.--31. 1. "PHY_ADR_CALVL_OBS0_2,Observation register contains lane specific CA training bits for slice 2. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1042,"
hexmask.long 0x4 0.--31. 1. "PHY_ADR_CALVL_OBS1_2,Observation register contains general CA training bits for slice 2. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1043,"
hexmask.long 0x8 0.--31. 1. "PHY_ADR_CALVL_OBS2_2,Observation register contains periodic CA training bits for slice 2. READ-ONLY"
group.long 0x5050++0x5B
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1044,"
hexmask.long.tbyte 0x0 0.--19. 1. "PHY_ADR_CALVL_FG_0_2,CA training foreground pattern 0 for address slice 2."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1045,"
hexmask.long.tbyte 0x4 0.--19. 1. "PHY_ADR_CALVL_BG_0_2,CA training background pattern 0 for address slice 2."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1046,"
hexmask.long.tbyte 0x8 0.--19. 1. "PHY_ADR_CALVL_FG_1_2,CA training foreground pattern 1 for address slice 2."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1047,"
hexmask.long.tbyte 0xC 0.--19. 1. "PHY_ADR_CALVL_BG_1_2,CA training background pattern 1 for address slice 2."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1048,"
hexmask.long.tbyte 0x10 0.--19. 1. "PHY_ADR_CALVL_FG_2_2,CA training foreground pattern 2 for address slice 2."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1049,"
hexmask.long.tbyte 0x14 0.--19. 1. "PHY_ADR_CALVL_BG_2_2,CA training background pattern 2 for address slice 2."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1050,"
hexmask.long.tbyte 0x18 0.--19. 1. "PHY_ADR_CALVL_FG_3_2,CA training foreground pattern 3 for address slice 2."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1051,"
hexmask.long.tbyte 0x1C 0.--19. 1. "PHY_ADR_CALVL_BG_3_2,CA training background pattern 3 for address slice 2."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1052,"
hexmask.long 0x20 0.--29. 1. "PHY_ADR_ADDR_SEL_2,Selects which DFI address pins connect to which CA pins for LPDDR3/4 for address slice 2."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1053,"
hexmask.long.byte 0x24 24.--29. 1. "PHY_ADR_SEG_MASK_2,Segment mask bit for address slice 2. Set to 1 to indicate that the bit is either CA 4 or CA 9."
newline
hexmask.long.byte 0x24 16.--21. 1. "PHY_ADR_BIT_MASK_2,Mask bit for address slice 2. Set to 1 to indicate that the bit is used."
newline
hexmask.long.word 0x24 0.--9. 1. "PHY_ADR_LP4_BOOT_SLV_DELAY_2,Address slave delay setting during the LPDDR4 boot frequency operation for address slice 2."
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1054,"
hexmask.long.byte 0x28 24.--29. 1. "PHY_ADR_SW_TXIO_CTRL_2,Controls address pad output enable for address slice 2. Set to 1 to disable output enable."
newline
hexmask.long.byte 0x28 16.--19. 1. "PHY_ADR_STATIC_TOG_DISABLE_2,Toggle control during static activity for address slice 2. Set bit to dsiable toggling  bit0: Write path delay line  bit1: Read path delay line  bit2: Read data path  bit3: clk_phy  bit4: master delay line."
newline
hexmask.long.byte 0x28 8.--13. 1. "PHY_ADR_CSLVL_TRAIN_MASK_2,Mask bit for CS training participation for address slice 2. Set to 1 to indicate that the bit is participating in CS training."
newline
hexmask.long.byte 0x28 0.--5. 1. "PHY_ADR_CALVL_TRAIN_MASK_2,Mask bit for CA training participation for address slice 2. Set to 1 to indicate that the bit is participating in CA training."
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1055,"
hexmask.long.byte 0x2C 0.--5. 1. "PHY_ADR_SW_TXPWR_CTRL_2,Disable address output enables in deep sleep mode for address slice 2."
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1056,"
bitfld.long 0x30 24.--26. "PHY_PAD_ADR_RX_PCLK_CLK_SEL_2,Reserved for address slice 2." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 8.--18. 1. "PHY_PAD_ADR_IO_CFG_2,Controls I/O pads for address pad for address slice 2. Bits [10:5] = Park value  bits [4] park override  bits [2:0] clk divider."
newline
hexmask.long.byte 0x30 0.--7. 1. "PHY_ADR_TSEL_SELECT_2,Tsel select values for address slice 2."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1057,"
hexmask.long.byte 0x34 24.--28. 1. "PHY_ADR1_SW_WRADDR_SHIFT_2,Manual override of CA bit 1 of automatic half_cycle_shift/cycle_shift for address slice 2. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x34 8.--18. 1. "PHY_ADR0_CLK_WR_SLAVE_DELAY_2,CA bit 0 slave delay setting for address slice 2."
newline
hexmask.long.byte 0x34 0.--4. 1. "PHY_ADR0_SW_WRADDR_SHIFT_2,Manual override of CA bit 0 of automatic half_cycle_shift/cycle_shift for address slice 2. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1058,"
hexmask.long.byte 0x38 16.--20. 1. "PHY_ADR2_SW_WRADDR_SHIFT_2,Manual override of CA bit 2 of automatic half_cycle_shift/cycle_shift for address slice 2. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x38 0.--10. 1. "PHY_ADR1_CLK_WR_SLAVE_DELAY_2,CA bit 1 slave delay setting for address slice 2."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1059,"
hexmask.long.byte 0x3C 16.--20. 1. "PHY_ADR3_SW_WRADDR_SHIFT_2,Manual override of CA bit 3 of automatic half_cycle_shift/cycle_shift for address slice 2. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x3C 0.--10. 1. "PHY_ADR2_CLK_WR_SLAVE_DELAY_2,CA bit 2 slave delay setting for address slice 2."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1060,"
hexmask.long.byte 0x40 16.--20. 1. "PHY_ADR4_SW_WRADDR_SHIFT_2,Manual override of CA bit 4 of automatic half_cycle_shift/cycle_shift for address slice 2. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x40 0.--10. 1. "PHY_ADR3_CLK_WR_SLAVE_DELAY_2,CA bit 3 slave delay setting for address slice 2."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1061,"
hexmask.long.byte 0x44 16.--20. 1. "PHY_ADR5_SW_WRADDR_SHIFT_2,Manual override of CA bit 5 of automatic half_cycle_shift/cycle_shift for address slice 2. Bit [0] enables override of half_cycle_shift. Bit [1] is the half_cycle_shift value. Bit [2] enables override of cycle shift. Bits [4:3].."
newline
hexmask.long.word 0x44 0.--10. 1. "PHY_ADR4_CLK_WR_SLAVE_DELAY_2,CA bit 4 slave delay setting for address slice 2."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1062,"
hexmask.long.byte 0x48 16.--19. 1. "PHY_ADR_SW_MASTER_MODE_2,Master delay line override settings for address slice 2. Bit [0] enables software half clock mode. Bit [1] is the software half clock mode value. Bit [2] enables software bypass mode. Bit [3] is the software bypass mode value."
newline
hexmask.long.word 0x48 0.--10. 1. "PHY_ADR5_CLK_WR_SLAVE_DELAY_2,CA bit 5 slave delay setting for address slice 2."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1063,"
hexmask.long.byte 0x4C 24.--31. 1. "PHY_ADR_MASTER_DELAY_WAIT_2,Wait cycles for master delay line locking algorithm for address slice 2. Bits [3:0] is the cycle wait count after a calibration clock setting change. Bits [7:4] is the cycle wait count after a master delay setting change."
newline
hexmask.long.byte 0x4C 16.--21. 1. "PHY_ADR_MASTER_DELAY_STEP_2,Incremental step size for master delay line locking algorithm for address slice 2."
newline
hexmask.long.word 0x4C 0.--10. 1. "PHY_ADR_MASTER_DELAY_START_2,Start value for master delay line locking algorithm for address slice 2."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1064,"
bitfld.long 0x50 24. "PHY_ADR_SW_CALVL_DVW_MIN_EN_2,Enables the software override data valid window size during CA training for address slice 2." "0,1"
newline
hexmask.long.word 0x50 8.--17. 1. "PHY_ADR_SW_CALVL_DVW_MIN_2,Sets the software override data valid window size during CA training for address slice 2."
newline
hexmask.long.byte 0x50 0.--7. 1. "PHY_ADR_MASTER_DELAY_HALF_MEASURE_2,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle for the master in address slice 2"
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1065,"
hexmask.long.byte 0x54 0.--3. 1. "PHY_ADR_CALVL_DLY_STEP_2,Sets the delay step size plus 1 during CA training for address slice 2."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1066,"
bitfld.long 0x58 8. "PHY_ADR_MEAS_DLY_STEP_ENABLE_2,Enables delay parameter setting using phy_adr_meas_dly_step_value for address slice 2." "0,1"
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hexmask.long.byte 0x58 0.--3. 1. "PHY_ADR_CALVL_CAPTURE_CNT_2,Number of samples to take at each ADDR slave delay setting during CA training for address slice 2."
group.long 0x5400++0x23
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1280,"
bitfld.long 0x0 0.--1. "PHY_FREQ_SEL,Specifies which copy of the frequency-dependent timing parameters will be used by the PHY." "0,1,2,3"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1281,"
hexmask.long.byte 0x4 24.--28. 1. "PHY_SW_GRP0_SHIFT_0,Address slice slave delay setting for address slice 4."
newline
bitfld.long 0x4 16.--17. "PHY_FREQ_SEL_INDEX,Selects which frequency set to update when PHY_FREQ_SEL_MULTICAST_EN is not set." "0,1,2,3"
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bitfld.long 0x4 8. "PHY_FREQ_SEL_MULTICAST_EN,When set  a register write will update parameters for all frequency sets simultaneously. Set to 1 to enable." "0,1"
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bitfld.long 0x4 0. "PHY_FREQ_SEL_FROM_REGIF,Indicates which source is used to select the frequency copy. When set to 1  the frequency select source is given by parameter PHY_FREQ_SEL from register I/F. When cleared to 0  the frequency select source is the PHY input signal.." "0,1"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1282,"
hexmask.long.byte 0x8 24.--28. 1. "PHY_SW_GRP0_SHIFT_1,Address slice slave delay setting for address slice 4."
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hexmask.long.byte 0x8 16.--20. 1. "PHY_SW_GRP3_SHIFT_0,Address slice slave delay setting for address slice 4."
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hexmask.long.byte 0x8 8.--12. 1. "PHY_SW_GRP2_SHIFT_0,Address slice slave delay setting for address slice 4."
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hexmask.long.byte 0x8 0.--4. 1. "PHY_SW_GRP1_SHIFT_0,Address slice slave delay setting for address slice 4."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1283,"
hexmask.long.byte 0xC 24.--28. 1. "PHY_SW_GRP0_SHIFT_2,Address slice slave delay setting for address slice 4."
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hexmask.long.byte 0xC 16.--20. 1. "PHY_SW_GRP3_SHIFT_1,Address slice slave delay setting for address slice 4."
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hexmask.long.byte 0xC 8.--12. 1. "PHY_SW_GRP2_SHIFT_1,Address slice slave delay setting for address slice 4."
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hexmask.long.byte 0xC 0.--4. 1. "PHY_SW_GRP1_SHIFT_1,Address slice slave delay setting for address slice 4."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1284,"
hexmask.long.byte 0x10 24.--28. 1. "PHY_SW_GRP0_SHIFT_3,Address slice slave delay setting for address slice 4."
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hexmask.long.byte 0x10 16.--20. 1. "PHY_SW_GRP3_SHIFT_2,Address slice slave delay setting for address slice 4."
newline
hexmask.long.byte 0x10 8.--12. 1. "PHY_SW_GRP2_SHIFT_2,Address slice slave delay setting for address slice 4."
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hexmask.long.byte 0x10 0.--4. 1. "PHY_SW_GRP1_SHIFT_2,Address slice slave delay setting for address slice 4."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1285,"
hexmask.long.byte 0x14 16.--20. 1. "PHY_SW_GRP3_SHIFT_3,Address slice slave delay setting for address slice 4."
newline
hexmask.long.byte 0x14 8.--12. 1. "PHY_SW_GRP2_SHIFT_3,Address slice slave delay setting for address slice 4."
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hexmask.long.byte 0x14 0.--4. 1. "PHY_SW_GRP1_SHIFT_3,Address slice slave delay setting for address slice 4."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1286,"
bitfld.long 0x18 24. "PHY_GRP_BYPASS_OVERRIDE,Address/control group slice bypass mode override setting." "0,1"
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hexmask.long.byte 0x18 16.--20. 1. "PHY_SW_GRP_BYPASS_SHIFT,Address/control group slice bypass mode shift settings."
newline
hexmask.long.word 0x18 0.--10. 1. "PHY_GRP_BYPASS_SLAVE_DELAY,Address/control group slice bypass mode slave delay setting."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1287,"
hexmask.long.word 0x1C 16.--26. 1. "PHY_CSLVL_START,Defines the CS training DDL start value."
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bitfld.long 0x1C 8. "PHY_MANUAL_UPDATE_PHYUPD_ENABLE,Manual update selection of all slave delay line settings. Set 1 to assert phyupd_req and wait phyupd_ack to update delay line  set 0 to update delay line directly." "0,1"
newline
bitfld.long 0x1C 0. "SC_PHY_MANUAL_UPDATE,Manual update of all slave delay line settings. Set to 1 to trigger. WRITE-ONLY" "0,1"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1288,"
bitfld.long 0x20 24. "SC_PHY_CSLVL_DEBUG_CONT,Allows the CS training state machine to advance [when in debug mode]. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x20 16. "PHY_CSLVL_DEBUG_MODE,Enables CS training debug mode. Set to 1 to enable." "0,1"
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hexmask.long.word 0x20 0.--10. 1. "PHY_CSLVL_COARSE_DLY,Defines the CS training DDL coarse cycle delay value."
wgroup.long 0x5424++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1289,"
bitfld.long 0x0 0. "SC_PHY_CSLVL_ERROR_CLR,Clears the CS training state machine error status. Set to 1 to trigger. WRITE-ONLY" "0,1"
rgroup.long 0x5428++0xB
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1290,"
hexmask.long 0x0 0.--31. 1. "PHY_CSLVL_OBS0,Observation register for CS training delay values. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1291,"
hexmask.long 0x4 0.--31. 1. "PHY_CSLVL_OBS1,Observation register for CS training algorithm status. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1292,"
hexmask.long 0x8 0.--31. 1. "PHY_CSLVL_OBS2,Observation register for periodic CS training delay values. READ-ONLY"
group.long 0x5434++0x27
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1293,"
bitfld.long 0x0 24. "PHY_LP4_BOOT_DISABLE,Controls the handling of the DFI frequency. When set to 1  DFI frequency 0 is considered the first operational frequency. When cleared to 0  DFI frequency 0 is the boot frequency and other DFI frequency values are operational.." "0,1"
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hexmask.long.word 0x0 8.--16. 1. "PHY_CSLVL_PERIODIC_START_OFFSET,Defines the relative offset from previous LE and TE to start periodic CSLVL with."
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bitfld.long 0x0 0. "PHY_CSLVL_ENABLE,CS training enable. Set to 1 to enable CS training during CA training." "0,1"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1294,"
hexmask.long.word 0x4 8.--18. 1. "PHY_CSLVL_QTR,Defines the CS training DDL 1/4 cycle delay value."
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bitfld.long 0x4 0.--1. "PHY_CSLVL_CS_MAP,CS training map. Set each CS bit to 1 to allow that CS to participate in CS training results. NOT CURRENTLY USED." "0,1,2,3"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1295,"
bitfld.long 0x8 24.--26. "PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE,Reserved for the address/control master." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 16.--19. 1. "PHY_CSLVL_COARSE_CAPTURE_CNT,Defines the number of samples to take at each GRP slave delay setting during CS training coarse CA training."
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hexmask.long.word 0x8 0.--10. 1. "PHY_CSLVL_COARSE_CHK,Defines the CS training coarse CA training DDL 1/16th cycle delay value."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1296,"
bitfld.long 0xC 24. "PHY_LP4_ACTIVE,Indicates an LPDDR4 device is connected to the PHY." "0,1"
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bitfld.long 0xC 16. "PHY_ADRCTL_LPDDR,Adds a cycle of delay for the address/control slices to match the address slice." "0,1"
newline
bitfld.long 0xC 8.--9. "PHY_DFI_PHYUPD_TYPE,Defines the value of the dfi_phyupd_type output signal to MC." "0,1,2,3"
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bitfld.long 0xC 0. "PHY_ADRCTL_SNAP_OBS_REGS,Initiates a snapshot of the internal observation registers for the address/control block. Set to 1 to trigger. WRITE-ONLY" "0,1"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1297,"
hexmask.long.byte 0x10 24.--27. 1. "PHY_SW_TXIO_CTRL_0,This register is used to control if command pad [CS/RAS...] should be shutoff for TX mode."
newline
bitfld.long 0x10 16. "PHY_CONTINUOUS_CLK_CAL_UPDATE,Continuous update of all latest PVTP PVTN and PVTR values to the CLK IO pads. Set to 1 to keep this enabled." "0,1"
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bitfld.long 0x10 8. "SC_PHY_UPDATE_CLK_CAL_VALUES,Manual update of all latest PVTP PVTN and PVTR values to the CLK IO pads. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x10 0. "PHY_LPDDR3_CS,Alters reset state polarity for LPDDR chip selects." "0,1"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1298,"
bitfld.long 0x14 24. "PHY_MEMCLK_SW_TXIO_CTRL,This register is used to control if clk pads should be shutoff for TX mode." "0,1"
newline
hexmask.long.byte 0x14 16.--19. 1. "PHY_SW_TXIO_CTRL_3,This register is used to control if command pad [CS/RAS...] should be shutoff for TX mode."
newline
hexmask.long.byte 0x14 8.--11. 1. "PHY_SW_TXIO_CTRL_2,This register is used to control if command pad [CS/RAS...] should be shutoff for TX mode."
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hexmask.long.byte 0x14 0.--3. 1. "PHY_SW_TXIO_CTRL_1,This register is used to control if command pad [CS/RAS...] should be shutoff for TX mode."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1299,"
hexmask.long.byte 0x18 24.--27. 1. "PHY_ADRCTL_SW_TXPWR_CTRL_3,This register is used to control if address/command pad [address/CS/RAS...] should be shutoff for TX mode in deep sleep mode."
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hexmask.long.byte 0x18 16.--19. 1. "PHY_ADRCTL_SW_TXPWR_CTRL_2,This register is used to control if address/command pad [address/CS/RAS...] should be shutoff for TX mode in deep sleep mode."
newline
hexmask.long.byte 0x18 8.--11. 1. "PHY_ADRCTL_SW_TXPWR_CTRL_1,This register is used to control if address/command pad [address/CS/RAS...] should be shutoff for TX mode in deep sleep mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "PHY_ADRCTL_SW_TXPWR_CTRL_0,This register is used to control if address/command pad [address/CS/RAS...] should be shutoff for TX mode in deep sleep mode."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1300,"
bitfld.long 0x1C 16. "PHY_BYTE_DISABLE_STATIC_TOG_DISABLE,Control to disable the toggle signal for data slice during static activity when dfi_data_byte_disable is asserted." "0,1"
newline
bitfld.long 0x1C 8. "PHY_TOP_STATIC_TOG_DISABLE,Disables the generation of the toggle for static clock based paths in the PHY to prevent assymetric aging." "0,1"
newline
bitfld.long 0x1C 0. "PHY_MEMCLK_SW_TXPWR_CTRL,This register is used to control if clk pads should be shutoff for TX mode in deep sleep mode." "0,1"
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1301,"
bitfld.long 0x20 24. "PHY_MEMCLK_STATIC_TOG_DISABLE,Control to disable toggle during static activity. bit0: clock disable." "0,1"
newline
hexmask.long.byte 0x20 16.--19. 1. "PHY_ADRCTL_STATIC_TOG_DISABLE,Control to disable toggle during static activity. bit0: Write path delay line disable; bit1: clock disable; bit2: adrctl master delay line disable [if exists]; bit3: adrctl misc core clk disable.[if exists]"
newline
hexmask.long.word 0x20 0.--15. 1. "PHY_STATIC_TOG_CONTROL,Clock divider to create toggle signal. Use long counter as the base."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1302,"
bitfld.long 0x24 0. "PHY_LP4_BOOT_PLL_BYPASS,PHY clock PLL bypass select." "0,1"
rgroup.long 0x545C++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1303,"
hexmask.long 0x0 0.--31. 1. "PHY_CLK_SWITCH_OBS,Observation register for Clock switch state machine READ-ONLY"
group.long 0x5460++0x23
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1304,"
hexmask.long.word 0x0 0.--15. 1. "PHY_PLL_WAIT,PHY clock PLL wait time after locking."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1305,"
bitfld.long 0x4 0. "PHY_SW_PLL_BYPASS,PHY clock PLL bypass select." "0,1"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1306,"
hexmask.long.byte 0x8 24.--27. 1. "PHY_SET_DFI_INPUT_3,Used to indicate the default value of the adrctl slice bits."
newline
hexmask.long.byte 0x8 16.--19. 1. "PHY_SET_DFI_INPUT_2,Used to indicate the default value of the adrctl slice bits."
newline
hexmask.long.byte 0x8 8.--11. 1. "PHY_SET_DFI_INPUT_1,Used to indicate the default value of the adrctl slice bits."
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hexmask.long.byte 0x8 0.--3. 1. "PHY_SET_DFI_INPUT_0,Used to indicate the default value of the adrctl slice bits."
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1307,"
bitfld.long 0xC 24.--25. "PHY_CS_ACS_ALLOCATION_BIT3_0,The map for which chip select is associated with each bit in the adrctl slice 0. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_0 bit3  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_0  if.." "0,1,2,3"
newline
bitfld.long 0xC 16.--17. "PHY_CS_ACS_ALLOCATION_BIT2_0,The map for which chip select is associated with each bit in the adrctl slice 0. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_0 bit2   0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_0 .." "0,1,2,3"
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bitfld.long 0xC 8.--9. "PHY_CS_ACS_ALLOCATION_BIT1_0,The map for which chip select is associated with each bit in the adrctl slice 0. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_0 bit1  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_0  if.." "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "PHY_CS_ACS_ALLOCATION_BIT0_0,The map for which chip select is associated with each bit in the adrctl slice 0. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_0 bit0  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_0  if.." "0,1,2,3"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1308,"
bitfld.long 0x10 24.--25. "PHY_CS_ACS_ALLOCATION_BIT3_1,The map for which chip select is associated with each bit in the adrctl slice 1. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_1 bit3  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_1  if.." "0,1,2,3"
newline
bitfld.long 0x10 16.--17. "PHY_CS_ACS_ALLOCATION_BIT2_1,The map for which chip select is associated with each bit in the adrctl slice 1. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_1 bit2   0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_1 .." "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "PHY_CS_ACS_ALLOCATION_BIT1_1,The map for which chip select is associated with each bit in the adrctl slice 1. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_1 bit1  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_1  if.." "0,1,2,3"
newline
bitfld.long 0x10 0.--1. "PHY_CS_ACS_ALLOCATION_BIT0_1,The map for which chip select is associated with each bit in the adrctl slice 1. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_1 bit0  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_1  if.." "0,1,2,3"
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1309,"
bitfld.long 0x14 24.--25. "PHY_CS_ACS_ALLOCATION_BIT3_2,The map for which chip select is associated with each bit in the adrctl slice 2. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_2 bit3  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_2  if.." "0,1,2,3"
newline
bitfld.long 0x14 16.--17. "PHY_CS_ACS_ALLOCATION_BIT2_2,The map for which chip select is associated with each bit in the adrctl slice 2. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_2 bit2   0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_2 .." "0,1,2,3"
newline
bitfld.long 0x14 8.--9. "PHY_CS_ACS_ALLOCATION_BIT1_2,The map for which chip select is associated with each bit in the adrctl slice 2. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_2 bit1  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_2  if.." "0,1,2,3"
newline
bitfld.long 0x14 0.--1. "PHY_CS_ACS_ALLOCATION_BIT0_2,The map for which chip select is associated with each bit in the adrctl slice 2. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_2 bit0  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_2  if.." "0,1,2,3"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1310,"
bitfld.long 0x18 24.--25. "PHY_CS_ACS_ALLOCATION_BIT3_3,The map for which chip select is associated with each bit in the adrctl slice 3. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_3 bit3  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_3  if.." "0,1,2,3"
newline
bitfld.long 0x18 16.--17. "PHY_CS_ACS_ALLOCATION_BIT2_3,The map for which chip select is associated with each bit in the adrctl slice 3. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_3 bit2   0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_3 .." "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "PHY_CS_ACS_ALLOCATION_BIT1_3,The map for which chip select is associated with each bit in the adrctl slice 3. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_3 bit1  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_3  if.." "0,1,2,3"
newline
bitfld.long 0x18 0.--1. "PHY_CS_ACS_ALLOCATION_BIT0_3,The map for which chip select is associated with each bit in the adrctl slice 3. Bit [n]  1 means cs[n]'s signal[CS/CKE/ODT/RST] is allocated on ACS_3 bit0  0 means cs[n]'s signal[CS/CKE/ODT/RST] is not tranfser on ACS_3  if.." "0,1,2,3"
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1311,"
hexmask.long.word 0x1C 16.--31. 1. "PHY_PLL_CTRL_OVERRIDE,Individual PHY clock PLL control overrides."
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hexmask.long.word 0x1C 0.--12. 1. "PHY_LP4_BOOT_PLL_CTRL,PHY deskew PLL controls for LPDDR4 boot frequency."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1312,"
bitfld.long 0x20 16.--17. "SC_PHY_PLL_SPO_CAL_SNAP_OBS,Register command to take a snapshot of PLL output. WRITE-ONLY" "0,1,2,3"
newline
hexmask.long.byte 0x20 8.--15. 1. "PHY_PLL_SPO_CAL_CTRL,PLL SPO Cal controls."
newline
bitfld.long 0x20 0. "PHY_USE_PLL_DSKEWCALLOCK,Use DSKEWCALLOCK or not." "0,1"
rgroup.long 0x5484++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1313,"
hexmask.long.word 0x0 0.--15. 1. "PHY_PLL_OBS_0,PHY TOP level clock PLL_0 observe values. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1314,"
hexmask.long.tbyte 0x4 0.--16. 1. "PHY_PLL_SPO_CAL_OBS_0,PHY TOP level PLL_0 SPO Cal observe values. READ-ONLY"
group.long 0x548C++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1315,"
hexmask.long.word 0x0 16.--27. 1. "PHY_LP4_BOOT_PLL_DESKEWCALIN_0,PHY TOP level PLL_0 lpddr4 boot deskewcal in values."
newline
hexmask.long.word 0x0 0.--11. 1. "PHY_PLL_DESKEWCALIN_0,PHY TOP level PLL_0 deskewcal in values."
rgroup.long 0x5490++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1316,"
hexmask.long.word 0x0 0.--15. 1. "PHY_PLL_OBS_1,PHY TOP level clock PLL_1 observe values. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1317,"
hexmask.long.tbyte 0x4 0.--16. 1. "PHY_PLL_SPO_CAL_OBS_1,PHY TOP level PLL_1 SPO Cal observe values. READ-ONLY"
group.long 0x5498++0x47
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1318,"
hexmask.long.word 0x0 16.--27. 1. "PHY_LP4_BOOT_PLL_DESKEWCALIN_1,PHY TOP level PLL_1 lpddr4 boot deskewcal in values."
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hexmask.long.word 0x0 0.--11. 1. "PHY_PLL_DESKEWCALIN_1,PHY TOP level PLL_1 deskewcal in values."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1319,"
hexmask.long.byte 0x4 24.--31. 1. "PHY_LP_WAKEUP,Specifies the number of cycles the PHY takes to wakeup in low power mode."
newline
hexmask.long.byte 0x4 16.--19. 1. "PHY_TCKSRE_WAIT,Specifies the number of cycles the PHY should wait before turning off the PLL for a deep sleep or DFS event."
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bitfld.long 0x4 8. "PHY_LP4_BOOT_LOW_FREQ_SEL,Control the PLL domain enter/exit from the negative clock edge for LPDDR4 boot frequency." "0,1"
newline
bitfld.long 0x4 0. "PHY_PLL_REFOUT_SEL,PHY PLL refout select." "0,1"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1320,"
hexmask.long.word 0x8 8.--17. 1. "PHY_LP_CTRLUPD_CNTR_CFG,Specifies the number of cycles the PHY takes from light sleep req deassert to ack deassert in low power mode."
newline
bitfld.long 0x8 0. "PHY_LS_IDLE_EN,Indicates the Reduced Idle Power State is enabled in low power mode." "0,1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1321,"
bitfld.long 0xC 24. "PHY_TDFI_PHY_WRDELAY,DFI timing parameter TDFI_PHY_WRDELAY." "0,1"
newline
hexmask.long.tbyte 0xC 0.--16. 1. "PHY_DS_EXIT_CTRL,Controls to reduce the deep sleep exit latency  when bit 16 is 1 deep sleep exit ack won't wait master delay line lock."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1322,"
hexmask.long.tbyte 0x10 0.--17. 1. "PHY_PAD_FDBK_TERM,Controls term settings for gate feedback pads."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1323,"
hexmask.long.tbyte 0x14 0.--16. 1. "PHY_PAD_DATA_TERM,Controls term settings for data pads."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1324,"
hexmask.long.tbyte 0x18 0.--16. 1. "PHY_PAD_DQS_TERM,Controls term settings for dqs pads."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1325,"
hexmask.long.tbyte 0x1C 0.--17. 1. "PHY_PAD_ADDR_TERM,Controls term settings for the address/control pads."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1326,"
hexmask.long.tbyte 0x20 0.--17. 1. "PHY_PAD_CLK_TERM,Controls term settings for clock pads."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1327,"
hexmask.long.tbyte 0x24 0.--17. 1. "PHY_PAD_ERR_TERM,Controls term settings for error pads."
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1328,"
hexmask.long.tbyte 0x28 0.--17. 1. "PHY_PAD_CKE_TERM,Controls term settings for cke pads."
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1329,"
hexmask.long.tbyte 0x2C 0.--17. 1. "PHY_PAD_RST_TERM,Controls term settings for reset_n pads."
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1330,"
hexmask.long.tbyte 0x30 0.--17. 1. "PHY_PAD_CS_TERM,Controls term settings for cs pads."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1331,"
hexmask.long.tbyte 0x34 0.--17. 1. "PHY_PAD_ODT_TERM,Controls term settings for odt pads."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1332,"
hexmask.long.word 0x38 16.--28. 1. "PHY_ADRCTL_LP3_RX_CAL,PHY CKE/RESET_N RX calibration controls."
newline
hexmask.long.word 0x38 0.--9. 1. "PHY_ADRCTL_RX_CAL,PHY address/control RX calibration controls."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1333,"
bitfld.long 0x3C 24. "PHY_CAL_START_0,Manual start for the pad calibration state machine for block 0. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
bitfld.long 0x3C 16. "PHY_CAL_CLEAR_0,Clear the pad calibration state machine and results for block 0. Set to 1 to trigger. WRITE-ONLY" "0,1"
newline
hexmask.long.word 0x3C 0.--12. 1. "PHY_CAL_MODE_0,Pad calibration mode bits for block 0. Bit [0] disables pad calibration upon initialization. Bit [1] enables automatic interval based calibration. Bits [3:2] set the base interval for the interval counter. Bits [7:4] are direct connections.."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1334,"
hexmask.long 0x40 0.--31. 1. "PHY_CAL_INTERVAL_COUNT_0,Pad calibration interval counter compare value for block 0."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1335,"
bitfld.long 0x44 8.--10. "PHY_LP4_BOOT_CAL_CLK_SELECT_0,Pad calibration pad clock frequency select setting for LPDDR4 boot frequency for block 0." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x44 0.--7. 1. "PHY_CAL_SAMPLE_WAIT_0,Pad calibration state machine wait count in pad clock cycles for block 0."
rgroup.long 0x54E0++0x13
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1336,"
hexmask.long.tbyte 0x0 0.--23. 1. "PHY_CAL_RESULT_OBS_0,Pad calibration results observation values for block 0. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1337,"
hexmask.long.tbyte 0x4 0.--23. 1. "PHY_CAL_RESULT2_OBS_0,Pad calibration results [CKE/RESET_N] observation values for block 0. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1338,"
hexmask.long.tbyte 0x8 0.--23. 1. "PHY_CAL_RESULT4_OBS_0,Pad calibration pass1 shadow results observation values for block 0. READ-ONLY"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1339,"
hexmask.long.tbyte 0xC 0.--23. 1. "PHY_CAL_RESULT5_OBS_0,Pad calibration pass2 shadow results observation values for block 0. READ-ONLY"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1340,"
hexmask.long.tbyte 0x10 0.--23. 1. "PHY_CAL_RESULT6_OBS_0,Pad calibration internal results observation delta values for block 0. READ-ONLY"
group.long 0x54F4++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1341,"
hexmask.long.byte 0x0 24.--30. 1. "PHY_CAL_CPTR_CNT_0,defines sample capture number in pad calibration process"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "PHY_CAL_RESULT7_OBS_0,Pad calibration internal results observation delta values for block 0. READ-ONLY"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1342,"
bitfld.long 0x4 24. "PHY_CAL_DBG_CFG_0,defines debug configuration in pad calibration process" "0,1"
newline
hexmask.long.byte 0x4 16.--23. 1. "PHY_CAL_RCV_FINE_ADJ_0,defines adjustment for RCV code in pad calibration process"
newline
hexmask.long.byte 0x4 8.--15. 1. "PHY_CAL_PD_FINE_ADJ_0,defines adjustment for PD code in pad calibration process"
newline
hexmask.long.byte 0x4 0.--7. 1. "PHY_CAL_PU_FINE_ADJ_0,defines adjustment for PU code in pad calibration process"
wgroup.long 0x54FC++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1343,"
bitfld.long 0x0 0. "SC_PHY_PAD_DBG_CONT_0,Allows the pad calibration state machine to advance [when in debug mode] for slice 0. Set to 1 to trigger. WRITE-ONLY" "0,1"
rgroup.long 0x5500++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1344,"
hexmask.long 0x0 0.--31. 1. "PHY_CAL_RESULT3_OBS_0,Pad calibration results first/last0/1 observation values for block 0. READ-ONLY"
group.long 0x5504++0x27
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1345,"
hexmask.long.tbyte 0x0 8.--27. 1. "PHY_CAL_SLOPE_ADJ_0,defines slope configure in pad calibration process"
newline
hexmask.long.byte 0x0 0.--7. 1. "PHY_ADRCTL_PVT_MAP_0,defines slope configure in pad calibration process"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1346,"
hexmask.long.tbyte 0x4 0.--19. 1. "PHY_CAL_SLOPE_ADJ_PASS2_0,defines slope configure for pass2 in pad calibration process"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1347,"
hexmask.long 0x8 0.--24. 1. "PHY_CAL_TWO_PASS_CFG_0,defines cal_en configure in pad calibration process"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1348,"
hexmask.long.byte 0xC 24.--29. 1. "PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0,Pad calibration pass1 pu results won't update if out of max delta range ."
newline
hexmask.long.tbyte 0xC 0.--22. 1. "PHY_CAL_SW_CAL_CFG_0,defines firmware based pad calibration process"
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1349,"
hexmask.long.byte 0x10 24.--29. 1. "PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0,Pad calibration pass2 pd results won't update if out of max delta range ."
newline
hexmask.long.byte 0x10 16.--21. 1. "PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0,Pad calibration pass2 pu results won't update if out of max delta range ."
newline
hexmask.long.byte 0x10 8.--12. 1. "PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0,Pad calibration pass1 rx results won't update if out of max delta range ."
newline
hexmask.long.byte 0x10 0.--5. 1. "PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0,Pad calibration pass1 pd results won't update if out of max delta range ."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1350,"
hexmask.long.byte 0x14 24.--28. 1. "PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0,Pad calibration pass1 rx results won't update if out of min delta range ."
newline
hexmask.long.byte 0x14 16.--21. 1. "PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0,Pad calibration pass1 pd results won't update if out of min delta range ."
newline
hexmask.long.byte 0x14 8.--13. 1. "PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0,Pad calibration pass1 pu results won't update if out of min delta range ."
newline
hexmask.long.byte 0x14 0.--4. 1. "PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0,Pad calibration pass2 rx results won't update if out of max delta range ."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1351,"
hexmask.long.byte 0x18 16.--20. 1. "PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0,Pad calibration pass2 rx results won't update if out of min delta range ."
newline
hexmask.long.byte 0x18 8.--13. 1. "PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0,Pad calibration pass2 pd results won't update if out of min delta range ."
newline
hexmask.long.byte 0x18 0.--5. 1. "PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0,Pad calibration pass2 pu results won't update if out of min delta range ."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1352,"
bitfld.long 0x1C 24. "PHY_AC_LPBK_ERR_CLEAR,Address/control loopback error clear. Set to 1 to clear error. WRITE-ONLY" "0,1"
newline
bitfld.long 0x1C 16. "PHY_ADRCTL_MANUAL_UPDATE,Address/control manual update of slave delay lines. Set to 1 to update. WRITE-ONLY" "0,1"
newline
hexmask.long.word 0x1C 0.--15. 1. "PHY_PAD_ATB_CTRL,Pad ATB control settings. Bit [0] is the enable signal. Bits [5:1] are the ATB data signals. Bits [15:8] are the 1 hot select for which pad is selected."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1353,"
hexmask.long.word 0x20 16.--24. 1. "PHY_AC_LPBK_CONTROL,Address/control slice loopback control setting."
newline
hexmask.long.byte 0x20 8.--11. 1. "PHY_AC_LPBK_ENABLE,Loopback enable for the address/control slices."
newline
bitfld.long 0x20 0.--1. "PHY_AC_LPBK_OBS_SELECT,Select value to map an individual loopback address/control slice observation register to the global observation register." "0,1,2,3"
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1354,"
hexmask.long.byte 0x24 8.--11. 1. "PHY_AC_PRBS_PATTERN_MASK,PRBS7 mask signal for address/control slice."
newline
hexmask.long.byte 0x24 0.--6. 1. "PHY_AC_PRBS_PATTERN_START,PRBS7 start pattern for address/control slice."
rgroup.long 0x552C++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1355,"
hexmask.long 0x0 0.--31. 1. "PHY_AC_LPBK_RESULT_OBS,Observation register for the loopback address/control slices. READ-ONLY"
group.long 0x5530++0x27
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1356,"
hexmask.long.byte 0x0 16.--21. 1. "PHY_AC_CLK_LPBK_CONTROL,Mem clk block loopback control setting."
newline
bitfld.long 0x0 8. "PHY_AC_CLK_LPBK_ENABLE,Loopback enable for mem clk blocks." "0,1"
newline
bitfld.long 0x0 0. "PHY_AC_CLK_LPBK_OBS_SELECT,Select value to map an individual loopback mem clk block observation register to the global observation register." "0,1"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1357,"
bitfld.long 0x4 24. "PHY_TOP_PWR_RDC_DISABLE,top param power reduction disable." "0,1"
newline
bitfld.long 0x4 16. "PHY_AC_PWR_RDC_DISABLE,ac slice power reduction disable." "0,1"
newline
hexmask.long.word 0x4 0.--15. 1. "PHY_AC_CLK_LPBK_RESULT_OBS,Observation register for loopback mem clk blocks. READ-ONLY"
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1358,"
bitfld.long 0x8 0. "PHY_AC_SLV_DLY_CTRL_GATE_DISABLE,ac slice slv_dly_control block power reduction disable." "0,1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1359,"
hexmask.long 0xC 0.--31. 1. "PHY_DATA_BYTE_ORDER_SEL,Used to define the data slice's byte swap for CA bits 7:0."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1360,"
bitfld.long 0x10 24.--25. "PHY_ADRCTL_MSTR_DLY_ENC_SEL_0,Select adrctl_mstr_dly_enc for the address/control slice 0 ." "0,1,2,3"
newline
bitfld.long 0x10 16.--18. "PHY_ADR_DISABLE,Disable the unused adr slice to save power." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 8.--12. 1. "PHY_CALVL_DEVICE_MAP,Define which device's DQ feedback data bits should be used during CA training"
newline
hexmask.long.byte 0x10 0.--7. 1. "PHY_DATA_BYTE_ORDER_SEL_HIGH,Used to define the data slice's byte swap for CA bits 9:8."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1361,"
bitfld.long 0x14 16.--17. "PHY_ADRCTL_MSTR_DLY_ENC_SEL_3,Select adrctl_mstr_dly_enc for the address/control slice 3 ." "0,1,2,3"
newline
bitfld.long 0x14 8.--9. "PHY_ADRCTL_MSTR_DLY_ENC_SEL_2,Select adrctl_mstr_dly_enc for the address/control slice 2 ." "0,1,2,3"
newline
bitfld.long 0x14 0.--1. "PHY_ADRCTL_MSTR_DLY_ENC_SEL_1,Select adrctl_mstr_dly_enc for the address/control slice 1 ." "0,1,2,3"
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1362,"
hexmask.long 0x18 0.--31. 1. "PHY_DDL_AC_ENABLE,PHY Address/Control DDL BIST mode enable."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1363,"
hexmask.long 0x1C 0.--25. 1. "PHY_DDL_AC_MODE,PHY Address/Control DDL BIST mode."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1364,"
hexmask.long.byte 0x20 16.--23. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_AC,Specify threshold value for PHY init update tracking for AC slice."
newline
bitfld.long 0x20 8.--10. "PHY_INIT_UPDATE_CONFIG,PHY init update function configuration." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x20 0.--5. 1. "PHY_DDL_AC_MASK,PHY Address/Control DDL BIST mask."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1365,"
bitfld.long 0x24 24.--26. "PHY_ERR_STATUS,PHY ERROR information." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24 16.--18. "PHY_ERR_MASK_EN,PHY ERROR information report mask enable." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 0.--15. 1. "PHY_CA_PARITY_ERR_PULSE_MIN,PHY alert_n pulse width minimux value for CA parity error."
rgroup.long 0x5558++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1366,"
hexmask.long 0x0 0.--31. 1. "PHY_DS0_DQS_ERR_COUNTER,PHY DATA SLICE 0 DQS ERROR counter."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1367,"
hexmask.long 0x4 0.--31. 1. "PHY_DS1_DQS_ERR_COUNTER,PHY DATA SLICE 1 DQS ERROR counter."
group.long 0x5560++0x7
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1368,"
rbitfld.long 0x0 24.--25. "PHY_DS_INIT_COMPLETE_OBS,Observation register for dfi_init_complete for data slice. Bit0 is for data_slice0; bit1 is for data_slice 1 ... READ-ONLY." "0,1,2,3"
newline
hexmask.long.word 0x0 8.--19. 1. "PHY_AC_INIT_COMPLETE_OBS,Observation register for dfi_init_complete for adr and ac slice. Bit 0 is for dfi_init_complete for all slices. Bit[7:4] is for adr slice  bit4 is adr_slice0...  if the adr slice number is 3  bit7 is 0. Bit8 is for ac_slice0;.."
newline
bitfld.long 0x0 0.--1. "PHY_DLL_RST_EN,PHY DDL reset software interface enable." "0,1,2,3"
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1369,"
hexmask.long.byte 0x4 24.--27. 1. "PHY_GRP_SHIFT_OBS_SELECT,Select value to map an individual address/control group slice automatic cycle/half_cycle shift settings to the observation register."
newline
hexmask.long.byte 0x4 16.--20. 1. "PHY_GRP_SLV_DLY_ENC_OBS_SELECT,Select value to map an individual address/control group slice slave delay to the encoded value observation register."
newline
bitfld.long 0x4 8. "PHY_ERR_IE,Control the IE signal of IO error pad." "0,1"
newline
bitfld.long 0x4 0. "PHY_UPDATE_MASK,Control to disable the generation of dfi_phyupd_req and use of dfi_ctrlupd_req. If this is 0 the PHY is normal mode; if this is 1  the PHY will not respond to dfi_ctrlupd_req or not to send dfi_phyupd_req" "0,1"
rgroup.long 0x5568++0x3
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1370,"
bitfld.long 0x0 16.--18. "PHY_GRP_SHIFT_OBS,Observation register for the address/control group automatic half cycle and cycle shift values. READ-ONLY" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--10. 1. "PHY_GRP_SLV_DLY_ENC_OBS,Observation register for all address/control group slice slave delay encoded values. READ-ONLY"
group.long 0x556C++0x8B
line.long 0x0 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1371,"
hexmask.long.tbyte 0x0 0.--17. 1. "PHY_PAD_CAL_IO_CFG_0,Pad calibration Controls PCLK/PARK pin and vref switch."
line.long 0x4 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1372,"
bitfld.long 0x4 16.--18. "PHY_PAD_ACS_RX_PCLK_CLK_SEL,Controls rx_pclk clk selection for acs pad." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x4 0.--15. 1. "PHY_PAD_ACS_IO_CFG,Controls PCLK/PARK pin for acs pad."
line.long 0x8 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1373,"
bitfld.long 0x8 0. "PHY_PLL_BYPASS,PHY clock PLL bypass select." "0,1"
line.long 0xC "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1374,"
bitfld.long 0xC 16. "PHY_LOW_FREQ_SEL,Enables the PHY to enter/exit the PLL domain from the negative clock edge. Set to 1 at low frequencies to enable." "0,1"
newline
hexmask.long.word 0xC 0.--12. 1. "PHY_PLL_CTRL,PHY clock PLL controls."
line.long 0x10 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1375,"
hexmask.long.byte 0x10 24.--27. 1. "PHY_CSLVL_DLY_STEP,Sets the delay step size plus 1 during CS training."
newline
hexmask.long.byte 0x10 16.--19. 1. "PHY_CSLVL_CAPTURE_CNT,Defines the number of samples to take at each GRP slave delay setting during CS training."
newline
hexmask.long.word 0x10 0.--11. 1. "PHY_PAD_VREF_CTRL_AC,Pad VREF control settings for the address/control."
line.long 0x14 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1376,"
bitfld.long 0x14 24. "PHY_LVL_MEAS_DLY_STEP_ENABLE,Enables the phy_adr_meas_dly_step_value to be used instead of the phy_cslvl_dly_step parameter." "0,1"
newline
bitfld.long 0x14 16. "PHY_SW_CSLVL_DVW_MIN_EN,Enables the software override data valid window size during CS training." "0,1"
newline
hexmask.long.word 0x14 0.--9. 1. "PHY_SW_CSLVL_DVW_MIN,Sets the software override data valid window size during CS training."
line.long 0x18 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1377,"
hexmask.long.word 0x18 16.--26. 1. "PHY_GRP1_SLAVE_DELAY_0,Address slice slave delay setting for address slice 1."
newline
hexmask.long.word 0x18 0.--10. 1. "PHY_GRP0_SLAVE_DELAY_0,Address slice slave delay setting for address slice 0."
line.long 0x1C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1378,"
hexmask.long.word 0x1C 16.--26. 1. "PHY_GRP3_SLAVE_DELAY_0,Address slice slave delay setting for address slice 3."
newline
hexmask.long.word 0x1C 0.--10. 1. "PHY_GRP2_SLAVE_DELAY_0,Address slice slave delay setting for address slice 2."
line.long 0x20 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1379,"
hexmask.long.word 0x20 16.--26. 1. "PHY_GRP1_SLAVE_DELAY_1,Address slice slave delay setting for address slice 1."
newline
hexmask.long.word 0x20 0.--10. 1. "PHY_GRP0_SLAVE_DELAY_1,Address slice slave delay setting for address slice 0."
line.long 0x24 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1380,"
hexmask.long.word 0x24 16.--26. 1. "PHY_GRP3_SLAVE_DELAY_1,Address slice slave delay setting for address slice 3."
newline
hexmask.long.word 0x24 0.--10. 1. "PHY_GRP2_SLAVE_DELAY_1,Address slice slave delay setting for address slice 2."
line.long 0x28 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1381,"
hexmask.long.word 0x28 16.--26. 1. "PHY_GRP1_SLAVE_DELAY_2,Address slice slave delay setting for address slice 1."
newline
hexmask.long.word 0x28 0.--10. 1. "PHY_GRP0_SLAVE_DELAY_2,Address slice slave delay setting for address slice 0."
line.long 0x2C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1382,"
hexmask.long.word 0x2C 16.--26. 1. "PHY_GRP3_SLAVE_DELAY_2,Address slice slave delay setting for address slice 3."
newline
hexmask.long.word 0x2C 0.--10. 1. "PHY_GRP2_SLAVE_DELAY_2,Address slice slave delay setting for address slice 2."
line.long 0x30 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1383,"
hexmask.long.word 0x30 0.--10. 1. "PHY_GRP0_SLAVE_DELAY_3,Address slice slave delay setting for address slice 0."
line.long 0x34 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1384,"
hexmask.long.word 0x34 0.--10. 1. "PHY_GRP1_SLAVE_DELAY_3,Address slice slave delay setting for address slice 1."
line.long 0x38 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1385,"
hexmask.long.word 0x38 0.--10. 1. "PHY_GRP2_SLAVE_DELAY_3,Address slice slave delay setting for address slice 2."
line.long 0x3C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1386,"
hexmask.long.word 0x3C 0.--10. 1. "PHY_GRP3_SLAVE_DELAY_3,Address slice slave delay setting for address slice 3."
line.long 0x40 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1387,"
hexmask.long 0x40 0.--29. 1. "PHY_PAD_FDBK_DRIVE,Controls drive settings for gate feedback pads."
line.long 0x44 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1388,"
hexmask.long.tbyte 0x44 0.--17. 1. "PHY_PAD_FDBK_DRIVE2,Controls drive settings [enslice/boost] for gate feedback pads."
line.long 0x48 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1389,"
hexmask.long 0x48 0.--30. 1. "PHY_PAD_DATA_DRIVE,Controls drive settings for data pads."
line.long 0x4C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1390,"
hexmask.long 0x4C 0.--31. 1. "PHY_PAD_DQS_DRIVE,Controls drive settings for dqs pads."
line.long 0x50 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1391,"
hexmask.long 0x50 0.--29. 1. "PHY_PAD_ADDR_DRIVE,Controls drive settings for the address/control pads."
line.long 0x54 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1392,"
hexmask.long 0x54 0.--27. 1. "PHY_PAD_ADDR_DRIVE2,Controls drive settings for the address/control pads."
line.long 0x58 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1393,"
hexmask.long 0x58 0.--31. 1. "PHY_PAD_CLK_DRIVE,Controls drive settings for clock pads."
line.long 0x5C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1394,"
hexmask.long.tbyte 0x5C 0.--18. 1. "PHY_PAD_CLK_DRIVE2,Controls drive settings for clock pads."
line.long 0x60 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1395,"
hexmask.long 0x60 0.--29. 1. "PHY_PAD_ERR_DRIVE,Controls drive settings for error pads."
line.long 0x64 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1396,"
hexmask.long 0x64 0.--27. 1. "PHY_PAD_ERR_DRIVE2,Controls drive settings for error pads."
line.long 0x68 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1397,"
hexmask.long 0x68 0.--29. 1. "PHY_PAD_CKE_DRIVE,Controls drive settings for cke pads."
line.long 0x6C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1398,"
hexmask.long 0x6C 0.--27. 1. "PHY_PAD_CKE_DRIVE2,Controls drive settings for cke pads."
line.long 0x70 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1399,"
hexmask.long 0x70 0.--29. 1. "PHY_PAD_RST_DRIVE,Controls drive settings for reset_n pads."
line.long 0x74 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1400,"
hexmask.long 0x74 0.--27. 1. "PHY_PAD_RST_DRIVE2,Controls drive settings for reset_n pads."
line.long 0x78 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1401,"
hexmask.long 0x78 0.--29. 1. "PHY_PAD_CS_DRIVE,Controls drive settings for cs pads."
line.long 0x7C "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1402,"
hexmask.long 0x7C 0.--27. 1. "PHY_PAD_CS_DRIVE2,Controls drive settings for cs pads."
line.long 0x80 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1403,"
hexmask.long 0x80 0.--29. 1. "PHY_PAD_ODT_DRIVE,Controls drive settings for odt pads."
line.long 0x84 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1404,"
hexmask.long 0x84 0.--27. 1. "PHY_PAD_ODT_DRIVE2,Controls drive settings for odt pads."
line.long 0x88 "CTLPHY_WRAP__CTL_CFG__CTLCFG_DENALI_PHY_1405,"
hexmask.long.byte 0x88 24.--30. 1. "PHY_CAL_SETTLING_PRD_0,Number of clock cycles to extend dfi_phyupd_req after the ack is received for settling of final values"
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hexmask.long.word 0x88 8.--23. 1. "PHY_CAL_VREF_SWITCH_TIMER_0,The settling time for a switch in VREF during IO pad calibration."
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bitfld.long 0x88 0.--2. "PHY_CAL_CLK_SELECT_0,Pad calibration pad clock frequency select setting for block 0." "0,1,2,3,4,5,6,7"
tree.end
tree "DDR16SS0_SS_CFG (DDR16SS0_SS_CFG)"
base ad:0xF300000
rgroup.long 0x0++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem."
hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID"
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hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version"
newline
bitfld.long 0x0 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor revision"
group.long 0x4++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_SS_CTL_REG,The Subsystem Control Register contains fields for control functions required for submodules in the subsystem."
bitfld.long 0x0 0. "PHY_PLL_BYPASS,Cadence PHY De-Skew PLL bypass. Write 1 to bypass PLL." "0,1"
group.long 0x20++0x1F
line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_CTL_REG,The VBUSM2AXI Control register contains control functions required for the VBUSM2AXI submodule."
bitfld.long 0x0 10. "SDRAM_3QT,Setting this field to a 1 will modify SDRAM Index to be 3/4 its programmed value to support 3  6  12 and 24 GB sizes." "0,1"
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hexmask.long.byte 0x0 5.--9. 1. "SDRAM_IDX,SDRAM Index = log2(connected SDRAM size) - 16. The sdram_idx describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Max size supported is.."
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hexmask.long.byte 0x0 0.--4. 1. "REGION_IDX,Region Index = log2(CBA region size) - 16. The region_idx describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Max size supported is.."
line.long 0x4 "REGS__SS_CFG__SSCFG_V2A_R1_MAT_REG,The Range 1 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 1 Match Register uses the.."
bitfld.long 0x4 31. "RANGE1_RANGEEN_A,The range1_rangeen_a enables the RouteID AND'd with range1_mask_a to match the range1_routeid_a" "0,1"
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bitfld.long 0x4 28.--30. "RANGE1_MASK_A,The range1_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x4 16.--27. 1. "RANGE1_ROUTEID_A,The range1_routeid_a is the value that is compared to the RouteID arriving on the command interface"
newline
bitfld.long 0x4 15. "RANGE1_RANGEEN_B,The range1_rangeen_b enables the RouteID AND'd with range1_mask_b to match the range1_routeid_b" "0,1"
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bitfld.long 0x4 12.--14. "RANGE1_MASK_B,The range1_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x4 0.--11. 1. "RANGE1_ROUTEID_B,The range1_routeid_b is the value that is compared to the RouteID arriving on the command interface"
line.long 0x8 "REGS__SS_CFG__SSCFG_V2A_R2_MAT_REG,The Range 2 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 2 Match Register uses the.."
bitfld.long 0x8 31. "RANGE2_RANGEEN_A,The range2_rangeen_a enables the RouteID AND'd with range2_mask_a to match the range2_routeid_a" "0,1"
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bitfld.long 0x8 28.--30. "RANGE2_MASK_A,The range2_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x8 16.--27. 1. "RANGE2_ROUTEID_A,The range2_routeid_a is the value that is compared to the RouteID arriving on the command interface"
newline
bitfld.long 0x8 15. "RANGE2_RANGEEN_B,The range2_rangeen_b enables the RouteID AND'd with range2_mask_b to match the range2_routeid_b" "0,1"
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bitfld.long 0x8 12.--14. "RANGE2_MASK_B,The range2_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x8 0.--11. 1. "RANGE2_ROUTEID_B,The range2_routeid_b is the value that is compared to the RouteID arriving on the command interface"
line.long 0xC "REGS__SS_CFG__SSCFG_V2A_R3_MAT_REG,The Range 3 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 3 Match Register uses the.."
bitfld.long 0xC 31. "RANGE3_RANGEEN_A,The range3_rangeen_a enables the RouteID AND'd with range3_mask_a to match the range3_routeid_a" "0,1"
newline
bitfld.long 0xC 28.--30. "RANGE3_MASK_A,The range3_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xC 16.--27. 1. "RANGE3_ROUTEID_A,The range3_routeid_a is the value that is compared to the RouteID arriving on the command interface"
newline
bitfld.long 0xC 15. "RANGE3_RANGEEN_B,The range3_rangeen_b enables the RouteID AND'd with range3_mask_b to match the range3_routeid_b" "0,1"
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bitfld.long 0xC 12.--14. "RANGE3_MASK_B,The range3_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xC 0.--11. 1. "RANGE3_ROUTEID_B,The range3_routeid_b is the value that is compared to the RouteID arriving on the command interface"
line.long 0x10 "REGS__SS_CFG__SSCFG_V2A_DEF_PRI_MAP_REG,The Default Priority Mapping Register is the default map for the inbound VBUSM.C priority to AXI priority."
bitfld.long 0x10 28.--30. "PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
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bitfld.long 0x10 24.--26. "PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
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bitfld.long 0x10 20.--22. "PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x10 16.--18. "PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x10 12.--14. "PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x10 8.--10. "PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x10 4.--6. "PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x10 0.--2. "PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
line.long 0x14 "REGS__SS_CFG__SSCFG_V2A_R1_PRI_MAP_REG,The Range 1 Priority Mapping Register is used to map the inbound VBUSM.C priority to AXI priority when a RouteID match 1 occurs. This allows the priority level to be changed from the Default Priority Mapping value."
bitfld.long 0x14 28.--30. "RANGE1_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
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bitfld.long 0x14 24.--26. "RANGE1_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
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bitfld.long 0x14 20.--22. "RANGE1_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x14 16.--18. "RANGE1_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
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bitfld.long 0x14 12.--14. "RANGE1_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x14 8.--10. "RANGE1_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x14 4.--6. "RANGE1_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x14 0.--2. "RANGE1_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
line.long 0x18 "REGS__SS_CFG__SSCFG_V2A_R2_PRI_MAP_REG,The Range 2 Priority Mapping Register is used to map the inbound VBUSM.C priority to AXI priority when a RouteID match 2 occurs. This allows the priority level to be changed from the Default Priority Mapping value."
bitfld.long 0x18 28.--30. "RANGE2_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x18 24.--26. "RANGE2_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x18 20.--22. "RANGE2_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x18 16.--18. "RANGE2_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x18 12.--14. "RANGE2_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x18 8.--10. "RANGE2_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x18 4.--6. "RANGE2_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x18 0.--2. "RANGE2_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
line.long 0x1C "REGS__SS_CFG__SSCFG_V2A_R3_PRI_MAP_REG,The Range 3 Priority Mapping Register is used to map the inbound VBUSM.C priority to AXI priority when a RouteID match 3 occurs. This allows the priority level to be changed from the Default Priority Mapping value."
bitfld.long 0x1C 28.--30. "RANGE3_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x1C 24.--26. "RANGE3_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x1C 20.--22. "RANGE3_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x1C 16.--18. "RANGE3_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x1C 12.--14. "RANGE3_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x1C 8.--10. "RANGE3_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x1C 4.--6. "RANGE3_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
newline
bitfld.long 0x1C 0.--2. "RANGE3_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
group.long 0x70++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_AERR_LOG1_REG,The Address Error Log 1 register displays the RouteID and lsb of the address for the first VBUSM.C command that was outside the programmed addressing range. Writing a 0x1 will clear all fields. Writing any other.."
hexmask.long.word 0x0 16.--31. 1. "AERR_ADDR_LSB,Address[15:0] of the VBUSM.C command"
newline
hexmask.long.word 0x0 0.--11. 1. "AERR_ROUTE_ID,RouteID of the VBUSM.C write command"
rgroup.long 0x74++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_AERR_LOG2_REG,The Address Error Log 2 registers displays the msb of the address for the first VBUSM.C command that was outside the programmed addressing range. This register will be cleared upon writing the Address Error Log 1.."
hexmask.long 0x0 0.--31. 1. "AERR_ADDR_MSB,Address[34:16] of the VBUSM.C command"
group.long 0x9C++0x13
line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_BUS_TO,"
hexmask.long.tbyte 0x0 0.--23. 1. "BUS_TIMER,AXI bus timeout value. Number of DDR clock cycles after which the VBUSM2AXI bridge times out if a hang on the controller AXI interface is detected. A value of N will be equal to N x 16 clocks. Writing a 0 will disable the timeout feature."
line.long 0x4 "REGS__SS_CFG__SSCFG_V2A_INT_RAW_REG,"
bitfld.long 0x4 5. "ECCM1BERR,Raw status of SDRAM ECC multi 1-bit errors in same SDRAM burst. Write 1 to set the (raw) status  mostly for debug. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x4 4. "ECC2BERR,Raw status of SDRAM ECC 2-bit error. Write 1 to set the (raw) status  mostly for debug. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x4 3. "ECC1BERR,Raw status of SDRAM ECC 1-bit error. Write 1 to set the (raw) status  mostly for debug. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x4 2. "TOERR,Raw status of VBUSM2AXI interrupt for controller AXI interface timeout. Write 1 to set the (raw) status  mostly for debug. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x4 1. "AERR,Raw status of VBUSM2AXI interrupt for VBUSM.C address outside the programmed range. Write 1 to set the (raw) status  mostly for debug. Writing a 0 has no effect." "0,1"
line.long 0x8 "REGS__SS_CFG__SSCFG_V2A_INT_STAT_REG,"
bitfld.long 0x8 5. "ECCM1BERR,Enabled status of SDRAM ECC multi 1-bit errors in same SDRAM burst. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared  i.e. even if not enabled). Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 4. "ECC2BERR,Enabled status of SDRAM ECC 2-bit error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared  i.e. even if not enabled). Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 3. "ECC1BERR,Enabled status of SDRAM ECC 1-bit error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared  i.e. even if not enabled). Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 2. "TOERR,Enabled status of VBUSM2AXI interrupt for controller AXI interface timeout. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared  i.e. even if not enabled). Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 1. "AERR,Enabled status of VBUSM2AXI interrupt for VBUSM.C address outside the programmed range. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared  i.e. even if not enabled). Writing a 0 has no effect." "0,1"
line.long 0xC "REGS__SS_CFG__SSCFG_V2A_INT_SET_REG,"
bitfld.long 0xC 5. "ECCM1BERR_EN,Enable set for SDRAM ECC multi 1-bit errors in same SDRAM burst. Writing a 1 will enable the interrupt  and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 4. "ECC2BERR_EN,Enable set for SDRAM ECC 2-bit error. Writing a 1 will enable the interrupt  and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 3. "ECC1BERR_EN,Enable set for SDRAM ECC 1-bit error. Writing a 1 will enable the interrupt  and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 2. "TOERR_EN,Enable set for VBUSM2AXI interrupt for controller AXI interface timeout. Writing a 1 will enable the interrupt  and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 1. "AERR_EN,Enable set for VBUSM2AXI interrupt for VBUSM.C address outside the programmed range. Writing a 1 will enable the interrupt  and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1"
line.long 0x10 "REGS__SS_CFG__SSCFG_V2A_INT_CLR_REG,"
bitfld.long 0x10 5. "ECCM1BERR_EN,Enable clear for SDRAM ECC multi 1-bit errors in same SDRAM burst. Writing a 1 will disable the interrupt  and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 4. "ECC2BERR_EN,Enable clear for SDRAM ECC 2-bit error. Writing a 1 will disable the interrupt  and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 3. "ECC1BERR_EN,Enable clear for SDRAM ECC 1-bit error. Writing a 1 will disable the interrupt  and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 2. "TOERR_EN,Enable clear for VBUSM2AXI interrupt for controller AXI interface timeout. Writing a 1 will disable the interrupt  and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 1. "AERR_EN,Enable clear for VBUSM2AXI interrupt for VBUSM.C address outside the programmed range. Writing a 1 will disable the interrupt  and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1"
wgroup.long 0xB0++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_EOI_REG,"
bitfld.long 0x0 0.--1. "EOI,Software End Of Interrupt (EOI) control. Write 0 for aerr/toerr interrupt. Write 1 for ecc1b interrupt. Write 2 for ecc2b interrupt. This field always reads 0 (no EOI memory)." "0,1,2,3"
group.long 0x100++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_PERF_CNT_SEL_REG,The Performance Counter Select register is used to select the statistic type to be counted in the corresponding Performance Counter register."
hexmask.long.byte 0x0 24.--29. 1. "CNT4_SEL,Statistic select for Performance Counter 4 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every.."
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hexmask.long.byte 0x0 16.--21. 1. "CNT3_SEL,Statistic select for Performance Counter 3 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every.."
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hexmask.long.byte 0x0 8.--13. 1. "CNT2_SEL,Statistic select for Performance Counter 2 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every.."
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hexmask.long.byte 0x0 0.--5. 1. "CNT1_SEL,Statistic select for Performance Counter 1 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every.."
rgroup.long 0x104++0xF
line.long 0x0 "REGS__SS_CFG__SSCFG_PERF_CNT1_REG,"
hexmask.long 0x0 0.--31. 1. "CNT1,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register."
line.long 0x4 "REGS__SS_CFG__SSCFG_PERF_CNT2_REG,"
hexmask.long 0x4 0.--31. 1. "CNT2,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register."
line.long 0x8 "REGS__SS_CFG__SSCFG_PERF_CNT3_REG,"
hexmask.long 0x8 0.--31. 1. "CNT3,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register."
line.long 0xC "REGS__SS_CFG__SSCFG_PERF_CNT4_REG,"
hexmask.long 0xC 0.--31. 1. "CNT4,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register."
group.long 0x120++0xB
line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_CTRL_REG,"
bitfld.long 0x0 8.--10. "COR_ECC_THRESH,Threshold for 1-bit ECC errors in multiple data words in an SDRAM burst that create an uncorrected error fault indication. Value of 0/1 means 2 or more 1-bit errors in multiple data words will result in an uncorrected error fault.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4. "WR_ALLOC,When set to 1  an unassigned ECC cache-line will be allocated for a write with routeID that do not match any of the mapped routeID's." "0,1"
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bitfld.long 0x0 2. "ECC_CK,Set 1 to enable ECC verification for read accesses when ecc_en=1. The value of this field is ignored when ecc_en=0. This bit must be set and kept static before using DDR." "0,1"
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bitfld.long 0x0 1. "RMW_EN,Read modify write enable. Set 1 to enable RMW functionality for sub-quanta accesses when ecc_en=1. This bit must be set to 1 if ecc_en is set to a 1 to ensure subquanta accesses to DRAM do not result in ECC errors. This bit must be set and kept.." "0,1"
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bitfld.long 0x0 0. "ECC_EN,DRAM ECC enable. Setting a 1 causes ECC to be written to DRAM. This bit must be set and kept static before using DDR." "0,1"
line.long 0x4 "REGS__SS_CFG__SSCFG_ECC_RID_INDX_REG,"
hexmask.long.byte 0x4 0.--5. 1. "ECCRID_ADR,This index specifies the ECC cache entry number that the eccrid_val is mapped to."
line.long 0x8 "REGS__SS_CFG__SSCFG_ECC_RID_VAL_REG,"
bitfld.long 0x8 15. "ECCRID_VAL_VLD,A 1 in this field indicates that value in eccrid_val is valid." "0,1"
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hexmask.long.word 0x8 0.--11. 1. "ECCRID_VAL,RouteID value written or read."
group.long 0x130++0x17
line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_R0_STR_ADDR_REG,"
hexmask.long.tbyte 0x0 0.--16. 1. "ECC_STR_ADR_0,Start caddress[31:16] for ECC range 0. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR."
line.long 0x4 "REGS__SS_CFG__SSCFG_ECC_R0_END_ADDR_REG,"
hexmask.long.tbyte 0x4 0.--16. 1. "ECC_END_ADR_0,End caddress[31:16] for ECC range 0. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR."
line.long 0x8 "REGS__SS_CFG__SSCFG_ECC_R1_STR_ADDR_REG,"
hexmask.long.tbyte 0x8 0.--16. 1. "ECC_STR_ADR_1,Start caddress[31:16] for ECC range 1. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR."
line.long 0xC "REGS__SS_CFG__SSCFG_ECC_R1_END_ADDR_REG,"
hexmask.long.tbyte 0xC 0.--16. 1. "ECC_END_ADR_1,End caddress[31:16] for ECC range 1. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR."
line.long 0x10 "REGS__SS_CFG__SSCFG_ECC_R2_STR_ADDR_REG,"
hexmask.long.tbyte 0x10 0.--16. 1. "ECC_STR_ADR_2,Start caddress[31:16] for ECC range 2. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR."
line.long 0x14 "REGS__SS_CFG__SSCFG_ECC_R2_END_ADDR_REG,"
hexmask.long.tbyte 0x14 0.--16. 1. "ECC_END_ADR_2,End caddress[31:16] for ECC range 2. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR."
group.long 0x150++0xB
line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_CNT_REG,"
hexmask.long.word 0x0 0.--15. 1. "ECC_1B_ERR_CNT,16-bit counter that displays number of 1-bit ECC errors on SDRAM data. Writing a 0x1 will clear this count. Writing any other value has no effect."
line.long 0x4 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_THRSH_REG,"
hexmask.long.word 0x4 0.--15. 1. "ECC_1B_ERR_THRSH,ECC 1-bit error threshold. The bridge will generate an interrupt when the ECC 1-bit error count is equal to or greater than this threshold. A value of 0 will disable the generation of interrupt."
line.long 0x8 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_ADR_LOG_REG,"
hexmask.long 0x8 0.--28. 1. "ECC_1B_ERR_ADR,ECC 1-bit error address. 16-byte aligned address that had the 1-bit ECC error. This field displays the first address logged in the 2 deep logging FIFO. Writing a 0x1 will pop the top element of the FIFO. Writing any other value has no.."
rgroup.long 0x15C++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_MSK_LOG_REG,"
hexmask.long.byte 0x0 0.--3. 1. "ECC_1B_ERR_MSK,ECC 1-bit error mask. Mask for the 32-byte data block that had the 1-bit ECC errors. Each bit represents an ECC quanta (8 bytes) in the 32-byte data block starting at address specified by ecc_1b_err_adr. Value of 1 on the bit represents an.."
group.long 0x160++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_2B_ERR_ADR_LOG_REG,"
hexmask.long 0x0 0.--28. 1. "ECC_2B_ERR_ADR,ECC 2-bit error address. 16-byte aligned address that had the 2-bit ECC error. Writing a 0x1 will clear this field and the ecc_2b_err_msk field. Writing any other value has no effect."
rgroup.long 0x164++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_2B_ERR_MSK_LOG_REG,"
hexmask.long.byte 0x0 0.--3. 1. "ECC_2B_ERR_MSK,ECC 2-bit error mask. Mask for the 32-byte data block that had the 2-bit ECC errors. Each bit represents an ECC quanta (8 bytes) in the 32-byte data block starting at address specified by ecc_2b_err_adr. Value of 1 on the bit represents an.."
group.long 0x184++0x27
line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL1_REG,"
hexmask.long.byte 0x0 24.--31. 1. "JTAG_DATAOUT_TSEL_RD_SEL,Controls jtag_dataout_tsel_rd_sel port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
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hexmask.long.byte 0x0 16.--23. 1. "JTAG_DATAOUT_TSEL_WR_SEL,Controls jtag_dataout_tsel_wr_sel port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
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hexmask.long.byte 0x0 8.--15. 1. "JTAG_DATAOUT_TSEL_ADDR_SEL,Controls jtag_dataout_tsel_addr_sel port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
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bitfld.long 0x0 7. "JTAG_DATAOUT_TSEL_ADDR_EN,Controls jtag_dataout_tsel_addr_en port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x0 6. "JTAG_DATAOUT_TSEL_EN,Controls jtag_dataout_tsel_en port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x0 5. "JTAG_ENABLE_TERM,Controls jtag_enable_term port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x0 4. "JTAG_ENABLE_OE,Controls jtag_enable_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x0 3. "JTAG_ENABLE_IE,Controls jtag_enable_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x0 2. "JTAG_ENABLE_DRIVE,Controls jtag_enable_drive port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x0 1. "JTAG_ENABLE,Controls jtag_enable port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x0 0. "HVM_TEST_EN,1=Enable HVM test functionality. 0=Disable HVM test functionality. Setting a 1 will enable control of PHY ports using PHY Test Control registers  and will enable 50 MHz clock to the jtag_dataout_pad_dslice_io_cfg[1] .." "0: Disable HVM test functionality,1: Enable HVM test functionality"
line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL2_REG,"
bitfld.long 0x4 31. "JTAG_DATAOUT_PAD_ADR_IO_CFG0,Controls jtag_dataout_pad_adr_io_cfg[0] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x4 30. "JTAG_DATAOUT_PAD_ACS_IO_CFG0,Controls jtag_dataout_pad_acs_io_cfg[0] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x4 29. "JTAG_DATAOUT_PAD_DSLICE_IO_CFG2,Controls jtag_dataout_pad_dslice_io_cfg[2] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x4 28. "JTAG_DATAOUT_PAD_DSLICE_IO_CFG0,Controls jtag_dataout_pad_dslice_io_cfg[0] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x4 27. "JTAG_DATAOUT_ATB_EN,Controls jtag_dataout_atb_en port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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hexmask.long.word 0x4 15.--26. 1. "JTAG_DATAOUT_VREF_CTRL_DQ,Controls jtag_dataout_vref_ctrl_dq port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
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hexmask.long.word 0x4 6.--14. 1. "JTAG_DATAOUT_PHY_RX_CAL_CODE,Controls jtag_dataout_phy_rx_cal_code port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
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hexmask.long.byte 0x4 0.--5. 1. "JTAG_DATAOUT_PHY_DSLICE_PAD_RX_CTLE_SETTING,Controls jtag_dataout_phy_dslice_pad_rx_ctle_setting port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
line.long 0x8 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL3_REG,"
hexmask.long.word 0x8 16.--31. 1. "JTAG_DATAOUT_ATB_CTRL,Controls jtag_dataout_atb_ctrl port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
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hexmask.long.word 0x8 0.--15. 1. "JTAG_DATAOUT_PAD_ATB_CTRL,Controls jtag_dataout_pad_atb_ctrl port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
line.long 0xC "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL4_REG,"
bitfld.long 0xC 31. "JTAG_DATAOUT_ERROR_N_OE,Controls jtag_dataout_error_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0xC 30. "JTAG_DATAOUT_PARITY_IN_OE,Controls jtag_dataout_parity_in_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0xC 28.--29. "JTAG_DATAOUT_ODT_OE,Controls jtag_dataout_odt_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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hexmask.long.word 0xC 14.--27. 1. "JTAG_DATAOUT_ADDRESS_OE,Controls jtag_dataout_address_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
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bitfld.long 0xC 12.--13. "JTAG_DATAOUT_BANK_OE,Controls jtag_dataout_bank_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0xC 10.--11. "JTAG_DATAOUT_BG_OE,Controls jtag_dataout_bg_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0xC 9. "JTAG_DATAOUT_WE_N_OE,Controls jtag_dataout_we_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0xC 8. "JTAG_DATAOUT_CAS_N_OE,Controls jtag_dataout_cas_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0xC 7. "JTAG_DATAOUT_RAS_N_OE,Controls jtag_dataout_ras_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0xC 6. "JTAG_DATAOUT_ACT_N_OE,Controls jtag_dataout_act_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0xC 4.--5. "JTAG_DATAOUT_CS_N_OE,Controls jtag_dataout_cs_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0xC 3. "JTAG_DATAOUT_MEM_CLK_0_OE,Controls jtag_dataout_mem_clk_0_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0xC 1.--2. "JTAG_DATAOUT_CKE_OE,Controls jtag_dataout_cke_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0xC 0. "JTAG_DATAOUT_RESET_N_OE,Controls jtag_dataout_reset_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
line.long 0x10 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL5_REG,"
bitfld.long 0x10 20.--21. "JTAG_DATAOUT_DQS_OE,Controls jtag_dataout_dqs_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x10 16.--17. "JTAG_DATAOUT_DM_OE,Controls jtag_dataout_dm_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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hexmask.long.word 0x10 0.--15. 1. "JTAG_DATAOUT_DATA_OE,Controls jtag_dataout_data_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
line.long 0x14 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL6_REG,"
bitfld.long 0x14 31. "JTAG_DATAOUT_ERROR_N,Controls jtag_dataout_error_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x14 30. "JTAG_DATAOUT_PARITY_IN,Controls jtag_dataout_parity_in port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x14 28.--29. "JTAG_DATAOUT_ODT,Controls jtag_dataout_odt port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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hexmask.long.word 0x14 14.--27. 1. "JTAG_DATAOUT_ADDRESS,Controls jtag_dataout_address port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
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bitfld.long 0x14 12.--13. "JTAG_DATAOUT_BANK,Controls jtag_dataout_bank port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x14 10.--11. "JTAG_DATAOUT_BG,Controls jtag_dataout_bg port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x14 9. "JTAG_DATAOUT_WE_N,Controls jtag_dataout_we_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x14 8. "JTAG_DATAOUT_CAS_N,Controls jtag_dataout_cas_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x14 7. "JTAG_DATAOUT_RAS_N,Controls jtag_dataout_ras_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x14 6. "JTAG_DATAOUT_ACT_N,Controls jtag_dataout_act_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x14 4.--5. "JTAG_DATAOUT_CS_N,Controls jtag_dataout_cs_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x14 3. "JTAG_DATAOUT_MEM_CLK_0,Controls jtag_dataout_mem_clk_0 port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x14 1.--2. "JTAG_DATAOUT_CKE,Controls jtag_dataout_cke port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x14 0. "JTAG_DATAOUT_RESET_N,Controls jtag_dataout_reset_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
line.long 0x18 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL7_REG,"
bitfld.long 0x18 20.--21. "JTAG_DATAOUT_DQS,Controls jtag_dataout_dqs port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x18 16.--17. "JTAG_DATAOUT_DM,Controls jtag_dataout_dm port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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hexmask.long.word 0x18 0.--15. 1. "JTAG_DATAOUT_DATA,Controls jtag_dataout_data port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
line.long 0x1C "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL8_REG,"
bitfld.long 0x1C 31. "JTAG_DATAOUT_ERROR_N_IE,Controls jtag_dataout_error_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x1C 30. "JTAG_DATAOUT_PARITY_IN_IE,Controls jtag_dataout_parity_in_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x1C 28.--29. "JTAG_DATAOUT_ODT_IE,Controls jtag_dataout_odt_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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hexmask.long.word 0x1C 14.--27. 1. "JTAG_DATAOUT_ADDRESS_IE,Controls jtag_dataout_address_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
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bitfld.long 0x1C 12.--13. "JTAG_DATAOUT_BANK_IE,Controls jtag_dataout_bank_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x1C 10.--11. "JTAG_DATAOUT_BG_IE,Controls jtag_dataout_bg_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x1C 9. "JTAG_DATAOUT_WE_N_IE,Controls jtag_dataout_we_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x1C 8. "JTAG_DATAOUT_CAS_N_IE,Controls jtag_dataout_cas_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x1C 7. "JTAG_DATAOUT_RAS_N_IE,Controls jtag_dataout_ras_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x1C 6. "JTAG_DATAOUT_ACT_N_IE,Controls jtag_dataout_act_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x1C 4.--5. "JTAG_DATAOUT_CS_N_IE,Controls jtag_dataout_cs_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x1C 3. "JTAG_DATAOUT_MEM_CLK_0_IE,Controls jtag_dataout_mem_clk_0_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
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bitfld.long 0x1C 1.--2. "JTAG_DATAOUT_CKE_IE,Controls jtag_dataout_cke_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x1C 0. "JTAG_DATAOUT_RESET_N_IE,Controls jtag_dataout_reset_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1"
line.long 0x20 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL9_REG,"
bitfld.long 0x20 20.--21. "JTAG_DATAOUT_DQS_IE,Controls jtag_dataout_dqs_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
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bitfld.long 0x20 16.--17. "JTAG_DATAOUT_DM_IE,Controls jtag_dataout_dm_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3"
newline
hexmask.long.word 0x20 0.--15. 1. "JTAG_DATAOUT_DATA_IE,Controls jtag_dataout_data_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1."
line.long 0x24 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL10_REG,"
hexmask.long.byte 0x24 0.--7. 1. "HVM_CLK_DIV,Divfactor to divide ddrss_ddr_pll_clk to generate PCLK for HVM tests when ddrss_bs_mode=0 and hvm_test_en=1. 0=div by 1  1=div by 2  and so on."
rgroup.long 0x1C0++0x7
line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_TEST_STAT1_REG,"
bitfld.long 0x0 31. "JTAG_DATAIN_ERROR_N,Displays value of jtag_datain_error_n port on the PHY." "0,1"
newline
bitfld.long 0x0 30. "JTAG_DATAIN_PARITY_IN,Displays value of jtag_datain_parity_in port on the PHY." "0,1"
newline
bitfld.long 0x0 28.--29. "JTAG_DATAIN_ODT,Displays value of jtag_datain_odt port on the PHY." "0,1,2,3"
newline
hexmask.long.word 0x0 14.--27. 1. "JTAG_DATAIN_ADDRESS,Displays value of jtag_datain_address port on the PHY."
newline
bitfld.long 0x0 12.--13. "JTAG_DATAIN_BANK,Displays value of jtag_datain_bank port on the PHY." "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "JTAG_DATAIN_BG,Displays value of jtag_datain_bg port on the PHY." "0,1,2,3"
newline
bitfld.long 0x0 9. "JTAG_DATAIN_WE_N,Displays value of jtag_datain_we_n port on the PHY." "0,1"
newline
bitfld.long 0x0 8. "JTAG_DATAIN_CAS_N,Displays value of jtag_datain_cas_n port on the PHY." "0,1"
newline
bitfld.long 0x0 7. "JTAG_DATAIN_RAS_N,Displays value of jtag_datain_ras_n port on the PHY." "0,1"
newline
bitfld.long 0x0 6. "JTAG_DATAIN_ACT_N,Displays value of jtag_datain_act_n port on the PHY." "0,1"
newline
bitfld.long 0x0 4.--5. "JTAG_DATAIN_CS_N,Displays value of jtag_datain_cs_n port on the PHY." "0,1,2,3"
newline
bitfld.long 0x0 3. "JTAG_DATAIN_MEM_CLK_0,Displays value of jtag_datain_mem_clk_0 port on the PHY." "0,1"
newline
bitfld.long 0x0 1.--2. "JTAG_DATAIN_CKE,Displays value of jtag_datain_cke port on the PHY." "0,1,2,3"
newline
bitfld.long 0x0 0. "JTAG_DATAIN_RESET_N,Displays value of jtag_datain_reset_n port on the PHY." "0,1"
line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_TEST_STAT2_REG,"
bitfld.long 0x4 20.--21. "JTAG_DATAIN_DQS,Displays value of jtag_datain_dqs port on the PHY." "0,1,2,3"
newline
bitfld.long 0x4 16.--17. "JTAG_DATAIN_DM,Displays value of jtag_datain_dm port on the PHY." "0,1,2,3"
newline
hexmask.long.word 0x4 0.--15. 1. "JTAG_DATAIN_DATA,Displays value of jtag_datain_data port on the PHY."
tree.end
tree.end
tree "DMASS0"
base ad:0x0
tree "DMASS0_BCDMA_0_BCDMA"
tree "DMASS0_BCDMA_0_BCDMA_BCHAN (DMASS0_BCDMA_0_BCDMA_BCHAN)"
base ad:0x48420000
group.long 0x0++0x3
line.long 0x0 "BCDMA_BCHAN_CFG,The Channel Configuration Register is used to initialize static mode settings for the Block Copy DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)."
bitfld.long 0x0 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.."
hexmask.long.byte 0x0 16.--19. 1. "CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-11 = RESERVED 12.."
newline
bitfld.long 0x0 10.--11. "BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes All other values are reserved The optimal burst size setting is 64 Bytes to maximize utilization of the channel FIFOs." "0: 32 Bytes,1: 64 Bytes All other values are reserved The..,?,?"
group.long 0x64++0x3
line.long 0x0 "BCDMA_BCHAN_PRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface."
bitfld.long 0x0 28.--30. "PRIORITY,Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel."
group.long 0x80++0x3
line.long 0x0 "BCDMA_BCHAN_ST_SCHED,The Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this.."
bitfld.long 0x0 0.--1. "PRIORITY,Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx/Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.."
tree.end
tree "DMASS0_BCDMA_0_BCDMA_BCHANRT (DMASS0_BCDMA_0_BCDMA_BCHANRT)"
base ad:0x4C000000
group.long 0x0++0x3
line.long 0x0 "BCDMA_BCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation."
bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.."
bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1"
bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1"
newline
bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set  the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1"
rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1"
group.long 0x8++0x3
line.long 0x0 "BCDMA_BCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This register.."
bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
rgroup.long 0x40++0xF
line.long 0x0 "BCDMA_BCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits."
bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
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bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
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bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1"
bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
newline
bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x4 "BCDMA_BCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits."
bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1"
bitfld.long 0x4 8. "TDNULL,Channel is trying to teardown and has met conditions" "0,1"
newline
bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule a transaction" "0,1"
bitfld.long 0x4 6. "CHANNEL_BUSY,The channel is active" "0,1"
bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1"
line.long 0x8 "BCDMA_BCHANRT_TRT_STATUS2,The Status Register provides a read only view of channel status bits."
bitfld.long 0x8 31. "RRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x8 30. "RXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x8 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
newline
bitfld.long 0x8 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
bitfld.long 0x8 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x8 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
newline
bitfld.long 0x8 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x8 22. "OK,The channel is ready to be scheduled" "0,1"
bitfld.long 0x8 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
newline
bitfld.long 0x8 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x8 17. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x8 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0xC "BCDMA_BCHANRT_TRT_STATUS3,The Status Register provides a read only view of channel status bits."
bitfld.long 0xC 31. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0xC 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1"
bitfld.long 0xC 24. "FIFO_BUSY,The fifo has data" "0,1"
group.long 0x80++0x3
line.long 0x0 "BCDMA_BCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.."
hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table"
group.long 0x100++0x3
line.long 0x0 "BCDMA_BCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.."
hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table"
group.long 0x400++0x3
line.long 0x0 "BCDMA_BCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel."
group.long 0x408++0x3
line.long 0x0 "BCDMA_BCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel."
group.long 0x410++0x3
line.long 0x0 "BCDMA_BCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel."
tree.end
tree "DMASS0_BCDMA_0_BCDMA_CRED (DMASS0_BCDMA_0_BCDMA_CRED)"
base ad:0x48400000
group.long 0x0++0x3
line.long 0x0 "BCDMA_CRED_CRED,The Credentials Register provides credentials to be used when performing memory accesses using this flow."
bitfld.long 0x0 26. "SECURE,Secure attribute" "0,1"
bitfld.long 0x0 24.--25. "PRIV,Privelege attribute" "0,1,2,3"
hexmask.long.byte 0x0 16.--23. 1. "PRIVID,Privelege ID attribute"
tree.end
tree "DMASS0_BCDMA_0_BCDMA_GCFG (DMASS0_BCDMA_0_BCDMA_GCFG)"
base ad:0x485C0100
rgroup.long 0x0++0x3
line.long 0x0 "BCDMA_GCFG_REVISION,The Revision Register contains the major and minor revisions for the module."
hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision"
group.long 0x4++0x7
line.long 0x0 "BCDMA_GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system."
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported."
line.long 0x4 "BCDMA_GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted."
bitfld.long 0x4 1. "SOFT,Soft" "0,1"
bitfld.long 0x4 0. "FREE,Free" "0,1"
group.long 0x10++0x3
line.long 0x0 "BCDMA_GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy."
bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1"
hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit"
rgroup.long 0x20++0x13
line.long 0x0 "BCDMA_GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports."
bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1"
bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1"
bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1"
bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1"
bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1"
newline
bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1"
bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1"
bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1"
bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1"
bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1"
newline
bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1"
bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1"
bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1"
bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1"
bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1"
newline
bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1"
bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1"
bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1"
bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1"
bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1"
line.long 0x4 "BCDMA_GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports."
bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1"
bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1"
bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1"
bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1"
line.long 0x8 "BCDMA_GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports."
hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count"
hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count"
hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count"
line.long 0xC "BCDMA_GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports."
hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count"
hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count"
line.long 0x10 "BCDMA_GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports."
hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count"
hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count"
hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count"
hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count"
group.long 0x60++0x7
line.long 0x0 "BCDMA_GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks"
hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals."
bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3"
bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3"
line.long 0x4 "BCDMA_GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks"
bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1"
newline
bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1"
bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1"
newline
bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3"
bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1"
hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals."
bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1"
newline
bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1"
bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1"
newline
bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1"
group.long 0x78++0x7
line.long 0x0 "BCDMA_GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register"
bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from"
hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers"
line.long 0x4 "BCDMA_GCFG_DBGD,This register provides read only debug data"
hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register"
tree.end
tree "DMASS0_BCDMA_0_BCDMA_RCHAN (DMASS0_BCDMA_0_BCDMA_RCHAN)"
base ad:0x484C2000
group.long 0x0++0x3
line.long 0x0 "BCDMA_RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)."
bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.."
newline
hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.."
newline
bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.."
newline
bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes All other values are reserved The optimal burst size setting is 64 Bytes to maximize utilization of the channel FIFOs." "0: 32 Bytes,1: 64 Bytes All other values are reserved The..,?,?"
group.long 0x64++0x7
line.long 0x0 "BCDMA_RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface."
bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel."
line.long 0x4 "BCDMA_RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register."
hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel."
group.long 0x80++0x3
line.long 0x0 "BCDMA_RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this.."
bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.."
tree.end
tree "DMASS0_BCDMA_0_BCDMA_RCHANRT (DMASS0_BCDMA_0_BCDMA_RCHANRT)"
base ad:0x4A820000
group.long 0x0++0x3
line.long 0x0 "BCDMA_RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation."
bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.."
bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1"
bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1"
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bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set  the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1"
rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1"
rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1"
group.long 0x8++0x3
line.long 0x0 "BCDMA_RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This register.."
bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
rgroup.long 0x40++0x7
line.long 0x0 "BCDMA_RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits."
bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
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bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
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bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1"
bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
newline
bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x4 "BCDMA_RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits."
bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1"
bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1"
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bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1"
bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1"
bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1"
group.long 0x80++0x3
line.long 0x0 "BCDMA_RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.."
hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table"
group.long 0x200++0x3F
line.long 0x0 "BCDMA_RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400."
hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x4 "BCDMA_RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401."
hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x8 "BCDMA_RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402."
hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0xC "BCDMA_RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403."
hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x10 "BCDMA_RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404."
hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x14 "BCDMA_RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405."
hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x18 "BCDMA_RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406."
hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x1C "BCDMA_RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407."
hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x20 "BCDMA_RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408."
hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x24 "BCDMA_RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409."
hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x28 "BCDMA_RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A."
hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x2C "BCDMA_RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B."
hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x30 "BCDMA_RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C."
hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x34 "BCDMA_RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D."
hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x38 "BCDMA_RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E."
hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x3C "BCDMA_RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F."
hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
group.long 0x400++0x3
line.long 0x0 "BCDMA_RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel."
group.long 0x408++0x3
line.long 0x0 "BCDMA_RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel."
group.long 0x410++0x3
line.long 0x0 "BCDMA_RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel."
tree.end
tree "DMASS0_BCDMA_0_BCDMA_RING (DMASS0_BCDMA_0_BCDMA_RING)"
base ad:0x48600000
group.long 0x40++0xB
line.long 0x0 "BCDMA_RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will reset.."
hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)"
line.long 0x4 "BCDMA_RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will reset.."
hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select"
hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)"
line.long 0x8 "BCDMA_RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and reset the pointers."
bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements."
tree.end
tree "DMASS0_BCDMA_0_BCDMA_RINGRT (DMASS0_BCDMA_0_BCDMA_RINGRT)"
base ad:0x4BC00000
group.long 0x10++0x3
line.long 0x0 "BCDMA_RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation."
hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation  this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.."
group.long 0x18++0x3
line.long 0x0 "BCDMA_RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be.."
hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed."
group.long 0x1010++0x3
line.long 0x0 "BCDMA_RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation."
bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation  this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.."
group.long 0x1018++0x3
line.long 0x0 "BCDMA_RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be.."
bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1"
hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed."
tree.end
tree "DMASS0_BCDMA_0_BCDMA_TCHAN (DMASS0_BCDMA_0_BCDMA_TCHAN)"
base ad:0x484A4000
group.long 0x0++0x3
line.long 0x0 "BCDMA_TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)."
bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.."
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hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.."
newline
bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes All other values are reserved The optimal burst size setting is 64 Bytes to maximize utilization of the channel FIFOs." "0: 32 Bytes,1: 64 Bytes All other values are reserved The..,?,?"
newline
bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.."
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bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet"
group.long 0x64++0x7
line.long 0x0 "BCDMA_TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface."
bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel."
line.long 0x4 "BCDMA_TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register."
hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel."
group.long 0x70++0x3
line.long 0x0 "BCDMA_TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be artificially reduced.."
hexmask.long.byte 0x0 0.--7. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth)  the maximum value varies by channel class (ultra-high.."
group.long 0x80++0x3
line.long 0x0 "BCDMA_TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this.."
bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.."
tree.end
tree "DMASS0_BCDMA_0_BCDMA_TCHANRT (DMASS0_BCDMA_0_BCDMA_TCHANRT)"
base ad:0x4AA40000
group.long 0x0++0x3
line.long 0x0 "BCDMA_TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation."
bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.."
bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1"
bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1"
newline
bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set  the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1"
rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1"
group.long 0x8++0x3
line.long 0x0 "BCDMA_TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This register.."
bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
rgroup.long 0x40++0x7
line.long 0x0 "BCDMA_TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits."
bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
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bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
newline
bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1"
bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
newline
bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x4 "BCDMA_TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits."
bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1"
bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1"
newline
bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1"
bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1"
bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1"
group.long 0x80++0x3
line.long 0x0 "BCDMA_TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.."
hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table"
group.long 0x200++0x3F
line.long 0x0 "BCDMA_TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400."
hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x4 "BCDMA_TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401."
hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x8 "BCDMA_TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402."
hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0xC "BCDMA_TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403."
hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x10 "BCDMA_TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404."
hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x14 "BCDMA_TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405."
hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x18 "BCDMA_TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406."
hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x1C "BCDMA_TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407."
hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x20 "BCDMA_TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408."
hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x24 "BCDMA_TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409."
hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x28 "BCDMA_TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A."
hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x2C "BCDMA_TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B."
hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x30 "BCDMA_TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C."
hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x34 "BCDMA_TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D."
hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x38 "BCDMA_TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E."
hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x3C "BCDMA_TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F."
hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
group.long 0x400++0x3
line.long 0x0 "BCDMA_TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel."
group.long 0x408++0x3
line.long 0x0 "BCDMA_TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel."
group.long 0x410++0x3
line.long 0x0 "BCDMA_TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel."
tree.end
tree.end
tree "DMASS0_ECC_AGGR_0_ECCAGGR (DMASS0_ECC_AGGR_0_ECCAGGR)"
base ad:0x3F005000
rgroup.long 0x0++0x3
line.long 0x0 "ECCAGGR_REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECCAGGR_REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECCAGGR_REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECCAGGR_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECCAGGR_REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECCAGGR_REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 26. "SEC_PROXY_BUFRAM_RAMECCC_PEND,Interrupt Pending Status for sec_proxy_bufram_rameccc_pend" "0,1"
bitfld.long 0x4 25. "SEC_PROXY_STRAM_RAMECCC_PEND,Interrupt Pending Status for sec_proxy_stram_rameccc_pend" "0,1"
newline
bitfld.long 0x4 24. "RINGACC_STRAM_RAMECC_PEND,Interrupt Pending Status for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x4 23. "MAP_RAMECC_PEND,Interrupt Pending Status for map_ramecc_pend" "0,1"
newline
bitfld.long 0x4 22. "SR_RAMECC_PEND,Interrupt Pending Status for sr_ramecc_pend" "0,1"
bitfld.long 0x4 21. "BCDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for bcdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x4 20. "BCDMA_STS_RAMECC1_PEND,Interrupt Pending Status for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x4 19. "BCDMA_STS_RAMECC0_PEND,Interrupt Pending Status for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x4 18. "BCDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x4 17. "BCDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 16. "BCDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 15. "BCDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 14. "BCDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 13. "PCFD1_RAMECC_PEND,Interrupt Pending Status for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 12. "PCFD0_RAMECC_PEND,Interrupt Pending Status for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x4 11. "BCDMA_STATE_RAMECC_PEND,Interrupt Pending Status for bcdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x4 10. "BCDMA_CFG_RAMECC_PEND,Interrupt Pending Status for bcdma_cfg_ramecc_pend" "0,1"
bitfld.long 0x4 9. "PKTDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for pktdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x4 8. "PKTDMA_STS_RAMECC1_PEND,Interrupt Pending Status for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x4 7. "PKTDMA_STS_RAMECC0_PEND,Interrupt Pending Status for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x4 6. "PKTDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x4 5. "PKTDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 4. "PKTDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 3. "PKTDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 2. "PKTDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 1. "PKTDMA_STATE_RAMECC_PEND,Interrupt Pending Status for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x4 0. "PKTDMA_CFG_RAMECC_PEND,Interrupt Pending Status for pktdma_cfg_ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECCAGGR_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 26. "SEC_PROXY_BUFRAM_RAMECCC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_bufram_rameccc_pend" "0,1"
bitfld.long 0x0 25. "SEC_PROXY_STRAM_RAMECCC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_stram_rameccc_pend" "0,1"
newline
bitfld.long 0x0 24. "RINGACC_STRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x0 23. "MAP_RAMECC_ENABLE_SET,Interrupt Enable Set Register for map_ramecc_pend" "0,1"
newline
bitfld.long 0x0 22. "SR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sr_ramecc_pend" "0,1"
bitfld.long 0x0 21. "BCDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x0 20. "BCDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x0 19. "BCDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x0 18. "BCDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x0 17. "BCDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 16. "BCDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 15. "BCDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 14. "BCDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 13. "PCFD1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 12. "PCFD0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x0 11. "BCDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x0 10. "BCDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_cfg_ramecc_pend" "0,1"
bitfld.long 0x0 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x0 8. "PKTDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x0 7. "PKTDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x0 6. "PKTDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x0 5. "PKTDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 4. "PKTDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 3. "PKTDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 2. "PKTDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "PKTDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "PKTDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_cfg_ramecc_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECCAGGR_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 26. "SEC_PROXY_BUFRAM_RAMECCC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_bufram_rameccc_pend" "0,1"
bitfld.long 0x0 25. "SEC_PROXY_STRAM_RAMECCC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_stram_rameccc_pend" "0,1"
newline
bitfld.long 0x0 24. "RINGACC_STRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x0 23. "MAP_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for map_ramecc_pend" "0,1"
newline
bitfld.long 0x0 22. "SR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sr_ramecc_pend" "0,1"
bitfld.long 0x0 21. "BCDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x0 20. "BCDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x0 19. "BCDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x0 18. "BCDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x0 17. "BCDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 16. "BCDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 15. "BCDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 14. "BCDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 13. "PCFD1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 12. "PCFD0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x0 11. "BCDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x0 10. "BCDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_cfg_ramecc_pend" "0,1"
bitfld.long 0x0 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x0 8. "PKTDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x0 7. "PKTDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x0 6. "PKTDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x0 5. "PKTDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 4. "PKTDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 3. "PKTDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 2. "PKTDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "PKTDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "PKTDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_cfg_ramecc_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECCAGGR_REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECCAGGR_REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 26. "SEC_PROXY_BUFRAM_RAMECCC_PEND,Interrupt Pending Status for sec_proxy_bufram_rameccc_pend" "0,1"
bitfld.long 0x4 25. "SEC_PROXY_STRAM_RAMECCC_PEND,Interrupt Pending Status for sec_proxy_stram_rameccc_pend" "0,1"
newline
bitfld.long 0x4 24. "RINGACC_STRAM_RAMECC_PEND,Interrupt Pending Status for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x4 23. "MAP_RAMECC_PEND,Interrupt Pending Status for map_ramecc_pend" "0,1"
newline
bitfld.long 0x4 22. "SR_RAMECC_PEND,Interrupt Pending Status for sr_ramecc_pend" "0,1"
bitfld.long 0x4 21. "BCDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for bcdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x4 20. "BCDMA_STS_RAMECC1_PEND,Interrupt Pending Status for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x4 19. "BCDMA_STS_RAMECC0_PEND,Interrupt Pending Status for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x4 18. "BCDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x4 17. "BCDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 16. "BCDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 15. "BCDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 14. "BCDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 13. "PCFD1_RAMECC_PEND,Interrupt Pending Status for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 12. "PCFD0_RAMECC_PEND,Interrupt Pending Status for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x4 11. "BCDMA_STATE_RAMECC_PEND,Interrupt Pending Status for bcdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x4 10. "BCDMA_CFG_RAMECC_PEND,Interrupt Pending Status for bcdma_cfg_ramecc_pend" "0,1"
bitfld.long 0x4 9. "PKTDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for pktdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x4 8. "PKTDMA_STS_RAMECC1_PEND,Interrupt Pending Status for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x4 7. "PKTDMA_STS_RAMECC0_PEND,Interrupt Pending Status for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x4 6. "PKTDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x4 5. "PKTDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 4. "PKTDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 3. "PKTDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 2. "PKTDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 1. "PKTDMA_STATE_RAMECC_PEND,Interrupt Pending Status for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x4 0. "PKTDMA_CFG_RAMECC_PEND,Interrupt Pending Status for pktdma_cfg_ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECCAGGR_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 26. "SEC_PROXY_BUFRAM_RAMECCC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_bufram_rameccc_pend" "0,1"
bitfld.long 0x0 25. "SEC_PROXY_STRAM_RAMECCC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_stram_rameccc_pend" "0,1"
newline
bitfld.long 0x0 24. "RINGACC_STRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x0 23. "MAP_RAMECC_ENABLE_SET,Interrupt Enable Set Register for map_ramecc_pend" "0,1"
newline
bitfld.long 0x0 22. "SR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sr_ramecc_pend" "0,1"
bitfld.long 0x0 21. "BCDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x0 20. "BCDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x0 19. "BCDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x0 18. "BCDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x0 17. "BCDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 16. "BCDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 15. "BCDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 14. "BCDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 13. "PCFD1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 12. "PCFD0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x0 11. "BCDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x0 10. "BCDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_cfg_ramecc_pend" "0,1"
bitfld.long 0x0 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x0 8. "PKTDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x0 7. "PKTDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x0 6. "PKTDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x0 5. "PKTDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 4. "PKTDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 3. "PKTDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 2. "PKTDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "PKTDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "PKTDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_cfg_ramecc_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECCAGGR_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 26. "SEC_PROXY_BUFRAM_RAMECCC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_bufram_rameccc_pend" "0,1"
bitfld.long 0x0 25. "SEC_PROXY_STRAM_RAMECCC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_stram_rameccc_pend" "0,1"
newline
bitfld.long 0x0 24. "RINGACC_STRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x0 23. "MAP_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for map_ramecc_pend" "0,1"
newline
bitfld.long 0x0 22. "SR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sr_ramecc_pend" "0,1"
bitfld.long 0x0 21. "BCDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x0 20. "BCDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x0 19. "BCDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x0 18. "BCDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x0 17. "BCDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 16. "BCDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 15. "BCDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 14. "BCDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 13. "PCFD1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 12. "PCFD0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x0 11. "BCDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x0 10. "BCDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_cfg_ramecc_pend" "0,1"
bitfld.long 0x0 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rngocc_ramecc_pend" "0,1"
newline
bitfld.long 0x0 8. "PKTDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x0 7. "PKTDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x0 6. "PKTDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x0 5. "PKTDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 4. "PKTDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 3. "PKTDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 2. "PKTDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "PKTDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "PKTDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_cfg_ramecc_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECCAGGR_REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECCAGGR_REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECCAGGR_REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECCAGGR_REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
base ad:0x0
tree "DMASS0_INTAGGR_0_INTAGGR"
tree "DMASS0_INTAGGR_0_INTAGGR_CFG (DMASS0_INTAGGR_0_INTAGGR_CFG)"
base ad:0x48110000
rgroup.quad 0x0++0x17
line.quad 0x0 "INTAGGR_CFG_REVISION,The Revision Register contains the major and minor revisions for the module."
hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field"
hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release."
bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision"
line.quad 0x8 "INTAGGR_CFG_INTCAP,The IntCap Register contains information on virtual interrupts."
hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count"
hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers"
line.quad 0x10 "INTAGGR_CFG_AUXCAP,The AuxCap Register contains information on additional capabilities."
hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid."
hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers"
hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation"
hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers"
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_GCNTCFG (DMASS0_INTAGGR_0_INTAGGR_GCNTCFG)"
base ad:0x48220000
group.quad 0x0++0x7
line.quad 0x0 "INTAGGR_GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_GCNTRTI (DMASS0_INTAGGR_0_INTAGGR_GCNTRTI)"
base ad:0x4A000000
group.quad 0x0++0x7
line.quad 0x0 "INTAGGR_GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a count has been processed by.."
hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write  this field will be decremented by the value written. Writing a value greater than the current count is.."
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_IMAP (DMASS0_INTAGGR_0_INTAGGR_IMAP)"
base ad:0x48100000
group.quad 0x0++0x7
line.quad 0x0 "INTAGGR_IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto."
hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in."
hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in."
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_INTR (DMASS0_INTAGGR_0_INTAGGR_INTR)"
base ad:0x48000000
group.quad 0x0++0x27
line.quad 0x0 "INTAGGR_INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output."
hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes  set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register."
line.quad 0x8 "INTAGGR_INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output."
hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes  set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register."
line.quad 0x10 "INTAGGR_INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt."
hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set"
line.quad 0x18 "INTAGGR_INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt."
hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared"
line.quad 0x20 "INTAGGR_INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt."
hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers"
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_L2G (DMASS0_INTAGGR_0_INTAGGR_L2G)"
base ad:0x48120000
group.quad 0x0++0x7
line.quad 0x0 "INTAGGR_L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event count is determined by.."
bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events  and to 1 for rising edge eventss" "0,1"
hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_MCAST (DMASS0_INTAGGR_0_INTAGGR_MCAST)"
base ad:0x48210000
group.quad 0x0++0x7
line.quad 0x0 "INTAGGR_MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this register. which is.."
bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set  this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "?,?"
hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable."
bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable."
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_UNMAP (DMASS0_INTAGGR_0_INTAGGR_UNMAP)"
base ad:0x48180000
group.quad 0x0++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x8000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x9000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0xA000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0xB000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0xC000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0xD000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x10000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x11000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x12000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x13000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x14000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x15000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x16000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x17000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
group.quad 0x18000++0x7
line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag."
bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set  this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "?,?"
hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable."
tree.end
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA"
tree "DMASS0_PKTDMA_0_PKTDMA_CRED (DMASS0_PKTDMA_0_PKTDMA_CRED)"
base ad:0x48410000
group.long 0x0++0x3
line.long 0x0 "PKTDMA_CRED_CRED,The Credentials Register provides credentials to be used when performing memory accesses using this flow."
bitfld.long 0x0 31. "CHK_SECURE,Check secure control bit" "0,1"
bitfld.long 0x0 26. "SECURE,Secure attribute" "0,1"
bitfld.long 0x0 24.--25. "PRIV,Privelege attribute" "0,1,2,3"
hexmask.long.byte 0x0 16.--23. 1. "PRIVID,Privelege ID attribute"
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_GCFG (DMASS0_PKTDMA_0_PKTDMA_GCFG)"
base ad:0x485C0000
rgroup.long 0x0++0x3
line.long 0x0 "PKTDMA_GCFG_REVISION,The Revision Register contains the major and minor revisions for the module."
hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision"
group.long 0x4++0x7
line.long 0x0 "PKTDMA_GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the PKTDMA in the system."
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported"
line.long 0x4 "PKTDMA_GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted."
bitfld.long 0x4 1. "SOFT,Soft" "0,1"
bitfld.long 0x4 0. "FREE,Free" "0,1"
group.long 0x10++0x3
line.long 0x0 "PKTDMA_GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy."
bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1"
hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit"
group.long 0x20++0x7
line.long 0x0 "PKTDMA_GCFG_CAP0,The Capabilities Register 0 specifies which standard features this PKTDMA instance supports."
line.long 0x4 "PKTDMA_GCFG_CAP1,The Capabilities Register 1 specifies which standard features this PKTDMA instance supports."
rgroup.long 0x28++0xB
line.long 0x0 "PKTDMA_GCFG_CAP2,The Capabilities Register 2 specifies how many resources this PKTDMA instance supports."
hexmask.long.word 0x0 18.--26. 1. "RCHAN_CNT,Rx internal channel count"
hexmask.long.word 0x0 0.--8. 1. "TCHAN_CNT,Tx internal channel count"
line.long 0x4 "PKTDMA_GCFG_CAP3,The Capabilities Register 3 specifies how many resources this PKTDMA instance supports."
hexmask.long.word 0x4 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count"
hexmask.long.word 0x4 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count"
hexmask.long.word 0x4 0.--13. 1. "RFLOW_CNT,Rx flow table entry count"
line.long 0x8 "PKTDMA_GCFG_CAP4,The Capabilities Register 4 specifies how many resources this PKTDMA instance supports."
hexmask.long.word 0x8 0.--13. 1. "TFLOW_CNT,Tx flow table entry count"
group.long 0x60++0x7
line.long 0x0 "PKTDMA_GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks"
bitfld.long 0x0 31. "NOGATE_RDU3,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 30. "NOGATE_RDU2,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 29. "NOGATE_RDU1,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 28. "NOGATE_RDU0,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 27. "NOGATE_TDU3,When set inhibits automatic gating of clock." "0,1"
newline
bitfld.long 0x0 26. "NOGATE_TDU2,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 25. "NOGATE_TDU1,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 24. "NOGATE_TDU0,When set inhibits automatic gating of clock." "0,1"
hexmask.long.word 0x0 13.--23. 1. "NOGATE_RSVD4,Reserved PM signals."
bitfld.long 0x0 12. "NOGATE_RDEC,When set inhibits automatic gating of clock." "0,1"
newline
bitfld.long 0x0 9.--11. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 8. "NOGATE_SDEC,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 5.--7. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4. "NOGATE_WARB,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x0 1.--3. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "NOGATE_CARB,When set inhibits automatic gating of clock." "0,1"
line.long 0x4 "PKTDMA_GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks"
bitfld.long 0x4 31. "NOGATE_RSVD12,Reserved PM signals." "0,1"
bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 28. "NOGATE_RSVD11,Reserved PM signals." "0,1"
bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1"
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bitfld.long 0x4 26. "NOGATE_RSVD10,Reserved PM signals." "0,1"
bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 23. "NOGATE_RSVD9,Reserved PM signals." "0,1"
bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1"
newline
bitfld.long 0x4 19.--21. "NOGATE_RSVD8,Reserved PM signals." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 16.--17. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3"
bitfld.long 0x4 15. "NOGATE_RFLOWFW,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 14. "NOGATE_RSVD6,Reserved PM signals." "0,1"
newline
bitfld.long 0x4 13. "NOGATE_RCU,When set inhibits automatic gating of clock." "0,1"
bitfld.long 0x4 12. "NOGATE_TCU,When set inhibits automatic gating of clock." "0,1"
hexmask.long.word 0x4 0.--11. 1. "NOGATE_RSVD5,Reserved PM signals."
group.long 0x78++0x3
line.long 0x0 "PKTDMA_GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register"
bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from"
hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers"
rgroup.long 0x7C++0x3
line.long 0x0 "PKTDMA_GCFG_DBGD,This register provides read only debug data"
hexmask.long 0x0 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register"
group.long 0x88++0x3
line.long 0x0 "PKTDMA_GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected until the pend bit.."
bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set  the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1"
hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet"
hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received"
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_RCHAN (DMASS0_PKTDMA_0_PKTDMA_RCHAN)"
base ad:0x484C0000
group.long 0x0++0x3
line.long 0x0 "PKTDMA_RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)."
bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.."
hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 2 = Channel.."
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bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 1 = 64 Bytes 2 = 128 Bytes All other values are reserved" "?,1: 64 Bytes,2: 128 Bytes All other values are reserved,?"
group.long 0x64++0x7
line.long 0x0 "PKTDMA_RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface."
bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel."
line.long 0x4 "PKTDMA_RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register."
hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel."
group.long 0x80++0x3
line.long 0x0 "PKTDMA_RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this.."
bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.."
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_RCHANRT (DMASS0_PKTDMA_0_PKTDMA_RCHANRT)"
base ad:0x4A800000
group.long 0x0++0x3
line.long 0x0 "PKTDMA_RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation."
bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.."
bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1"
bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1"
bitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1"
rgroup.long 0x40++0x7
line.long 0x0 "PKTDMA_RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits."
bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
newline
bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1"
newline
bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x4 "PKTDMA_RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits."
bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1"
bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1"
bitfld.long 0x4 7. "CHANNEL_OK,The channel is trying to schedule work" "0,1"
newline
bitfld.long 0x4 6. "CHANNEL_BUSY,The channel has active work" "0,1"
bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1"
group.long 0x80++0x3
line.long 0x0 "PKTDMA_RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.."
hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table"
group.long 0x200++0x3F
line.long 0x0 "PKTDMA_RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400."
hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x4 "PKTDMA_RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401."
hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x8 "PKTDMA_RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402."
hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0xC "PKTDMA_RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403."
hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x10 "PKTDMA_RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404."
hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x14 "PKTDMA_RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405."
hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x18 "PKTDMA_RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406."
hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x1C "PKTDMA_RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407."
hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x20 "PKTDMA_RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408."
hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x24 "PKTDMA_RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409."
hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x28 "PKTDMA_RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A."
hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x2C "PKTDMA_RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B."
hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x30 "PKTDMA_RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C."
hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x34 "PKTDMA_RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D."
hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x38 "PKTDMA_RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E."
hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x3C "PKTDMA_RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F."
hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
group.long 0x400++0xB
line.long 0x0 "PKTDMA_RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel."
line.long 0x4 "PKTDMA_RCHANRT_RRT_DCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x4 0.--31. 1. "DCNT,Current dropped packet count for the channel."
line.long 0x8 "PKTDMA_RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x8 0.--31. 1. "BCNT,Current completed payload byte count for the channel."
group.long 0x410++0x3
line.long 0x0 "PKTDMA_RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel."
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_RFLOW (DMASS0_PKTDMA_0_PKTDMA_RFLOW)"
base ad:0x48430000
group.long 0x0++0x3
line.long 0x0 "PKTDMA_RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in.."
bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear  the port DMA will clear the Extended Packet Info Present bit in.." "0,1"
bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear  the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1"
bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor starvation) occurs. 0 = Starvation errors result in dropping packet and incrementing dropped packet.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in the channel waiting.."
hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.."
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_RING (DMASS0_PKTDMA_0_PKTDMA_RING)"
base ad:0x485E0000
group.long 0x40++0xB
line.long 0x0 "PKTDMA_RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will reset.."
hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)"
line.long 0x4 "PKTDMA_RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will reset.."
hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select"
hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)"
line.long 0x8 "PKTDMA_RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and reset the pointers."
bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements."
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_RINGRT (DMASS0_PKTDMA_0_PKTDMA_RINGRT)"
base ad:0x4B800000
group.long 0x10++0x3
line.long 0x0 "PKTDMA_RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation."
hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation  this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.."
group.long 0x18++0x3
line.long 0x0 "PKTDMA_RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be.."
hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed."
group.long 0x1010++0x3
line.long 0x0 "PKTDMA_RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation."
bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation  this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.."
group.long 0x1018++0x3
line.long 0x0 "PKTDMA_RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be.."
bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1"
hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed."
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_TCHAN (DMASS0_PKTDMA_0_PKTDMA_TCHAN)"
base ad:0x484A0000
group.long 0x0++0x3
line.long 0x0 "PKTDMA_TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)."
bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.."
newline
bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,1: DMA controller will filter extended packet info.."
newline
bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,1: DMA controller will filter PS words"
newline
hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 2 = Channel.."
newline
bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 1 = 64 Bytes 2 = 128 Bytes All other values are reserved" "?,1: 64 Bytes,2: 128 Bytes All other values are reserved,?"
newline
bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.."
newline
bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet"
group.long 0x64++0x7
line.long 0x0 "PKTDMA_TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface."
bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel."
line.long 0x4 "PKTDMA_TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register."
hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel."
group.long 0x70++0x3
line.long 0x0 "PKTDMA_TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be artificially reduced.."
hexmask.long.byte 0x0 0.--7. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width but must be greater than 32 bytes + the burst size  the maximum.."
group.long 0x80++0x3
line.long 0x0 "PKTDMA_TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this.."
bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.."
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_TCHANRT (DMASS0_PKTDMA_0_PKTDMA_TCHANRT)"
base ad:0x4AA00000
group.long 0x0++0x3
line.long 0x0 "PKTDMA_TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation."
bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.."
bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1"
bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1"
bitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1"
rgroup.long 0x40++0x7
line.long 0x0 "PKTDMA_TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits."
bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
newline
bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1"
newline
bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x4 "PKTDMA_TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits."
bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x4 26. "SOP_WAVAIL,The FIFO has space for the start of a packet" "0,1"
bitfld.long 0x4 25. "MOP_WAVAIL,The FIFO has space for the middle of a packet" "0,1"
bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1"
newline
bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to attempt to teardown" "0,1"
bitfld.long 0x4 7. "CHANNEL_OK,The channel is trying to schedule work" "0,1"
bitfld.long 0x4 6. "CHANNEL_BUSY,The channel has active work" "0,1"
bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1"
group.long 0x80++0x3
line.long 0x0 "PKTDMA_TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.."
hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table"
group.long 0x200++0x3F
line.long 0x0 "PKTDMA_TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400."
hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x4 "PKTDMA_TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401."
hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x8 "PKTDMA_TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402."
hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0xC "PKTDMA_TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403."
hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x10 "PKTDMA_TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404."
hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x14 "PKTDMA_TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405."
hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x18 "PKTDMA_TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406."
hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x1C "PKTDMA_TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407."
hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x20 "PKTDMA_TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408."
hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x24 "PKTDMA_TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409."
hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x28 "PKTDMA_TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A."
hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x2C "PKTDMA_TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B."
hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x30 "PKTDMA_TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C."
hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x34 "PKTDMA_TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D."
hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x38 "PKTDMA_TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E."
hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
line.long 0x3C "PKTDMA_TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F."
hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)."
group.long 0x400++0x3
line.long 0x0 "PKTDMA_TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel."
group.long 0x408++0x3
line.long 0x0 "PKTDMA_TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel."
group.long 0x410++0x3
line.long 0x0 "PKTDMA_TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel."
hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel."
tree.end
tree.end
tree "DMASS0_PSILCFG_0_PSILCFG_PROXY (DMASS0_PSILCFG_0_PSILCFG_PROXY)"
base ad:0x48130000
rgroup.long 0x0++0x3
line.long 0x0 "PSILCFG_PROXY_REVISION,The Revision Register contains the major and minor revisions for the module."
hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision"
group.long 0x10++0x3
line.long 0x0 "PSILCFG_PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy."
bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set  this bit is persistent until manually cleared" "0,1"
hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit"
group.long 0x100++0xB
line.long 0x0 "PSILCFG_PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction."
bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1"
bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1"
bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1"
hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent"
line.long 0x4 "PSILCFG_PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction."
hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write"
hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction"
line.long 0x8 "PSILCFG_PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction."
hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written"
group.long 0x140++0x3
line.long 0x0 "PSILCFG_PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction."
hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read"
tree.end
base ad:0x0
tree "DMASS0_PSILSS_0"
tree "DMASS0_PSILSS_0_ETLSW_MMRS (DMASS0_PSILSS_0_ETLSW_MMRS)"
base ad:0x48230000
rgroup.long 0x0++0x7
line.long 0x0 "ETLSW_MMRS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "ETLSW_MMRS_config,The Config Register shows configured params."
hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported."
group.long 0x10++0x3
line.long 0x0 "ETLSW_MMRS_event,The Event Register defines the event to produce for a link down event."
hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce."
rgroup.long 0x20++0x3
line.long 0x0 "ETLSW_MMRS_link,The Link Register shows the current status of the endpoint links."
hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links."
group.long 0x40++0x3
line.long 0x0 "ETLSW_MMRS_down,The Link Down Register shows which links are down for the endpoints."
hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links."
tree.end
tree "DMASS0_PSILSS_0_PSILSS_MMRS (DMASS0_PSILSS_0_PSILSS_MMRS)"
base ad:0x48140000
rgroup.long 0x0++0x7
line.long 0x0 "PSILSS_MMRS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "PSILSS_MMRS_config,The Config Register shows configured params."
hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported."
group.long 0x10++0x3
line.long 0x0 "PSILSS_MMRS_event,The Event Register defines the event to produce for a link down event."
hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce."
rgroup.long 0x20++0x3
line.long 0x0 "PSILSS_MMRS_link,The Link Register shows the current status of the endpoint links."
hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links."
group.long 0x40++0x3
line.long 0x0 "PSILSS_MMRS_down,The Link Down Register shows which links are down for the endpoints."
hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links."
tree.end
tree.end
tree "DMASS0_RINGACC_0_RINGACC"
tree "DMASS0_RINGACC_0_RINGACC_CFG (DMASS0_RINGACC_0_RINGACC_CFG)"
base ad:0x49800000
group.long 0x40++0x13
line.long 0x0 "RINGACC_CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring. or to.."
hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)"
line.long 0x4 "RINGACC_CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring. or to.."
hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)"
line.long 0x8 "RINGACC_CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies.."
bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3"
bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "0: 4 bytes,1: 8 bytes,2: 16 bytes,3: 32 bytes,4: 64 bytes,5: 128 bytes,6: 256 bytes,7: RESERVED"
hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number."
line.long 0xC "RINGACC_CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring."
hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue."
line.long 0x10 "RINGACC_CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access."
bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.."
hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue."
tree.end
tree "DMASS0_RINGACC_0_RINGACC_GCFG (DMASS0_RINGACC_0_RINGACC_GCFG)"
base ad:0x48240000
rgroup.long 0x0++0x3
line.long 0x0 "RINGACC_GCFG_revision,The Revision Register contains the major and minor revisions for the module."
hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision"
group.long 0x10++0x3
line.long 0x0 "RINGACC_GCFG_trace_ctl,Trace Control Register"
bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable"
bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue"
bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data"
hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue."
group.long 0x20++0x3
line.long 0x0 "RINGACC_GCFG_overflow,Overflow Queue Register"
hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function."
group.long 0x40++0x3
line.long 0x0 "RINGACC_GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error."
hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error."
rgroup.long 0x44++0x3
line.long 0x0 "RINGACC_GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event is pending."
bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push"
hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error."
tree.end
tree "DMASS0_RINGACC_0_RINGACC_ISC (DMASS0_RINGACC_0_RINGACC_ISC)"
base ad:0x45848000
group.long 0x0++0x7
line.long 0x0 "RINGACC_ISC_ISC_control,The ISC a Region b Control Register defines the control fields for the ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared. Has precedence over priv set bits." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure. Has precedence over secure enable bits." "0,1"
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
line.long 0x4 "RINGACC_ISC_ISC_control2,The ISC a Region b Control Register 2 defines the control fields for the ISC."
bitfld.long 0x4 31. "PASS_V,No virtID replacement  pass through value." "0,1"
bitfld.long 0x4 28.--29. "ATYPE,Defines the output address type. 0 = physical no memory attributes. 1 = intermediate. 2 = virtual. 3 = physical with memory attributes." "0: physical no memory attributes,1: intermediate,2: virtual,3: physical with memory attributes"
hexmask.long.word 0x4 16.--27. 1. "VIRTID,Virt ID."
tree.end
tree "DMASS0_RINGACC_0_RINGACC_RT (DMASS0_RINGACC_0_RINGACC_RT)"
base ad:0x49000000
group.long 0x10++0x3
line.long 0x0 "RINGACC_RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation."
hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation  this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.."
group.long 0x18++0xF
line.long 0x0 "RINGACC_RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be used.."
hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed."
line.long 0x4 "RINGACC_RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel."
hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.."
line.long 0x8 "RINGACC_RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for.."
hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed."
line.long 0xC "RINGACC_RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel."
hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.."
tree.end
tree "DMASS0_RINGACC_0_RINGACC_SRC_FIFOS (DMASS0_RINGACC_0_RINGACC_SRC_FIFOS)"
base ad:0x4E000000
group.long 0x0++0x3
line.long 0x0 "RINGACC__SRC__FIFOS_RING_HEAD_DATA,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are used to access.."
hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data"
group.long 0x200++0x3
line.long 0x0 "RINGACC__SRC__FIFOS_RING_TAIL_DATA,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are used to access.."
hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data"
group.long 0x400++0x3
line.long 0x0 "RINGACC__SRC__FIFOS_PEEK_HEAD_DATA,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address locations that are.."
hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode."
group.long 0x600++0x3
line.long 0x0 "RINGACC__SRC__FIFOS_PEEK_TAIL_DATA,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address locations that are.."
hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head or tail element data. Reserved for rings in ring mode."
tree.end
tree.end
tree.end
tree "ECAP"
base ad:0x0
tree "ECAP0_CTL_STS (ECAP0_CTL_STS)"
base ad:0x23100000
group.long 0x0++0x17
line.long 0x0 "CTL_STS_TSCNT,"
hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32 bit Counter register which is used as the Capture time-base"
line.long 0x4 "CTL_STS_CNTPHS,"
hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter Phase value register that can be programmed for phase Lag/Lead. This register shadows TSCNT and is loaded into TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve Phase control sync with respect to other ECAP.."
line.long 0x8 "CTL_STS_CAP1,"
hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes / initialisation 3. APRD shadow register (i.e. CAP3) when used in APWM mode"
line.long 0xC "CTL_STS_CAP2,"
hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes 3. ACMP shadow register (i.e. CAP4) when used in APWM mode"
line.long 0x10 "CTL_STS_CAP3,"
hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register In APMW mode this is the Period Shadow (APER) register. User updates the PWM Period value via this register. In this mode CAP3 (APRD) shadows CAP1"
line.long 0x14 "CTL_STS_CAP4,"
hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register In APMW mode this is the Compare Shadow (ACMP) register. User updates the PWM Compare value via this register. In this mode CAP4 (ACMP) shadows CAP2"
group.long 0x28++0xB
line.long 0x0 "CTL_STS_ECCTL,"
hexmask.long.byte 0x0 27.--31. 1. "FILTER,"
bitfld.long 0x0 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1"
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bitfld.long 0x0 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1"
bitfld.long 0x0 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1"
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bitfld.long 0x0 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3"
bitfld.long 0x0 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event." "0,1"
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bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1"
bitfld.long 0x0 19. "REARM_RESET,One-Shot Re-arming  i.e. Wait for stop Trigger: Writing a One Arms the One-Shot sequence  i.e.: 1. Resets the Mod4 counter to zero 2. Un-freezes the Mod4 counter 3. Enables Capture Register Loads; Writing a zero has no effect. Reading always.." "0,1"
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bitfld.long 0x0 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen  i.e.Capture sequence is stopped. 2'b00 Stop after Capture Event 1; 2'b01 Stop after Capture Event 2; 2'b10.." "0,1,2,3"
bitfld.long 0x0 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1"
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bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3"
hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale  by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10; . . . . .; 5'b11110 divide by 60;.."
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bitfld.long 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1"
bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4: 1'b0 Do Not reset Counter on Capture Event 4 (absolute time stamp); 1'b1 Reset Counter after Event 4 time-stamp has been captured (used in Difference mode operation)" "?,?"
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bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3: 1'b0 Do Not reset Counter on Capture Event 3 (absolute time stamp); 1'b1 Reset Counter after Event 3 time-stamp has been captured (used in Difference mode operation)" "?,?"
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bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2: 1'b0 Do Not reset Counter on Capture Event 2 (absolute time stamp); 1'b1 Reset Counter after Event 2 time-stamp has been captured (used in Difference mode operation)" "?,?"
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bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1: 1'b0 Do Not reset Counter on Capture Event 1 (absolute time stamp); 1'b1 Reset Counter after Event 1 time-stamp has been captured (used in Difference mode operation)" "?,1: 1'b0 Do Not reset Counter on Capture Event 1"
newline
bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1"
line.long 0x4 "CTL_STS_ECINT_EN_FLG,"
rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode." "0,1"
rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset. Reading a 0 indicates no event occurred Notes: This flag is only active in APWM mode." "0,1"
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rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred. Note: This flag is active in CAP & APWM mode." "0,1"
rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
newline
rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
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rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1"
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bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1"
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bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1"
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bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1"
newline
bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1"
line.long 0x8 "CTL_STS_ECINT_CLR_FRC,"
bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1"
bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1"
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bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1"
bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4: Writing a 1 to this bit will set the CEVT4 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?"
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bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3: Writing a 1 to this bit will set the CEVT3 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?"
bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2: Writing a 1 to this bit will set the CEVT2 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?"
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bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1: Writing a 1 to this bit will set the CEVT1 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,1: Writing a 1 to this bit will set the CEVT1 flag.."
bitfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
bitfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
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bitfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
bitfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
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bitfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
bitfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Writing a 0 will have no effect. Always reads back a 0." "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "CTL_STS_PID,"
bitfld.long 0x0 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,"
hexmask.long.byte 0x0 11.--15. 1. "RTL,"
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bitfld.long 0x0 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM," "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,"
tree.end
tree "ECAP1_CTL_STS (ECAP1_CTL_STS)"
base ad:0x23110000
group.long 0x0++0x17
line.long 0x0 "CTL_STS_TSCNT,"
hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32 bit Counter register which is used as the Capture time-base"
line.long 0x4 "CTL_STS_CNTPHS,"
hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter Phase value register that can be programmed for phase Lag/Lead. This register shadows TSCNT and is loaded into TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve Phase control sync with respect to other ECAP.."
line.long 0x8 "CTL_STS_CAP1,"
hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes / initialisation 3. APRD shadow register (i.e. CAP3) when used in APWM mode"
line.long 0xC "CTL_STS_CAP2,"
hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes 3. ACMP shadow register (i.e. CAP4) when used in APWM mode"
line.long 0x10 "CTL_STS_CAP3,"
hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register In APMW mode this is the Period Shadow (APER) register. User updates the PWM Period value via this register. In this mode CAP3 (APRD) shadows CAP1"
line.long 0x14 "CTL_STS_CAP4,"
hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register In APMW mode this is the Compare Shadow (ACMP) register. User updates the PWM Compare value via this register. In this mode CAP4 (ACMP) shadows CAP2"
group.long 0x28++0xB
line.long 0x0 "CTL_STS_ECCTL,"
hexmask.long.byte 0x0 27.--31. 1. "FILTER,"
bitfld.long 0x0 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1"
newline
bitfld.long 0x0 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1"
bitfld.long 0x0 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1"
newline
bitfld.long 0x0 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3"
bitfld.long 0x0 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event." "0,1"
newline
bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1"
bitfld.long 0x0 19. "REARM_RESET,One-Shot Re-arming  i.e. Wait for stop Trigger: Writing a One Arms the One-Shot sequence  i.e.: 1. Resets the Mod4 counter to zero 2. Un-freezes the Mod4 counter 3. Enables Capture Register Loads; Writing a zero has no effect. Reading always.." "0,1"
newline
bitfld.long 0x0 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen  i.e.Capture sequence is stopped. 2'b00 Stop after Capture Event 1; 2'b01 Stop after Capture Event 2; 2'b10.." "0,1,2,3"
bitfld.long 0x0 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1"
newline
bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3"
hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale  by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10; . . . . .; 5'b11110 divide by 60;.."
newline
bitfld.long 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1"
bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4: 1'b0 Do Not reset Counter on Capture Event 4 (absolute time stamp); 1'b1 Reset Counter after Event 4 time-stamp has been captured (used in Difference mode operation)" "?,?"
newline
bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3: 1'b0 Do Not reset Counter on Capture Event 3 (absolute time stamp); 1'b1 Reset Counter after Event 3 time-stamp has been captured (used in Difference mode operation)" "?,?"
newline
bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2: 1'b0 Do Not reset Counter on Capture Event 2 (absolute time stamp); 1'b1 Reset Counter after Event 2 time-stamp has been captured (used in Difference mode operation)" "?,?"
newline
bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1: 1'b0 Do Not reset Counter on Capture Event 1 (absolute time stamp); 1'b1 Reset Counter after Event 1 time-stamp has been captured (used in Difference mode operation)" "?,1: 1'b0 Do Not reset Counter on Capture Event 1"
newline
bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1"
line.long 0x4 "CTL_STS_ECINT_EN_FLG,"
rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode." "0,1"
rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset. Reading a 0 indicates no event occurred Notes: This flag is only active in APWM mode." "0,1"
newline
rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred. Note: This flag is active in CAP & APWM mode." "0,1"
rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
newline
rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
newline
rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1"
newline
bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1"
newline
bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1"
newline
bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1"
newline
bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1"
line.long 0x8 "CTL_STS_ECINT_CLR_FRC,"
bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1"
bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1"
bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4: Writing a 1 to this bit will set the CEVT4 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?"
newline
bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3: Writing a 1 to this bit will set the CEVT3 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?"
bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2: Writing a 1 to this bit will set the CEVT2 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?"
newline
bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1: Writing a 1 to this bit will set the CEVT1 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,1: Writing a 1 to this bit will set the CEVT1 flag.."
bitfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
bitfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
bitfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
bitfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Writing a 0 will have no effect. Always reads back a 0." "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "CTL_STS_PID,"
bitfld.long 0x0 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,"
hexmask.long.byte 0x0 11.--15. 1. "RTL,"
newline
bitfld.long 0x0 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM," "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,"
tree.end
tree "ECAP2_CTL_STS (ECAP2_CTL_STS)"
base ad:0x23120000
group.long 0x0++0x17
line.long 0x0 "CTL_STS_TSCNT,"
hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32 bit Counter register which is used as the Capture time-base"
line.long 0x4 "CTL_STS_CNTPHS,"
hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter Phase value register that can be programmed for phase Lag/Lead. This register shadows TSCNT and is loaded into TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve Phase control sync with respect to other ECAP.."
line.long 0x8 "CTL_STS_CAP1,"
hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes / initialisation 3. APRD shadow register (i.e. CAP3) when used in APWM mode"
line.long 0xC "CTL_STS_CAP2,"
hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes 3. ACMP shadow register (i.e. CAP4) when used in APWM mode"
line.long 0x10 "CTL_STS_CAP3,"
hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register In APMW mode this is the Period Shadow (APER) register. User updates the PWM Period value via this register. In this mode CAP3 (APRD) shadows CAP1"
line.long 0x14 "CTL_STS_CAP4,"
hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register In APMW mode this is the Compare Shadow (ACMP) register. User updates the PWM Compare value via this register. In this mode CAP4 (ACMP) shadows CAP2"
group.long 0x28++0xB
line.long 0x0 "CTL_STS_ECCTL,"
hexmask.long.byte 0x0 27.--31. 1. "FILTER,"
bitfld.long 0x0 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1"
newline
bitfld.long 0x0 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1"
bitfld.long 0x0 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1"
newline
bitfld.long 0x0 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3"
bitfld.long 0x0 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event." "0,1"
newline
bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1"
bitfld.long 0x0 19. "REARM_RESET,One-Shot Re-arming  i.e. Wait for stop Trigger: Writing a One Arms the One-Shot sequence  i.e.: 1. Resets the Mod4 counter to zero 2. Un-freezes the Mod4 counter 3. Enables Capture Register Loads; Writing a zero has no effect. Reading always.." "0,1"
newline
bitfld.long 0x0 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen  i.e.Capture sequence is stopped. 2'b00 Stop after Capture Event 1; 2'b01 Stop after Capture Event 2; 2'b10.." "0,1,2,3"
bitfld.long 0x0 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1"
newline
bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3"
hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale  by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10; . . . . .; 5'b11110 divide by 60;.."
newline
bitfld.long 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1"
bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4: 1'b0 Do Not reset Counter on Capture Event 4 (absolute time stamp); 1'b1 Reset Counter after Event 4 time-stamp has been captured (used in Difference mode operation)" "?,?"
newline
bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3: 1'b0 Do Not reset Counter on Capture Event 3 (absolute time stamp); 1'b1 Reset Counter after Event 3 time-stamp has been captured (used in Difference mode operation)" "?,?"
newline
bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2: 1'b0 Do Not reset Counter on Capture Event 2 (absolute time stamp); 1'b1 Reset Counter after Event 2 time-stamp has been captured (used in Difference mode operation)" "?,?"
newline
bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1: 1'b0 Do Not reset Counter on Capture Event 1 (absolute time stamp); 1'b1 Reset Counter after Event 1 time-stamp has been captured (used in Difference mode operation)" "?,1: 1'b0 Do Not reset Counter on Capture Event 1"
newline
bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1"
line.long 0x4 "CTL_STS_ECINT_EN_FLG,"
rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode." "0,1"
rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset. Reading a 0 indicates no event occurred Notes: This flag is only active in APWM mode." "0,1"
newline
rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred. Note: This flag is active in CAP & APWM mode." "0,1"
rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
newline
rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
newline
rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1"
rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1"
newline
bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1"
newline
bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1"
newline
bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1"
newline
bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1"
line.long 0x8 "CTL_STS_ECINT_CLR_FRC,"
bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1"
bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1"
bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4: Writing a 1 to this bit will set the CEVT4 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?"
newline
bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3: Writing a 1 to this bit will set the CEVT3 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?"
bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2: Writing a 1 to this bit will set the CEVT2 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?"
newline
bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1: Writing a 1 to this bit will set the CEVT1 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,1: Writing a 1 to this bit will set the CEVT1 flag.."
bitfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
bitfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
bitfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
bitfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1"
newline
bitfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Writing a 0 will have no effect. Always reads back a 0." "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "CTL_STS_PID,"
bitfld.long 0x0 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,"
hexmask.long.byte 0x0 11.--15. 1. "RTL,"
newline
bitfld.long 0x0 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM," "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,"
tree.end
tree.end
tree "ECC"
base ad:0x0
tree "ECC_AGGR0_ECC_AGGR (ECC_AGGR0_ECC_AGGR)"
base ad:0x3F00F000
rgroup.long 0x0++0x3
line.long 0x0 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 2. "ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_PEND,Interrupt Pending Status for Itimer_mgr1024_main_0__efifo_ramecc_pend" "0,1"
bitfld.long 0x4 1. "ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_PEND,Interrupt Pending Status for Itimer_mgr1024_main_0__reprog_fsm_ramecc_pend" "0,1"
newline
bitfld.long 0x4 0. "ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_PEND,Interrupt Pending Status for Itimer_mgr1024_main_0__timer_fsm_ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 2. "ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Itimer_mgr1024_main_0__efifo_ramecc_pend" "0,1"
bitfld.long 0x0 1. "ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Itimer_mgr1024_main_0__reprog_fsm_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Itimer_mgr1024_main_0__timer_fsm_ramecc_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 2. "ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Itimer_mgr1024_main_0__efifo_ramecc_pend" "0,1"
bitfld.long 0x0 1. "ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Itimer_mgr1024_main_0__reprog_fsm_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Itimer_mgr1024_main_0__timer_fsm_ramecc_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 2. "ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_PEND,Interrupt Pending Status for Itimer_mgr1024_main_0__efifo_ramecc_pend" "0,1"
bitfld.long 0x4 1. "ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_PEND,Interrupt Pending Status for Itimer_mgr1024_main_0__reprog_fsm_ramecc_pend" "0,1"
newline
bitfld.long 0x4 0. "ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_PEND,Interrupt Pending Status for Itimer_mgr1024_main_0__timer_fsm_ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 2. "ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Itimer_mgr1024_main_0__efifo_ramecc_pend" "0,1"
bitfld.long 0x0 1. "ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Itimer_mgr1024_main_0__reprog_fsm_ramecc_pend" "0,1"
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bitfld.long 0x0 0. "ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for Itimer_mgr1024_main_0__timer_fsm_ramecc_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 2. "ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Itimer_mgr1024_main_0__efifo_ramecc_pend" "0,1"
bitfld.long 0x0 1. "ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Itimer_mgr1024_main_0__reprog_fsm_ramecc_pend" "0,1"
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bitfld.long 0x0 0. "ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Itimer_mgr1024_main_0__timer_fsm_ramecc_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "ECC_AGGR1_ECC_AGGR (ECC_AGGR1_ECC_AGGR)"
base ad:0x701000
rgroup.long 0x0++0x3
line.long 0x0 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
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hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 5. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Iam64_main_fw_cbass_main_0_am64_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1"
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bitfld.long 0x4 4. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 3. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 2. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 1. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 0. "IMAILBOX8_MAIN_0__RAMECC_PEND,Interrupt Pending Status for Imailbox8_main_0__ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 5. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 4. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 3. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 2. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 1. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 0. "IMAILBOX8_MAIN_0__RAMECC_ENABLE_SET,Interrupt Enable Set Register for Imailbox8_main_0__ramecc_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 5. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 4. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 3. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 2. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 1. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 0. "IMAILBOX8_MAIN_0__RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Imailbox8_main_0__ramecc_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 5. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for Iam64_main_fw_cbass_main_0_am64_main_fw_cbass_main_SYSCLK0_4_clk_edc_ctrl_cbass_int_main_SYSCLK0_4_busecc_pend" "0,1"
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bitfld.long 0x4 4. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 3. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 2. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 1. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 0. "IMAILBOX8_MAIN_0__RAMECC_PEND,Interrupt Pending Status for Imailbox8_main_0__ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 5. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 4. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 3. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 2. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 1. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 0. "IMAILBOX8_MAIN_0__RAMECC_ENABLE_SET,Interrupt Enable Set Register for Imailbox8_main_0__ramecc_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 5. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 4. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 3. "IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 2. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x0 1. "IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 0. "IMAILBOX8_MAIN_0__RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for Imailbox8_main_0__ramecc_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "ELM0 (ELM0)"
base ad:0x25010000
rgroup.long 0x0++0x3
line.long 0x0 "MEM_ELM_REVISION,This register contains the IP revision code."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_0,Read returns 0"
hexmask.long.byte 0x0 0.--7. 1. "REV_NUMBER,IP revision number [RTL] [7:4] Major revision [3:0] Minor revision"
group.long 0x10++0x3
line.long 0x0 "MEM_ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
bitfld.long 0x0 8. "CLOCKACTIVITYOCP,OCP Clock activity when module is in IDLE mode [during wake up mode period]" "0,1"
bitfld.long 0x0 3.--4. "SIDLEMODE,Slave interface power management [IDLE req/ack control]" "0,1,2,3"
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bitfld.long 0x0 1. "SOFTRESET,Module Software Reset The bit is automatically reset by the hardware [During reads  it always returns 0] It has same effect as the OCP Hardware reset" "0,1"
bitfld.long 0x0 0. "AUTOGATING,Internal OCP clock gating strategy [no module visible impact other than saving power]" "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_ELM_SYSSTATUS,Internal Reset monitoring (OCP domain)"
bitfld.long 0x0 0. "RESETDONE,Internal Reset monitoring [OCP domain] Undefined since: on HW perspective reset state is 0 on SW user perspective when module is accessible is 1" "0,1"
group.long 0x18++0xB
line.long 0x0 "MEM_ELM_IRQSTATUS,Interrupt status. This register doubles as a status register for the error location processes."
bitfld.long 0x0 8. "PAGE_VALID,Error location status for a full page  based on the mask definition Read 0x0: error locations invalid for all polynomials enabled in the ECC_INTERRUPT_MASK register Read 0x1: all error locations valid Write 0x0: no effect Write 0x1: clear.." "0: no effect Write,1: clear interrupt"
bitfld.long 0x0 7. "LOC_VALID_7,Error location status for syndrome polynomial 7 Read 0x0: no syndrome processed or process in progress Read 0x1: error location process completed Write 0x0: no effect Write 0x1: clear interrupt" "0: no effect Write,1: clear interrupt"
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bitfld.long 0x0 6. "LOC_VALID_6,Error location status for syndrome polynomial 6" "0,1"
bitfld.long 0x0 5. "LOC_VALID_5,Error location status for syndrome polynomial 5" "0,1"
newline
bitfld.long 0x0 4. "LOC_VALID_4,Error location status for syndrome polynomial 4" "0,1"
bitfld.long 0x0 3. "LOC_VALID_3,Error location status for syndrome polynomial 3" "0,1"
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bitfld.long 0x0 2. "LOC_VALID_2,Error location status for syndrome polynomial 2" "0,1"
bitfld.long 0x0 1. "LOC_VALID_1,Error location status for syndrome polynomial 1" "0,1"
newline
bitfld.long 0x0 0. "LOC_VALID_0,Error location status for syndrome polynomial 0" "0,1"
line.long 0x4 "MEM_ELM_IRQENABLE,Interrupt enable"
bitfld.long 0x4 8. "PAGE_MASK,Page interrupt mask bit 0: disable interrupt 1: enable interrupt" "0: disable interrupt,1: enable interrupt"
bitfld.long 0x4 7. "LOCATION_MASK_7,Error location interrupt mask bit for syndrome polynomial 7" "0,1"
newline
bitfld.long 0x4 6. "LOCATION_MASK_6,Error location interrupt mask bit for syndrome polynomial 6" "0,1"
bitfld.long 0x4 5. "LOCATION_MASK_5,Error location interrupt mask bit for syndrome polynomial 5" "0,1"
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bitfld.long 0x4 4. "LOCATION_MASK_4,Error location interrupt mask bit for syndrome polynomial 4" "0,1"
bitfld.long 0x4 3. "LOCATION_MASK_3,Error location interrupt mask bit for syndrome polynomial 3" "0,1"
newline
bitfld.long 0x4 2. "LOCATION_MASK_2,Error location interrupt mask bit for syndrome polynomial 2" "0,1"
bitfld.long 0x4 1. "LOCATION_MASK_1,Error location interrupt mask bit for syndrome polynomial 1" "0,1"
newline
bitfld.long 0x4 0. "LOCATION_MASK_0,Error location interrupt mask bit for syndrome polynomial 0 0: disable interrupt 1: enable interrupt" "0: disable interrupt,1: enable interrupt"
line.long 0x8 "MEM_ELM_LOCATION_CONFIG,ECC algorithm parameters"
hexmask.long.word 0x8 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error location engine is used  in number of nibbles [4-bits entities]"
bitfld.long 0x8 0.--1. "ECC_BCH_LEVEL,Error correction level 0x0: 4 bits 0x1: 8 bits 0x2: 16 bits 0x3: reserved" "0: 4 bits,1: 8 bits,2: 16 bits,3: reserved"
group.long 0x80++0x3
line.long 0x0 "MEM_ELM_PAGE_CTRL,Page definition"
bitfld.long 0x0 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x0 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode Must be 0 in continuous mode" "0,1"
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bitfld.long 0x0 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x0 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode Must be 0 in continuous mode" "0,1"
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bitfld.long 0x0 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x0 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode Must be 0 in continuous mode" "0,1"
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bitfld.long 0x0 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x0 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode Must be 0 in continuous mode" "0,1"
group.long 0x400++0x1B
line.long 0x0 "MEM_ELM_SYNDROME_FRAGMENT_0,Input syndrome polynomial bits 0 to 31."
hexmask.long 0x0 0.--31. 1. "SYNDROME_0,Syndrome bits 0 to 31"
line.long 0x4 "MEM_ELM_SYNDROME_FRAGMENT_1,Input syndrome polynomial bits 32 to 63."
hexmask.long 0x4 0.--31. 1. "SYNDROME_1,Syndrome bits 32 to 63"
line.long 0x8 "MEM_ELM_SYNDROME_FRAGMENT_2,Input syndrome polynomial bits 64 to 95."
hexmask.long 0x8 0.--31. 1. "SYNDROME_2,Syndrome bits 64 to 95"
line.long 0xC "MEM_ELM_SYNDROME_FRAGMENT_3,Input syndrome polynomial bits 96 to 127"
hexmask.long 0xC 0.--31. 1. "SYNDROME_3,Syndrome bits 96 to 127"
line.long 0x10 "MEM_ELM_SYNDROME_FRAGMENT_4,Input syndrome polynomial bits 128 to 159."
hexmask.long 0x10 0.--31. 1. "SYNDROME_4,Syndrome bits 128 to 159"
line.long 0x14 "MEM_ELM_SYNDROME_FRAGMENT_5,Input syndrome polynomial bits 160 to 191."
hexmask.long 0x14 0.--31. 1. "SYNDROME_5,Syndrome bits 160 to 191"
line.long 0x18 "MEM_ELM_SYNDROME_FRAGMENT_6,Input syndrome polynomial bits 192 to 207."
bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit 0x0: this syndrome polynomial should not be processed 0x1: this syndrome polynomial must be processed" "0: this syndrome polynomial should not be processed,1: this syndrome polynomial must be processed"
hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207"
rgroup.long 0x800++0x3
line.long 0x0 "MEM_ELM_LOCATION_STATUS,Exit status for the syndrome polynomial processing"
bitfld.long 0x0 8. "ECC_CORRECTABLE,Error location process exit status 0x0: ECC error location process failed Number of errors and error locations are invalid 0x1: all errors were successfully located Number of errors and error locations are valid" "0: ECC error location process failed Number of..,1: all errors were successfully located Number of.."
hexmask.long.byte 0x0 0.--4. 1. "ECC_NB_ERRORS,Number of errors detected and located"
rgroup.long 0x880++0x3F
line.long 0x0 "MEM_ELM_ERROR_LOCATION_0,Error location register"
hexmask.long.word 0x0 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x4 "MEM_ELM_ERROR_LOCATION_1,Error location register"
hexmask.long.word 0x4 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x8 "MEM_ELM_ERROR_LOCATION_2,Error location register"
hexmask.long.word 0x8 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0xC "MEM_ELM_ERROR_LOCATION_3,Error location register"
hexmask.long.word 0xC 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x10 "MEM_ELM_ERROR_LOCATION_4,Error location register"
hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x14 "MEM_ELM_ERROR_LOCATION_5,Error location register"
hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x18 "MEM_ELM_ERROR_LOCATION_6,Error location register"
hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x1C "MEM_ELM_ERROR_LOCATION_7,Error location register"
hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x20 "MEM_ELM_ERROR_LOCATION_8,Error location register"
hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x24 "MEM_ELM_ERROR_LOCATION_9,Error location register"
hexmask.long.word 0x24 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x28 "MEM_ELM_ERROR_LOCATION_10,Error location register"
hexmask.long.word 0x28 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x2C "MEM_ELM_ERROR_LOCATION_11,Error location register"
hexmask.long.word 0x2C 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x30 "MEM_ELM_ERROR_LOCATION_12,Error location register"
hexmask.long.word 0x30 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x34 "MEM_ELM_ERROR_LOCATION_13,Error location register"
hexmask.long.word 0x34 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x38 "MEM_ELM_ERROR_LOCATION_14,Error location register"
hexmask.long.word 0x38 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
line.long 0x3C "MEM_ELM_ERROR_LOCATION_15,Error location register"
hexmask.long.word 0x3C 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
tree.end
tree "EPWM"
base ad:0x0
tree "EPWM0_EPWM (EPWM0_EPWM)"
base ad:0x23000000
group.word 0x0++0xB
line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3"
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1"
bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter  the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset  the counter is frozen  therefore  this bit has no meaning To make this bit meaningful  you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved."
hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0  then the synchronization event is ignored and the time-base counter is not loaded with.."
line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register"
hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.."
line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register"
hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0  then the shadow is enabled.."
group.word 0xE++0x17
line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1"
bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved."
hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register"
hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.."
line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register"
hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.."
line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms  the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low  a one-shot trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low  a cycle-by-cycle trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the.."
group.word 0x28++0x3
line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
rgroup.word 0x2C++0x1
line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
group.word 0x2E++0x7
line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled  ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated  the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
rgroup.word 0x36++0x5
line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
group.word 0x3C++0x1
line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width"
bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility."
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R]  maintained by IP design owner"
bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]"
tree.end
tree "EPWM1_EPWM (EPWM1_EPWM)"
base ad:0x23010000
group.word 0x0++0xB
line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3"
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1"
bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter  the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset  the counter is frozen  therefore  this bit has no meaning To make this bit meaningful  you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved."
hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0  then the synchronization event is ignored and the time-base counter is not loaded with.."
line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register"
hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.."
line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register"
hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0  then the shadow is enabled.."
group.word 0xE++0x17
line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1"
bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved."
hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register"
hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.."
line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register"
hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.."
line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms  the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low  a one-shot trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low  a cycle-by-cycle trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the.."
group.word 0x28++0x3
line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
rgroup.word 0x2C++0x1
line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
group.word 0x2E++0x7
line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled  ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated  the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
rgroup.word 0x36++0x5
line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
group.word 0x3C++0x1
line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width"
bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility."
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R]  maintained by IP design owner"
bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]"
tree.end
tree "EPWM2_EPWM (EPWM2_EPWM)"
base ad:0x23020000
group.word 0x0++0xB
line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3"
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1"
bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter  the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset  the counter is frozen  therefore  this bit has no meaning To make this bit meaningful  you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved."
hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0  then the synchronization event is ignored and the time-base counter is not loaded with.."
line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register"
hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.."
line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register"
hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0  then the shadow is enabled.."
group.word 0xE++0x17
line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1"
bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved."
hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register"
hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.."
line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register"
hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.."
line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms  the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low  a one-shot trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low  a cycle-by-cycle trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the.."
group.word 0x28++0x3
line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
rgroup.word 0x2C++0x1
line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
group.word 0x2E++0x7
line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled  ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated  the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
rgroup.word 0x36++0x5
line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
group.word 0x3C++0x1
line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width"
bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility."
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R]  maintained by IP design owner"
bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]"
tree.end
tree "EPWM3_EPWM (EPWM3_EPWM)"
base ad:0x23030000
group.word 0x0++0xB
line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3"
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1"
bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter  the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset  the counter is frozen  therefore  this bit has no meaning To make this bit meaningful  you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved."
hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0  then the synchronization event is ignored and the time-base counter is not loaded with.."
line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register"
hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.."
line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register"
hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0  then the shadow is enabled.."
group.word 0xE++0x17
line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1"
bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved."
hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register"
hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.."
line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register"
hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.."
line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms  the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low  a one-shot trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low  a cycle-by-cycle trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the.."
group.word 0x28++0x3
line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
rgroup.word 0x2C++0x1
line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
group.word 0x2E++0x7
line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled  ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated  the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
rgroup.word 0x36++0x5
line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
group.word 0x3C++0x1
line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width"
bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility."
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R]  maintained by IP design owner"
bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]"
tree.end
tree "EPWM4_EPWM (EPWM4_EPWM)"
base ad:0x23040000
group.word 0x0++0xB
line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3"
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1"
bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter  the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset  the counter is frozen  therefore  this bit has no meaning To make this bit meaningful  you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved."
hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0  then the synchronization event is ignored and the time-base counter is not loaded with.."
line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register"
hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.."
line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register"
hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0  then the shadow is enabled.."
group.word 0xE++0x17
line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1"
bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved."
hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register"
hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.."
line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register"
hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.."
line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms  the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low  a one-shot trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low  a cycle-by-cycle trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the.."
group.word 0x28++0x3
line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
rgroup.word 0x2C++0x1
line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
group.word 0x2E++0x7
line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled  ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated  the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
rgroup.word 0x36++0x5
line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
group.word 0x3C++0x1
line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width"
bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility."
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R]  maintained by IP design owner"
bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]"
tree.end
tree "EPWM5_EPWM (EPWM5_EPWM)"
base ad:0x23050000
group.word 0x0++0xB
line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3"
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1"
bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter  the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset  the counter is frozen  therefore  this bit has no meaning To make this bit meaningful  you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved."
hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0  then the synchronization event is ignored and the time-base counter is not loaded with.."
line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register"
hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.."
line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register"
hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0  then the shadow is enabled.."
group.word 0xE++0x17
line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1"
bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved."
hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register"
hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.."
line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register"
hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.."
line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms  the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low  a one-shot trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low  a cycle-by-cycle trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the.."
group.word 0x28++0x3
line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
rgroup.word 0x2C++0x1
line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
group.word 0x2E++0x7
line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled  ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated  the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
rgroup.word 0x36++0x5
line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
group.word 0x3C++0x1
line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width"
bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility."
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R]  maintained by IP design owner"
bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]"
tree.end
tree "EPWM6_EPWM (EPWM6_EPWM)"
base ad:0x23060000
group.word 0x0++0xB
line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3"
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1"
bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter  the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset  the counter is frozen  therefore  this bit has no meaning To make this bit meaningful  you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved."
hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0  then the synchronization event is ignored and the time-base counter is not loaded with.."
line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register"
hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.."
line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register"
hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0  then the shadow is enabled.."
group.word 0xE++0x17
line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1"
bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved."
hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register"
hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.."
line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register"
hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.."
line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms  the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low  a one-shot trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low  a cycle-by-cycle trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the.."
group.word 0x28++0x3
line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
rgroup.word 0x2C++0x1
line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
group.word 0x2E++0x7
line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled  ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated  the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
rgroup.word 0x36++0x5
line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
group.word 0x3C++0x1
line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width"
bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility."
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R]  maintained by IP design owner"
bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]"
tree.end
tree "EPWM7_EPWM (EPWM7_EPWM)"
base ad:0x23070000
group.word 0x0++0xB
line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3"
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1"
bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter  the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset  the counter is frozen  therefore  this bit has no meaning To make this bit meaningful  you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved."
hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0  then the synchronization event is ignored and the time-base counter is not loaded with.."
line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register"
hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.."
line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register"
hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0  then the shadow is enabled.."
group.word 0xE++0x17
line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1"
bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved."
hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register"
hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.."
line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register"
hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.."
line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms  the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low  a one-shot trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low  a cycle-by-cycle trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the.."
group.word 0x28++0x3
line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
rgroup.word 0x2C++0x1
line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
group.word 0x2E++0x7
line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled  ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated  the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
rgroup.word 0x36++0x5
line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
group.word 0x3C++0x1
line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width"
bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility."
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R]  maintained by IP design owner"
bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]"
tree.end
tree "EPWM8_EPWM (EPWM8_EPWM)"
base ad:0x23080000
group.word 0x0++0xB
line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3"
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1"
bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter  the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset  the counter is frozen  therefore  this bit has no meaning To make this bit meaningful  you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved."
hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0  then the synchronization event is ignored and the time-base counter is not loaded with.."
line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register"
hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.."
line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register"
hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0  then the shadow is enabled.."
group.word 0xE++0x17
line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1"
bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved."
hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register"
hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.."
line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register"
hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal  the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.."
line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition  in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition  in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode  a continuous force takes effect on the next TBCLK edge In shadow mode  a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms  the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low  a one-shot trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low  a cycle-by-cycle trip event occurs for this ePWM module When the event occurs  the action defined in the TZCTL register is taken on the.."
group.word 0x28++0x3
line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
rgroup.word 0x2C++0x1
line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
group.word 0x2E++0x7
line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled  ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated  the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
rgroup.word 0x36++0x5
line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
group.word 0x3C++0x1
line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width"
bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility."
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R]  maintained by IP design owner"
bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]"
tree.end
tree.end
tree "EQEP"
base ad:0x0
tree "EQEP0_REG (EQEP0_REG)"
base ad:0x23200000
group.long 0x0++0xF
line.long 0x0 "REG_QPOSCNT,Position Counter"
hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.."
line.long 0x4 "REG_QPOSINIT,Position Counter Init"
hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter InitThis register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.."
line.long 0x8 "REG_QPOSMAX,Maximum Position Count"
hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position CountThis register contains the maximum position counter value. Writes to this register should always be full 32-bit writes."
line.long 0xC "REG_QPOSCMP,Position Compare"
hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter [QPOSCNT] to generate sync output and/or interrupt on compare match."
rgroup.long 0x10++0xB
line.long 0x0 "REG_QPOSILAT,Index Position Latch"
hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits."
line.long 0x4 "REG_QPOSSLAT,Strobe Position Latch"
hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits."
line.long 0x8 "REG_QPOSLAT,Position Latch"
hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event."
group.long 0x1C++0x7
line.long 0x0 "REG_QUTMR,QEP Unit Timer"
hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit TimerThis register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated."
line.long 0x4 "REG_QUPRD,QEP Unit Period"
hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit PeriodThis register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.."
group.word 0x24++0xD
line.word 0x0 "REG_QWDTMR,QEP Watchdog Timer"
hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.."
line.word 0x2 "REG_QWDPRD,QEP Watchdog Period"
hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer.When the watchdog timer value matches the watchdog period value  a watchdog timeout interrupt is generated."
line.word 0x4 "REG_QDECCTL_TYPE2,Quadrature Decoder Control"
bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
bitfld.word 0x4 13. "SOEN,Sync output-enable" "0,1"
bitfld.word 0x4 12. "SPSEL,Sync output pin selection" "0,1"
bitfld.word 0x4 11. "XCR,External Clock Rate" "0,1"
bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
newline
bitfld.word 0x4 9. "IGATE,Index pulse gating option" "0,1"
bitfld.word 0x4 8. "QAP,QEPA input polarity" "0,1"
bitfld.word 0x4 7. "QBP,QEPB input polarity" "0,1"
bitfld.word 0x4 6. "QIP,QEPI input polarity" "0,1"
bitfld.word 0x4 5. "QSP,QEPS input polarity" "0,1"
newline
bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode  Behavior same as existing devices1 - Enhancement for Direction change during Index will be enabled" "0,1"
line.word 0x6 "REG_QEPCTL,QEP Control"
bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
bitfld.word 0x6 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3"
bitfld.word 0x6 8.--9. "IEI,Index event init of position count" "0,1,2,3"
bitfld.word 0x6 7. "SWI,Software init position counter" "0,1"
newline
bitfld.word 0x6 6. "SEL,Strobe event latch of position counter" "0,1"
bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3"
bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset" "0,1"
bitfld.word 0x6 2. "QCLM,QEP capture latch mode" "0,1"
bitfld.word 0x6 1. "UTE,QEP unit timer enable" "0,1"
newline
bitfld.word 0x6 0. "WDE,QEP watchdog enable" "0,1"
line.word 0x8 "REG_QCAPCTL,Qaudrature Capture Control"
bitfld.word 0x8 15. "CEN,Enable eQEP capture" "0,1"
bitfld.word 0x8 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler"
line.word 0xA "REG_QPOSCTL,Position Compare Control"
bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable" "0,1"
bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load" "0,1"
bitfld.word 0xA 13. "PCPOL,Polarity of sync output" "0,1"
bitfld.word 0xA 12. "PCE,Position compare enable/disable" "0,1"
hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width"
line.word 0xC "REG_QEINT_TYPE1,QEP Interrupt Control"
bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable" "0,1"
bitfld.word 0xC 11. "UTO,Unit time out interrupt enable" "0,1"
bitfld.word 0xC 10. "IEL,Index event latch interrupt enable" "0,1"
bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable" "0,1"
bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable" "0,1"
newline
bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable" "0,1"
bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable" "0,1"
bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable" "0,1"
bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable" "0,1"
bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable" "0,1"
newline
bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable" "0,1"
bitfld.word 0xC 1. "PCE,Position counter error interrupt enable" "0,1"
rgroup.word 0x32++0x1
line.word 0x0 "REG_QFLG_TYPE1,QEP Interrupt Flag"
bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag" "0,1"
bitfld.word 0x0 11. "UTO,Unit time out interrupt flag" "0,1"
bitfld.word 0x0 10. "IEL,Index event latch interrupt flag" "0,1"
bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag" "0,1"
bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag" "0,1"
newline
bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag" "0,1"
bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag" "0,1"
bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag" "0,1"
bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag" "0,1"
bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag" "0,1"
newline
bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0 1. "PCE,Position counter error interrupt flag" "0,1"
bitfld.word 0x0 0. "INT,Global interrupt status flag" "0,1"
group.word 0x34++0x9
line.word 0x0 "REG_QCLR_TYPE1,QEP Interrupt Clear"
bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag" "0,1"
bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag" "0,1"
bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag" "0,1"
bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
newline
bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
newline
bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag" "0,1"
bitfld.word 0x0 0. "INT,Global interrupt clear flag" "0,1"
line.word 0x2 "REG_QFRC_TYPE1,QEP Interrupt Force"
bitfld.word 0x2 12. "QMAE,Force QMA error interrupt" "0,1"
bitfld.word 0x2 11. "UTO,Force unit time out interrupt" "0,1"
bitfld.word 0x2 10. "IEL,Force index event latch interrupt" "0,1"
bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt" "0,1"
bitfld.word 0x2 8. "PCM,Force position-compare match interrupt" "0,1"
newline
bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt" "0,1"
bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt" "0,1"
bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt" "0,1"
bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt" "0,1"
bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt" "0,1"
newline
bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt" "0,1"
bitfld.word 0x2 1. "PCE,Force position counter error interrupt" "0,1"
line.word 0x4 "REG_QEPSTS_TYPE1,QEP Status"
bitfld.word 0x4 7. "UPEVNT,Unit position event flag" "0,1"
rbitfld.word 0x4 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker." "0,1"
rbitfld.word 0x4 5. "QDF,Quadrature direction flag" "0,1"
rbitfld.word 0x4 4. "QDLF,eQEP direction latch flag" "0,1"
bitfld.word 0x4 3. "COEF,Capture overflow error flag" "0,1"
newline
bitfld.word 0x4 2. "CDEF,Capture direction error flag" "0,1"
bitfld.word 0x4 1. "FIMF,First index marker flag" "0,1"
rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event." "0,1"
line.word 0x6 "REG_QCTMR,QEP Capture Timer"
hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit."
line.word 0x8 "REG_QCPRD,QEP Capture Period"
hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events"
rgroup.word 0x3E++0x3
line.word 0x0 "REG_QCTMRLAT,QEP Capture Latch"
hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz.  unit timeout event  reading the eQEP position counter."
line.word 0x2 "REG_QCPRDLAT,QEP Capture Period Latch"
hexmask.word 0x2 0.--15. 1. "QCPRDLAT,eQEP capture period value can be latched into this register on two events viz.  unit timeout event  reading the eQEP position counter."
group.word 0x42++0x1
line.word 0x0 "REG_Reserved_1,"
rgroup.long 0x60++0x3
line.long 0x0 "REG_REV_TYPE2,QEP Revision Number"
bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7"
group.long 0x64++0xB
line.long 0x0 "REG_QEPSTROBESEL,QEP Strobe select register"
bitfld.long 0x0 0.--1. "STROBESEL,Strobe source select:" "0,1,2,3"
line.long 0x4 "REG_QMACTRL,QMA Control register"
bitfld.long 0x4 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected010 : QMA Mode-2 operation selected011 : QMA Module is bypassed [reserved]1xx : QMA Module is bypassed [reserved]" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected010 : QMA Mode-2..,?,?,?,?,?,?"
line.long 0x8 "REG_QEPSRCSEL,QEP Source Select Register"
hexmask.long.byte 0x8 12.--15. 1. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent."
hexmask.long.byte 0x8 8.--11. 1. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent."
hexmask.long.byte 0x8 4.--7. 1. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent."
hexmask.long.byte 0x8 0.--3. 1. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent."
group.word 0x70++0x1
line.word 0x0 "REG_Reserved_2,"
tree.end
tree "EQEP1_REG (EQEP1_REG)"
base ad:0x23210000
group.long 0x0++0xF
line.long 0x0 "REG_QPOSCNT,Position Counter"
hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.."
line.long 0x4 "REG_QPOSINIT,Position Counter Init"
hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter InitThis register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.."
line.long 0x8 "REG_QPOSMAX,Maximum Position Count"
hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position CountThis register contains the maximum position counter value. Writes to this register should always be full 32-bit writes."
line.long 0xC "REG_QPOSCMP,Position Compare"
hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter [QPOSCNT] to generate sync output and/or interrupt on compare match."
rgroup.long 0x10++0xB
line.long 0x0 "REG_QPOSILAT,Index Position Latch"
hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits."
line.long 0x4 "REG_QPOSSLAT,Strobe Position Latch"
hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits."
line.long 0x8 "REG_QPOSLAT,Position Latch"
hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event."
group.long 0x1C++0x7
line.long 0x0 "REG_QUTMR,QEP Unit Timer"
hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit TimerThis register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated."
line.long 0x4 "REG_QUPRD,QEP Unit Period"
hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit PeriodThis register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.."
group.word 0x24++0xD
line.word 0x0 "REG_QWDTMR,QEP Watchdog Timer"
hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.."
line.word 0x2 "REG_QWDPRD,QEP Watchdog Period"
hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer.When the watchdog timer value matches the watchdog period value  a watchdog timeout interrupt is generated."
line.word 0x4 "REG_QDECCTL_TYPE2,Quadrature Decoder Control"
bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
bitfld.word 0x4 13. "SOEN,Sync output-enable" "0,1"
bitfld.word 0x4 12. "SPSEL,Sync output pin selection" "0,1"
bitfld.word 0x4 11. "XCR,External Clock Rate" "0,1"
bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
newline
bitfld.word 0x4 9. "IGATE,Index pulse gating option" "0,1"
bitfld.word 0x4 8. "QAP,QEPA input polarity" "0,1"
bitfld.word 0x4 7. "QBP,QEPB input polarity" "0,1"
bitfld.word 0x4 6. "QIP,QEPI input polarity" "0,1"
bitfld.word 0x4 5. "QSP,QEPS input polarity" "0,1"
newline
bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode  Behavior same as existing devices1 - Enhancement for Direction change during Index will be enabled" "0,1"
line.word 0x6 "REG_QEPCTL,QEP Control"
bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
bitfld.word 0x6 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3"
bitfld.word 0x6 8.--9. "IEI,Index event init of position count" "0,1,2,3"
bitfld.word 0x6 7. "SWI,Software init position counter" "0,1"
newline
bitfld.word 0x6 6. "SEL,Strobe event latch of position counter" "0,1"
bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3"
bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset" "0,1"
bitfld.word 0x6 2. "QCLM,QEP capture latch mode" "0,1"
bitfld.word 0x6 1. "UTE,QEP unit timer enable" "0,1"
newline
bitfld.word 0x6 0. "WDE,QEP watchdog enable" "0,1"
line.word 0x8 "REG_QCAPCTL,Qaudrature Capture Control"
bitfld.word 0x8 15. "CEN,Enable eQEP capture" "0,1"
bitfld.word 0x8 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler"
line.word 0xA "REG_QPOSCTL,Position Compare Control"
bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable" "0,1"
bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load" "0,1"
bitfld.word 0xA 13. "PCPOL,Polarity of sync output" "0,1"
bitfld.word 0xA 12. "PCE,Position compare enable/disable" "0,1"
hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width"
line.word 0xC "REG_QEINT_TYPE1,QEP Interrupt Control"
bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable" "0,1"
bitfld.word 0xC 11. "UTO,Unit time out interrupt enable" "0,1"
bitfld.word 0xC 10. "IEL,Index event latch interrupt enable" "0,1"
bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable" "0,1"
bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable" "0,1"
newline
bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable" "0,1"
bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable" "0,1"
bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable" "0,1"
bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable" "0,1"
bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable" "0,1"
newline
bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable" "0,1"
bitfld.word 0xC 1. "PCE,Position counter error interrupt enable" "0,1"
rgroup.word 0x32++0x1
line.word 0x0 "REG_QFLG_TYPE1,QEP Interrupt Flag"
bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag" "0,1"
bitfld.word 0x0 11. "UTO,Unit time out interrupt flag" "0,1"
bitfld.word 0x0 10. "IEL,Index event latch interrupt flag" "0,1"
bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag" "0,1"
bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag" "0,1"
newline
bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag" "0,1"
bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag" "0,1"
bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag" "0,1"
bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag" "0,1"
bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag" "0,1"
newline
bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0 1. "PCE,Position counter error interrupt flag" "0,1"
bitfld.word 0x0 0. "INT,Global interrupt status flag" "0,1"
group.word 0x34++0x9
line.word 0x0 "REG_QCLR_TYPE1,QEP Interrupt Clear"
bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag" "0,1"
bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag" "0,1"
bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag" "0,1"
bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
newline
bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
newline
bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag" "0,1"
bitfld.word 0x0 0. "INT,Global interrupt clear flag" "0,1"
line.word 0x2 "REG_QFRC_TYPE1,QEP Interrupt Force"
bitfld.word 0x2 12. "QMAE,Force QMA error interrupt" "0,1"
bitfld.word 0x2 11. "UTO,Force unit time out interrupt" "0,1"
bitfld.word 0x2 10. "IEL,Force index event latch interrupt" "0,1"
bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt" "0,1"
bitfld.word 0x2 8. "PCM,Force position-compare match interrupt" "0,1"
newline
bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt" "0,1"
bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt" "0,1"
bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt" "0,1"
bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt" "0,1"
bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt" "0,1"
newline
bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt" "0,1"
bitfld.word 0x2 1. "PCE,Force position counter error interrupt" "0,1"
line.word 0x4 "REG_QEPSTS_TYPE1,QEP Status"
bitfld.word 0x4 7. "UPEVNT,Unit position event flag" "0,1"
rbitfld.word 0x4 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker." "0,1"
rbitfld.word 0x4 5. "QDF,Quadrature direction flag" "0,1"
rbitfld.word 0x4 4. "QDLF,eQEP direction latch flag" "0,1"
bitfld.word 0x4 3. "COEF,Capture overflow error flag" "0,1"
newline
bitfld.word 0x4 2. "CDEF,Capture direction error flag" "0,1"
bitfld.word 0x4 1. "FIMF,First index marker flag" "0,1"
rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event." "0,1"
line.word 0x6 "REG_QCTMR,QEP Capture Timer"
hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit."
line.word 0x8 "REG_QCPRD,QEP Capture Period"
hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events"
rgroup.word 0x3E++0x3
line.word 0x0 "REG_QCTMRLAT,QEP Capture Latch"
hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz.  unit timeout event  reading the eQEP position counter."
line.word 0x2 "REG_QCPRDLAT,QEP Capture Period Latch"
hexmask.word 0x2 0.--15. 1. "QCPRDLAT,eQEP capture period value can be latched into this register on two events viz.  unit timeout event  reading the eQEP position counter."
group.word 0x42++0x1
line.word 0x0 "REG_Reserved_1,"
rgroup.long 0x60++0x3
line.long 0x0 "REG_REV_TYPE2,QEP Revision Number"
bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7"
group.long 0x64++0xB
line.long 0x0 "REG_QEPSTROBESEL,QEP Strobe select register"
bitfld.long 0x0 0.--1. "STROBESEL,Strobe source select:" "0,1,2,3"
line.long 0x4 "REG_QMACTRL,QMA Control register"
bitfld.long 0x4 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected010 : QMA Mode-2 operation selected011 : QMA Module is bypassed [reserved]1xx : QMA Module is bypassed [reserved]" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected010 : QMA Mode-2..,?,?,?,?,?,?"
line.long 0x8 "REG_QEPSRCSEL,QEP Source Select Register"
hexmask.long.byte 0x8 12.--15. 1. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent."
hexmask.long.byte 0x8 8.--11. 1. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent."
hexmask.long.byte 0x8 4.--7. 1. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent."
hexmask.long.byte 0x8 0.--3. 1. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent."
group.word 0x70++0x1
line.word 0x0 "REG_Reserved_2,"
tree.end
tree "EQEP2_REG (EQEP2_REG)"
base ad:0x23220000
group.long 0x0++0xF
line.long 0x0 "REG_QPOSCNT,Position Counter"
hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.."
line.long 0x4 "REG_QPOSINIT,Position Counter Init"
hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter InitThis register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.."
line.long 0x8 "REG_QPOSMAX,Maximum Position Count"
hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position CountThis register contains the maximum position counter value. Writes to this register should always be full 32-bit writes."
line.long 0xC "REG_QPOSCMP,Position Compare"
hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter [QPOSCNT] to generate sync output and/or interrupt on compare match."
rgroup.long 0x10++0xB
line.long 0x0 "REG_QPOSILAT,Index Position Latch"
hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits."
line.long 0x4 "REG_QPOSSLAT,Strobe Position Latch"
hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits."
line.long 0x8 "REG_QPOSLAT,Position Latch"
hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event."
group.long 0x1C++0x7
line.long 0x0 "REG_QUTMR,QEP Unit Timer"
hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit TimerThis register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated."
line.long 0x4 "REG_QUPRD,QEP Unit Period"
hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit PeriodThis register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.."
group.word 0x24++0xD
line.word 0x0 "REG_QWDTMR,QEP Watchdog Timer"
hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.."
line.word 0x2 "REG_QWDPRD,QEP Watchdog Period"
hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer.When the watchdog timer value matches the watchdog period value  a watchdog timeout interrupt is generated."
line.word 0x4 "REG_QDECCTL_TYPE2,Quadrature Decoder Control"
bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
bitfld.word 0x4 13. "SOEN,Sync output-enable" "0,1"
bitfld.word 0x4 12. "SPSEL,Sync output pin selection" "0,1"
bitfld.word 0x4 11. "XCR,External Clock Rate" "0,1"
bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
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bitfld.word 0x4 9. "IGATE,Index pulse gating option" "0,1"
bitfld.word 0x4 8. "QAP,QEPA input polarity" "0,1"
bitfld.word 0x4 7. "QBP,QEPB input polarity" "0,1"
bitfld.word 0x4 6. "QIP,QEPI input polarity" "0,1"
bitfld.word 0x4 5. "QSP,QEPS input polarity" "0,1"
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bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode  Behavior same as existing devices1 - Enhancement for Direction change during Index will be enabled" "0,1"
line.word 0x6 "REG_QEPCTL,QEP Control"
bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
bitfld.word 0x6 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3"
bitfld.word 0x6 8.--9. "IEI,Index event init of position count" "0,1,2,3"
bitfld.word 0x6 7. "SWI,Software init position counter" "0,1"
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bitfld.word 0x6 6. "SEL,Strobe event latch of position counter" "0,1"
bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3"
bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset" "0,1"
bitfld.word 0x6 2. "QCLM,QEP capture latch mode" "0,1"
bitfld.word 0x6 1. "UTE,QEP unit timer enable" "0,1"
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bitfld.word 0x6 0. "WDE,QEP watchdog enable" "0,1"
line.word 0x8 "REG_QCAPCTL,Qaudrature Capture Control"
bitfld.word 0x8 15. "CEN,Enable eQEP capture" "0,1"
bitfld.word 0x8 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler"
line.word 0xA "REG_QPOSCTL,Position Compare Control"
bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable" "0,1"
bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load" "0,1"
bitfld.word 0xA 13. "PCPOL,Polarity of sync output" "0,1"
bitfld.word 0xA 12. "PCE,Position compare enable/disable" "0,1"
hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width"
line.word 0xC "REG_QEINT_TYPE1,QEP Interrupt Control"
bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable" "0,1"
bitfld.word 0xC 11. "UTO,Unit time out interrupt enable" "0,1"
bitfld.word 0xC 10. "IEL,Index event latch interrupt enable" "0,1"
bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable" "0,1"
bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable" "0,1"
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bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable" "0,1"
bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable" "0,1"
bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable" "0,1"
bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable" "0,1"
bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable" "0,1"
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bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable" "0,1"
bitfld.word 0xC 1. "PCE,Position counter error interrupt enable" "0,1"
rgroup.word 0x32++0x1
line.word 0x0 "REG_QFLG_TYPE1,QEP Interrupt Flag"
bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag" "0,1"
bitfld.word 0x0 11. "UTO,Unit time out interrupt flag" "0,1"
bitfld.word 0x0 10. "IEL,Index event latch interrupt flag" "0,1"
bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag" "0,1"
bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag" "0,1"
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bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag" "0,1"
bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag" "0,1"
bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag" "0,1"
bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag" "0,1"
bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag" "0,1"
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bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0 1. "PCE,Position counter error interrupt flag" "0,1"
bitfld.word 0x0 0. "INT,Global interrupt status flag" "0,1"
group.word 0x34++0x9
line.word 0x0 "REG_QCLR_TYPE1,QEP Interrupt Clear"
bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag" "0,1"
bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag" "0,1"
bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag" "0,1"
bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
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bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
newline
bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag" "0,1"
bitfld.word 0x0 0. "INT,Global interrupt clear flag" "0,1"
line.word 0x2 "REG_QFRC_TYPE1,QEP Interrupt Force"
bitfld.word 0x2 12. "QMAE,Force QMA error interrupt" "0,1"
bitfld.word 0x2 11. "UTO,Force unit time out interrupt" "0,1"
bitfld.word 0x2 10. "IEL,Force index event latch interrupt" "0,1"
bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt" "0,1"
bitfld.word 0x2 8. "PCM,Force position-compare match interrupt" "0,1"
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bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt" "0,1"
bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt" "0,1"
bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt" "0,1"
bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt" "0,1"
bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt" "0,1"
newline
bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt" "0,1"
bitfld.word 0x2 1. "PCE,Force position counter error interrupt" "0,1"
line.word 0x4 "REG_QEPSTS_TYPE1,QEP Status"
bitfld.word 0x4 7. "UPEVNT,Unit position event flag" "0,1"
rbitfld.word 0x4 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker." "0,1"
rbitfld.word 0x4 5. "QDF,Quadrature direction flag" "0,1"
rbitfld.word 0x4 4. "QDLF,eQEP direction latch flag" "0,1"
bitfld.word 0x4 3. "COEF,Capture overflow error flag" "0,1"
newline
bitfld.word 0x4 2. "CDEF,Capture direction error flag" "0,1"
bitfld.word 0x4 1. "FIMF,First index marker flag" "0,1"
rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event." "0,1"
line.word 0x6 "REG_QCTMR,QEP Capture Timer"
hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit."
line.word 0x8 "REG_QCPRD,QEP Capture Period"
hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events"
rgroup.word 0x3E++0x3
line.word 0x0 "REG_QCTMRLAT,QEP Capture Latch"
hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz.  unit timeout event  reading the eQEP position counter."
line.word 0x2 "REG_QCPRDLAT,QEP Capture Period Latch"
hexmask.word 0x2 0.--15. 1. "QCPRDLAT,eQEP capture period value can be latched into this register on two events viz.  unit timeout event  reading the eQEP position counter."
group.word 0x42++0x1
line.word 0x0 "REG_Reserved_1,"
rgroup.long 0x60++0x3
line.long 0x0 "REG_REV_TYPE2,QEP Revision Number"
bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7"
group.long 0x64++0xB
line.long 0x0 "REG_QEPSTROBESEL,QEP Strobe select register"
bitfld.long 0x0 0.--1. "STROBESEL,Strobe source select:" "0,1,2,3"
line.long 0x4 "REG_QMACTRL,QMA Control register"
bitfld.long 0x4 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected010 : QMA Mode-2 operation selected011 : QMA Module is bypassed [reserved]1xx : QMA Module is bypassed [reserved]" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected010 : QMA Mode-2..,?,?,?,?,?,?"
line.long 0x8 "REG_QEPSRCSEL,QEP Source Select Register"
hexmask.long.byte 0x8 12.--15. 1. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent."
hexmask.long.byte 0x8 8.--11. 1. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent."
hexmask.long.byte 0x8 4.--7. 1. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent."
hexmask.long.byte 0x8 0.--3. 1. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent."
group.word 0x70++0x1
line.word 0x0 "REG_Reserved_2,"
tree.end
tree.end
tree "ESM0_CFG (ESM0_CFG)"
base ad:0x420000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "CFG_INFO,The Info Register gives the configuration Inforrmation of this ESM."
bitfld.long 0x4 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1"
hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups"
hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Total number of Error Groups"
group.long 0x8++0x3
line.long 0x0 "CFG_EN,The Global Enable Register has the master interrupt mask"
hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Enable"
wgroup.long 0xC++0x3
line.long 0x0 "CFG_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables"
hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset"
group.long 0x10++0xF
line.long 0x0 "CFG_ERR_RAW,Raw Status/Set Register for Configuration Errors"
hexmask.long.byte 0x0 0.--5. 1. "STS,This is the raw status for config errors"
line.long 0x4 "CFG_ERR_STS,Config Error Enable and Clear Register"
hexmask.long.byte 0x4 0.--5. 1. "MSK,This is the masked status/clear for config errors"
line.long 0x8 "CFG_ERR_EN_SET,Config Error Enable Set Register"
hexmask.long.byte 0x8 0.--5. 1. "MSK,This is the mask enable set for config errors"
line.long 0xC "CFG_ERR_EN_CLR,Config Error Interrupt Enabled Clear register"
hexmask.long.byte 0xC 0.--5. 1. "MSK,This is the mask enable clear for config errors"
rgroup.long 0x20++0xF
line.long 0x0 "CFG_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt"
hexmask.long.word 0x0 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt"
hexmask.long.word 0x0 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt"
line.long 0x4 "CFG_HI_PRI,Shows which is the highest priority outstanding high priority interrupt"
hexmask.long.word 0x4 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt"
hexmask.long.word 0x4 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt"
line.long 0x8 "CFG_LOW,Shows which groups have oustanding low priority interrupts"
hexmask.long 0x8 0.--31. 1. "STS,This is the raw status for config errors"
line.long 0xC "CFG_HI,Shows which groups have oustanding high priority interrupts"
hexmask.long 0xC 0.--31. 1. "STS,This is the raw status for config errors"
wgroup.long 0x30++0x3
line.long 0x0 "CFG_EOI,End of Interrupt Register"
hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced"
group.long 0x40++0x3
line.long 0x0 "CFG_PIN_CTRL,This register controls the error_pin_n output"
hexmask.long.byte 0x0 4.--7. 1. "PWM_EN,PWM enable"
hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin Control Key"
rgroup.long 0x44++0x7
line.long 0x0 "CFG_PIN_STS,This register reflects the status of the error_pin_n output"
bitfld.long 0x0 0. "VAL,Value of the error_pin_n" "0,1"
line.long 0x4 "CFG_PIN_CNTR,This register shows the current value of the error pin counter"
hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Current Counter Value"
group.long 0x4C++0x3
line.long 0x0 "CFG_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_PWMH_PIN_CNTR,This register shows the current value of the error pin PWM high counter"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value"
group.long 0x54++0x3
line.long 0x0 "CFG_PWMH_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM High Counter"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_PWML_PIN_CNTR,This register shows the current value of the error pin PWM low counter"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value"
group.long 0x5C++0x3
line.long 0x0 "CFG_PWML_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM Low Counter"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value"
group.long 0x400++0x1B
line.long 0x0 "CFG_RAW,Raw Status/Set Register for Group A Errors"
hexmask.long 0x0 0.--31. 1. "STS,This is the raw status/set for errors Group A"
line.long 0x4 "CFG_STS,Error Enable and Clear Register"
hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status/clear for errors in Group A"
line.long 0x8 "CFG_INTR_EN_SET,Level Error Enable Set Register"
hexmask.long 0x8 0.--31. 1. "MSK,This is the mask enable set for errors in Group A"
line.long 0xC "CFG_INTR_EN_CLR,Level Error Interrupt Enabled Clear register"
hexmask.long 0xC 0.--31. 1. "MSK,This is the mask enable clear for errors in Group A"
line.long 0x10 "CFG_INT_PRIO,Level Error Interrupt Enabled Clear register"
hexmask.long 0x10 0.--31. 1. "MSK,This is interrupt priority for errors in Group A"
line.long 0x14 "CFG_PIN_EN_SET,Level Error Interrupt Enabled Clear register"
hexmask.long 0x14 0.--31. 1. "MSK,This is the error pin influence enable set for errors in Group A"
line.long 0x18 "CFG_PIN_EN_CLR,Level Error Interrupt Enabled Clear register"
hexmask.long 0x18 0.--31. 1. "MSK,This is the error pin influence enable clear for errors in Group A"
tree.end
tree "FSIRX"
base ad:0x0
tree "FSIRX0_CFG (FSIRX0_CFG)"
base ad:0x23500000
group.word 0x0++0xB
line.word 0x0 "CFG_RX_MASTER_CTRL_ALTB_,Receive master control register"
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1  the FSI RX inputs [RXCLK  RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1"
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bitThis bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module  acting as a SPI master  to clock data into the.." "0,1"
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bitThis bit enables the internal loopback functionality of the FSI receiver. By enabling this bit  a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1"
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bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset bitThis bit controls the receiver master core reset. In order to receive any frame  this bit must be cleared.Note: For reset to take affect  the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h.." "0,1"
line.word 0x2 "CFG_Reserved_1,"
line.word 0x4 "CFG_Reserved_2,"
line.word 0x6 "CFG_Reserved_3,"
line.word 0x8 "CFG_RX_OPER_CTRL,Receive operation control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x8 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bitThis bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h [R/W] = The ping watchdog.." "0,1"
bitfld.word 0x8 7. "ECC_SEL,ECC Data Width Select bitThis bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h [R/W] = 32-bit ECC is used.1h [R/W] = 16-bit ECC is used." "0,1"
hexmask.word.byte 0x8 3.--6. 1. "N_WORDS,Number of Words to ReceiveThis field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.."
bitfld.word 0x8 2. "SPI_MODE,SPI Mode Enable bitThis bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1"
newline
bitfld.word 0x8 0.--1. "DATA_WIDTH,Receive Data Width Select bitThese bits decide the number of data lines used for receiving data. 0h [R/W] = Data will be received on one data line  RXD0.1h [R/W] = Data will be received on two data lines  RXD0 and RXD1.2h  3h [R/W] = Reserved" "0,1,2,3"
line.word 0xA "CFG_Reserved_4,"
rgroup.word 0xC++0x3
line.word 0x0 "CFG_RX_FRAME_INFO,Receive frame control register"
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame TypeThis field indicates the type of frame that was successfully received last. 0000b [R/W] = A ping frame was received0100b [R/W] = A DATA_1_WORD frame was received [16-bit data].0101b [R/W] = A DATA_2_WORD frame was received.."
line.word 0x2 "CFG_RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User DataThis field contains the 8-bit user data field of the last successfully received frame."
hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame TagThis field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x2 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.word 0x10++0x3
line.word 0x0 "CFG_RX_DMA_CTRL,Receive DMA event control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bitThis bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h [R/W] = A DMA event will not be generated.1h [R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA.." "0,1"
line.word 0x2 "CFG_Reserved_5,"
rgroup.word 0x14++0x3
line.word 0x0 "CFG_RX_EVT_STS_ALT1_,Receive event and error status flag register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match FlagThis bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match FlagThis bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched data.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match FlagThis bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched ping.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received FlagThis bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No data frame has been received.1h [R] = A data frame has been.." "0,1"
newline
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun FlagThis bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can also.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received FlagThis bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No ping frame has been received.1h [R] = A ping frame has been.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received FlagThis bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No error frame has been received.1h [R] = An error frame has been.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun FlagThis bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done FlagThis bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No frame has been successfully received.1h [R] = A frame.." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun FlagThis bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Receive buffer overrun has not.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error FlagThis bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid end-of-frame has not been received.1h [R] =.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error FlagThis bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid frame type has not been received.1h [R] = Invalid frame.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error FlagThis bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC.." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout FlagThis bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Frame watchdog timeout has not occured.1h [R] = Frame.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout FlagThis bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Ping watchdog timeout has not occured.1h [R] = Ping watchdog.." "0,1"
line.word 0x2 "CFG_RX_CRC_INFO,Receive CRC info of received and computed CRC"
hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC ValueThis bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping.."
hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC ValueThis bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames."
wgroup.word 0x18++0x3
line.word 0x0 "CFG_RX_EVT_CLR_ALT1_,Receive event and error clear register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [R/W] = Writing a 0 to this bit will have no effect.1h [R/W] = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
line.word 0x2 "CFG_RX_EVT_FRC_ALT1_,Receive event and error flag force register"
bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
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bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W].." "0,1"
bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1"
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bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
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bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] = Writing.." "0,1"
bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
group.word 0x1C++0x1
line.word 0x0 "CFG_RX_BUF_PTR_LOAD,Receive buffer pointer load register"
hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load.This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The value.."
rgroup.word 0x1E++0x1
line.word 0x0 "CFG_RX_BUF_PTR_STS,Receive buffer pointer status register"
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive BufferThis bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer."
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer IndexThis bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission."
group.word 0x20++0x3
line.word 0x0 "CFG_RX_FRAME_WD_CTRL,Receive frame watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bitThis bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF].." "0,1"
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bitThis bit will reset the frame watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The frame watchdog counter will be reset to 0." "0,1"
line.word 0x2 "CFG_Reserved_6,"
group.long 0x24++0x3
line.long 0x0 "CFG_RX_FRAME_WD_REF,Receive frame watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference ValueThis is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached."
rgroup.long 0x28++0x3
line.long 0x0 "CFG_RX_FRAME_WD_CNT,Receive frame watchdog current count"
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST  a match with FRAME_WD_REF  or the.."
group.word 0x2C++0x1
line.word 0x0 "CFG_RX_PING_WD_CTRL,Receive ping watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bitThis bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached  it will generate a.." "0,1"
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bitThis bit will reset the ping watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The ping watchdog counter will be reset to 0." "0,1"
rgroup.word 0x2E++0x1
line.word 0x0 "CFG_RX_PING_TAG,Receive ping tag register"
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame TagThis field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x0 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.long 0x30++0x3
line.long 0x0 "CFG_RX_PING_WD_REF,Receive ping watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference ValueThis is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached."
rgroup.long 0x34++0x3
line.long 0x0 "CFG_RX_PING_WD_CNT,Receive pingwatchdog current count"
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST  a match with PING_WD_REF  or the reception.."
group.word 0x38++0x7
line.word 0x0 "CFG_RX_INT1_CTRL_ALT1_,Receive interrupt control register for RX_INT1. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A frame.." "0,1"
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = An.." "0,1"
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W].." "0,1"
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] =.." "0,1"
line.word 0x2 "CFG_RX_INT2_CTRL_ALT1_,Receive interrupt control register for RX_INT2. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A frame.." "0,1"
bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A buffer.." "0,1"
bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = An.." "0,1"
bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W].." "0,1"
bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] =.." "0,1"
line.word 0x4 "CFG_RX_LOCK_CTRL,Receive lock control register"
hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bitThis bit locks the contents of all the receive control registers that support a lock protection. Once locked  further writes will not take effect until SYSRS unlocks the register. Once set  further writes even to this.." "0,1"
line.word 0x6 "CFG_Reserved_7,"
group.long 0x40++0x3
line.long 0x0 "CFG_RX_ECC_DATA,Receive ECC data register"
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.."
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.."
group.word 0x44++0x3
line.word 0x0 "CFG_RX_ECC_VAL,Receive ECC value register"
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED checkThis field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register."
line.word 0x2 "CFG_Reserved_8,"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_RX_ECC_SEC_DATA,Receive ECC corrected data register"
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected DataThe ECC corrected data will be available in this register. This value is valid only when there are no bit errors  or a single bit error was detected. Otherwise  the contents of this register are invalid and should.."
rgroup.word 0x4C++0x1
line.word 0x0 "CFG_RX_ECC_LOG,Receive ECC log and status register"
bitfld.word 0x0 1. "MBE,Multiple Bit Errors DetectedThis bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set  the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h [R] Multiple Bit Errors.." "0,1"
bitfld.word 0x0 0. "SBE,Single Bit Error DetectedThis bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h [R] No bit errors were detected. The value in.." "0,1"
group.word 0x4E++0x7
line.word 0x0 "CFG_Reserved_9,"
line.word 0x2 "CFG_RX_FRAME_TAG_CMP,Receive frame tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x2 8. "CMP_EN,Frame Tag Compare Enable bitSet this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming frame tag will trigger the.." "0,1"
hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Frame Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.."
hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Frame Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames."
line.word 0x4 "CFG_RX_PING_TAG_CMP,Receive ping tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x4 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x4 8. "CMP_EN,Ping Tag Compare Enable bitSet this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming ping tag will trigger a ping frame tag.." "0,1"
hexmask.word.byte 0x4 4.--7. 1. "TAG_MASK,Ping Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.."
hexmask.word.byte 0x4 0.--3. 1. "TAG_REF,Ping Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames."
line.word 0x6 "CFG_Reserved_10,"
group.word 0x60++0x3
line.word 0x0 "CFG_RX_DLYLINE_CTRL,Receive delay line control register. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the.."
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the.."
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLKThis bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly from.."
line.word 0x2 "CFG_Reserved_11,"
rgroup.long 0x70++0x3
line.long 0x0 "CFG_RX_VIS_1,Receive debug visibility register 1"
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bitThis bit indicates the status of the receiver core. If this bit is set  the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1"
group.word 0x74++0x1
line.word 0x0 "CFG_Reserved_12,"
rgroup.word 0x80++0x1
line.word 0x0 "CFG_RX_BUF_BASE,Base address for receive data buffer"
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base AddressThis is the base address of the 16-word data buffer used by the receiver."
tree.end
tree "FSIRX1_CFG (FSIRX1_CFG)"
base ad:0x23510000
group.word 0x0++0xB
line.word 0x0 "CFG_RX_MASTER_CTRL_ALTB_,Receive master control register"
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1  the FSI RX inputs [RXCLK  RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1"
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bitThis bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module  acting as a SPI master  to clock data into the.." "0,1"
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bitThis bit enables the internal loopback functionality of the FSI receiver. By enabling this bit  a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1"
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bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset bitThis bit controls the receiver master core reset. In order to receive any frame  this bit must be cleared.Note: For reset to take affect  the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h.." "0,1"
line.word 0x2 "CFG_Reserved_1,"
line.word 0x4 "CFG_Reserved_2,"
line.word 0x6 "CFG_Reserved_3,"
line.word 0x8 "CFG_RX_OPER_CTRL,Receive operation control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x8 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bitThis bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h [R/W] = The ping watchdog.." "0,1"
bitfld.word 0x8 7. "ECC_SEL,ECC Data Width Select bitThis bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h [R/W] = 32-bit ECC is used.1h [R/W] = 16-bit ECC is used." "0,1"
hexmask.word.byte 0x8 3.--6. 1. "N_WORDS,Number of Words to ReceiveThis field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.."
bitfld.word 0x8 2. "SPI_MODE,SPI Mode Enable bitThis bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1"
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bitfld.word 0x8 0.--1. "DATA_WIDTH,Receive Data Width Select bitThese bits decide the number of data lines used for receiving data. 0h [R/W] = Data will be received on one data line  RXD0.1h [R/W] = Data will be received on two data lines  RXD0 and RXD1.2h  3h [R/W] = Reserved" "0,1,2,3"
line.word 0xA "CFG_Reserved_4,"
rgroup.word 0xC++0x3
line.word 0x0 "CFG_RX_FRAME_INFO,Receive frame control register"
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame TypeThis field indicates the type of frame that was successfully received last. 0000b [R/W] = A ping frame was received0100b [R/W] = A DATA_1_WORD frame was received [16-bit data].0101b [R/W] = A DATA_2_WORD frame was received.."
line.word 0x2 "CFG_RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User DataThis field contains the 8-bit user data field of the last successfully received frame."
hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame TagThis field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x2 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.word 0x10++0x3
line.word 0x0 "CFG_RX_DMA_CTRL,Receive DMA event control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bitThis bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h [R/W] = A DMA event will not be generated.1h [R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA.." "0,1"
line.word 0x2 "CFG_Reserved_5,"
rgroup.word 0x14++0x3
line.word 0x0 "CFG_RX_EVT_STS_ALT1_,Receive event and error status flag register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match FlagThis bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match FlagThis bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched data.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match FlagThis bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched ping.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received FlagThis bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No data frame has been received.1h [R] = A data frame has been.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun FlagThis bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can also.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received FlagThis bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No ping frame has been received.1h [R] = A ping frame has been.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received FlagThis bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No error frame has been received.1h [R] = An error frame has been.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun FlagThis bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done FlagThis bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No frame has been successfully received.1h [R] = A frame.." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun FlagThis bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Receive buffer overrun has not.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error FlagThis bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid end-of-frame has not been received.1h [R] =.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error FlagThis bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid frame type has not been received.1h [R] = Invalid frame.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error FlagThis bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC.." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout FlagThis bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Frame watchdog timeout has not occured.1h [R] = Frame.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout FlagThis bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Ping watchdog timeout has not occured.1h [R] = Ping watchdog.." "0,1"
line.word 0x2 "CFG_RX_CRC_INFO,Receive CRC info of received and computed CRC"
hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC ValueThis bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping.."
hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC ValueThis bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames."
wgroup.word 0x18++0x3
line.word 0x0 "CFG_RX_EVT_CLR_ALT1_,Receive event and error clear register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [R/W] = Writing a 0 to this bit will have no effect.1h [R/W] = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
line.word 0x2 "CFG_RX_EVT_FRC_ALT1_,Receive event and error flag force register"
bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
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bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W].." "0,1"
bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1"
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bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
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bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] = Writing.." "0,1"
bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
group.word 0x1C++0x1
line.word 0x0 "CFG_RX_BUF_PTR_LOAD,Receive buffer pointer load register"
hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load.This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The value.."
rgroup.word 0x1E++0x1
line.word 0x0 "CFG_RX_BUF_PTR_STS,Receive buffer pointer status register"
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive BufferThis bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer."
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer IndexThis bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission."
group.word 0x20++0x3
line.word 0x0 "CFG_RX_FRAME_WD_CTRL,Receive frame watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bitThis bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF].." "0,1"
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bitThis bit will reset the frame watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The frame watchdog counter will be reset to 0." "0,1"
line.word 0x2 "CFG_Reserved_6,"
group.long 0x24++0x3
line.long 0x0 "CFG_RX_FRAME_WD_REF,Receive frame watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference ValueThis is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached."
rgroup.long 0x28++0x3
line.long 0x0 "CFG_RX_FRAME_WD_CNT,Receive frame watchdog current count"
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST  a match with FRAME_WD_REF  or the.."
group.word 0x2C++0x1
line.word 0x0 "CFG_RX_PING_WD_CTRL,Receive ping watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bitThis bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached  it will generate a.." "0,1"
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bitThis bit will reset the ping watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The ping watchdog counter will be reset to 0." "0,1"
rgroup.word 0x2E++0x1
line.word 0x0 "CFG_RX_PING_TAG,Receive ping tag register"
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame TagThis field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x0 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.long 0x30++0x3
line.long 0x0 "CFG_RX_PING_WD_REF,Receive ping watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference ValueThis is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached."
rgroup.long 0x34++0x3
line.long 0x0 "CFG_RX_PING_WD_CNT,Receive pingwatchdog current count"
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST  a match with PING_WD_REF  or the reception.."
group.word 0x38++0x7
line.word 0x0 "CFG_RX_INT1_CTRL_ALT1_,Receive interrupt control register for RX_INT1. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A frame.." "0,1"
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = An.." "0,1"
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W].." "0,1"
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] =.." "0,1"
line.word 0x2 "CFG_RX_INT2_CTRL_ALT1_,Receive interrupt control register for RX_INT2. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A frame.." "0,1"
bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A buffer.." "0,1"
bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = An.." "0,1"
bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W].." "0,1"
bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] =.." "0,1"
line.word 0x4 "CFG_RX_LOCK_CTRL,Receive lock control register"
hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bitThis bit locks the contents of all the receive control registers that support a lock protection. Once locked  further writes will not take effect until SYSRS unlocks the register. Once set  further writes even to this.." "0,1"
line.word 0x6 "CFG_Reserved_7,"
group.long 0x40++0x3
line.long 0x0 "CFG_RX_ECC_DATA,Receive ECC data register"
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.."
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.."
group.word 0x44++0x3
line.word 0x0 "CFG_RX_ECC_VAL,Receive ECC value register"
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED checkThis field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register."
line.word 0x2 "CFG_Reserved_8,"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_RX_ECC_SEC_DATA,Receive ECC corrected data register"
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected DataThe ECC corrected data will be available in this register. This value is valid only when there are no bit errors  or a single bit error was detected. Otherwise  the contents of this register are invalid and should.."
rgroup.word 0x4C++0x1
line.word 0x0 "CFG_RX_ECC_LOG,Receive ECC log and status register"
bitfld.word 0x0 1. "MBE,Multiple Bit Errors DetectedThis bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set  the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h [R] Multiple Bit Errors.." "0,1"
bitfld.word 0x0 0. "SBE,Single Bit Error DetectedThis bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h [R] No bit errors were detected. The value in.." "0,1"
group.word 0x4E++0x7
line.word 0x0 "CFG_Reserved_9,"
line.word 0x2 "CFG_RX_FRAME_TAG_CMP,Receive frame tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x2 8. "CMP_EN,Frame Tag Compare Enable bitSet this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming frame tag will trigger the.." "0,1"
hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Frame Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.."
hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Frame Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames."
line.word 0x4 "CFG_RX_PING_TAG_CMP,Receive ping tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x4 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x4 8. "CMP_EN,Ping Tag Compare Enable bitSet this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming ping tag will trigger a ping frame tag.." "0,1"
hexmask.word.byte 0x4 4.--7. 1. "TAG_MASK,Ping Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.."
hexmask.word.byte 0x4 0.--3. 1. "TAG_REF,Ping Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames."
line.word 0x6 "CFG_Reserved_10,"
group.word 0x60++0x3
line.word 0x0 "CFG_RX_DLYLINE_CTRL,Receive delay line control register. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the.."
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the.."
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLKThis bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly from.."
line.word 0x2 "CFG_Reserved_11,"
rgroup.long 0x70++0x3
line.long 0x0 "CFG_RX_VIS_1,Receive debug visibility register 1"
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bitThis bit indicates the status of the receiver core. If this bit is set  the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1"
group.word 0x74++0x1
line.word 0x0 "CFG_Reserved_12,"
rgroup.word 0x80++0x1
line.word 0x0 "CFG_RX_BUF_BASE,Base address for receive data buffer"
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base AddressThis is the base address of the 16-word data buffer used by the receiver."
tree.end
tree "FSIRX2_CFG (FSIRX2_CFG)"
base ad:0x23520000
group.word 0x0++0xB
line.word 0x0 "CFG_RX_MASTER_CTRL_ALTB_,Receive master control register"
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1  the FSI RX inputs [RXCLK  RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1"
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bitThis bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module  acting as a SPI master  to clock data into the.." "0,1"
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bitThis bit enables the internal loopback functionality of the FSI receiver. By enabling this bit  a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1"
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bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset bitThis bit controls the receiver master core reset. In order to receive any frame  this bit must be cleared.Note: For reset to take affect  the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h.." "0,1"
line.word 0x2 "CFG_Reserved_1,"
line.word 0x4 "CFG_Reserved_2,"
line.word 0x6 "CFG_Reserved_3,"
line.word 0x8 "CFG_RX_OPER_CTRL,Receive operation control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x8 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bitThis bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h [R/W] = The ping watchdog.." "0,1"
bitfld.word 0x8 7. "ECC_SEL,ECC Data Width Select bitThis bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h [R/W] = 32-bit ECC is used.1h [R/W] = 16-bit ECC is used." "0,1"
hexmask.word.byte 0x8 3.--6. 1. "N_WORDS,Number of Words to ReceiveThis field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.."
bitfld.word 0x8 2. "SPI_MODE,SPI Mode Enable bitThis bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1"
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bitfld.word 0x8 0.--1. "DATA_WIDTH,Receive Data Width Select bitThese bits decide the number of data lines used for receiving data. 0h [R/W] = Data will be received on one data line  RXD0.1h [R/W] = Data will be received on two data lines  RXD0 and RXD1.2h  3h [R/W] = Reserved" "0,1,2,3"
line.word 0xA "CFG_Reserved_4,"
rgroup.word 0xC++0x3
line.word 0x0 "CFG_RX_FRAME_INFO,Receive frame control register"
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame TypeThis field indicates the type of frame that was successfully received last. 0000b [R/W] = A ping frame was received0100b [R/W] = A DATA_1_WORD frame was received [16-bit data].0101b [R/W] = A DATA_2_WORD frame was received.."
line.word 0x2 "CFG_RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User DataThis field contains the 8-bit user data field of the last successfully received frame."
hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame TagThis field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x2 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.word 0x10++0x3
line.word 0x0 "CFG_RX_DMA_CTRL,Receive DMA event control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bitThis bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h [R/W] = A DMA event will not be generated.1h [R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA.." "0,1"
line.word 0x2 "CFG_Reserved_5,"
rgroup.word 0x14++0x3
line.word 0x0 "CFG_RX_EVT_STS_ALT1_,Receive event and error status flag register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match FlagThis bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match FlagThis bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched data.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match FlagThis bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched ping.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received FlagThis bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No data frame has been received.1h [R] = A data frame has been.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun FlagThis bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can also.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received FlagThis bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No ping frame has been received.1h [R] = A ping frame has been.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received FlagThis bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No error frame has been received.1h [R] = An error frame has been.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun FlagThis bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done FlagThis bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No frame has been successfully received.1h [R] = A frame.." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun FlagThis bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Receive buffer overrun has not.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error FlagThis bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid end-of-frame has not been received.1h [R] =.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error FlagThis bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid frame type has not been received.1h [R] = Invalid frame.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error FlagThis bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC.." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout FlagThis bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Frame watchdog timeout has not occured.1h [R] = Frame.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout FlagThis bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Ping watchdog timeout has not occured.1h [R] = Ping watchdog.." "0,1"
line.word 0x2 "CFG_RX_CRC_INFO,Receive CRC info of received and computed CRC"
hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC ValueThis bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping.."
hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC ValueThis bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames."
wgroup.word 0x18++0x3
line.word 0x0 "CFG_RX_EVT_CLR_ALT1_,Receive event and error clear register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [R/W] = Writing a 0 to this bit will have no effect.1h [R/W] = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
line.word 0x2 "CFG_RX_EVT_FRC_ALT1_,Receive event and error flag force register"
bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
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bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W].." "0,1"
bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1"
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bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
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bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] = Writing.." "0,1"
bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
group.word 0x1C++0x1
line.word 0x0 "CFG_RX_BUF_PTR_LOAD,Receive buffer pointer load register"
hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load.This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The value.."
rgroup.word 0x1E++0x1
line.word 0x0 "CFG_RX_BUF_PTR_STS,Receive buffer pointer status register"
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive BufferThis bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer."
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer IndexThis bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission."
group.word 0x20++0x3
line.word 0x0 "CFG_RX_FRAME_WD_CTRL,Receive frame watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bitThis bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF].." "0,1"
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bitThis bit will reset the frame watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The frame watchdog counter will be reset to 0." "0,1"
line.word 0x2 "CFG_Reserved_6,"
group.long 0x24++0x3
line.long 0x0 "CFG_RX_FRAME_WD_REF,Receive frame watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference ValueThis is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached."
rgroup.long 0x28++0x3
line.long 0x0 "CFG_RX_FRAME_WD_CNT,Receive frame watchdog current count"
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST  a match with FRAME_WD_REF  or the.."
group.word 0x2C++0x1
line.word 0x0 "CFG_RX_PING_WD_CTRL,Receive ping watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bitThis bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached  it will generate a.." "0,1"
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bitThis bit will reset the ping watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The ping watchdog counter will be reset to 0." "0,1"
rgroup.word 0x2E++0x1
line.word 0x0 "CFG_RX_PING_TAG,Receive ping tag register"
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame TagThis field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x0 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.long 0x30++0x3
line.long 0x0 "CFG_RX_PING_WD_REF,Receive ping watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference ValueThis is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached."
rgroup.long 0x34++0x3
line.long 0x0 "CFG_RX_PING_WD_CNT,Receive pingwatchdog current count"
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST  a match with PING_WD_REF  or the reception.."
group.word 0x38++0x7
line.word 0x0 "CFG_RX_INT1_CTRL_ALT1_,Receive interrupt control register for RX_INT1. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A frame.." "0,1"
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = An.." "0,1"
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W].." "0,1"
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] =.." "0,1"
line.word 0x2 "CFG_RX_INT2_CTRL_ALT1_,Receive interrupt control register for RX_INT2. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A frame.." "0,1"
bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A buffer.." "0,1"
bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = An.." "0,1"
bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W].." "0,1"
bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] =.." "0,1"
line.word 0x4 "CFG_RX_LOCK_CTRL,Receive lock control register"
hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bitThis bit locks the contents of all the receive control registers that support a lock protection. Once locked  further writes will not take effect until SYSRS unlocks the register. Once set  further writes even to this.." "0,1"
line.word 0x6 "CFG_Reserved_7,"
group.long 0x40++0x3
line.long 0x0 "CFG_RX_ECC_DATA,Receive ECC data register"
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.."
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.."
group.word 0x44++0x3
line.word 0x0 "CFG_RX_ECC_VAL,Receive ECC value register"
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED checkThis field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register."
line.word 0x2 "CFG_Reserved_8,"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_RX_ECC_SEC_DATA,Receive ECC corrected data register"
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected DataThe ECC corrected data will be available in this register. This value is valid only when there are no bit errors  or a single bit error was detected. Otherwise  the contents of this register are invalid and should.."
rgroup.word 0x4C++0x1
line.word 0x0 "CFG_RX_ECC_LOG,Receive ECC log and status register"
bitfld.word 0x0 1. "MBE,Multiple Bit Errors DetectedThis bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set  the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h [R] Multiple Bit Errors.." "0,1"
bitfld.word 0x0 0. "SBE,Single Bit Error DetectedThis bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h [R] No bit errors were detected. The value in.." "0,1"
group.word 0x4E++0x7
line.word 0x0 "CFG_Reserved_9,"
line.word 0x2 "CFG_RX_FRAME_TAG_CMP,Receive frame tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x2 8. "CMP_EN,Frame Tag Compare Enable bitSet this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming frame tag will trigger the.." "0,1"
hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Frame Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.."
hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Frame Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames."
line.word 0x4 "CFG_RX_PING_TAG_CMP,Receive ping tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x4 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x4 8. "CMP_EN,Ping Tag Compare Enable bitSet this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming ping tag will trigger a ping frame tag.." "0,1"
hexmask.word.byte 0x4 4.--7. 1. "TAG_MASK,Ping Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.."
hexmask.word.byte 0x4 0.--3. 1. "TAG_REF,Ping Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames."
line.word 0x6 "CFG_Reserved_10,"
group.word 0x60++0x3
line.word 0x0 "CFG_RX_DLYLINE_CTRL,Receive delay line control register. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the.."
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the.."
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLKThis bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly from.."
line.word 0x2 "CFG_Reserved_11,"
rgroup.long 0x70++0x3
line.long 0x0 "CFG_RX_VIS_1,Receive debug visibility register 1"
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bitThis bit indicates the status of the receiver core. If this bit is set  the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1"
group.word 0x74++0x1
line.word 0x0 "CFG_Reserved_12,"
rgroup.word 0x80++0x1
line.word 0x0 "CFG_RX_BUF_BASE,Base address for receive data buffer"
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base AddressThis is the base address of the 16-word data buffer used by the receiver."
tree.end
tree "FSIRX3_CFG (FSIRX3_CFG)"
base ad:0x23530000
group.word 0x0++0xB
line.word 0x0 "CFG_RX_MASTER_CTRL_ALTB_,Receive master control register"
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1  the FSI RX inputs [RXCLK  RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1"
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bitThis bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module  acting as a SPI master  to clock data into the.." "0,1"
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bitThis bit enables the internal loopback functionality of the FSI receiver. By enabling this bit  a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1"
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bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset bitThis bit controls the receiver master core reset. In order to receive any frame  this bit must be cleared.Note: For reset to take affect  the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h.." "0,1"
line.word 0x2 "CFG_Reserved_1,"
line.word 0x4 "CFG_Reserved_2,"
line.word 0x6 "CFG_Reserved_3,"
line.word 0x8 "CFG_RX_OPER_CTRL,Receive operation control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x8 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bitThis bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h [R/W] = The ping watchdog.." "0,1"
bitfld.word 0x8 7. "ECC_SEL,ECC Data Width Select bitThis bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h [R/W] = 32-bit ECC is used.1h [R/W] = 16-bit ECC is used." "0,1"
hexmask.word.byte 0x8 3.--6. 1. "N_WORDS,Number of Words to ReceiveThis field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.."
bitfld.word 0x8 2. "SPI_MODE,SPI Mode Enable bitThis bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1"
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bitfld.word 0x8 0.--1. "DATA_WIDTH,Receive Data Width Select bitThese bits decide the number of data lines used for receiving data. 0h [R/W] = Data will be received on one data line  RXD0.1h [R/W] = Data will be received on two data lines  RXD0 and RXD1.2h  3h [R/W] = Reserved" "0,1,2,3"
line.word 0xA "CFG_Reserved_4,"
rgroup.word 0xC++0x3
line.word 0x0 "CFG_RX_FRAME_INFO,Receive frame control register"
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame TypeThis field indicates the type of frame that was successfully received last. 0000b [R/W] = A ping frame was received0100b [R/W] = A DATA_1_WORD frame was received [16-bit data].0101b [R/W] = A DATA_2_WORD frame was received.."
line.word 0x2 "CFG_RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User DataThis field contains the 8-bit user data field of the last successfully received frame."
hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame TagThis field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x2 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.word 0x10++0x3
line.word 0x0 "CFG_RX_DMA_CTRL,Receive DMA event control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bitThis bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h [R/W] = A DMA event will not be generated.1h [R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA.." "0,1"
line.word 0x2 "CFG_Reserved_5,"
rgroup.word 0x14++0x3
line.word 0x0 "CFG_RX_EVT_STS_ALT1_,Receive event and error status flag register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match FlagThis bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match FlagThis bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched data.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match FlagThis bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched ping.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received FlagThis bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No data frame has been received.1h [R] = A data frame has been.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun FlagThis bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can also.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received FlagThis bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No ping frame has been received.1h [R] = A ping frame has been.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received FlagThis bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No error frame has been received.1h [R] = An error frame has been.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun FlagThis bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done FlagThis bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No frame has been successfully received.1h [R] = A frame.." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun FlagThis bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Receive buffer overrun has not.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error FlagThis bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid end-of-frame has not been received.1h [R] =.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error FlagThis bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid frame type has not been received.1h [R] = Invalid frame.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error FlagThis bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC.." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout FlagThis bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Frame watchdog timeout has not occured.1h [R] = Frame.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout FlagThis bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Ping watchdog timeout has not occured.1h [R] = Ping watchdog.." "0,1"
line.word 0x2 "CFG_RX_CRC_INFO,Receive CRC info of received and computed CRC"
hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC ValueThis bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping.."
hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC ValueThis bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames."
wgroup.word 0x18++0x3
line.word 0x0 "CFG_RX_EVT_CLR_ALT1_,Receive event and error clear register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [R/W] = Writing a 0 to this bit will have no effect.1h [R/W] = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
line.word 0x2 "CFG_RX_EVT_FRC_ALT1_,Receive event and error flag force register"
bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
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bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W].." "0,1"
bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1"
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bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
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bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] = Writing.." "0,1"
bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
group.word 0x1C++0x1
line.word 0x0 "CFG_RX_BUF_PTR_LOAD,Receive buffer pointer load register"
hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load.This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The value.."
rgroup.word 0x1E++0x1
line.word 0x0 "CFG_RX_BUF_PTR_STS,Receive buffer pointer status register"
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive BufferThis bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer."
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer IndexThis bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission."
group.word 0x20++0x3
line.word 0x0 "CFG_RX_FRAME_WD_CTRL,Receive frame watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bitThis bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF].." "0,1"
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bitThis bit will reset the frame watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The frame watchdog counter will be reset to 0." "0,1"
line.word 0x2 "CFG_Reserved_6,"
group.long 0x24++0x3
line.long 0x0 "CFG_RX_FRAME_WD_REF,Receive frame watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference ValueThis is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached."
rgroup.long 0x28++0x3
line.long 0x0 "CFG_RX_FRAME_WD_CNT,Receive frame watchdog current count"
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST  a match with FRAME_WD_REF  or the.."
group.word 0x2C++0x1
line.word 0x0 "CFG_RX_PING_WD_CTRL,Receive ping watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bitThis bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached  it will generate a.." "0,1"
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bitThis bit will reset the ping watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The ping watchdog counter will be reset to 0." "0,1"
rgroup.word 0x2E++0x1
line.word 0x0 "CFG_RX_PING_TAG,Receive ping tag register"
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame TagThis field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x0 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.long 0x30++0x3
line.long 0x0 "CFG_RX_PING_WD_REF,Receive ping watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference ValueThis is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached."
rgroup.long 0x34++0x3
line.long 0x0 "CFG_RX_PING_WD_CNT,Receive pingwatchdog current count"
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST  a match with PING_WD_REF  or the reception.."
group.word 0x38++0x7
line.word 0x0 "CFG_RX_INT1_CTRL_ALT1_,Receive interrupt control register for RX_INT1. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A frame.." "0,1"
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = An.." "0,1"
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W].." "0,1"
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] =.." "0,1"
line.word 0x2 "CFG_RX_INT2_CTRL_ALT1_,Receive interrupt control register for RX_INT2. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A frame.." "0,1"
bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A buffer.." "0,1"
bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = An.." "0,1"
bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W].." "0,1"
bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] =.." "0,1"
line.word 0x4 "CFG_RX_LOCK_CTRL,Receive lock control register"
hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bitThis bit locks the contents of all the receive control registers that support a lock protection. Once locked  further writes will not take effect until SYSRS unlocks the register. Once set  further writes even to this.." "0,1"
line.word 0x6 "CFG_Reserved_7,"
group.long 0x40++0x3
line.long 0x0 "CFG_RX_ECC_DATA,Receive ECC data register"
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.."
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.."
group.word 0x44++0x3
line.word 0x0 "CFG_RX_ECC_VAL,Receive ECC value register"
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED checkThis field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register."
line.word 0x2 "CFG_Reserved_8,"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_RX_ECC_SEC_DATA,Receive ECC corrected data register"
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected DataThe ECC corrected data will be available in this register. This value is valid only when there are no bit errors  or a single bit error was detected. Otherwise  the contents of this register are invalid and should.."
rgroup.word 0x4C++0x1
line.word 0x0 "CFG_RX_ECC_LOG,Receive ECC log and status register"
bitfld.word 0x0 1. "MBE,Multiple Bit Errors DetectedThis bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set  the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h [R] Multiple Bit Errors.." "0,1"
bitfld.word 0x0 0. "SBE,Single Bit Error DetectedThis bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h [R] No bit errors were detected. The value in.." "0,1"
group.word 0x4E++0x7
line.word 0x0 "CFG_Reserved_9,"
line.word 0x2 "CFG_RX_FRAME_TAG_CMP,Receive frame tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x2 8. "CMP_EN,Frame Tag Compare Enable bitSet this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming frame tag will trigger the.." "0,1"
hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Frame Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.."
hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Frame Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames."
line.word 0x4 "CFG_RX_PING_TAG_CMP,Receive ping tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x4 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x4 8. "CMP_EN,Ping Tag Compare Enable bitSet this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming ping tag will trigger a ping frame tag.." "0,1"
hexmask.word.byte 0x4 4.--7. 1. "TAG_MASK,Ping Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.."
hexmask.word.byte 0x4 0.--3. 1. "TAG_REF,Ping Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames."
line.word 0x6 "CFG_Reserved_10,"
group.word 0x60++0x3
line.word 0x0 "CFG_RX_DLYLINE_CTRL,Receive delay line control register. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the.."
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the.."
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLKThis bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly from.."
line.word 0x2 "CFG_Reserved_11,"
rgroup.long 0x70++0x3
line.long 0x0 "CFG_RX_VIS_1,Receive debug visibility register 1"
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bitThis bit indicates the status of the receiver core. If this bit is set  the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1"
group.word 0x74++0x1
line.word 0x0 "CFG_Reserved_12,"
rgroup.word 0x80++0x1
line.word 0x0 "CFG_RX_BUF_BASE,Base address for receive data buffer"
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base AddressThis is the base address of the 16-word data buffer used by the receiver."
tree.end
tree "FSIRX4_CFG (FSIRX4_CFG)"
base ad:0x23540000
group.word 0x0++0xB
line.word 0x0 "CFG_RX_MASTER_CTRL_ALTB_,Receive master control register"
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1  the FSI RX inputs [RXCLK  RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1"
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bitThis bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module  acting as a SPI master  to clock data into the.." "0,1"
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bitThis bit enables the internal loopback functionality of the FSI receiver. By enabling this bit  a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1"
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bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset bitThis bit controls the receiver master core reset. In order to receive any frame  this bit must be cleared.Note: For reset to take affect  the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h.." "0,1"
line.word 0x2 "CFG_Reserved_1,"
line.word 0x4 "CFG_Reserved_2,"
line.word 0x6 "CFG_Reserved_3,"
line.word 0x8 "CFG_RX_OPER_CTRL,Receive operation control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x8 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bitThis bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h [R/W] = The ping watchdog.." "0,1"
bitfld.word 0x8 7. "ECC_SEL,ECC Data Width Select bitThis bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h [R/W] = 32-bit ECC is used.1h [R/W] = 16-bit ECC is used." "0,1"
hexmask.word.byte 0x8 3.--6. 1. "N_WORDS,Number of Words to ReceiveThis field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.."
bitfld.word 0x8 2. "SPI_MODE,SPI Mode Enable bitThis bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1"
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bitfld.word 0x8 0.--1. "DATA_WIDTH,Receive Data Width Select bitThese bits decide the number of data lines used for receiving data. 0h [R/W] = Data will be received on one data line  RXD0.1h [R/W] = Data will be received on two data lines  RXD0 and RXD1.2h  3h [R/W] = Reserved" "0,1,2,3"
line.word 0xA "CFG_Reserved_4,"
rgroup.word 0xC++0x3
line.word 0x0 "CFG_RX_FRAME_INFO,Receive frame control register"
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame TypeThis field indicates the type of frame that was successfully received last. 0000b [R/W] = A ping frame was received0100b [R/W] = A DATA_1_WORD frame was received [16-bit data].0101b [R/W] = A DATA_2_WORD frame was received.."
line.word 0x2 "CFG_RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User DataThis field contains the 8-bit user data field of the last successfully received frame."
hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame TagThis field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x2 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.word 0x10++0x3
line.word 0x0 "CFG_RX_DMA_CTRL,Receive DMA event control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bitThis bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h [R/W] = A DMA event will not be generated.1h [R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA.." "0,1"
line.word 0x2 "CFG_Reserved_5,"
rgroup.word 0x14++0x3
line.word 0x0 "CFG_RX_EVT_STS_ALT1_,Receive event and error status flag register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match FlagThis bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match FlagThis bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched data.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match FlagThis bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched ping.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received FlagThis bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No data frame has been received.1h [R] = A data frame has been.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun FlagThis bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can also.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received FlagThis bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No ping frame has been received.1h [R] = A ping frame has been.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received FlagThis bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No error frame has been received.1h [R] = An error frame has been.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun FlagThis bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done FlagThis bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No frame has been successfully received.1h [R] = A frame.." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun FlagThis bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Receive buffer overrun has not.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error FlagThis bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid end-of-frame has not been received.1h [R] =.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error FlagThis bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid frame type has not been received.1h [R] = Invalid frame.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error FlagThis bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC.." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout FlagThis bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Frame watchdog timeout has not occured.1h [R] = Frame.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout FlagThis bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Ping watchdog timeout has not occured.1h [R] = Ping watchdog.." "0,1"
line.word 0x2 "CFG_RX_CRC_INFO,Receive CRC info of received and computed CRC"
hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC ValueThis bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping.."
hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC ValueThis bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames."
wgroup.word 0x18++0x3
line.word 0x0 "CFG_RX_EVT_CLR_ALT1_,Receive event and error clear register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [R/W] = Writing a 0 to this bit will have no effect.1h [R/W] = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
line.word 0x2 "CFG_RX_EVT_FRC_ALT1_,Receive event and error flag force register"
bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
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bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W].." "0,1"
bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1"
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bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
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bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] = Writing.." "0,1"
bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
group.word 0x1C++0x1
line.word 0x0 "CFG_RX_BUF_PTR_LOAD,Receive buffer pointer load register"
hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load.This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The value.."
rgroup.word 0x1E++0x1
line.word 0x0 "CFG_RX_BUF_PTR_STS,Receive buffer pointer status register"
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive BufferThis bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer."
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer IndexThis bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission."
group.word 0x20++0x3
line.word 0x0 "CFG_RX_FRAME_WD_CTRL,Receive frame watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bitThis bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF].." "0,1"
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bitThis bit will reset the frame watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The frame watchdog counter will be reset to 0." "0,1"
line.word 0x2 "CFG_Reserved_6,"
group.long 0x24++0x3
line.long 0x0 "CFG_RX_FRAME_WD_REF,Receive frame watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference ValueThis is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached."
rgroup.long 0x28++0x3
line.long 0x0 "CFG_RX_FRAME_WD_CNT,Receive frame watchdog current count"
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST  a match with FRAME_WD_REF  or the.."
group.word 0x2C++0x1
line.word 0x0 "CFG_RX_PING_WD_CTRL,Receive ping watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bitThis bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached  it will generate a.." "0,1"
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bitThis bit will reset the ping watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The ping watchdog counter will be reset to 0." "0,1"
rgroup.word 0x2E++0x1
line.word 0x0 "CFG_RX_PING_TAG,Receive ping tag register"
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame TagThis field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x0 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.long 0x30++0x3
line.long 0x0 "CFG_RX_PING_WD_REF,Receive ping watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference ValueThis is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached."
rgroup.long 0x34++0x3
line.long 0x0 "CFG_RX_PING_WD_CNT,Receive pingwatchdog current count"
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST  a match with PING_WD_REF  or the reception.."
group.word 0x38++0x7
line.word 0x0 "CFG_RX_INT1_CTRL_ALT1_,Receive interrupt control register for RX_INT1. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A frame.." "0,1"
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = An.." "0,1"
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W].." "0,1"
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] =.." "0,1"
line.word 0x2 "CFG_RX_INT2_CTRL_ALT1_,Receive interrupt control register for RX_INT2. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A frame.." "0,1"
bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A buffer.." "0,1"
bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = An.." "0,1"
bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W].." "0,1"
bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] =.." "0,1"
line.word 0x4 "CFG_RX_LOCK_CTRL,Receive lock control register"
hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bitThis bit locks the contents of all the receive control registers that support a lock protection. Once locked  further writes will not take effect until SYSRS unlocks the register. Once set  further writes even to this.." "0,1"
line.word 0x6 "CFG_Reserved_7,"
group.long 0x40++0x3
line.long 0x0 "CFG_RX_ECC_DATA,Receive ECC data register"
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.."
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.."
group.word 0x44++0x3
line.word 0x0 "CFG_RX_ECC_VAL,Receive ECC value register"
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED checkThis field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register."
line.word 0x2 "CFG_Reserved_8,"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_RX_ECC_SEC_DATA,Receive ECC corrected data register"
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected DataThe ECC corrected data will be available in this register. This value is valid only when there are no bit errors  or a single bit error was detected. Otherwise  the contents of this register are invalid and should.."
rgroup.word 0x4C++0x1
line.word 0x0 "CFG_RX_ECC_LOG,Receive ECC log and status register"
bitfld.word 0x0 1. "MBE,Multiple Bit Errors DetectedThis bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set  the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h [R] Multiple Bit Errors.." "0,1"
bitfld.word 0x0 0. "SBE,Single Bit Error DetectedThis bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h [R] No bit errors were detected. The value in.." "0,1"
group.word 0x4E++0x7
line.word 0x0 "CFG_Reserved_9,"
line.word 0x2 "CFG_RX_FRAME_TAG_CMP,Receive frame tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x2 8. "CMP_EN,Frame Tag Compare Enable bitSet this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming frame tag will trigger the.." "0,1"
hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Frame Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.."
hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Frame Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames."
line.word 0x4 "CFG_RX_PING_TAG_CMP,Receive ping tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x4 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x4 8. "CMP_EN,Ping Tag Compare Enable bitSet this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming ping tag will trigger a ping frame tag.." "0,1"
hexmask.word.byte 0x4 4.--7. 1. "TAG_MASK,Ping Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.."
hexmask.word.byte 0x4 0.--3. 1. "TAG_REF,Ping Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames."
line.word 0x6 "CFG_Reserved_10,"
group.word 0x60++0x3
line.word 0x0 "CFG_RX_DLYLINE_CTRL,Receive delay line control register. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the.."
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the.."
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLKThis bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly from.."
line.word 0x2 "CFG_Reserved_11,"
rgroup.long 0x70++0x3
line.long 0x0 "CFG_RX_VIS_1,Receive debug visibility register 1"
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bitThis bit indicates the status of the receiver core. If this bit is set  the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1"
group.word 0x74++0x1
line.word 0x0 "CFG_Reserved_12,"
rgroup.word 0x80++0x1
line.word 0x0 "CFG_RX_BUF_BASE,Base address for receive data buffer"
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base AddressThis is the base address of the 16-word data buffer used by the receiver."
tree.end
tree "FSIRX5_CFG (FSIRX5_CFG)"
base ad:0x23550000
group.word 0x0++0xB
line.word 0x0 "CFG_RX_MASTER_CTRL_ALTB_,Receive master control register"
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1  the FSI RX inputs [RXCLK  RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1"
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bitThis bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module  acting as a SPI master  to clock data into the.." "0,1"
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bitThis bit enables the internal loopback functionality of the FSI receiver. By enabling this bit  a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1"
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bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset bitThis bit controls the receiver master core reset. In order to receive any frame  this bit must be cleared.Note: For reset to take affect  the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h.." "0,1"
line.word 0x2 "CFG_Reserved_1,"
line.word 0x4 "CFG_Reserved_2,"
line.word 0x6 "CFG_Reserved_3,"
line.word 0x8 "CFG_RX_OPER_CTRL,Receive operation control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x8 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bitThis bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h [R/W] = The ping watchdog.." "0,1"
bitfld.word 0x8 7. "ECC_SEL,ECC Data Width Select bitThis bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h [R/W] = 32-bit ECC is used.1h [R/W] = 16-bit ECC is used." "0,1"
hexmask.word.byte 0x8 3.--6. 1. "N_WORDS,Number of Words to ReceiveThis field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.."
bitfld.word 0x8 2. "SPI_MODE,SPI Mode Enable bitThis bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1"
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bitfld.word 0x8 0.--1. "DATA_WIDTH,Receive Data Width Select bitThese bits decide the number of data lines used for receiving data. 0h [R/W] = Data will be received on one data line  RXD0.1h [R/W] = Data will be received on two data lines  RXD0 and RXD1.2h  3h [R/W] = Reserved" "0,1,2,3"
line.word 0xA "CFG_Reserved_4,"
rgroup.word 0xC++0x3
line.word 0x0 "CFG_RX_FRAME_INFO,Receive frame control register"
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame TypeThis field indicates the type of frame that was successfully received last. 0000b [R/W] = A ping frame was received0100b [R/W] = A DATA_1_WORD frame was received [16-bit data].0101b [R/W] = A DATA_2_WORD frame was received.."
line.word 0x2 "CFG_RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User DataThis field contains the 8-bit user data field of the last successfully received frame."
hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame TagThis field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x2 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.word 0x10++0x3
line.word 0x0 "CFG_RX_DMA_CTRL,Receive DMA event control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bitThis bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h [R/W] = A DMA event will not be generated.1h [R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA.." "0,1"
line.word 0x2 "CFG_Reserved_5,"
rgroup.word 0x14++0x3
line.word 0x0 "CFG_RX_EVT_STS_ALT1_,Receive event and error status flag register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match FlagThis bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match FlagThis bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched data.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match FlagThis bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No tag-matched ping.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received FlagThis bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No data frame has been received.1h [R] = A data frame has been.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun FlagThis bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can also.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received FlagThis bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No ping frame has been received.1h [R] = A ping frame has been.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received FlagThis bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No error frame has been received.1h [R] = An error frame has been.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun FlagThis bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done FlagThis bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = No frame has been successfully received.1h [R] = A frame.." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun FlagThis bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Receive buffer overrun has not.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error FlagThis bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid end-of-frame has not been received.1h [R] =.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error FlagThis bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Invalid frame type has not been received.1h [R] = Invalid frame.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error FlagThis bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC.." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout FlagThis bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Frame watchdog timeout has not occured.1h [R] = Frame.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout FlagThis bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h [R] = Ping watchdog timeout has not occured.1h [R] = Ping watchdog.." "0,1"
line.word 0x2 "CFG_RX_CRC_INFO,Receive CRC info of received and computed CRC"
hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC ValueThis bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping.."
hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC ValueThis bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames."
wgroup.word 0x18++0x3
line.word 0x0 "CFG_RX_EVT_CLR_ALT1_,Receive event and error clear register"
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
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bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [R/W] = Writing a 0 to this bit will have no effect.1h [R/W] = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1"
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bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1"
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to.." "0,1"
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bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1"
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bitThis bit clears the corresponding bit in the RX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1"
line.word 0x2 "CFG_RX_EVT_FRC_ALT1_,Receive event and error flag force register"
bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
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bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W].." "0,1"
bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1"
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bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
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bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] = Writing.." "0,1"
bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bitThis bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1"
group.word 0x1C++0x1
line.word 0x0 "CFG_RX_BUF_PTR_LOAD,Receive buffer pointer load register"
hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load.This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The value.."
rgroup.word 0x1E++0x1
line.word 0x0 "CFG_RX_BUF_PTR_STS,Receive buffer pointer status register"
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive BufferThis bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer."
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer IndexThis bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission."
group.word 0x20++0x3
line.word 0x0 "CFG_RX_FRAME_WD_CTRL,Receive frame watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bitThis bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF].." "0,1"
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bitThis bit will reset the frame watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The frame watchdog counter will be reset to 0." "0,1"
line.word 0x2 "CFG_Reserved_6,"
group.long 0x24++0x3
line.long 0x0 "CFG_RX_FRAME_WD_REF,Receive frame watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference ValueThis is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached."
rgroup.long 0x28++0x3
line.long 0x0 "CFG_RX_FRAME_WD_CNT,Receive frame watchdog current count"
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST  a match with FRAME_WD_REF  or the.."
group.word 0x2C++0x1
line.word 0x0 "CFG_RX_PING_WD_CTRL,Receive ping watchdog control register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bitThis bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached  it will generate a.." "0,1"
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bitThis bit will reset the ping watchdog counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [W] = The ping watchdog counter will be reset to 0." "0,1"
rgroup.word 0x2E++0x1
line.word 0x0 "CFG_RX_PING_TAG,Receive ping tag register"
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame TagThis field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag."
bitfld.word 0x0 0. "ZERO,Zero bitThis bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0]  application software can directly index into an array of 32-bit data." "?,?"
group.long 0x30++0x3
line.long 0x0 "CFG_RX_PING_WD_REF,Receive ping watchdog counter reference. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference ValueThis is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached."
rgroup.long 0x34++0x3
line.long 0x0 "CFG_RX_PING_WD_CNT,Receive pingwatchdog current count"
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter ValueThis is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST  a match with PING_WD_REF  or the reception.."
group.word 0x38++0x7
line.word 0x0 "CFG_RX_INT1_CTRL_ALT1_,Receive interrupt control register for RX_INT1. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A frame.." "0,1"
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = An.." "0,1"
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A.." "0,1"
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bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W].." "0,1"
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bitThis is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT1.1h [R/W] =.." "0,1"
line.word 0x2 "CFG_RX_INT2_CTRL_ALT1_,Receive interrupt control register for RX_INT2. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on.." "0,1"
bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A frame.." "0,1"
bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A buffer.." "0,1"
bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = An.." "0,1"
bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A.." "0,1"
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bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] = A CRC error.." "0,1"
bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W].." "0,1"
bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bitThis is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h [R/W] = This event will not trigger an interrupt on RX_INT2.1h [R/W] =.." "0,1"
line.word 0x4 "CFG_RX_LOCK_CTRL,Receive lock control register"
hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key.In order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bitThis bit locks the contents of all the receive control registers that support a lock protection. Once locked  further writes will not take effect until SYSRS unlocks the register. Once set  further writes even to this.." "0,1"
line.word 0x6 "CFG_Reserved_7,"
group.long 0x40++0x3
line.long 0x0 "CFG_RX_ECC_DATA,Receive ECC data register"
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.."
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.."
group.word 0x44++0x3
line.word 0x0 "CFG_RX_ECC_VAL,Receive ECC value register"
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED checkThis field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register."
line.word 0x2 "CFG_Reserved_8,"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_RX_ECC_SEC_DATA,Receive ECC corrected data register"
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected DataThe ECC corrected data will be available in this register. This value is valid only when there are no bit errors  or a single bit error was detected. Otherwise  the contents of this register are invalid and should.."
rgroup.word 0x4C++0x1
line.word 0x0 "CFG_RX_ECC_LOG,Receive ECC log and status register"
bitfld.word 0x0 1. "MBE,Multiple Bit Errors DetectedThis bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set  the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h [R] Multiple Bit Errors.." "0,1"
bitfld.word 0x0 0. "SBE,Single Bit Error DetectedThis bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h [R] No bit errors were detected. The value in.." "0,1"
group.word 0x4E++0x7
line.word 0x0 "CFG_Reserved_9,"
line.word 0x2 "CFG_RX_FRAME_TAG_CMP,Receive frame tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x2 8. "CMP_EN,Frame Tag Compare Enable bitSet this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming frame tag will trigger the.." "0,1"
hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Frame Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.."
hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Frame Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames."
line.word 0x4 "CFG_RX_PING_TAG_CMP,Receive ping tag compare register. Protected by LOCK field in RX_LOCK_CTRL register."
bitfld.word 0x4 9. "BROADCAST_EN,Broadcast Enable bitThis will enable the reception of a ping frame broadcast. When this bit is set  bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1  a ping tag match event will.." "0,1"
bitfld.word 0x4 8. "CMP_EN,Ping Tag Compare Enable bitSet this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK  TAG_REF  and the incoming ping tag will trigger a ping frame tag.." "0,1"
hexmask.word.byte 0x4 4.--7. 1. "TAG_MASK,Ping Tag MaskAny bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.."
hexmask.word.byte 0x4 0.--3. 1. "TAG_REF,Ping Tag ReferenceThe reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames."
line.word 0x6 "CFG_Reserved_10,"
group.word 0x60++0x3
line.word 0x0 "CFG_RX_DLYLINE_CTRL,Receive delay line control register. Protected by LOCK field in RX_LOCK_CTRL register."
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the.."
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the.."
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLKThis bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h [R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly from.."
line.word 0x2 "CFG_Reserved_11,"
rgroup.long 0x70++0x3
line.long 0x0 "CFG_RX_VIS_1,Receive debug visibility register 1"
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bitThis bit indicates the status of the receiver core. If this bit is set  the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1"
group.word 0x74++0x1
line.word 0x0 "CFG_Reserved_12,"
rgroup.word 0x80++0x1
line.word 0x0 "CFG_RX_BUF_BASE,Base address for receive data buffer"
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base AddressThis is the base address of the 16-word data buffer used by the receiver."
tree.end
tree.end
tree "FSITX"
base ad:0x0
tree "FSITX0_CFG (FSITX0_CFG)"
base ad:0x23600000
group.word 0x0++0x11
line.word 0x0 "CFG_TX_MASTER_CTRL,Transmit master control register"
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write KeyIn order to write to any bit in this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x0 1. "FLUSH,Flush Operation Start bitThis bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the.." "0,1"
bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset bitThis bit controls the transmitter master core reset. In order to send any frame  this bit must be cleared. 0h [R/W] = Transmitter core is not in reset and can transmit frames.1h [R/W] = Transmitter core is held.." "0,1"
line.word 0x2 "CFG_Reserved_1,"
line.word 0x4 "CFG_TX_CLK_CTRL,Transmit clock control register. Protected by LOCK field in TX_LOCK_CTRL register."
hexmask.word.byte 0x4 2.--9. 1. "PRESCALE_VAL,Clock Divider Prescale ValueThe input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h [R/W] = Reserved1h [R/W] = Input clock /12h [R/W] = Input clock /23h.."
bitfld.word 0x4 1. "CLK_EN,Clock Divider Enable bitThis bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h [R/W] = The input clock divider is not enabled and the clock is not connected to the transmitter core.1h [R/W] = The.." "0,1"
bitfld.word 0x4 0. "CLK_RST,Clock Divider Reset bitThis bit will reset the clock counter in the clock divider. 0h [R/W] = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set.1h [R/W] = The clock.." "0,1"
line.word 0x6 "CFG_Reserved_2,"
line.word 0x8 "CFG_TX_OPER_CTRL_LO_ALT1_,Transmit operation control register low. Protected by LOCK field in TX_LOCK_CTRL register."
bitfld.word 0x8 9. "TDM_ENABLE,Transmit TDM Mode Enable bit.This bit enables the TDM Mode for multi-slave TDM operation. 0h [R/W] Transmit TDM Mode is not enabled.1h [R/W] Transmit TDM Mode is enabled." "0,1"
bitfld.word 0x8 8. "SEL_PLLCLK,Input Clock Select bitThis bit selects the input clock source for the transmitter core. 0h [R/W] = SYSCLK is the source of the transmitter clock into the clock prescaler.1h [R/W] = PLLRAWCLK is the source of the transmitter core clock into the.." "0,1"
bitfld.word 0x8 7. "PING_TO_MODE,Ping Counter Reset Mode Select bitThis bit selects when the ping counter will reset. 0h [R/W] = The ping counter will reset and restart only on hardware initiated ping frames  when ping counter has timed out.1h [R/W] = The ping counter will.." "0,1"
bitfld.word 0x8 6. "SW_CRC,CRC Source Select bitThis bit selects the source of the CRC value that is transmitted. 0h [R/W] = The transmitted CRC value is computed by hardware.1h [R/W] = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC.." "0,1"
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bitfld.word 0x8 3.--5. "START_MODE,Transmission Start Mode Select bitThese bits select the method by which a new frame transmission is started. 0h [R/W] = Only a software write to TX_FRAME_CTRL.START initiate a new transmission.1h [R/W] = The configured external trigger will.." "0,1,2,3,4,5,6,7"
bitfld.word 0x8 2. "SPI_MODE,SPI Mode Select bitThis bit enables and disables SPI compatibility mode. 0h [R/W] = FSI is in normal mode of operation.1h [R/W] = FSI is operating in SPI compatibility mode." "0,1"
bitfld.word 0x8 0.--1. "DATA_WIDTH,Transmit Data Width Select bitsThese bits define the number of data lines used by the transmitter. 0h [R/W] = Data will be transmitted on one data line [TXD0]1h [R/W] = Data will be transmitted on two data lines [TXD0 and TXD1]. The format of.." "0,1,2,3"
line.word 0xA "CFG_TX_OPER_CTRL_HI_ALT1_,Transmit operation control register high. Protected by LOCK field in TX_LOCK_CTRL register."
hexmask.word.byte 0xA 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select bitThese bits define which of the 32 external inputs will be used as the source for the external input trigger. 00h [R/W] = Trigger 1 is the source.01h [R/W] = Trigger 2 is the source.02h [R/W] = Trigger 3 is the.."
bitfld.word 0xA 6. "ECC_SEL,ECC Data Width Select bitThis bit selects between 16-bit and 32-bit ECC computation. 0h [R/W] = 32-bit ECC is used.1h [R/W] = 16-bit ECC is used." "0,1"
bitfld.word 0xA 5. "FORCE_ERR,Error Frame Force bitThis bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The.." "0,1"
line.word 0xC "CFG_TX_FRAME_CTRL,Transmit frame control register"
bitfld.word 0xC 15. "START,Start Transmission bitThis bit will cause the FSI to start transmitting the next frame. 0h [R/W] = Writing a 0 to this bit will have no effect.1h [R/W] = Start the next transmission. This bit will be cleared by hardware." "0,1"
hexmask.word.byte 0xC 4.--7. 1. "N_WORDS,Number of Words to be TransmittedThis field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than.."
hexmask.word.byte 0xC 0.--3. 1. "FRAME_TYPE,Transmit Frame TypeThis field determines the type of frame that will be transmitted next. 0000b [R/W] = Ping Frame. This frame can be sent either by software or automatically by hardware.0100b [R/W] = DATA_1_WORD Frame. One word data frame.."
line.word 0xE "CFG_TX_FRAME_TAG_UDATA,Transmit frame tag and user data register"
hexmask.word.byte 0xE 8.--15. 1. "USER_DATA,User Data bitsThis is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior."
hexmask.word.byte 0xE 0.--3. 1. "FRAME_TAG,This will be used only for software initiated transmissions.Frame tag bitsThis is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This.."
line.word 0x10 "CFG_TX_BUF_PTR_LOAD,Transmit buffer pointer control load register"
hexmask.word.byte 0x10 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load bitsThese bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be.."
rgroup.word 0x12++0x1
line.word 0x0 "CFG_TX_BUF_PTR_STS,Transmit buffer pointer control status register"
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be.."
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer IndexThis bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission."
group.word 0x14++0x3
line.word 0x0 "CFG_TX_PING_CTRL_ALT1_,Transmit ping control register. Protected by LOCK field in TX_LOCK_CTRL register."
hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select bitsThis bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h [R/W] = Trigger 1 will be used to.."
bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable bitThis bit will allow the external trigger logic to generate a ping frame. 0h [R/W] = External triggers will not be used to generate ping frames.1h [R/W] = The selected external trigger [selected by EXT_TRIG_SEL bits].." "0,1"
bitfld.word 0x0 1. "TIMER_EN,Ping Timer Enable bitThis bit will enable the ping timer for generating periodic ping frames. 0h [R/W] = The ping timer is disabled and will not generate ping frames.1h [R/W] = The ping timer is enabled and can be used to generate ping.." "0,1"
bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset bitThis bit will reset the the ping counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [R/W] = The ping counter will be reset to 0." "0,1"
line.word 0x2 "CFG_TX_PING_TAG,Transmit ping tag register"
hexmask.word.byte 0x2 0.--3. 1. "TAG,Ping Frame TagThis field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is.."
group.long 0x18++0x3
line.long 0x0 "CFG_TX_PING_TO_REF,Transmit ping timeout counter reference. Protected by LOCK field in TX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference Value.This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached  it will generate a timeout event  triggering a ping frame transmission."
rgroup.long 0x1C++0x3
line.long 0x0 "CFG_TX_PING_TO_CNT,Transmit ping timeout current count"
hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter ValueThis register contains the current value of the ping timer counter. After reset  this counter will increment until it reaches the reference value [TX_PING_TO_REF]  at which point it generates a ping frame transmission."
group.word 0x20++0x7
line.word 0x0 "CFG_TX_INT_CTRL,Transmit interrupt event control register. Protected by LOCK field in TX_LOCK_CTRL register."
bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable PING Timer Interrupt to INT2This bit allows the event to generate an interrupt on the INT2 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT2.1h [R/W] = The ping timer event will trigger an interrupt on TX_INT2." "0,1"
bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2This bit allows the event to generate an interrupt on the INT2 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT2.1h [R/W] = A Buffer Overrun condition will trigger an interrupt.." "0,1"
bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2This bit allows the event to generate an interrupt on the INT2 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT2.1h [R/W] = A Buffer Underrun condition will trigger an.." "0,1"
bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done interrupt to INT2This bit allows the event to generate an interrupt on the INT2 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT2.1h [R/W] = A Frame Done event will trigger an interrupt on TX_INT2." "0,1"
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bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1This bit allows the event to generate an interrupt on the INT1 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT1.1h [R/W] = The ping timer event will trigger an interrupt on TX_INT1." "0,1"
bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1This bit allows the event to generate an interrupt on the INT1 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT1.1h [R/W] = A Buffer Overrun condition will trigger an interrupt.." "0,1"
bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1This bit allows the event to generate an interrupt on the INT1 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT1.1h [R/W] = A Buffer Underrun condition will trigger an.." "0,1"
bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done interrupt to INT1This bit allows the event to generate an interrupt on the INT1 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT1.1h [R/W] = A Frame Done event will trigger an interrupt on TX_INT1." "0,1"
line.word 0x2 "CFG_TX_DMA_CTRL,Transmit DMA event control register. Protected by LOCK field in TX_LOCK_CTRL register."
bitfld.word 0x2 0. "DMA_EVT_EN,DMA Event Enable bitThis bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h [R/W] = A DMA event will not be generated.1h [R/W] = A DMA event will be generated upon the completion of a transmitted frame." "0,1"
line.word 0x4 "CFG_TX_LOCK_CTRL,Transmit lock control register"
hexmask.word.byte 0x4 8.--15. 1. "KEY,Write KeyIn order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bitThis bit locks the contents of all the transmit control registers that support a lock protection. Once locked  further writes will not take effect until a SYSRS has reset this register. Once set  further writes to.." "0,1"
line.word 0x6 "CFG_Reserved_3,"
rgroup.word 0x28++0x1
line.word 0x0 "CFG_TX_EVT_STS,Transmit event and error status flag register"
bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag BitThis bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by writing.." "0,1"
bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag BitThis bit inditcates that buffer overrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h [R] = Buffer Overrun has not occured.1h [R] = Buffer Overrun has occured. To.." "0,1"
bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag BitThis bit inditcates that buffer underrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h [R] = Buffer Underrun has not occured.1h [R] = Buffer Underrun has occured." "0,1"
bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag BitThis bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h [R] = Frame Done.." "0,1"
group.word 0x2A++0x1
line.word 0x0 "CFG_Reserved_4,"
wgroup.word 0x2C++0x3
line.word 0x0 "CFG_TX_EVT_CLR,Transmit event and error clear register"
bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear bitThis bit clears the corresponding bit in the TX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1"
bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear bitThis bit clears the corresponding bit in the TX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register.." "0,1"
bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear bitThis bit clears the corresponding bit in the TX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register.." "0,1"
bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear bitThis bit clears the corresponding bit in the TX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0." "0,1"
line.word 0x2 "CFG_TX_EVT_FRC,Transmit event and error flag force register"
bitfld.word 0x2 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force bitThis bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 2. "BUF_OVERRUN,Buffer Overrun Flag Force bitThis bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [R/W].." "0,1"
bitfld.word 0x2 1. "BUF_UNDERRUN,Buffer Underrun Flag Force bitThis bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W].." "0,1"
bitfld.word 0x2 0. "FRAME_DONE,Frame Done Flag Force bitThis bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
group.word 0x30++0x3
line.word 0x0 "CFG_TX_USER_CRC,Transmit user-defined CRC register"
hexmask.word.byte 0x0 0.--7. 1. "USER_CRC,User-defined CRCThis register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option [TX_OPER_CTRL_LO.SW_CRC = 1]. This register is ignored if the hardware CRC generation is.."
line.word 0x2 "CFG_Reserved_5,"
group.long 0x34++0xF
line.long 0x0 "CFG_Reserved_6,"
line.long 0x4 "CFG_Reserved_7,"
line.long 0x8 "CFG_Reserved_8,"
line.long 0xC "CFG_TX_ECC_DATA,Transmit ECC data register"
hexmask.long.word 0xC 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.."
hexmask.long.word 0xC 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.."
rgroup.word 0x44++0x1
line.word 0x0 "CFG_TX_ECC_VAL,Transmit ECC value register"
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC ValueThis field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register."
group.word 0x46++0x1
line.word 0x0 "CFG_Reserved_9,"
group.word 0x80++0x1
line.word 0x0 "CFG_TX_BUF_BASE,Base address for transmit buffer"
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base AddressThis is the base address of the 16-word data buffer used by the transmitter."
tree.end
tree "FSITX1_CFG (FSITX1_CFG)"
base ad:0x23610000
group.word 0x0++0x11
line.word 0x0 "CFG_TX_MASTER_CTRL,Transmit master control register"
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write KeyIn order to write to any bit in this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x0 1. "FLUSH,Flush Operation Start bitThis bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the.." "0,1"
bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset bitThis bit controls the transmitter master core reset. In order to send any frame  this bit must be cleared. 0h [R/W] = Transmitter core is not in reset and can transmit frames.1h [R/W] = Transmitter core is held.." "0,1"
line.word 0x2 "CFG_Reserved_1,"
line.word 0x4 "CFG_TX_CLK_CTRL,Transmit clock control register. Protected by LOCK field in TX_LOCK_CTRL register."
hexmask.word.byte 0x4 2.--9. 1. "PRESCALE_VAL,Clock Divider Prescale ValueThe input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h [R/W] = Reserved1h [R/W] = Input clock /12h [R/W] = Input clock /23h.."
bitfld.word 0x4 1. "CLK_EN,Clock Divider Enable bitThis bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h [R/W] = The input clock divider is not enabled and the clock is not connected to the transmitter core.1h [R/W] = The.." "0,1"
bitfld.word 0x4 0. "CLK_RST,Clock Divider Reset bitThis bit will reset the clock counter in the clock divider. 0h [R/W] = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set.1h [R/W] = The clock.." "0,1"
line.word 0x6 "CFG_Reserved_2,"
line.word 0x8 "CFG_TX_OPER_CTRL_LO_ALT1_,Transmit operation control register low. Protected by LOCK field in TX_LOCK_CTRL register."
bitfld.word 0x8 9. "TDM_ENABLE,Transmit TDM Mode Enable bit.This bit enables the TDM Mode for multi-slave TDM operation. 0h [R/W] Transmit TDM Mode is not enabled.1h [R/W] Transmit TDM Mode is enabled." "0,1"
bitfld.word 0x8 8. "SEL_PLLCLK,Input Clock Select bitThis bit selects the input clock source for the transmitter core. 0h [R/W] = SYSCLK is the source of the transmitter clock into the clock prescaler.1h [R/W] = PLLRAWCLK is the source of the transmitter core clock into the.." "0,1"
bitfld.word 0x8 7. "PING_TO_MODE,Ping Counter Reset Mode Select bitThis bit selects when the ping counter will reset. 0h [R/W] = The ping counter will reset and restart only on hardware initiated ping frames  when ping counter has timed out.1h [R/W] = The ping counter will.." "0,1"
bitfld.word 0x8 6. "SW_CRC,CRC Source Select bitThis bit selects the source of the CRC value that is transmitted. 0h [R/W] = The transmitted CRC value is computed by hardware.1h [R/W] = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC.." "0,1"
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bitfld.word 0x8 3.--5. "START_MODE,Transmission Start Mode Select bitThese bits select the method by which a new frame transmission is started. 0h [R/W] = Only a software write to TX_FRAME_CTRL.START initiate a new transmission.1h [R/W] = The configured external trigger will.." "0,1,2,3,4,5,6,7"
bitfld.word 0x8 2. "SPI_MODE,SPI Mode Select bitThis bit enables and disables SPI compatibility mode. 0h [R/W] = FSI is in normal mode of operation.1h [R/W] = FSI is operating in SPI compatibility mode." "0,1"
bitfld.word 0x8 0.--1. "DATA_WIDTH,Transmit Data Width Select bitsThese bits define the number of data lines used by the transmitter. 0h [R/W] = Data will be transmitted on one data line [TXD0]1h [R/W] = Data will be transmitted on two data lines [TXD0 and TXD1]. The format of.." "0,1,2,3"
line.word 0xA "CFG_TX_OPER_CTRL_HI_ALT1_,Transmit operation control register high. Protected by LOCK field in TX_LOCK_CTRL register."
hexmask.word.byte 0xA 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select bitThese bits define which of the 32 external inputs will be used as the source for the external input trigger. 00h [R/W] = Trigger 1 is the source.01h [R/W] = Trigger 2 is the source.02h [R/W] = Trigger 3 is the.."
bitfld.word 0xA 6. "ECC_SEL,ECC Data Width Select bitThis bit selects between 16-bit and 32-bit ECC computation. 0h [R/W] = 32-bit ECC is used.1h [R/W] = 16-bit ECC is used." "0,1"
bitfld.word 0xA 5. "FORCE_ERR,Error Frame Force bitThis bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The.." "0,1"
line.word 0xC "CFG_TX_FRAME_CTRL,Transmit frame control register"
bitfld.word 0xC 15. "START,Start Transmission bitThis bit will cause the FSI to start transmitting the next frame. 0h [R/W] = Writing a 0 to this bit will have no effect.1h [R/W] = Start the next transmission. This bit will be cleared by hardware." "0,1"
hexmask.word.byte 0xC 4.--7. 1. "N_WORDS,Number of Words to be TransmittedThis field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than.."
hexmask.word.byte 0xC 0.--3. 1. "FRAME_TYPE,Transmit Frame TypeThis field determines the type of frame that will be transmitted next. 0000b [R/W] = Ping Frame. This frame can be sent either by software or automatically by hardware.0100b [R/W] = DATA_1_WORD Frame. One word data frame.."
line.word 0xE "CFG_TX_FRAME_TAG_UDATA,Transmit frame tag and user data register"
hexmask.word.byte 0xE 8.--15. 1. "USER_DATA,User Data bitsThis is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior."
hexmask.word.byte 0xE 0.--3. 1. "FRAME_TAG,This will be used only for software initiated transmissions.Frame tag bitsThis is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This.."
line.word 0x10 "CFG_TX_BUF_PTR_LOAD,Transmit buffer pointer control load register"
hexmask.word.byte 0x10 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load bitsThese bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be.."
rgroup.word 0x12++0x1
line.word 0x0 "CFG_TX_BUF_PTR_STS,Transmit buffer pointer control status register"
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be.."
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer IndexThis bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission."
group.word 0x14++0x3
line.word 0x0 "CFG_TX_PING_CTRL_ALT1_,Transmit ping control register. Protected by LOCK field in TX_LOCK_CTRL register."
hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select bitsThis bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h [R/W] = Trigger 1 will be used to.."
bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable bitThis bit will allow the external trigger logic to generate a ping frame. 0h [R/W] = External triggers will not be used to generate ping frames.1h [R/W] = The selected external trigger [selected by EXT_TRIG_SEL bits].." "0,1"
bitfld.word 0x0 1. "TIMER_EN,Ping Timer Enable bitThis bit will enable the ping timer for generating periodic ping frames. 0h [R/W] = The ping timer is disabled and will not generate ping frames.1h [R/W] = The ping timer is enabled and can be used to generate ping.." "0,1"
bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset bitThis bit will reset the the ping counter to 0. This bit will always be read as 0. 0h [R/W] = Writing a 0 to this bit has no effect.1h [R/W] = The ping counter will be reset to 0." "0,1"
line.word 0x2 "CFG_TX_PING_TAG,Transmit ping tag register"
hexmask.word.byte 0x2 0.--3. 1. "TAG,Ping Frame TagThis field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is.."
group.long 0x18++0x3
line.long 0x0 "CFG_TX_PING_TO_REF,Transmit ping timeout counter reference. Protected by LOCK field in TX_LOCK_CTRL register."
hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference Value.This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached  it will generate a timeout event  triggering a ping frame transmission."
rgroup.long 0x1C++0x3
line.long 0x0 "CFG_TX_PING_TO_CNT,Transmit ping timeout current count"
hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter ValueThis register contains the current value of the ping timer counter. After reset  this counter will increment until it reaches the reference value [TX_PING_TO_REF]  at which point it generates a ping frame transmission."
group.word 0x20++0x7
line.word 0x0 "CFG_TX_INT_CTRL,Transmit interrupt event control register. Protected by LOCK field in TX_LOCK_CTRL register."
bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable PING Timer Interrupt to INT2This bit allows the event to generate an interrupt on the INT2 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT2.1h [R/W] = The ping timer event will trigger an interrupt on TX_INT2." "0,1"
bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2This bit allows the event to generate an interrupt on the INT2 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT2.1h [R/W] = A Buffer Overrun condition will trigger an interrupt.." "0,1"
bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2This bit allows the event to generate an interrupt on the INT2 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT2.1h [R/W] = A Buffer Underrun condition will trigger an.." "0,1"
bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done interrupt to INT2This bit allows the event to generate an interrupt on the INT2 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT2.1h [R/W] = A Frame Done event will trigger an interrupt on TX_INT2." "0,1"
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bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1This bit allows the event to generate an interrupt on the INT1 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT1.1h [R/W] = The ping timer event will trigger an interrupt on TX_INT1." "0,1"
bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1This bit allows the event to generate an interrupt on the INT1 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT1.1h [R/W] = A Buffer Overrun condition will trigger an interrupt.." "0,1"
bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1This bit allows the event to generate an interrupt on the INT1 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT1.1h [R/W] = A Buffer Underrun condition will trigger an.." "0,1"
bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done interrupt to INT1This bit allows the event to generate an interrupt on the INT1 line. 0h [R/W] = This event will not trigger an interrupt on TX_INT1.1h [R/W] = A Frame Done event will trigger an interrupt on TX_INT1." "0,1"
line.word 0x2 "CFG_TX_DMA_CTRL,Transmit DMA event control register. Protected by LOCK field in TX_LOCK_CTRL register."
bitfld.word 0x2 0. "DMA_EVT_EN,DMA Event Enable bitThis bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h [R/W] = A DMA event will not be generated.1h [R/W] = A DMA event will be generated upon the completion of a transmitted frame." "0,1"
line.word 0x4 "CFG_TX_LOCK_CTRL,Transmit lock control register"
hexmask.word.byte 0x4 8.--15. 1. "KEY,Write KeyIn order to write to this register  0xA5 must be written to this field at the same time. Otherwise  writes are ignored. The key is cleared immediately after writing  so it must be written again for every change to this register."
bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bitThis bit locks the contents of all the transmit control registers that support a lock protection. Once locked  further writes will not take effect until a SYSRS has reset this register. Once set  further writes to.." "0,1"
line.word 0x6 "CFG_Reserved_3,"
rgroup.word 0x28++0x1
line.word 0x0 "CFG_TX_EVT_STS,Transmit event and error status flag register"
bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag BitThis bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by writing.." "0,1"
bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag BitThis bit inditcates that buffer overrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h [R] = Buffer Overrun has not occured.1h [R] = Buffer Overrun has occured. To.." "0,1"
bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag BitThis bit inditcates that buffer underrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h [R] = Buffer Underrun has not occured.1h [R] = Buffer Underrun has occured." "0,1"
bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag BitThis bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h [R] = Frame Done.." "0,1"
group.word 0x2A++0x1
line.word 0x0 "CFG_Reserved_4,"
wgroup.word 0x2C++0x3
line.word 0x0 "CFG_TX_EVT_CLR,Transmit event and error clear register"
bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear bitThis bit clears the corresponding bit in the TX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1"
bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear bitThis bit clears the corresponding bit in the TX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register.." "0,1"
bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear bitThis bit clears the corresponding bit in the TX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register.." "0,1"
bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear bitThis bit clears the corresponding bit in the TX_EVT_STS register. 0h [W] = Writing a 0 to this bit will have no effect.1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0." "0,1"
line.word 0x2 "CFG_TX_EVT_FRC,Transmit event and error flag force register"
bitfld.word 0x2 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force bitThis bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1"
bitfld.word 0x2 2. "BUF_OVERRUN,Buffer Overrun Flag Force bitThis bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [R/W].." "0,1"
bitfld.word 0x2 1. "BUF_UNDERRUN,Buffer Underrun Flag Force bitThis bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W].." "0,1"
bitfld.word 0x2 0. "FRAME_DONE,Frame Done Flag Force bitThis bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h [W] =.." "0,1"
group.word 0x30++0x3
line.word 0x0 "CFG_TX_USER_CRC,Transmit user-defined CRC register"
hexmask.word.byte 0x0 0.--7. 1. "USER_CRC,User-defined CRCThis register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option [TX_OPER_CTRL_LO.SW_CRC = 1]. This register is ignored if the hardware CRC generation is.."
line.word 0x2 "CFG_Reserved_5,"
group.long 0x34++0xF
line.long 0x0 "CFG_Reserved_6,"
line.long 0x4 "CFG_Reserved_7,"
line.long 0x8 "CFG_Reserved_8,"
line.long 0xC "CFG_TX_ECC_DATA,Transmit ECC data register"
hexmask.long.word 0xC 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.."
hexmask.long.word 0xC 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC DataWriting to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.."
rgroup.word 0x44++0x1
line.word 0x0 "CFG_TX_ECC_VAL,Transmit ECC value register"
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC ValueThis field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register."
group.word 0x46++0x1
line.word 0x0 "CFG_Reserved_9,"
group.word 0x80++0x1
line.word 0x0 "CFG_TX_BUF_BASE,Base address for transmit buffer"
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base AddressThis is the base address of the 16-word data buffer used by the transmitter."
tree.end
tree.end
tree "FSS0"
base ad:0x0
tree "FSS0_CFG (FSS0_CFG)"
base ad:0xFC00000
rgroup.long 0x0++0x3
line.long 0x0 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility"
hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision"
tree.end
base ad:0x0
tree "FSS0_FSAS_0"
tree "FSS0_FSAS_0_DAT"
tree "FSS0_FSAS_0_DAT_REG0 (FSS0_FSAS_0_DAT_REG0)"
base ad:0x400000000
group.long 0x0++0x3
line.long 0x0 "DAT_REG0_hpb_data_mem,FSAS data region0"
hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region0"
tree.end
tree "FSS0_FSAS_0_DAT_REG1 (FSS0_FSAS_0_DAT_REG1)"
base ad:0x60000000
group.long 0x0++0x3
line.long 0x0 "DAT_REG1_hpb_data_mem,FSAS boot data region1"
hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region1"
tree.end
tree "FSS0_FSAS_0_DAT_REG3 (FSS0_FSAS_0_DAT_REG3)"
base ad:0x500000000
group.long 0x0++0x3
line.long 0x0 "DAT_REG3_hpb_data_mem,FSAS bypass data region3"
hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region1"
tree.end
tree.end
tree "FSS0_FSAS_0_FSAS_CFG (FSS0_FSAS_0_FSAS_CFG)"
base ad:0xFC10000
rgroup.long 0x0++0x3
line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility"
hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision"
group.long 0x4++0x1F
line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_SYSCONFIG,Controls various parameters of the cotroller state."
bitfld.long 0x0 8. "OSPI_32B_DISABLE_MODE,0 OSPI 32bit mode enabled. 1 OSPI 32bit mode disabled" "0,1"
bitfld.long 0x0 7. "DISXIP,0 XIP Prefetch Enabled. 1 XIP prefetch disabled" "0,1"
bitfld.long 0x0 6. "OSPI_DDR_DISABLE_MODE,0 OSPI DDR mode enabled. 1 OSPI DDR mode disabled" "0,1"
newline
bitfld.long 0x0 3. "ECC_DISABLE_ADR,0 Block address within ECC calculation  1 Block address not within ECC calculation" "0,1"
rbitfld.long 0x0 2. "FSS_AES_EN_IPCFG,1 select security  0 disable security" "0,1"
bitfld.long 0x0 0. "ECC_EN,0 ECC disabled. 1 ECC enabled" "0,1"
line.long 0x4 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_FRAG_ADR,This FRAG_ADR is the address of a request that frag_hi or frag_lo boundary occurs"
hexmask.long 0x4 0.--31. 1. "FRAG_ADDR,This address is used to determine the boundary of frag_hi and flag_lo"
line.long 0x8 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_FRAG_CTL,The FRAG_CTL determins which frag region is fragmented"
bitfld.long 0x8 1. "FRAG_HI,When set any address greater than or equal to frag_addr will be fragmented to 16 bits" "0,1"
bitfld.long 0x8 0. "FRAG_LO,When set any address less than frag_addr will be fragmented to 16 bits" "0,1"
line.long 0xC "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_EOI,The End of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the EOI for MISC interrupt sources. An eoi_write signal will be generated and another interrupt will be.."
bitfld.long 0xC 0. "EOI_VECTOR,Write with bit position of targeted interrupt. (E.g. Ext FSS ECC is bit 0). Upon write  level interrupt will clear and if un-serviced will issue another pulse interrupt" "0,1"
line.long 0x10 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_STATUS_RAW,The IRQ_STATUS_RAW register allows the interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x10 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1"
bitfld.long 0x10 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1"
bitfld.long 0x10 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1"
line.long 0x14 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_STATUS,The IRQ_STATUS register allows the interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x14 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1"
bitfld.long 0x14 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1"
bitfld.long 0x14 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1"
line.long 0x18 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ENABLE_SET,The IRQ_ENABLE_SET register allows the interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled"
bitfld.long 0x18 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1"
bitfld.long 0x18 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1"
bitfld.long 0x18 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1"
line.long 0x1C "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ENABLE_CLR,The IRQ_ENABLE_CLR register allows the interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled"
bitfld.long 0x1C 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1"
bitfld.long 0x1C 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1"
bitfld.long 0x1C 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1"
group.long 0x30++0x7
line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_RGSTRT,This defines the start of the ECC region in 4KBytes steps."
hexmask.long.tbyte 0x0 0.--19. 1. "R_START,This defines the start of the ECC region in 4KBytes steps. Address start = {start[19:0]  0x000} 0x0 means the start is 0x0000_0000 0x1 means the start is 0x0000_1000 0xA means the start is 0x0000_A000 Note the offset + size should be <=.."
line.long 0x4 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_RGSIZ,This defines the size of the ECC region in 4KBytes steps."
hexmask.long.tbyte 0x4 0.--19. 1. "R_SIZE,This defines the size of the ECC region in 4KBytes steps 0x0 means the size is zero and disabled 0x1 means the size is 4KBytes 0xA means the size is 40KBytes 0xF_FFFF means the size is 4GBytes Note the offset + size should be <= 4GBytes  wrap.."
rgroup.long 0x70++0x3
line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_BLOCK_ADR,The ERR_ECC_BLOCK_ADR register holds the current top of stack ECC error block address. this is only valid when the ecc_err_valid is set"
hexmask.long 0x0 5.--31. 1. "ECC_ERROR_BLOCK_ADDR,ECC 32 byte aligned block address"
group.long 0x74++0x7
line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_TYPE,The ERR_ECC_TYPE register holds the current top of stack ECC error info. this is only valid when the ecc_err_valid is set"
bitfld.long 0x0 31. "ECC_ERR_VALID,When set indicates that there is valid ECC error information available  Writing a one to this register will pop the top of the stack" "0,1"
rbitfld.long 0x0 5. "ECC_ERR_ADR,When set indicates that there was a single error detected within the address field" "0,1"
rbitfld.long 0x0 4. "ECC_ERR_MAC,When set indicates that there was a single error detected within the MAC field" "0,1"
newline
rbitfld.long 0x0 3. "ECC_ERR_DA1,When set indicates that there was a single error detected within the High Data word" "0,1"
rbitfld.long 0x0 2. "ECC_ERR_DA0,When set indicates that there was a single error detected within the Low Data word" "0,1"
rbitfld.long 0x0 1. "ECC_ERR_DED,When set indicates that there was a double error detected for the block" "0,1"
newline
rbitfld.long 0x0 0. "ECC_ERR_SEC,hen set indicates that there was a single error detected for the block" "0,1"
line.long 0x4 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_WRT_TYPE,The ERR_WRT_TYPE register holds the current top of stack write error info. this is only valid when the wrt_err_valid is set"
bitfld.long 0x4 31. "WRT_ERR_VALID,When set indicates that there is valid write error information available  Writing a one to this register will pop the top of the stack" "0,1"
rbitfld.long 0x4 13. "WRT_ERR_BEN,When set indicates that there was a write error due to a non-contiguous byte enables" "0,1"
rbitfld.long 0x4 12. "WRT_ERR_ADR,When set indicates that there was a write error due to a non-aligned address" "0,1"
newline
hexmask.long.word 0x4 0.--11. 1. "WRT_ERR_ROUTEID,Indicates the Route ID for the Master that caused the write error"
tree.end
tree "FSS0_FSAS_0_OTFA_CFG (FSS0_FSAS_0_OTFA_CFG)"
base ad:0xFC20000
rgroup.long 0x0++0x3
line.long 0x0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_revid,"
hexmask.long 0x0 0.--31. 1. "REVID,REVID"
group.long 0x4++0x21B
line.long 0x0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_scfg,"
bitfld.long 0x0 0.--1. "IDLE_MODE,IDLE MODE" "0,1,2,3"
line.long 0x4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_isr,"
hexmask.long.byte 0x4 12.--15. 1. "MAC_ERR,MAC error"
hexmask.long.byte 0x4 8.--11. 1. "WRT_ERR,Write error"
hexmask.long.byte 0x4 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region"
newline
hexmask.long.byte 0x4 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule"
line.long 0x8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_is,"
hexmask.long.byte 0x8 12.--15. 1. "MAC_ERR,MAC error"
hexmask.long.byte 0x8 8.--11. 1. "WRT_ERR,Write error"
hexmask.long.byte 0x8 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region"
newline
hexmask.long.byte 0x8 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule"
line.long 0xC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_ies,"
hexmask.long.byte 0xC 12.--15. 1. "MAC_ERR,MAC error"
hexmask.long.byte 0xC 8.--11. 1. "WRT_ERR,Write error"
hexmask.long.byte 0xC 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region"
newline
hexmask.long.byte 0xC 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule"
line.long 0x10 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_iec,"
hexmask.long.byte 0x10 12.--15. 1. "MAC_ERR,MAC error"
hexmask.long.byte 0x10 8.--11. 1. "WRT_ERR,Write error"
hexmask.long.byte 0x10 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region"
newline
hexmask.long.byte 0x10 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule"
line.long 0x14 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_ccfg,"
bitfld.long 0x14 31. "MASTER_EN_RD,This register controls the enabling the functionality of this IP Disabled and Bypass mode active" "0,1"
bitfld.long 0x14 9. "ERROR_RESP_EN,This register controls the enabling the the ocp error response for mac errors" "0,1"
bitfld.long 0x14 8. "OTFA_WAIT,This register allows the ability to stop accepting any new transactions from getting accepted and allow the current transactions to complete" "0,1"
newline
bitfld.long 0x14 6. "CACHE_ENABLE,MAC cache enable" "0,1"
bitfld.long 0x14 5. "CACHE_EVICT_MODE,cache evict mode" "0,1"
bitfld.long 0x14 4. "KEY_SIZE,Key Size  0 128 Bit 1 256 Bit" "0,1"
newline
hexmask.long.byte 0x14 0.--3. 1. "RD_WRT_OPT,This register defines the static allocation of the AES cores to read transactions. The remainder will be allocated to write transactions"
line.long 0x18 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_cstatus,"
rbitfld.long 0x18 31. "BUSY,0 No transactions are active  crypto or none crypto 1 One or more transactions are active  crypto or none crypto" "0,1"
rbitfld.long 0x18 30. "CRYPTO_BUSY,0 No transactions are active  crypto or none crypto 1 One or more transactions are active  crypto or none crypto" "0,1"
hexmask.long.word 0x18 16.--29. 1. "RD_STALL_EVENT_CNT,rd stall event do to lack of eng"
newline
hexmask.long.word 0x18 0.--13. 1. "WRT_STALL_EVENT_CNT,wrt stall event do to lack of eng"
line.long 0x1C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg0,"
bitfld.long 0x1C 4. "WRT_PROTECT0,WRT protect" "0,1"
bitfld.long 0x1C 2.--3. "MAC_MODE0,MAC mode" "0,1,2,3"
bitfld.long 0x1C 0.--1. "AES_MODE0,AES mode" "0,1,2,3"
line.long 0x20 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst0,"
hexmask.long.tbyte 0x20 0.--19. 1. "M_START0,This defines the start of the mac buffer in 4KBytes steps"
line.long 0x24 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst0,"
hexmask.long.tbyte 0x24 0.--19. 1. "R_START0,This defines the start of the crypto region in 4KBytes steps"
line.long 0x28 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi0,"
hexmask.long.tbyte 0x28 0.--19. 1. "R_SIZE0,This defines the size of the crypto region in 4KBytes steps"
line.long 0x2C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye00,"
hexmask.long 0x2C 0.--31. 1. "R_KEY_E00,Key E"
line.long 0x30 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye01,"
hexmask.long 0x30 0.--31. 1. "R_KEY_E01,Key E"
line.long 0x34 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye02,"
hexmask.long 0x34 0.--31. 1. "R_KEY_E02,Key E"
line.long 0x38 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye03,"
hexmask.long 0x38 0.--31. 1. "R_KEY_E03,Key E"
line.long 0x3C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye04,"
hexmask.long 0x3C 0.--31. 1. "R_KEY_E04,Key E"
line.long 0x40 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye05,"
hexmask.long 0x40 0.--31. 1. "R_KEY_E05,Key E"
line.long 0x44 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye06,"
hexmask.long 0x44 0.--31. 1. "R_KEY_E06,Key E"
line.long 0x48 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye07,"
hexmask.long 0x48 0.--31. 1. "R_KEY_E07,Key E"
line.long 0x4C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep00,"
hexmask.long 0x4C 0.--31. 1. "R_KEY_EP00,Key EP"
line.long 0x50 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep01,"
hexmask.long 0x50 0.--31. 1. "R_KEY_EP01,Key EP"
line.long 0x54 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep02,"
hexmask.long 0x54 0.--31. 1. "R_KEY_EP02,Key EP"
line.long 0x58 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep03,"
hexmask.long 0x58 0.--31. 1. "R_KEY_EP03,Key EP"
line.long 0x5C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep04,"
hexmask.long 0x5C 0.--31. 1. "R_KEY_EP04,Key EP"
line.long 0x60 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep05,"
hexmask.long 0x60 0.--31. 1. "R_KEY_EP05,Key EP"
line.long 0x64 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep06,"
hexmask.long 0x64 0.--31. 1. "R_KEY_EP06,Key EP"
line.long 0x68 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep07,"
hexmask.long 0x68 0.--31. 1. "R_KEY_EP07,Key EP"
line.long 0x6C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya00,"
hexmask.long 0x6C 0.--31. 1. "R_KEY_A00,Key A"
line.long 0x70 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya01,"
hexmask.long 0x70 0.--31. 1. "R_KEY_A01,Key A"
line.long 0x74 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya02,"
hexmask.long 0x74 0.--31. 1. "R_KEY_A02,Key A"
line.long 0x78 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya03,"
hexmask.long 0x78 0.--31. 1. "R_KEY_A03,Key A"
line.long 0x7C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap00,"
hexmask.long 0x7C 0.--31. 1. "R_KEY_AP00,Key AP"
line.long 0x80 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap01,"
hexmask.long 0x80 0.--31. 1. "R_KEY_AP01,Key AP"
line.long 0x84 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap02,"
hexmask.long 0x84 0.--31. 1. "R_KEY_AP02,Key AP"
line.long 0x88 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap03,"
hexmask.long 0x88 0.--31. 1. "R_KEY_AP03,Key AP"
line.long 0x8C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv00,"
hexmask.long 0x8C 0.--31. 1. "R_IV00,IV"
line.long 0x90 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv01,"
hexmask.long 0x90 0.--31. 1. "R_IV01,IV"
line.long 0x94 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv02,"
hexmask.long 0x94 0.--31. 1. "R_IV02,IV"
line.long 0x98 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv03,"
hexmask.long 0x98 0.--31. 1. "R_IV03,IV"
line.long 0x9C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg1,"
bitfld.long 0x9C 4. "WRT_PROTECT1,WRT protect" "0,1"
bitfld.long 0x9C 2.--3. "MAC_MODE1,MAC mode" "0,1,2,3"
bitfld.long 0x9C 0.--1. "AES_MODE1,AES mode" "0,1,2,3"
line.long 0xA0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst1,"
hexmask.long.tbyte 0xA0 0.--19. 1. "M_START1,This defines the start of the mac buffer in 4KBytes steps"
line.long 0xA4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst1,"
hexmask.long.tbyte 0xA4 0.--19. 1. "R_START1,This defines the start of the crypto region in 4KBytes steps"
line.long 0xA8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi1,"
hexmask.long.tbyte 0xA8 0.--19. 1. "R_SIZE1,This defines the size of the crypto region in 4KBytes steps"
line.long 0xAC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye10,"
hexmask.long 0xAC 0.--31. 1. "R_KEY_E10,Key E"
line.long 0xB0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye11,"
hexmask.long 0xB0 0.--31. 1. "R_KEY_E11,Key E"
line.long 0xB4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye12,"
hexmask.long 0xB4 0.--31. 1. "R_KEY_E12,Key E"
line.long 0xB8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye13,"
hexmask.long 0xB8 0.--31. 1. "R_KEY_E13,Key E"
line.long 0xBC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye14,"
hexmask.long 0xBC 0.--31. 1. "R_KEY_E14,Key E"
line.long 0xC0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye15,"
hexmask.long 0xC0 0.--31. 1. "R_KEY_E15,Key E"
line.long 0xC4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye16,"
hexmask.long 0xC4 0.--31. 1. "R_KEY_E16,Key E"
line.long 0xC8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye17,"
hexmask.long 0xC8 0.--31. 1. "R_KEY_E17,Key E"
line.long 0xCC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep10,"
hexmask.long 0xCC 0.--31. 1. "R_KEY_EP10,Key EP"
line.long 0xD0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep11,"
hexmask.long 0xD0 0.--31. 1. "R_KEY_EP11,Key EP"
line.long 0xD4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep12,"
hexmask.long 0xD4 0.--31. 1. "R_KEY_EP12,Key EP"
line.long 0xD8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep13,"
hexmask.long 0xD8 0.--31. 1. "R_KEY_EP13,Key EP"
line.long 0xDC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep14,"
hexmask.long 0xDC 0.--31. 1. "R_KEY_EP14,Key EP"
line.long 0xE0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep15,"
hexmask.long 0xE0 0.--31. 1. "R_KEY_EP15,Key EP"
line.long 0xE4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep16,"
hexmask.long 0xE4 0.--31. 1. "R_KEY_EP16,Key EP"
line.long 0xE8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep17,"
hexmask.long 0xE8 0.--31. 1. "R_KEY_EP17,Key EP"
line.long 0xEC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya10,"
hexmask.long 0xEC 0.--31. 1. "R_KEY_A10,Key A"
line.long 0xF0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya11,"
hexmask.long 0xF0 0.--31. 1. "R_KEY_A11,Key A"
line.long 0xF4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya12,"
hexmask.long 0xF4 0.--31. 1. "R_KEY_A12,Key A"
line.long 0xF8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya13,"
hexmask.long 0xF8 0.--31. 1. "R_KEY_A13,Key A"
line.long 0xFC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap10,"
hexmask.long 0xFC 0.--31. 1. "R_KEY_AP10,Key AP"
line.long 0x100 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap11,"
hexmask.long 0x100 0.--31. 1. "R_KEY_AP11,Key AP"
line.long 0x104 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap12,"
hexmask.long 0x104 0.--31. 1. "R_KEY_AP12,Key AP"
line.long 0x108 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap13,"
hexmask.long 0x108 0.--31. 1. "R_KEY_AP13,Key AP"
line.long 0x10C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv10,"
hexmask.long 0x10C 0.--31. 1. "R_IV10,IV"
line.long 0x110 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv11,"
hexmask.long 0x110 0.--31. 1. "R_IV11,IV"
line.long 0x114 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv12,"
hexmask.long 0x114 0.--31. 1. "R_IV12,IV"
line.long 0x118 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv13,"
hexmask.long 0x118 0.--31. 1. "R_IV13,IV"
line.long 0x11C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg2,"
bitfld.long 0x11C 4. "WRT_PROTECT2,WRT protect" "0,1"
bitfld.long 0x11C 2.--3. "MAC_MODE2,MAC mode" "0,1,2,3"
bitfld.long 0x11C 0.--1. "AES_MODE2,AES mode" "0,1,2,3"
line.long 0x120 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst2,"
hexmask.long.tbyte 0x120 0.--19. 1. "M_START2,This defines the start of the mac buffer in 4KBytes steps"
line.long 0x124 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst2,"
hexmask.long.tbyte 0x124 0.--19. 1. "R_START2,This defines the start of the crypto region in 4KBytes steps"
line.long 0x128 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi2,"
hexmask.long.tbyte 0x128 0.--19. 1. "R_SIZE2,This defines the size of the crypto region in 4KBytes steps"
line.long 0x12C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye20,"
hexmask.long 0x12C 0.--31. 1. "R_KEY_E20,Key E"
line.long 0x130 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye21,"
hexmask.long 0x130 0.--31. 1. "R_KEY_E21,Key E"
line.long 0x134 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye22,"
hexmask.long 0x134 0.--31. 1. "R_KEY_E22,Key E"
line.long 0x138 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye23,"
hexmask.long 0x138 0.--31. 1. "R_KEY_E23,Key E"
line.long 0x13C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye24,"
hexmask.long 0x13C 0.--31. 1. "R_KEY_E24,Key E"
line.long 0x140 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye25,"
hexmask.long 0x140 0.--31. 1. "R_KEY_E25,Key E"
line.long 0x144 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye26,"
hexmask.long 0x144 0.--31. 1. "R_KEY_E26,Key E"
line.long 0x148 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye27,"
hexmask.long 0x148 0.--31. 1. "R_KEY_E27,Key E"
line.long 0x14C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep20,"
hexmask.long 0x14C 0.--31. 1. "R_KEY_EP20,Key EP"
line.long 0x150 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep21,"
hexmask.long 0x150 0.--31. 1. "R_KEY_EP21,Key EP"
line.long 0x154 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep22,"
hexmask.long 0x154 0.--31. 1. "R_KEY_EP22,Key EP"
line.long 0x158 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep23,"
hexmask.long 0x158 0.--31. 1. "R_KEY_EP23,Key EP"
line.long 0x15C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep24,"
hexmask.long 0x15C 0.--31. 1. "R_KEY_EP24,Key EP"
line.long 0x160 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep25,"
hexmask.long 0x160 0.--31. 1. "R_KEY_EP25,Key EP"
line.long 0x164 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep26,"
hexmask.long 0x164 0.--31. 1. "R_KEY_EP26,Key EP"
line.long 0x168 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep27,"
hexmask.long 0x168 0.--31. 1. "R_KEY_EP27,Key EP"
line.long 0x16C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya20,"
hexmask.long 0x16C 0.--31. 1. "R_KEY_A20,Key A"
line.long 0x170 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya21,"
hexmask.long 0x170 0.--31. 1. "R_KEY_A21,Key A"
line.long 0x174 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya22,"
hexmask.long 0x174 0.--31. 1. "R_KEY_A22,Key A"
line.long 0x178 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya23,"
hexmask.long 0x178 0.--31. 1. "R_KEY_A23,Key A"
line.long 0x17C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap20,"
hexmask.long 0x17C 0.--31. 1. "R_KEY_AP20,Key AP"
line.long 0x180 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap21,"
hexmask.long 0x180 0.--31. 1. "R_KEY_AP21,Key AP"
line.long 0x184 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap22,"
hexmask.long 0x184 0.--31. 1. "R_KEY_AP22,Key AP"
line.long 0x188 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap23,"
hexmask.long 0x188 0.--31. 1. "R_KEY_AP23,Key AP"
line.long 0x18C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv20,"
hexmask.long 0x18C 0.--31. 1. "R_IV20,IV"
line.long 0x190 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv21,"
hexmask.long 0x190 0.--31. 1. "R_IV21,IV"
line.long 0x194 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv22,"
hexmask.long 0x194 0.--31. 1. "R_IV22,IV"
line.long 0x198 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv23,"
hexmask.long 0x198 0.--31. 1. "R_IV23,IV"
line.long 0x19C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg3,"
bitfld.long 0x19C 4. "WRT_PROTECT3,WRT protect" "0,1"
bitfld.long 0x19C 2.--3. "MAC_MODE3,MAC mode" "0,1,2,3"
bitfld.long 0x19C 0.--1. "AES_MODE3,AES mode" "0,1,2,3"
line.long 0x1A0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst3,"
hexmask.long.tbyte 0x1A0 0.--19. 1. "M_START3,This defines the start of the mac buffer in 4KBytes steps"
line.long 0x1A4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst3,"
hexmask.long.tbyte 0x1A4 0.--19. 1. "R_START3,This defines the start of the crypto region in 4KBytes steps"
line.long 0x1A8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi3,"
hexmask.long.tbyte 0x1A8 0.--19. 1. "R_SIZE3,This defines the size of the crypto region in 4KBytes steps"
line.long 0x1AC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye30,"
hexmask.long 0x1AC 0.--31. 1. "R_KEY_E30,Key E"
line.long 0x1B0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye31,"
hexmask.long 0x1B0 0.--31. 1. "R_KEY_E31,Key E"
line.long 0x1B4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye32,"
hexmask.long 0x1B4 0.--31. 1. "R_KEY_E32,Key E"
line.long 0x1B8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye33,"
hexmask.long 0x1B8 0.--31. 1. "R_KEY_E33,Key E"
line.long 0x1BC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye34,"
hexmask.long 0x1BC 0.--31. 1. "R_KEY_E34,Key E"
line.long 0x1C0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye35,"
hexmask.long 0x1C0 0.--31. 1. "R_KEY_E35,Key E"
line.long 0x1C4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye36,"
hexmask.long 0x1C4 0.--31. 1. "R_KEY_E36,Key E"
line.long 0x1C8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye37,"
hexmask.long 0x1C8 0.--31. 1. "R_KEY_E37,Key E"
line.long 0x1CC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep30,"
hexmask.long 0x1CC 0.--31. 1. "R_KEY_EP30,Key EP"
line.long 0x1D0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep31,"
hexmask.long 0x1D0 0.--31. 1. "R_KEY_EP31,Key EP"
line.long 0x1D4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep32,"
hexmask.long 0x1D4 0.--31. 1. "R_KEY_EP32,Key EP"
line.long 0x1D8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep33,"
hexmask.long 0x1D8 0.--31. 1. "R_KEY_EP33,Key EP"
line.long 0x1DC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep34,"
hexmask.long 0x1DC 0.--31. 1. "R_KEY_EP34,Key EP"
line.long 0x1E0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep35,"
hexmask.long 0x1E0 0.--31. 1. "R_KEY_EP35,Key EP"
line.long 0x1E4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep36,"
hexmask.long 0x1E4 0.--31. 1. "R_KEY_EP36,Key EP"
line.long 0x1E8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep37,"
hexmask.long 0x1E8 0.--31. 1. "R_KEY_EP37,Key EP"
line.long 0x1EC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya30,"
hexmask.long 0x1EC 0.--31. 1. "R_KEY_A30,Key A"
line.long 0x1F0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya31,"
hexmask.long 0x1F0 0.--31. 1. "R_KEY_A31,Key A"
line.long 0x1F4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya32,"
hexmask.long 0x1F4 0.--31. 1. "R_KEY_A32,Key A"
line.long 0x1F8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya33,"
hexmask.long 0x1F8 0.--31. 1. "R_KEY_A33,Key A"
line.long 0x1FC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap30,"
hexmask.long 0x1FC 0.--31. 1. "R_KEY_AP30,Key AP"
line.long 0x200 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap31,"
hexmask.long 0x200 0.--31. 1. "R_KEY_AP31,Key AP"
line.long 0x204 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap32,"
hexmask.long 0x204 0.--31. 1. "R_KEY_AP32,Key AP"
line.long 0x208 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap33,"
hexmask.long 0x208 0.--31. 1. "R_KEY_AP33,Key AP"
line.long 0x20C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv30,"
hexmask.long 0x20C 0.--31. 1. "R_IV30,IV"
line.long 0x210 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv31,"
hexmask.long 0x210 0.--31. 1. "R_IV31,IV"
line.long 0x214 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv32,"
hexmask.long 0x214 0.--31. 1. "R_IV32,IV"
line.long 0x218 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv33,"
hexmask.long 0x218 0.--31. 1. "R_IV33,IV"
rgroup.long 0x220++0xF
line.long 0x0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_irqaddinfo0,"
hexmask.long 0x0 0.--31. 1. "IRQ_MADDR,Master Address which caused the event"
line.long 0x4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_irqaddinfo1,"
hexmask.long.byte 0x4 14.--17. 1. "IRQ_MLEN,Master LENGTH which caused the event"
bitfld.long 0x4 11.--13. "IRQ_MSEQ,Master SEQ which caused the event" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 8.--10. "IRQ_MCMD,Master CMD which caused the event" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 0.--7. 1. "IRQ_MID,Master TAG ID which caused the event"
line.long 0x8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_maccacheinfo,"
hexmask.long.word 0x8 0.--15. 1. "CACHE_MISS_EVENT_CNT,MAC Cache Miss event cnt"
line.long 0xC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rmwrmcnt,"
hexmask.long.word 0xC 16.--31. 1. "RM_EVENT_CNT,RM event cnt"
hexmask.long.word 0xC 0.--15. 1. "RMW_EVENT_CNT,RMW event cnt"
tree.end
tree.end
tree "FSS0_OSPI_0_OSPI0"
tree "FSS0_OSPI_0_OSPI0_CTRL (FSS0_OSPI_0_OSPI0_CTRL)"
base ad:0xFC40000
group.long 0x0++0x2B
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg,Octal-SPI Configuration Register"
rbitfld.long 0x0 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal  so there will be some inherent delay on the generation of this status signal." "0,1"
newline
bitfld.long 0x0 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode [i.e. Macronix MX25]. It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device.." "0,1"
newline
bitfld.long 0x0 29. "CRC_ENABLE_FLD,CRC enable bit This bit is to be set in case the target Flash Device supports CRC [Macronix MX25]. It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode." "0,1"
newline
bitfld.long 0x0 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to 1 between consecutive PHY pipeline reads transfers and de-asserted to 0 otherwise." "0,1"
newline
bitfld.long 0x0 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol." "0,1"
newline
bitfld.long 0x0 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines [bits [13:10]]. Value=1 Active slave is selected based on actual AHB address [the partition for each device is calculated with respect to.." "0: Active slave is selected based on Peripheral..,?"
newline
hexmask.long.byte 0x0 19.--22. 1. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor: SPI baud rate = [master reference clock] baud_rate_divisor"
newline
bitfld.long 0x0 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately: Value=0 : If XIP is enabled  then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the.." "0: If XIP is enabled,1: Operate the device in XIP mode immediately Use.."
newline
bitfld.long 0x0 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ: Value=0 : If XIP is enabled  then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled  then setting to ?1? will inform the controller that the.." "0: If XIP is enabled,1: If XIP is disabled"
newline
bitfld.long 0x0 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping: [Direct Access Mode Only] When set to 1  the incoming AHB address will be adapted and sent to the FLASH device as [address + N]  where N is the value stored in the remap address register." "0,1"
newline
bitfld.long 0x0 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable" "0,1"
newline
bitfld.long 0x0 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary." "0,1"
newline
hexmask.long.byte 0x0 10.--13. 1. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0  ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 [no peripheral selected] else ss[3:0] directly drives n_ss_out[3:0]"
newline
bitfld.long 0x0 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode: 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode [n_ss_out = ss]" "0: only 1 of 4 selects n_ss_out[3:0] is active,1: allow external 4-to-16 decode [n_ss_out = ss]"
newline
bitfld.long 0x0 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable: 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode  any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid.." "0: Use Direct Access Controller/Indirect Access..,1: legacy Mode is enabled"
newline
bitfld.long 0x0 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller: 0 : disable the Direct Access Controller once current transfer of the data word [FF_W] is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access.." "0: disable the Direct Access Controller once..,1: enable the Direct Access Controller When the.."
newline
bitfld.long 0x0 6. "RESET_CFG_FLD,RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output]" "0: RESET feature on DQ3 pin of the device,1: RESET feature on dedicated pin of the device.."
newline
bitfld.long 0x0 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1"
newline
bitfld.long 0x0 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1"
newline
bitfld.long 0x0 3. "PHY_MODE_ENABLE_FLD,PHY mode enable: When enabled  the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module." "0,1"
newline
bitfld.long 0x0 2. "SEL_CLK_PHASE_FLD,Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word" "0: the SPI clock is active outside the word,1: the SPI clock is inactive outside the word"
newline
bitfld.long 0x0 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word: 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high" "0: the SPI clock is quiescent low,1: the SPI clock is quiescent high"
newline
bitfld.long 0x0 0. "ENB_SPI_FLD,Octal-SPI Enable: 0 : disable the Octal-SPI  once current transfer of the data word [FF_W] is complete. 1 : enable the Octal-SPI  when spi_enable = 0  all output enables are inactive and all pins are set to input mode." "0: disable the Octal-SPI,1: enable the Octal-SPI"
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg,Device Read Instruction Configuration Register"
hexmask.long.byte 0x4 24.--28. 1. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction."
newline
bitfld.long 0x4 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1"
newline
bitfld.long 0x4 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers  DQ0 and DQ1 are used as both.." "0: SIO mode data is shifted to the device on DQ0..,1: Used for Dual Input/Output instructions,2: Used for Quad Input/Output instructions,3: Used for Quad Input/Output instructions"
newline
bitfld.long 0x4 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0  DQ1  DQ2.." "0: Addresses can be shifted to the device on DQ0 only,1: Addresses can be shifted to the device on DQ0..,2: Addresses can be shifted to the device on DQ0,3: Addresses can be shifted to the device on DQ[7:0]"
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bitfld.long 0x4 10. "DDR_EN_FLD,DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands" "0,1"
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bitfld.long 0x4 8.--9. "INSTR_TYPE_FLD,Instruction Type: 0 : Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1 : Use DIO-SPI mode [Instructions  Address and Data always sent on DQ0 and DQ1] 2 : Use QIO-SPI mode [Instructions  Address and Data.." "0: Use Standard SPI mode [instruction always..,1: Use DIO-SPI mode [Instructions,2: Use QIO-SPI mode [Instructions,3: Use Octal-IO-SPI mode [Instructions"
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hexmask.long.byte 0x4 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode"
line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_wr_config_reg,Device Write Instruction Configuration Register"
hexmask.long.byte 0x8 24.--28. 1. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction."
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bitfld.long 0x8 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers  DQ0 and DQ1 are used as both.." "0: SIO mode data is shifted to the device on DQ0..,1: Used for Dual Input/Output instructions,2: Used for Quad Input/Output instructions,3: Used for Quad Input/Output instructions"
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bitfld.long 0x8 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0  DQ1  DQ2.." "0: Addresses can be shifted to the device on DQ0 only,1: Addresses can be shifted to the device on DQ0..,2: Addresses can be shifted to the device on DQ0,3: Addresses can be shifted to the device on DQ[7:0]"
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bitfld.long 0x8 8. "WEL_DIS_FLD,WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC" "0,1"
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hexmask.long.byte 0x8 0.--7. 1. "WR_OPCODE_FLD,Write Opcode"
line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_delay_reg,Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles.."
hexmask.long.byte 0xC 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never.."
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hexmask.long.byte 0xC 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and.."
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hexmask.long.byte 0xC 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select [n_ss_out]. By default  the chip select will be deasserted on the cycle following the.."
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hexmask.long.byte 0xC 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer."
line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rd_data_capture_reg,Read Data Capture Register"
hexmask.long.byte 0x10 16.--19. 1. "DDR_READ_DELAY_FLD,DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored."
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bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit: If enabled  signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.." "0,1"
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bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection: Choose edge on which data outputs from flash memory will be sampled" "0,1"
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hexmask.long.byte 0x10 1.--4. 1. "DELAY_FLD,Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles"
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bitfld.long 0x10 0. "BYPASS_FLD,Bypass the adapted loopback clock circuit" "0,1"
line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_size_config_reg,Device Size Configuration Register"
bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?"
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bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?"
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bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?"
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bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?"
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hexmask.long.byte 0x14 16.--20. 1. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number."
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hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries."
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hexmask.long.byte 0x14 0.--3. 1. "NUM_ADDR_BYTES_FLD,Number of address bytes. A value of 0 indicates 1 byte."
line.long 0x18 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_partition_cfg_reg,SRAM Partition Configuration Register"
hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM  in units of SRAM locations. By default  half of the SRAM is reserved for indirect read operation  and half for indirect write. The size of this register.."
line.long 0x1C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_ind_AHB_addr_trigger_reg,Indirect AHB Address Trigger Register"
hexmask.long 0x1C 0.--31. 1. "ADDR_FLD,This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15  then the AHB request will be completed by fetching.."
line.long 0x20 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dma_periph_config_reg,DMA Peripheral Configuration Register"
hexmask.long.byte 0x20 8.--11. 1. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual.."
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hexmask.long.byte 0x20 0.--3. 1. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The.."
line.long 0x24 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_remap_addr_reg,Remap Address Register"
hexmask.long 0x24 0.--31. 1. "VALUE_FLD,This register is used to remap an incoming AHB address to a different address used by the FLASH device."
line.long 0x28 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_mode_bit_config_reg,Mode Bit Configuration Register"
hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data [lower] The first CRC byte returned after RX data chunk."
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hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data [upper] The second CRC byte returned after RX data chunk."
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bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit When enabled  the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly." "0,1"
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bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled."
rgroup.long 0x2C++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_fill_reg,SRAM Fill Register"
hexmask.long.word 0x0 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level [Indirect Write Partition]: Identifies the current fill level of the SRAM Indirect Write partition"
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hexmask.long.word 0x0 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level [Indirect Read Partition]: Identifies the current fill level of the SRAM Indirect Read partition"
group.long 0x30++0x17
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_tx_thresh_reg,TX Threshold Register"
hexmask.long.byte 0x0 0.--4. 1. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated"
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rx_thresh_reg,RX Threshold Register"
hexmask.long.byte 0x4 0.--4. 1. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated"
line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_write_completion_ctrl_reg,Write Completion Control Register: This register defines how the controller will poll the device following a write transfer"
hexmask.long.byte 0x8 24.--31. 1. "POLL_REP_DELAY_FLD,Defines additional delay for maintain Chip Select de-asserted during auto-polling phase"
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hexmask.long.byte 0x8 16.--23. 1. "POLL_COUNT_FLD,Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register."
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bitfld.long 0x8 15. "ENABLE_POLLING_EXP_FLD,Set to '1' for enabling auto-polling expiration." "0,1"
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bitfld.long 0x8 14. "DISABLE_POLLING_FLD,This switches off the automatic polling function" "0,1"
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bitfld.long 0x8 13. "POLLING_POLARITY_FLD,Defines the polling polarity. If '1'  then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0'  then the write transfer to the device will be complete if the polled bit is equal to '0'." "0,1"
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bitfld.long 0x8 8.--10. "POLLING_BIT_INDEX_FLD,Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 0.--7. 1. "OPCODE_FLD,Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default  this will poll the standard device STATUS.."
line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_no_of_polls_bef_exp_reg,Polling Expiration Register"
hexmask.long 0xC 0.--31. 1. "NO_OF_POLLS_BEF_EXP_FLD,Number of polls cycles before expiration"
line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_status_reg,Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of.."
bitfld.long 0x10 19. "ECC_FAIL_FLD,ECC failure This interrupt informs the system that Flash Device reported ECC error." "0,1"
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bitfld.long 0x10 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk." "0,1"
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bitfld.long 0x10 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid New RX CRC data was captured from Flash Device" "0,1"
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bitfld.long 0x10 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller." "0,1"
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bitfld.long 0x10 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request." "0,1"
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bitfld.long 0x10 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1"
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bitfld.long 0x10 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1"
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bitfld.long 0x10 11. "RX_FIFO_FULL_FLD,Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "0: FIFO is not full,1: FIFO is full"
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bitfld.long 0x10 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries  1 : FIFO has >= THRESHOLD entries" "0: FIFO has less than RX THRESHOLD entries,1: FIFO has >= THRESHOLD entries"
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bitfld.long 0x10 9. "TX_FIFO_FULL_FLD,Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full  1 : FIFO is full" "0: FIFO is not full,1: FIFO is full"
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bitfld.long 0x10 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries  1 : FIFO has less than THRESHOLD entries" "0: FIFO has >= THRESHOLD entries,1: FIFO has less than THRESHOLD entries"
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bitfld.long 0x10 7. "RECV_OVERFLOW_FLD,Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX.." "0: no overflow has been detected,1: an overflow has occurred"
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bitfld.long 0x10 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1"
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bitfld.long 0x10 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1"
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bitfld.long 0x10 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected." "0,1"
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bitfld.long 0x10 3. "INDIRECT_READ_REJECT_FLD,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1"
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bitfld.long 0x10 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1"
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bitfld.long 0x10 1. "UNDERFLOW_DET_FLD,Underflow Detected: 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with.." "0: no underflow has been detected,1: underflow is detected and an attempt to transfer.."
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bitfld.long 0x10 0. "MODE_M_FAIL_FLD,Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode [multi-master contention]. These conditions will clear the spi_enable bit and disable the SPI." "0: no mode fault has been detected,1: a mode fault has occurred"
line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_mask_reg,Interrupt Mask: 0 : the interrupt for the corresponding interrupt status register bit is disabled."
bitfld.long 0x14 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1"
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bitfld.long 0x14 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1"
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bitfld.long 0x14 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1"
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bitfld.long 0x14 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1"
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bitfld.long 0x14 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1"
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bitfld.long 0x14 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1"
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bitfld.long 0x14 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1"
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bitfld.long 0x14 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1"
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bitfld.long 0x14 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1"
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bitfld.long 0x14 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1"
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bitfld.long 0x14 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1"
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bitfld.long 0x14 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1"
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bitfld.long 0x14 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1"
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bitfld.long 0x14 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1"
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bitfld.long 0x14 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1"
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bitfld.long 0x14 3. "INDIRECT_READ_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1"
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bitfld.long 0x14 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1"
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bitfld.long 0x14 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1"
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bitfld.long 0x14 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1"
group.long 0x50++0xB
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_lower_wr_prot_reg,Lower Write Protection Register"
hexmask.long 0x0 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register."
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_upper_wr_prot_reg,Upper Write Protection Register"
hexmask.long 0x4 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register."
line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_wr_prot_ctrl_reg,Write Protection Control Register"
bitfld.long 0x8 1. "ENB_FLD,Write Protection Enable Bit: When set to 1  any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source.." "0,1"
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bitfld.long 0x8 0. "INV_FLD,Write Protection Inversion Bit: When set to 1  the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0  the protection region.." "0,1"
group.long 0x60++0x23
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_ctrl_reg,Indirect Read Transfer Control Register"
rbitfld.long 0x0 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed." "0,1,2,3"
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bitfld.long 0x0 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1"
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rbitfld.long 0x0 4. "RD_QUEUED_FLD,Two indirect read operations have been queued" "0,1"
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bitfld.long 0x0 3. "SRAM_FULL_FLD,SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.; indirect operation [status]" "0,1"
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rbitfld.long 0x0 2. "RD_STATUS_FLD,Indirect Read Status: Indirect read operation in progress [status]" "0,1"
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bitfld.long 0x0 1. "CANCEL_FLD,Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations." "0,1"
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bitfld.long 0x0 0. "START_FLD,Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation." "0,1"
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_watermark_reg,Indirect Read Transfer Watermark Register"
hexmask.long 0x4 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark  an interrupt is also generated. This field can be disabled by writing a value of all.."
line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_start_reg,Indirect Read Transfer Start Address Register"
hexmask.long 0x8 0.--31. 1. "ADDR_FLD,This is the start address from which the indirect access will commence its READ operation."
line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_num_bytes_reg,Indirect Read Transfer Number Bytes Register"
hexmask.long 0xC 0.--31. 1. "VALUE_FLD,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM."
line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_ctrl_reg,Indirect Write Transfer Control Register"
rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed." "0,1,2,3"
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bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1"
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rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1"
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rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status: Indirect write operation in progress [status]" "0,1"
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bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations." "0,1"
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bitfld.long 0x10 0. "START_FLD,Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation." "0,1"
line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_watermark_reg,Indirect Write Transfer Watermark Register"
hexmask.long 0x14 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark  an interrupt is also generated. This field can be disabled by writing a value.."
line.long 0x18 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_start_reg,Indirect Write Transfer Start Address Register"
hexmask.long 0x18 0.--31. 1. "ADDR_FLD,Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation."
line.long 0x1C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_num_bytes_reg,Indirect Write Transfer Number Bytes Register"
hexmask.long 0x1C 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM."
line.long 0x20 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_trigger_addr_range_reg,Indirect Trigger Address Range Register"
hexmask.long.byte 0x20 0.--3. 1. "IND_RANGE_WIDTH_FLD,This is the address offset of Indirect Trigger Address Register."
group.long 0x8C++0xB
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_command_ctrl_mem_reg,Flash Command Control Memory Register"
hexmask.long.word 0x0 20.--28. 1. "MEM_BANK_ADDR_FLD,The address of the Memory Bank which data will be read from."
newline
bitfld.long 0x0 16.--18. "NB_OF_STIG_READ_BYTES_FLD,It defines the number of read bytes for the extended STIG." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Last requested data from the STIG Memory Bank."
newline
rbitfld.long 0x0 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request." "0,1"
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_ctrl_reg,Flash Command Control Register"
hexmask.long.byte 0x4 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode: The command opcode field should be setup before triggering the command. For example  0x20 maps to SubSector Erase. Writing to the execute field [bit 0] of this register launches the command. NOTE : Using this approach to.."
newline
bitfld.long 0x4 23. "ENB_READ_DATA_FLD,Read Data Enable: Set to 1 if the command specified in the command opcode field [bits 31:24] requires read data bytes to be received from the device." "?,?"
newline
bitfld.long 0x4 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 19. "ENB_COMD_ADDR_FLD,Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field." "?,?"
newline
bitfld.long 0x4 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1"
newline
bitfld.long 0x4 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes: Set to the number of address bytes required [the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS]. This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1.." "0: 1 address byte,1: 2 address bytes,2: 3 address bytes,3: 4 address bytes"
newline
bitfld.long 0x4 15. "ENB_WRITE_DATA_FLD,Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device." "0,1"
newline
bitfld.long 0x4 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte  7 for 8 bytes." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 7.--11. 1. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register."
newline
bitfld.long 0x4 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit." "0,1"
newline
rbitfld.long 0x4 1. "CMD_EXEC_STATUS_FLD,Command execution in progress." "0,1"
newline
bitfld.long 0x4 0. "CMD_EXEC_FLD,Execute the command." "0,1"
line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_addr_reg,Flash Command Address Register"
hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Command Address: This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the address used by the command specified in the opcode field [bits 31:24] of the Flash Command Control.."
rgroup.long 0xA0++0x7
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_lower_reg,Flash Command Read Data Register (Lower)"
hexmask.long 0x0 0.--31. 1. "DATA_FLD,This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low."
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_upper_reg,Flash Command Read Data Register (Upper)"
hexmask.long 0x4 0.--31. 1. "DATA_FLD,This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low."
group.long 0xA8++0x13
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_lower_reg,Flash Command Write Data Register (Lower)"
hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for.."
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_upper_reg,Flash Command Write Data Register (Upper)"
hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for.."
line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_polling_flash_status_reg,Polling Flash Status Register"
hexmask.long.byte 0x8 16.--19. 1. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling"
newline
rbitfld.long 0x8 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid: This should be set when value in bits from 7 to 0 is valid." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device"
line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_configuration_reg,PHY Configuration Register"
bitfld.long 0xC 31. "PHY_CONFIG_RESYNC_FLD,This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields." "0,1"
newline
bitfld.long 0xC 30. "PHY_CONFIG_RESET_FLD,DLL Reset bit: This bit is used for reset of Delay Lines by software." "0,1"
newline
bitfld.long 0xC 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass: This field determines id RX DLL is bypassed." "0,1"
newline
hexmask.long.byte 0xC 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk."
newline
hexmask.long.byte 0xC 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk."
line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_master_control_reg,PHY DLL Master Control Register"
bitfld.long 0x10 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay." "0,1"
newline
bitfld.long 0x10 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs." "0,1"
newline
bitfld.long 0x10 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the DLL."
rgroup.long 0xBC++0x7
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_lower_reg,DLL Observable Register Lower"
hexmask.long.byte 0x0 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative dll_lock_inc register."
newline
hexmask.long.byte 0x0 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative dll_lock_dec register."
newline
bitfld.long 0x0 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done." "0,1"
newline
hexmask.long.byte 0x0 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,Reports the DLL encoder value from the master DLL to the slave DLLs."
newline
hexmask.long.byte 0x0 3.--7. 1. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,Reports the number of increments or decrements required for the master DLL to complete the locking process."
newline
bitfld.long 0x0 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,Defines the mode in which the DLL has achieved the lock." "0,1,2,3"
newline
bitfld.long 0x0 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,Indicates status of DLL." "0,1"
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_upper_reg,DLL Observable Register Upper"
hexmask.long.byte 0x4 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,Holds the encoded value for the TX delay line for this slice."
newline
hexmask.long.byte 0x4 0.--6. 1. "DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD,Holds the encoded value for the RX delay line for this slice."
group.long 0xE0++0x7
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_lower_reg,Opcode Extension Register (Lower)"
hexmask.long.byte 0x0 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcode"
newline
hexmask.long.byte 0x0 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode"
newline
hexmask.long.byte 0x0 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode"
newline
hexmask.long.byte 0x0 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode"
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_upper_reg,Opcode Extension Register (Upper)"
hexmask.long.byte 0x4 24.--31. 1. "WEL_OPCODE_FLD,First byte of any WEL Opcode"
newline
hexmask.long.byte 0x4 16.--23. 1. "EXT_WEL_OPCODE_FLD,Supplement byte of any WEL Opcode"
rgroup.long 0xFC++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_module_id_reg,Module ID Register"
hexmask.long.byte 0x0 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register"
newline
hexmask.long.word 0x0 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number"
newline
bitfld.long 0x0 0.--1. "CONF_FLD,Configuration ID number: 0 : OCTAL + PHY Configuration 1 : OCTAL Configuration 2 : QUAD + PHY Configuration 3 : QUAD Configuration" "0: OCTAL + PHY Configuration,1: OCTAL Configuration,2: QUAD + PHY Configuration,3: QUAD Configuration"
tree.end
tree "FSS0_OSPI_0_OSPI0_ECC_AGGR (FSS0_OSPI_0_OSPI0_ECC_AGGR)"
base ad:0x716000
rgroup.long 0x0++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "FSS0_OSPI_0_OSPI0_SS_CFG (FSS0_OSPI_0_OSPI0_SS_CFG)"
base ad:0xFC44000
rgroup.long 0x0++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
newline
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_CTRL,The Control Register contains general control bits for the ospi"
bitfld.long 0x0 3. "PIPELINE_MODE_FLUSH,1 - Flush Cadence Flash Controller FIFO by forcin gAHB SEL low. 0 - AHB Sel to Cadence Controller is 1" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_STAT,The Status register provide general status bits for the ospi"
bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress  1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done"
wgroup.long 0x20++0x3
line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_EOI,End of Interrupt Register"
hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targetted interrupt. (E.g. Ext TS is bit 0). Upon write  level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt"
tree.end
tree.end
tree.end
tree "GPIO"
base ad:0x0
tree "GPIO0 (GPIO0)"
base ad:0x600000
rgroup.long 0x0++0x7
line.long 0x0 "MEM_pid,GPIO Periperal ID Register"
bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code"
bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code"
line.long 0x4 "MEM_PCR,Peripheral Control Register"
bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x4 0. "FREE,For GPIO  the FREE bit is fixed at 1  which means GPIO runs free in emulation suspend" "0,1"
group.long 0x8++0x3
line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register"
hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable 0 = disable  1 = enable"
group.long 0x10++0xF
line.long 0x0 "MEM_DIR01,Direction Register"
hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits  0 = output  1 = input"
hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits  0 = output  1 = input"
line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register"
hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x20++0x3
line.long 0x0 "MEM_IN_DATA01,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits"
hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits"
group.long 0x24++0x23
line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits"
line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits"
line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR23,Direction Register"
hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits  0 = output  1 = input"
hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x48++0x3
line.long 0x0 "MEM_IN_DATA23,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits"
hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits"
group.long 0x4C++0x23
line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits"
line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits"
line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR45,Direction Register"
hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits  0 = output  1 = input"
hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x70++0x3
line.long 0x0 "MEM_IN_DATA45,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits"
hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits"
group.long 0x74++0x23
line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits"
line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits"
line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR67,Direction Register"
hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits  0 = output  1 = input"
hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x98++0x3
line.long 0x0 "MEM_IN_DATA67,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits"
hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits"
group.long 0x9C++0x23
line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits"
line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits"
line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR8,Direction Register"
hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register"
hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0xC0++0x3
line.long 0x0 "MEM_IN_DATA8,Bank Status Register"
hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits"
group.long 0xC4++0x13
line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits"
line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits"
line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register"
hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
tree.end
tree "GPIO1 (GPIO1)"
base ad:0x601000
rgroup.long 0x0++0x7
line.long 0x0 "MEM_pid,GPIO Periperal ID Register"
bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code"
bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code"
line.long 0x4 "MEM_PCR,Peripheral Control Register"
bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x4 0. "FREE,For GPIO  the FREE bit is fixed at 1  which means GPIO runs free in emulation suspend" "0,1"
group.long 0x8++0x3
line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register"
hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable 0 = disable  1 = enable"
group.long 0x10++0xF
line.long 0x0 "MEM_DIR01,Direction Register"
hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits  0 = output  1 = input"
hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits  0 = output  1 = input"
line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register"
hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x20++0x3
line.long 0x0 "MEM_IN_DATA01,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits"
hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits"
group.long 0x24++0x23
line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits"
line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits"
line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR23,Direction Register"
hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits  0 = output  1 = input"
hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x48++0x3
line.long 0x0 "MEM_IN_DATA23,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits"
hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits"
group.long 0x4C++0x23
line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits"
line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits"
line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR45,Direction Register"
hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits  0 = output  1 = input"
hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x70++0x3
line.long 0x0 "MEM_IN_DATA45,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits"
hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits"
group.long 0x74++0x23
line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits"
line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits"
line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR67,Direction Register"
hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits  0 = output  1 = input"
hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x98++0x3
line.long 0x0 "MEM_IN_DATA67,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits"
hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits"
group.long 0x9C++0x23
line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits"
line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits"
line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR8,Direction Register"
hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register"
hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0xC0++0x3
line.long 0x0 "MEM_IN_DATA8,Bank Status Register"
hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits"
group.long 0xC4++0x13
line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits"
line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits"
line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register"
hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
tree.end
tree.end
tree "GPMC0_CFG (GPMC0_CFG)"
base ad:0x3B000000
group.long 0x0++0x3
line.long 0x0 "CFG_GPMC_REVISION,This register contains the IP revision code"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reads returns 0"
hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0  0x21 for 2.1"
group.long 0x10++0xF
line.long 0x0 "CFG_GPMC_SYSCONFIG,This register controls the various parameters of the OCP interface"
hexmask.long 0x0 5.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
bitfld.long 0x0 3.--4. "IDLEMODE," "0,1,2,3"
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bitfld.long 0x0 2. "RESERVED,Write 0 for future compatibility Reads returns 0" "0,1"
bitfld.long 0x0 1. "RESERVED,This bit must be kept 0 for normal functioning of the IP. Do not set this bit to 1" "0,1"
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bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
line.long 0x4 "CFG_GPMC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reads returns 0"
hexmask.long.byte 0x4 1.--7. 1. "RESERVED,Reads returns 0 [reserved for OCP-socket status information]"
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rbitfld.long 0x4 0. "RESETDONE,Internal reset monitoring" "0,1"
line.long 0x8 "CFG_GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt."
hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
bitfld.long 0x8 11. "WAIT3EDGEDETECTIONSTATUS,Status of the Wait3 Edge Detection interrupt" "0,1"
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bitfld.long 0x8 10. "WAIT2EDGEDETECTIONSTATUS,Status of the Wait2 Edge Detection interrupt" "0,1"
bitfld.long 0x8 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interrupt" "0,1"
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bitfld.long 0x8 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interrupt" "0,1"
hexmask.long.byte 0x8 2.--7. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
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bitfld.long 0x8 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interrupt" "0,1"
bitfld.long 0x8 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interrupt" "0,1"
line.long 0xC "CFG_GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis."
hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
bitfld.long 0xC 11. "WAIT3EDGEDETECTIONENABLE,Enables the Wait3 Edge Detection interrupt" "0,1"
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bitfld.long 0xC 10. "WAIT2EDGEDETECTIONENABLE,Enables the Wait2 Edge Detection interrupt" "0,1"
bitfld.long 0xC 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt" "0,1"
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bitfld.long 0xC 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt" "0,1"
hexmask.long.byte 0xC 2.--7. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
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bitfld.long 0xC 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in pre-fetch or write posting mode" "0,1"
bitfld.long 0xC 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt" "0,1"
group.long 0x40++0xB
line.long 0x0 "CFG_GPMC_TIMEOUT_CONTROL,The GPMC_TIMEOUT_CONTROL register allows the user to set the start value of the timeout counter"
hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
hexmask.long.word 0x0 4.--12. 1. "TIMEOUTSTARTVALUE,Start value of the time-out counter [0x000 corresponds to 0 GPMC.FCLK cycle  0x001 corresponds to 1 GmpcClk cycle  &  0x1FF corresponds to 511 GPMC.FCLK cyles.]"
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bitfld.long 0x0 1.--3. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature" "0,1"
line.long 0x4 "CFG_GPMC_ERR_ADDRESS,The GPMC_ERR_ADDRESS register stores the address of the illegal access when an error occurs"
bitfld.long 0x4 31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1"
hexmask.long 0x4 0.--30. 1. "ILLEGALADD,Address of illegal access : A30[0 for memory region  1 for GPMC register region] and A29-A0[1 GBytes maximum]"
line.long 0x8 "CFG_GPMC_ERR_TYPE,The GPMC_ERR_TYPE register stores the type of error when an error occurs"
hexmask.long.tbyte 0x8 11.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
rbitfld.long 0x8 8.--10. "ILLEGALMCMD,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
rbitfld.long 0x8 4. "ERRORNOTSUPPADD,Not supported Address error" "0,1"
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rbitfld.long 0x8 3. "ERRORNOTSUPPMCMD,Not supported Command error" "0,1"
rbitfld.long 0x8 2. "ERRORTIMEOUT,Time-out error" "0,1"
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bitfld.long 0x8 1. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1"
bitfld.long 0x8 0. "ERRORVALID,Error validity status - Must be explicitely cleared with a write 1 transaction" "0,1"
group.long 0x50++0x7
line.long 0x0 "CFG_GPMC_CONFIG,The configuration register allows global configuration of the GPMC"
hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
bitfld.long 0x0 11. "WAIT3PINPOLARITY,Selects the polarity of input pin WAIT3" "0,1"
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bitfld.long 0x0 10. "WAIT2PINPOLARITY,Selects the polarity of input pin WAIT2" "0,1"
bitfld.long 0x0 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1" "0,1"
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bitfld.long 0x0 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0" "0,1"
bitfld.long 0x0 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4. "WRITEPROTECT,Controls the WP output pin level" "0,1"
bitfld.long 0x0 2.--3. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3"
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bitfld.long 0x0 1. "LIMITEDADDRESS,Limited Address device support" "0,1"
bitfld.long 0x0 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "0,1"
line.long 0x4 "CFG_GPMC_STATUS,The status register provides global status bits of the GPMC"
hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
rbitfld.long 0x4 11. "WAIT3STATUS,Is a copy of input pin WAIT3. [Reset value is WAIT3 input pin sampled at IC reset]" "0,1"
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rbitfld.long 0x4 10. "WAIT2STATUS,Is a copy of input pin WAIT2. [Reset value is WAIT2 input pin sampled at IC reset]" "0,1"
rbitfld.long 0x4 9. "WAIT1STATUS,Is a copy of input pin WAIT1. [Reset value is WAIT1 input pin sampled at IC reset]" "0,1"
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rbitfld.long 0x4 8. "WAIT0STATUS,Is a copy of input pin WAIT0. [Reset value is WAIT0 input pin sampled at IC reset]" "0,1"
hexmask.long.byte 0x4 1.--7. 1. "RESERVED,Write 0's for future compatibility Reads returns 0"
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rbitfld.long 0x4 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer" "0,1"
group.long 0x1E0++0x7
line.long 0x0 "CFG_GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1"
bitfld.long 0x0 31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1"
bitfld.long 0x0 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC.FCLK cycles to be substracted from RdCycleTime  WrCycleTime  AccessTime  CSRdOffTime  CSWrOffTime  ADVRdOffTime  ADVWrOffTime  OEOffTime  WEOffTime [0x0 corresponds to 0 GPMC.FCLK cycle  0x1 corresponds to 1.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization" "0,1"
bitfld.long 0x0 24.--26. "ENGINECSSELECTOR,Selects the CS where Prefetch Postwrite engine is active [0x0 corresponds toCS0  0x1 corresponds to CS1  &  0x7 corresponds to CS7]" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration" "0,1"
bitfld.long 0x0 20.--22. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 16.--19. 1. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a direct memory access and a PFPW engine access  the direct memory access is always serviced. If the PFPWEnRoundRobin is enabled  0x0 means : the next access is granted to the PFPW engine  0x1 means :.."
bitfld.long 0x0 15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1"
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hexmask.long.byte 0x0 8.--14. 1. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request [0x00 corresponds to 0 byte  0x01 corresponds to 1 byte  &  0x40 corresponds to 64 bytes]"
bitfld.long 0x0 7. "ENABLEENGINE,Enables the Prefetch Postwite engine" "0,1"
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bitfld.long 0x0 6. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1"
bitfld.long 0x0 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode" "0,1,2,3"
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bitfld.long 0x0 3. "SYNCHROMODE,Selects when the engine starts the access to CS" "0,1"
bitfld.long 0x0 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization" "0,1"
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bitfld.long 0x0 1. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1"
bitfld.long 0x0 0. "ACCESSMODE,Selects pre-fetch read or write posting accesses" "0,1"
line.long 0x4 "CFG_GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2"
hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
hexmask.long.word 0x4 0.--13. 1. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected CS [0x0000 corresponds to 0 byte  0x0001 corresponds to 1 byte  &  0x2000 corresponds to 8 Kbytes]"
group.long 0x1EC++0x17
line.long 0x0 "CFG_GPMC_PREFETCH_CONTROL,Prefetch engine control"
hexmask.long 0x0 1.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
bitfld.long 0x0 0. "STARTENGINE,Resets the FIFO pointer and starts the engine" "0,1"
line.long 0x4 "CFG_GPMC_PREFETCH_STATUS,Prefetch engine status"
bitfld.long 0x4 31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1"
hexmask.long.byte 0x4 24.--30. 1. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written [0x00 corresponds to 0 byte available to be read or 0 free empty place to be written  &  0x40 corresponds to 64 bytes available to be read or 64 empty.."
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hexmask.long.byte 0x4 17.--23. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
rbitfld.long 0x4 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value" "0,1"
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bitfld.long 0x4 14.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3"
hexmask.long.word 0x4 0.--13. 1. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value [0x0000 corresponds to 0 byte remaining to be read or to be written  0x0001 corresponds to 1 byte remaining to be read or to be written .."
line.long 0x8 "CFG_GPMC_ECC_CONFIG,ECC configuration"
hexmask.long.word 0x8 17.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
bitfld.long 0x8 16. "ECCALGORITHM,ECC algorithm used 0x0: Hamming code 0x1: BCH code" "0: Hamming code,1: BCH code"
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bitfld.long 0x8 14.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3"
bitfld.long 0x8 12.--13. "ECCBCHTSEL,Error correction capability used for BCH 0x0: up to 4 bits error correction [t = 4] 0x1: up to 8 bits error correction [t=8] 0x2: up to 16 bits error correction [t=16] 0x3: reserved" "0: up to 4 bits error correction [t = 4],1: up to 8 bits error correction [t=8],2: up to 16 bits error correction [t=16],3: reserved"
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hexmask.long.byte 0x8 8.--11. 1. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm. See the BCH syndrome/parity calculator module functional specification for more details"
bitfld.long 0x8 7. "ECC16B,Selects an ECC calculated on 16 columns" "0,1"
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bitfld.long 0x8 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH algorithm 0x0: 1 sector [512kB page] 0x1: 2 sectors ... 0x3: 4 sectors [2kB page] ... 0x7: 8 sectors [4kB page]" "0: 1 sector [512kB page],1: 2 sectors,?,3: 4 sectors [2kB page],?,?,?,7: 8 sectors [4kB page]"
bitfld.long 0x8 1.--3. "ECCCS,Selects the CS where ECC is computed" "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0. "ECCENABLE,Enables the ECC feature" "0,1"
line.long 0xC "CFG_GPMC_ECC_CONTROL,ECC control"
hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
bitfld.long 0xC 8. "ECCCLEAR,Clear all ECC result registers [Reads returns 0 - Writes 1 to this field clear all ECC result registers - Writes 0 are ignored]" "0,1"
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hexmask.long.byte 0xC 4.--7. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
hexmask.long.byte 0xC 0.--3. 1. "ECCPOINTER,Selects ECC result register [Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored]; Other enums: writing other values disables the.."
line.long 0x10 "CFG_GPMC_ECC_SIZE_CONFIG,ECC size"
bitfld.long 0x10 30.--31. "RESERVED,Write 0's for future compatibility. Read returns 3" "0,1,2,3"
hexmask.long.byte 0x10 22.--29. 1. "ECCSIZE1,Defines ECC size 1 [0x00 corresponds to 2 Bytes  0x01 corresponds to 4 Bytes  0x02 corresponds to 6 Bytes  0x03 corresponds to 8 Bytes  &  0xFF corresponds to 512 Bytes]"
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bitfld.long 0x10 20.--21. "RESERVED,Write 0's for future compatibility. Read returns 3" "0,1,2,3"
hexmask.long.byte 0x10 12.--19. 1. "ECCSIZE0,Defines ECC size 0 [0x00 corresponds to 2 Bytes  0x01 corresponds to 4 Bytes  0x02 corresponds to 6 Bytes  0x03 corresponds to 8 Bytes  &  0xFF corresponds to 512 Bytes]"
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bitfld.long 0x10 9.--11. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register" "0,1"
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bitfld.long 0x10 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register" "0,1"
bitfld.long 0x10 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register" "0,1"
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bitfld.long 0x10 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register" "0,1"
bitfld.long 0x10 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register" "0,1"
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bitfld.long 0x10 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register" "0,1"
bitfld.long 0x10 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register" "0,1"
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bitfld.long 0x10 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register" "0,1"
bitfld.long 0x10 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register" "0,1"
line.long 0x14 "CFG_GPMC_ECC_RESULT,ECC result register"
hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
rbitfld.long 0x14 27. "P2048O,Odd Row Parity bit 2048  only used for ECC computed on 512 Bytes" "0,1"
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rbitfld.long 0x14 26. "P1024O,Odd Row Parity bit 1024" "0,1"
rbitfld.long 0x14 25. "P512O,Odd Row Parity bit 512" "0,1"
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rbitfld.long 0x14 24. "P256O,Odd Row Parity bit 256" "0,1"
rbitfld.long 0x14 23. "P128O,Odd Row Parity bit 128" "0,1"
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rbitfld.long 0x14 22. "P64O,Odd Row Parity bit 64" "0,1"
rbitfld.long 0x14 21. "P32O,Odd Row Parity bit 32" "0,1"
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rbitfld.long 0x14 20. "P16O,Odd Row Parity bit 16" "0,1"
rbitfld.long 0x14 19. "P8O,Odd Row Parity bit 8" "0,1"
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rbitfld.long 0x14 18. "P4O,Odd Column Parity bit 4" "0,1"
rbitfld.long 0x14 17. "P2O,Odd Column Parity bit 2" "0,1"
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rbitfld.long 0x14 16. "P1O,Odd Column Parity bit 1" "0,1"
hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
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rbitfld.long 0x14 11. "P2048E,Even Row Parity bit 2048  only used for ECC computed on 512 Bytes" "0,1"
rbitfld.long 0x14 10. "P1024E,Even Row Parity bit 1024" "0,1"
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rbitfld.long 0x14 9. "P512E,Even Row Parity bit 512" "0,1"
rbitfld.long 0x14 8. "P256E,Even Row Parity bit 256" "0,1"
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rbitfld.long 0x14 7. "P128E,Even Row Parity bit 128" "0,1"
rbitfld.long 0x14 6. "P64E,Even Row Parity bit 64" "0,1"
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rbitfld.long 0x14 5. "P32E,Even Row Parity bit 32" "0,1"
rbitfld.long 0x14 4. "P16E,Even Row Parity bit 16" "0,1"
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rbitfld.long 0x14 3. "P8E,Even Row Parity bit 8" "0,1"
rbitfld.long 0x14 2. "P4E,Even Column Parity bit 4" "0,1"
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rbitfld.long 0x14 1. "P2E,Even Column Parity bit 2" "0,1"
rbitfld.long 0x14 0. "P1E,Even Column Parity bit 1" "0,1"
wgroup.long 0x2D0++0x3
line.long 0x0 "CFG_GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface."
hexmask.long.word 0x0 0.--15. 1. "BCH_DATA,Data to be included in the BCH calculation. Only bits 0 to 7 are taken into account if the calculator is configured to use 8 bits data [ECC16B = 0]"
group.long 0x60++0x1B
line.long 0x0 "CFG_GPMC_CONFIG1,The configuration 1 register sets signal control parameters per chip select"
bitfld.long 0x0 31. "WRAPBURST,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1"
bitfld.long 0x0 30. "READMULTIPLE,Selects the read single or multiple access" "0,1"
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bitfld.long 0x0 29. "READTYPE,Selects the read mode operation" "0,1"
bitfld.long 0x0 28. "WRITEMULTIPLE,Selects the write single or multiple access" "0,1"
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bitfld.long 0x0 27. "WRITETYPE,Selects the write mode operation" "0,1"
bitfld.long 0x0 25.--26. "CLKACTIVATIONTIME,Output GPMC.CLK activation time" "0,1,2,3"
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bitfld.long 0x0 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page [burst] length" "0,1,2,3"
bitfld.long 0x0 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses [Reset value is BOOTWAITEN input pin sampled at IC reset]" "0,1"
newline
bitfld.long 0x0 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "0,1"
bitfld.long 0x0 20. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1"
newline
bitfld.long 0x0 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "0,1,2,3"
bitfld.long 0x0 16.--17. "WAITPINSELECT,Selects the input WAIT pin for this chip select [Reset value is BOOTWAITSELECT input pin sampled at IC reset for CS0 and 0 for CS1-7]" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3"
bitfld.long 0x0 12.--13. "DEVICESIZE,Selects the device size attached [Reset value is BOOTDEVICESIZE input pin sampled at IC reset for CS0 and 01 for CS1-7]" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "DEVICETYPE,Selects the attached device type" "0,1,2,3"
bitfld.long 0x0 8.--9. "MUXADDDATA,Enables the Address and data multiplexed protocol [Reset value is CS0MUXDEVICE input pin sampled at IC reset for CS0 and 0 for CS1-7]" "0,1,2,3"
newline
bitfld.long 0x0 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor [Rd/WRCycleTime  AccessTime  PageBurstAccessTime  CSOnTime  CSRd/WrOffTime  ADVOnTime  ADVRd/WrOffTime  OEOnTime  OEOffTime  WEOnTime  WEOffTime  Cycle2CycleDelay  BusTurnAround  TimeOutStartValue]" "0,1"
newline
bitfld.long 0x0 2.--3. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3"
bitfld.long 0x0 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC.FCLK clock" "0,1,2,3"
line.long 0x4 "CFG_GPMC_CONFIG2,Chip-select signal timing parameter configuration"
hexmask.long.word 0x4 21.--31. 1. "RESERVED,Write 0's for future compatibility Reads returns 0"
hexmask.long.byte 0x4 16.--20. 1. "CSWROFFTIME,CS# de-assertion time from start cycle time for write accesses [0x00 corresponds to 0 GPMC.FCLK cycle  0x01 corresponds to 1 GPMC.FCLK cycle  &  0x1F corresponds to 31 GPMC.FCLK cycles]"
newline
bitfld.long 0x4 13.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 8.--12. 1. "CSRDOFFTIME,CS# de-assertion time from start cycle time for read accesses [0x00 corresponds to 0 GPMC.FCLK cycle  0x01 corresponds to 1 GPMC.FCLK cycle  &  0x1F corresponds to 31 GPMC.FCLK cycles]"
newline
bitfld.long 0x4 7. "CSEXTRADELAY,CS# Add Extra Half GPMC.FCLK cycle" "0,1"
bitfld.long 0x4 4.--6. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 0.--3. 1. "CSONTIME,CS# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle  0x1 corresponds to 1 GPMC.FCLK cycle  &  0xF corresponds to 15 GPMC.FCLK cycles]"
line.long 0x8 "CFG_GPMC_CONFIG3,ADV# signal timing parameter configuration"
rbitfld.long 0x8 31. "RESERVED_1,Write 0's for future compatibility. Read returns 0" "0,1"
bitfld.long 0x8 28.--30. "ADVAADMUXWROFFTIME,ADV# de-assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x8 27. "RESERVED_0,Write 0's for future compatibility. Read returns 0" "0,1"
bitfld.long 0x8 24.--26. "ADVAADMUXRDOFFTIME,ADV# assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 21.--23. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 16.--20. 1. "ADVWROFFTIME,ADV# de-assertion time from start cycle time for write accesses [0x00 corresponds to 0 GPMC.FCLK cycle  0x01 corresponds to 1 GPMC.FCLK cycle  &  0x1F corresponds to 31 GPMC.FCLK cycles]"
newline
bitfld.long 0x8 13.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 8.--12. 1. "ADVRDOFFTIME,ADV# de-assertion time from start cycle time for read accesses[0x00 corresponds to 0 GPMC.FCLK cycle  0x01 corresponds to 1 GPMC.FCLK cycle  &  0x1F corresponds to 31 GPMC.FCLK cycles]"
newline
bitfld.long 0x8 7. "ADVEXTRADELAY,ADV# Add Extra Half GPMC.FCLK cycle" "0,1"
bitfld.long 0x8 4.--6. "ADVAADMUXONTIME,ADV# assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 0.--3. 1. "ADVONTIME,ADV# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle  0x1 corresponds to 1 GPMC.FCLK cycle  &  0xF corresponds to 15 GPMC.FCLK cycles]"
line.long 0xC "CFG_GPMC_CONFIG4,WE# and OE# signals timing parameter configuration"
rbitfld.long 0xC 29.--31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 24.--28. 1. "WEOFFTIME,WE# de-assertion time from start cycle time [0x00 corresponds to 0 GPMC.FCLK cycle  0x01 corresponds to 1 GPMC.FCLK cycle  &  0x1F corresponds to 31 GPMC.FCLK cycles]"
newline
bitfld.long 0xC 23. "WEEXTRADELAY,WE# Add Extra Half GPMC.FCLK cycle" "0,1"
bitfld.long 0xC 20.--22. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xC 16.--19. 1. "WEONTIME,WE# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle  0x1 corresponds to 1 GPMC.FCLK cycle  &  0xF corresponds to 15 GPMC.FCLK cycles]"
bitfld.long 0xC 13.--15. "OEAADMUXOFFTIME,OE# de-assertion time for the first address phase in an AAD-Mux access" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xC 8.--12. 1. "OEOFFTIME,OE# de-assertion time from start cycle time [0x00 corresponds to 0 GPMC.FCLK cycle  0x01 corresponds to 1 GPMC.FCLK cycle  &  0x1F corresponds to 31 GPMC.FCLK cycles]"
bitfld.long 0xC 7. "OEEXTRADELAY,OE# Add Extra Half GPMC.FCLK cycle" "0,1"
newline
bitfld.long 0xC 4.--6. "OEAADMUXONTIME,OE# assertion time for the first address phase in an AAD-Mux access" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 0.--3. 1. "OEONTIME,OE# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle  0x1 corresponds to 1 GPMC.FCLK cycle  &  0xF corresponds to 15 GPMC.FCLK cycles]"
line.long 0x10 "CFG_GPMC_CONFIG5,RdAccessTime and CycleTime timing parameters configuration"
hexmask.long.byte 0x10 28.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
hexmask.long.byte 0x10 24.--27. 1. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access [0x0 corresponds to 0 GPMC.FCLK cycle  0x1 corresponds to 1 GPMC.FCLK cycle  &  0xF corresponds to 15 GPMC.FCLK cycles]"
newline
bitfld.long 0x10 21.--23. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 16.--20. 1. "RDACCESSTIME,Delay between start cycle time and first data valid [0x00 corresponds to 0 GPMC.FCLK cycle  0x01 corresponds to 1 GPMC.FCLK cycle  &  0x1F corresponds to 31 GPMC.FCLK cycles]"
newline
bitfld.long 0x10 13.--15. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 8.--12. 1. "WRCYCLETIME,Total write cycle time [0x00 corresponds to 0 GPMC.FCLK cycle  0x01 corresponds to 1 GPMC.FCLK cycle  &  0x1F corresponds to 31 GPMC.FCLK cycles]"
newline
bitfld.long 0x10 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 0.--4. 1. "RDCYCLETIME,Total read cycle time [0x00 corresponds to 0 GPMC.FCLK cycle  0x01 corresponds to 1 GPMC.FCLK cycle  &  0x1F corresponds to 31 GPMC.FCLK cycles]"
line.long 0x14 "CFG_GPMC_CONFIG6,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration"
bitfld.long 0x14 31. "RESERVED,TI Internal use - Do not modify" "0,1"
bitfld.long 0x14 29.--30. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3"
newline
hexmask.long.byte 0x14 24.--28. 1. "WRACCESSTIME,Delay from StartAccessTime to the GPMC.FCLK rising edge corresponding the the GPMC.CLK rising edge used by the attached memory for the first data capture [0x00 corresponds to 0 GPMC.FCLK cycle  0x01 corresponds to 1 GPMC.FCLK cycle  &  0x1F.."
hexmask.long.byte 0x14 20.--23. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
newline
hexmask.long.byte 0x14 16.--19. 1. "WRDATAONADMUXBUS,Specifies on which GPMC.FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus"
hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
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hexmask.long.byte 0x14 8.--11. 1. "CYCLE2CYCLEDELAY,Chip select high pulse delay between two successive accesses [0x0 corresponds to 0 GPMC.FCLK cycle  0x1 corresponds to 1 GPMC.FCLK cycle  &  0xF corresponds to 15 GPMC.FCLK cycles]"
bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add Cycle2CycleDelay between two successive accesses to the same chip-select [any access type]" "0,1"
newline
bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add Cycle2CycleDelay between two successive accesses to a different chip-select [any access type]" "0,1"
bitfld.long 0x14 4.--5. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3"
newline
hexmask.long.byte 0x14 0.--3. 1. "BUSTURNAROUND,Bus turn around latency between two successive accesses to the same chip-select [rd to wr] or to a different chip-select [read to read and read to write] [0x0 corresponds to 0 GPMC.FCLK cycle  0x1 corresponds to 1 GPMC.FCLK cycle  &  0xF.."
line.long 0x18 "CFG_GPMC_CONFIG7,Chip-select address mapping configuration"
hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0"
hexmask.long.byte 0x18 8.--11. 1. "MASKADDRESS,Chip-select mask address"
newline
bitfld.long 0x18 7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1"
bitfld.long 0x18 6. "CSVALID,Chip-select enable [reset value is 1 for CS0 and 0 for CS1-7]" "0,1"
newline
hexmask.long.byte 0x18 0.--5. 1. "BASEADDRESS,Chip-select base address"
wgroup.long 0x7C++0x7
line.long 0x0 "CFG_GPMC_NAND_COMMAND,This Register is not a true register. just a address location."
hexmask.long 0x0 0.--31. 1. "GPMC_NAND_COMMAND_0,"
line.long 0x4 "CFG_GPMC_NAND_ADDRESS,This Register is not a true register. just a address location."
hexmask.long 0x4 0.--31. 1. "GPMC_NAND_ADDRESS_0,"
group.long 0x84++0x3
line.long 0x0 "CFG_GPMC_NAND_DATA,This Register is not a true register. just a address location."
hexmask.long 0x0 0.--31. 1. "GPMC_NAND_DATA_0,"
rgroup.long 0x240++0xF
line.long 0x0 "CFG_GPMC_BCH_RESULT_0,BCH ECC result. bits 0 to 31"
hexmask.long 0x0 0.--31. 1. "BCH_RESULT_0,BCH ECC result  bits 0 to 31"
line.long 0x4 "CFG_GPMC_BCH_RESULT_1,BCH ECC result. bits 32 to 63"
hexmask.long 0x4 0.--31. 1. "BCH_RESULT_1,BCH ECC result  bits 32 to 63"
line.long 0x8 "CFG_GPMC_BCH_RESULT_2,BCH ECC result. bits 64 to 95"
hexmask.long 0x8 0.--31. 1. "BCH_RESULT_2,BCH ECC result  bits 64 to 95"
line.long 0xC "CFG_GPMC_BCH_RESULT_3,BCH ECC result. bits 96 to 127"
hexmask.long 0xC 0.--31. 1. "BCH_RESULT_3,BCH ECC result  bits 96 to 127"
rgroup.long 0x300++0xB
line.long 0x0 "CFG_GPMC_BCH_RESULT_4,BCH ECC result. bits 128 to 159"
hexmask.long 0x0 0.--31. 1. "BCH_RESULT_4,BCH ECC result  bits 128 to 159"
line.long 0x4 "CFG_GPMC_BCH_RESULT_5,BCH ECC result. bits 160 to 191"
hexmask.long 0x4 0.--31. 1. "BCH_RESULT_5,BCH ECC result  bits 160 to 191"
line.long 0x8 "CFG_GPMC_BCH_RESULT_6,BCH ECC result. bits 192 to 207"
hexmask.long.word 0x8 0.--15. 1. "BCH_RESULT_6,BCH ECC result  bits 192 to 207"
tree.end
tree "GTC0_GTC"
base ad:0x0
tree "GTC0_GTC_CFG0 (GTC0_GTC_CFG0)"
base ad:0xA80000
rgroup.long 0x0++0x7
line.long 0x0 "GTC_CFG0_PID,"
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
line.long 0x4 "GTC_CFG0_GTC_PID,"
bitfld.long 0x4 30.--31. "GTC_PID_SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x4 28.--29. "GTC_PID_BU,Business unit - Processors" "0,1,2,3"
hexmask.long.word 0x4 16.--27. 1. "GTC_PID_FUNC,Module functional identifier - GTC module"
hexmask.long.byte 0x4 11.--15. 1. "GTC_PID_R_RTL,RTL revision number - actual value determined by RTL"
bitfld.long 0x4 8.--10. "GTC_PID_X_MAJOR,Major revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 6.--7. "GTC_PID_CUSTOM,Custom revision number - actual value determined by RTL" "0,1,2,3"
hexmask.long.byte 0x4 0.--5. 1. "GTC_PID_Y_MINOR,Minor revision number - actual value determined by RTL"
group.long 0x8++0x3
line.long 0x0 "GTC_CFG0_PUSHEVT,"
hexmask.long.byte 0x0 0.--5. 1. "PUSHEVT_EXPBIT_SEL,Selects which bit [63:0] of the System Counter value is exported on the push_evt output. This field controls the 64:1 mux that drives the push_evt output."
tree.end
tree "GTC0_GTC_CFG1 (GTC0_GTC_CFG1)"
base ad:0xA90000
group.long 0x0++0x3
line.long 0x0 "GTC_CFG1_CNTCR,"
hexmask.long.tbyte 0x0 8.--31. 1. "CNTCR_FCREQ,Frequency Change Request"
bitfld.long 0x0 1. "CNTCR_HDBG,Halt on Debug" "0,1"
bitfld.long 0x0 0. "CNTCR_EN,Enable System Counter" "0,1"
rgroup.long 0x4++0xB
line.long 0x0 "GTC_CFG1_CNTSR,"
hexmask.long.tbyte 0x0 8.--31. 1. "CNTSR_FCACK,Frequency Change Ackowledge"
bitfld.long 0x0 1. "CNTSR_DBGH,Debug Halt" "0,1"
line.long 0x4 "GTC_CFG1_CNTCV_LO,"
hexmask.long 0x4 0.--31. 1. "CNTCV_LO_COUNTVALUE,Indicates bits [31:0] of the System Counter value."
line.long 0x8 "GTC_CFG1_CNTCV_HI,"
hexmask.long 0x8 0.--31. 1. "CNTCV_HI_COUNTVALUE,Indicates bits [63:32] of the System Counter value."
group.long 0x20++0x3
line.long 0x0 "GTC_CFG1_CNTFID0,"
hexmask.long 0x0 0.--31. 1. "CNTFID0_FREQVALUE,Indicates the base update frequency of the System Counter in Hz."
rgroup.long 0x24++0x3
line.long 0x0 "GTC_CFG1_CNTFID1,"
hexmask.long 0x0 0.--31. 1. "CNTFID1_FREQVALUE,Frequency table end indicator"
tree.end
tree "GTC0_GTC_CFG2 (GTC0_GTC_CFG2)"
base ad:0xAA0000
rgroup.long 0x0++0x7
line.long 0x0 "GTC_CFG2_CNTCVS_LO,"
hexmask.long 0x0 0.--31. 1. "CNTCVS_LO_COUNTVALUE,Indicates bits [31:0] of the System Counter value."
line.long 0x4 "GTC_CFG2_CNTCVS_HI,"
hexmask.long 0x4 0.--31. 1. "CNTCVS_HI_COUNTVALUE,Indicates bits [63:32] of the System Counter value."
tree.end
tree "GTC0_GTC_CFG3 (GTC0_GTC_CFG3)"
base ad:0xAB0000
rgroup.long 0x8++0x3
line.long 0x0 "GTC_CFG3_CNTTIDR,"
hexmask.long.byte 0x0 28.--31. 1. "CNTTIDR_FRAME7,Indicates the features of timer frame7. Each 4 bit field has the following meaning:"
hexmask.long.byte 0x0 24.--27. 1. "CNTTIDR_FRAME6,Indicates the features of timer frame6. Each 4 bit field has the following meaning:"
hexmask.long.byte 0x0 20.--23. 1. "CNTTIDR_FRAME5,Indicates the features of timer frame5. Each 4 bit field has the following meaning:"
hexmask.long.byte 0x0 16.--19. 1. "CNTTIDR_FRAME4,Indicates the features of timer frame4. Each 4 bit field has the following meaning:"
hexmask.long.byte 0x0 12.--15. 1. "CNTTIDR_FRAME3,Indicates the features of timer frame3. Each 4 bit field has the following meaning:"
hexmask.long.byte 0x0 8.--11. 1. "CNTTIDR_FRAME2,Indicates the features of timer frame2. Each 4 bit field has the following meaning:"
hexmask.long.byte 0x0 4.--7. 1. "CNTTIDR_FRAME1,Indicates the features of timer frame1. Each 4 bit field has the following meaning:"
newline
hexmask.long.byte 0x0 0.--3. 1. "CNTTIDR_FRAME0,Indicates the features of timer frame0. Each 4 bit field has the following meaning:"
tree.end
tree.end
tree "I2C"
base ad:0x0
tree "I2C0_CFG (I2C0_CFG)"
base ad:0x20000000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix  and resets to"
bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix  or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix  or major feature change"
line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x0 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
group.long 0x24++0x2B
line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1"
newline
bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1"
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bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)."
bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x7
line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
rgroup.long 0x90++0x3
line.long 0x0 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1"
group.long 0x94++0xB
line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode"
bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
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bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode"
line.long 0x4 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count"
line.long 0x8 "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x1B
line.long 0x0 "CFG_I2C_CON,I2C configuration register."
bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x0 10. "MST,Master/slave mode" "0,1"
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bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1"
newline
bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x4 "CFG_I2C_OA,Own address register"
bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 0.--9. 1. "OA,Own address"
line.long 0x8 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x8 0.--9. 1. "SA,Slave address"
line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
newline
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status"
hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status"
group.long 0xC4++0xB
line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1"
line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2"
hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2"
line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1"
group.long 0xD4++0x3
line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "I2C1_CFG (I2C1_CFG)"
base ad:0x20010000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix  and resets to"
bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix  or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix  or major feature change"
line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x0 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
group.long 0x24++0x2B
line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1"
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bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)."
bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x7
line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
rgroup.long 0x90++0x3
line.long 0x0 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1"
group.long 0x94++0xB
line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode"
bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode"
line.long 0x4 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count"
line.long 0x8 "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x1B
line.long 0x0 "CFG_I2C_CON,I2C configuration register."
bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x0 10. "MST,Master/slave mode" "0,1"
newline
bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1"
newline
bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x4 "CFG_I2C_OA,Own address register"
bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 0.--9. 1. "OA,Own address"
line.long 0x8 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x8 0.--9. 1. "SA,Slave address"
line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
newline
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status"
hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status"
group.long 0xC4++0xB
line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1"
line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2"
hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2"
line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1"
group.long 0xD4++0x3
line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "I2C2_CFG (I2C2_CFG)"
base ad:0x20020000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix  and resets to"
bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix  or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix  or major feature change"
line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x0 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
group.long 0x24++0x2B
line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
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bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1"
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bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
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bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1"
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bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)."
bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x7
line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
rgroup.long 0x90++0x3
line.long 0x0 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1"
group.long 0x94++0xB
line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode"
bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode"
line.long 0x4 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count"
line.long 0x8 "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x1B
line.long 0x0 "CFG_I2C_CON,I2C configuration register."
bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x0 10. "MST,Master/slave mode" "0,1"
newline
bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1"
newline
bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x4 "CFG_I2C_OA,Own address register"
bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 0.--9. 1. "OA,Own address"
line.long 0x8 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x8 0.--9. 1. "SA,Slave address"
line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
newline
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status"
hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status"
group.long 0xC4++0xB
line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1"
line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2"
hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2"
line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1"
group.long 0xD4++0x3
line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "I2C3_CFG (I2C3_CFG)"
base ad:0x20030000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix  and resets to"
bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix  or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix  or major feature change"
line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x0 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
group.long 0x24++0x2B
line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1"
newline
bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)."
bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x7
line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
rgroup.long 0x90++0x3
line.long 0x0 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1"
group.long 0x94++0xB
line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode"
bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode"
line.long 0x4 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count"
line.long 0x8 "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x1B
line.long 0x0 "CFG_I2C_CON,I2C configuration register."
bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x0 10. "MST,Master/slave mode" "0,1"
newline
bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1"
newline
bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x4 "CFG_I2C_OA,Own address register"
bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 0.--9. 1. "OA,Own address"
line.long 0x8 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x8 0.--9. 1. "SA,Slave address"
line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
newline
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status"
hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status"
group.long 0xC4++0xB
line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1"
line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2"
hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2"
line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1"
group.long 0xD4++0x3
line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree.end
tree "MAILBOX0_MAILBOX_CLUSTER"
base ad:0x0
tree "MAILBOX0_MAILBOX_CLUSTER_0_REGS0 (MAILBOX0_MAILBOX_CLUSTER_0_REGS0)"
base ad:0x29000000
rgroup.long 0x0++0x3
line.long 0x0 "REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family."
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z"
newline
bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z"
group.long 0x10++0x3
line.long 0x0 "REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset."
bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads  it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1"
group.long 0x40++0x3
line.long 0x0 "REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox."
hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]"
rgroup.long 0x80++0x3
line.long 0x0 "REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO"
bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]"
bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7"
wgroup.long 0x140++0x3
line.long 0x0 "REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance."
bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
group.long 0x100++0xF
line.long 0x0 "REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ."
bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
newline
bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
newline
bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
newline
bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
newline
bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
newline
bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
newline
bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x4 "REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information."
bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x8 "REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
line.long 0xC "REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
tree.end
tree "MAILBOX0_MAILBOX_CLUSTER_1_REGS1 (MAILBOX0_MAILBOX_CLUSTER_1_REGS1)"
base ad:0x29010000
rgroup.long 0x0++0x3
line.long 0x0 "REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family."
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z"
newline
bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z"
group.long 0x10++0x3
line.long 0x0 "REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset."
bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads  it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1"
group.long 0x40++0x3
line.long 0x0 "REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox."
hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]"
rgroup.long 0x80++0x3
line.long 0x0 "REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO"
bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]"
bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7"
wgroup.long 0x140++0x3
line.long 0x0 "REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance."
bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
group.long 0x100++0xF
line.long 0x0 "REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ."
bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
newline
bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
newline
bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
newline
bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
newline
bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
newline
bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
newline
bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x4 "REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information."
bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x8 "REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
line.long 0xC "REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
tree.end
tree "MAILBOX0_MAILBOX_CLUSTER_2_REGS2 (MAILBOX0_MAILBOX_CLUSTER_2_REGS2)"
base ad:0x29020000
rgroup.long 0x0++0x3
line.long 0x0 "REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family."
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z"
newline
bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z"
group.long 0x10++0x3
line.long 0x0 "REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset."
bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads  it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1"
group.long 0x40++0x3
line.long 0x0 "REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox."
hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]"
rgroup.long 0x80++0x3
line.long 0x0 "REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO"
bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]"
bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7"
wgroup.long 0x140++0x3
line.long 0x0 "REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance."
bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
group.long 0x100++0xF
line.long 0x0 "REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ."
bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
newline
bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
newline
bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
newline
bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
newline
bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
newline
bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
newline
bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x4 "REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information."
bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x8 "REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
line.long 0xC "REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
tree.end
tree "MAILBOX0_MAILBOX_CLUSTER_3_REGS3 (MAILBOX0_MAILBOX_CLUSTER_3_REGS3)"
base ad:0x29030000
rgroup.long 0x0++0x3
line.long 0x0 "REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family."
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z"
newline
bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z"
group.long 0x10++0x3
line.long 0x0 "REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset."
bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads  it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1"
group.long 0x40++0x3
line.long 0x0 "REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox."
hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]"
rgroup.long 0x80++0x3
line.long 0x0 "REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO"
bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]"
bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7"
wgroup.long 0x140++0x3
line.long 0x0 "REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance."
bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
group.long 0x100++0xF
line.long 0x0 "REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ."
bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
newline
bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
newline
bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
newline
bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
newline
bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
newline
bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
newline
bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x4 "REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information."
bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x8 "REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
line.long 0xC "REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
tree.end
tree "MAILBOX0_MAILBOX_CLUSTER_4_REGS4 (MAILBOX0_MAILBOX_CLUSTER_4_REGS4)"
base ad:0x29040000
rgroup.long 0x0++0x3
line.long 0x0 "REGS4_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family."
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z"
newline
bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z"
group.long 0x10++0x3
line.long 0x0 "REGS4_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset."
bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads  it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1"
group.long 0x40++0x3
line.long 0x0 "REGS4_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox."
hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]"
rgroup.long 0x80++0x3
line.long 0x0 "REGS4_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO"
bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "REGS4_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]"
bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7"
wgroup.long 0x140++0x3
line.long 0x0 "REGS4_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance."
bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
group.long 0x100++0xF
line.long 0x0 "REGS4_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ."
bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
newline
bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
newline
bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
newline
bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
newline
bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
newline
bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
newline
bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x4 "REGS4_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information."
bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x8 "REGS4_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
line.long 0xC "REGS4_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
tree.end
tree "MAILBOX0_MAILBOX_CLUSTER_5_REGS5 (MAILBOX0_MAILBOX_CLUSTER_5_REGS5)"
base ad:0x29050000
rgroup.long 0x0++0x3
line.long 0x0 "REGS5_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family."
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z"
newline
bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z"
group.long 0x10++0x3
line.long 0x0 "REGS5_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset."
bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads  it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1"
group.long 0x40++0x3
line.long 0x0 "REGS5_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox."
hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]"
rgroup.long 0x80++0x3
line.long 0x0 "REGS5_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO"
bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "REGS5_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]"
bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7"
wgroup.long 0x140++0x3
line.long 0x0 "REGS5_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance."
bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
group.long 0x100++0xF
line.long 0x0 "REGS5_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ."
bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
newline
bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
newline
bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
newline
bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
newline
bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
newline
bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
newline
bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x4 "REGS5_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information."
bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x8 "REGS5_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
line.long 0xC "REGS5_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
tree.end
tree "MAILBOX0_MAILBOX_CLUSTER_6_REGS6 (MAILBOX0_MAILBOX_CLUSTER_6_REGS6)"
base ad:0x29060000
rgroup.long 0x0++0x3
line.long 0x0 "REGS6_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family."
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z"
newline
bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z"
group.long 0x10++0x3
line.long 0x0 "REGS6_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset."
bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads  it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1"
group.long 0x40++0x3
line.long 0x0 "REGS6_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox."
hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]"
rgroup.long 0x80++0x3
line.long 0x0 "REGS6_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO"
bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "REGS6_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]"
bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7"
wgroup.long 0x140++0x3
line.long 0x0 "REGS6_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance."
bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
group.long 0x100++0xF
line.long 0x0 "REGS6_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ."
bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
newline
bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
newline
bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
newline
bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
newline
bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
newline
bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
newline
bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x4 "REGS6_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information."
bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x8 "REGS6_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
line.long 0xC "REGS6_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
tree.end
tree "MAILBOX0_MAILBOX_CLUSTER_7_REGS7 (MAILBOX0_MAILBOX_CLUSTER_7_REGS7)"
base ad:0x29070000
rgroup.long 0x0++0x3
line.long 0x0 "REGS7_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family."
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z"
newline
bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z"
group.long 0x10++0x3
line.long 0x0 "REGS7_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset."
bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads  it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1"
group.long 0x40++0x3
line.long 0x0 "REGS7_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox."
hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]"
rgroup.long 0x80++0x3
line.long 0x0 "REGS7_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO"
bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "REGS7_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]"
bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7"
wgroup.long 0x140++0x3
line.long 0x0 "REGS7_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance."
bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
group.long 0x100++0xF
line.long 0x0 "REGS7_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ."
bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
newline
bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
newline
bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
newline
bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
newline
bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
newline
bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
newline
bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x4 "REGS7_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information."
bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x8 "REGS7_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1"
line.long 0xC "REGS7_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]."
bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
newline
bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1"
tree.end
tree.end
tree "MAIN_GPIOMUX_INTROUTER0_CFG (MAIN_GPIOMUX_INTROUTER0_CFG)"
base ad:0xA00000
rgroup.long 0x0++0x3
line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register"
bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function"
hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version"
bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version"
group.long 0x4++0x3
line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register"
bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "MUX_CNTL,Mux control for interrupt N"
tree.end
tree "MCAN0"
base ad:0x0
tree "MCAN0_CFG (MCAN0_CFG)"
base ad:0x20701000
rgroup.long 0x0++0x7
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)"
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release"
newline
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321"
hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value"
group.long 0x8++0x37
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable"
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1"
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler"
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point"
newline
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point"
hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection"
rbitfld.long 0x8 7. "RX,Receive Pin" "0,1"
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1"
line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM"
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration"
bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1"
newline
bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1"
bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1"
newline
bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1"
bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1"
newline
bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1"
newline
bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x10 0. "INIT,Initialization" "0,1"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing"
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
newline
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector"
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter"
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode"
hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter"
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter"
line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field"
line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field"
line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field"
line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field"
rgroup.long 0x40++0x7
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
newline
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1"
newline
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1"
bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1"
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
bitfld.long 0x4 5. "EP,Error Passive" "0,1"
newline
bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
group.long 0x48++0x4B
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags"
bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
newline
bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1"
bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x8 24. "EW,Warning Status" "0,1"
newline
bitfld.long 0x8 23. "EP,Error Passive" "0,1"
bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1"
bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1"
newline
bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1"
newline
bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1"
bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1"
newline
bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1"
newline
bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x8 9. "TC,Transmission Complete" "0,1"
bitfld.long 0x8 8. "HPM,High Priority Message" "0,1"
newline
bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1"
bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
newline
bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1"
newline
bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable"
bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
newline
bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1"
bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1"
newline
bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
newline
bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
newline
bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
newline
bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
newline
bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
newline
bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
newline
bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)"
bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
newline
bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1"
bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1"
newline
bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
newline
bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
newline
bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
newline
bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
newline
bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1"
newline
bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
newline
bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1"
bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field"
line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field"
line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field"
line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field"
line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field"
line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field"
line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames"
bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1"
newline
bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address"
line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address"
line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field"
line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939"
hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask"
rgroup.long 0x94++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages"
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
group.long 0x98++0xB
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31"
bitfld.long 0x0 31. "ND31,New Data" "0,1"
bitfld.long 0x0 30. "ND30,New Data" "0,1"
bitfld.long 0x0 29. "ND29,New Data" "0,1"
newline
bitfld.long 0x0 28. "ND28,New Data" "0,1"
bitfld.long 0x0 27. "ND27,New Data" "0,1"
bitfld.long 0x0 26. "ND26,New Data" "0,1"
newline
bitfld.long 0x0 25. "ND25,New Data" "0,1"
bitfld.long 0x0 24. "ND24,New Data" "0,1"
bitfld.long 0x0 23. "ND23,New Data" "0,1"
newline
bitfld.long 0x0 22. "ND22,New Data" "0,1"
bitfld.long 0x0 21. "ND21,New Data" "0,1"
bitfld.long 0x0 20. "ND20,New Data" "0,1"
newline
bitfld.long 0x0 19. "ND19,New Data" "0,1"
bitfld.long 0x0 18. "ND18,New Data" "0,1"
bitfld.long 0x0 17. "ND17,New Data" "0,1"
newline
bitfld.long 0x0 16. "ND16,New Data" "0,1"
bitfld.long 0x0 15. "ND15,New Data" "0,1"
bitfld.long 0x0 14. "ND14,New Data" "0,1"
newline
bitfld.long 0x0 13. "ND13,New Data" "0,1"
bitfld.long 0x0 12. "ND12,New Data" "0,1"
bitfld.long 0x0 11. "ND11,New Data" "0,1"
newline
bitfld.long 0x0 10. "ND10,New Data" "0,1"
bitfld.long 0x0 9. "ND9,New Data" "0,1"
bitfld.long 0x0 8. "ND8,New Data" "0,1"
newline
bitfld.long 0x0 7. "ND7,New Data" "0,1"
bitfld.long 0x0 6. "ND6,New Data" "0,1"
bitfld.long 0x0 5. "ND5,New Data" "0,1"
newline
bitfld.long 0x0 4. "ND4,New Data" "0,1"
bitfld.long 0x0 3. "ND3,New Data" "0,1"
bitfld.long 0x0 2. "ND2,New Data" "0,1"
newline
bitfld.long 0x0 1. "ND1,New Data" "0,1"
bitfld.long 0x0 0. "ND0,New Data" "0,1"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63"
bitfld.long 0x4 31. "ND63,New Data" "0,1"
bitfld.long 0x4 30. "ND62,New Data" "0,1"
bitfld.long 0x4 29. "ND61,New Data" "0,1"
newline
bitfld.long 0x4 28. "ND60,New Data" "0,1"
bitfld.long 0x4 27. "ND59,New Data" "0,1"
bitfld.long 0x4 26. "ND58,New Data" "0,1"
newline
bitfld.long 0x4 25. "ND57,New Data" "0,1"
bitfld.long 0x4 24. "ND56,New Data" "0,1"
bitfld.long 0x4 23. "ND55,New Data" "0,1"
newline
bitfld.long 0x4 22. "ND54,New Data" "0,1"
bitfld.long 0x4 21. "ND53,New Data" "0,1"
bitfld.long 0x4 20. "ND52,New Data" "0,1"
newline
bitfld.long 0x4 19. "ND51,New Data" "0,1"
bitfld.long 0x4 18. "ND50,New Data" "0,1"
bitfld.long 0x4 17. "ND49,New Data" "0,1"
newline
bitfld.long 0x4 16. "ND48,New Data" "0,1"
bitfld.long 0x4 15. "ND47,New Data" "0,1"
bitfld.long 0x4 14. "ND46,New Data" "0,1"
newline
bitfld.long 0x4 13. "ND45,New Data" "0,1"
bitfld.long 0x4 12. "ND44,New Data" "0,1"
bitfld.long 0x4 11. "ND43,New Data" "0,1"
newline
bitfld.long 0x4 10. "ND42,New Data" "0,1"
bitfld.long 0x4 9. "ND41,New Data" "0,1"
bitfld.long 0x4 8. "ND40,New Data" "0,1"
newline
bitfld.long 0x4 7. "ND39,New Data" "0,1"
bitfld.long 0x4 6. "ND38,New Data" "0,1"
bitfld.long 0x4 5. "ND37,New Data" "0,1"
newline
bitfld.long 0x4 4. "ND36,New Data" "0,1"
bitfld.long 0x4 3. "ND35,New Data" "0,1"
bitfld.long 0x4 2. "ND34,New Data" "0,1"
newline
bitfld.long 0x4 1. "ND33,New Data" "0,1"
bitfld.long 0x4 0. "ND32,New Data" "0,1"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address"
bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
newline
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
rgroup.long 0xA4++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level"
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
newline
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
group.long 0xA8++0xB
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level"
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section"
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address"
bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
newline
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
rgroup.long 0xB4++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level"
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1"
newline
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
group.long 0xB8++0xB
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames"
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address"
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
newline
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
rgroup.long 0xC4++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level"
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1"
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index"
newline
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
group.long 0xC8++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission"
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
rgroup.long 0xCC++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request"
bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1"
bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1"
bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1"
bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1"
bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1"
bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1"
bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1"
bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1"
bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1"
bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1"
bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1"
bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1"
bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1"
bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1"
bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1"
bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1"
bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1"
bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1"
bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1"
bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1"
bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1"
bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1"
group.long 0xD0++0x7
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests"
bitfld.long 0x0 31. "AR31,Add request" "0,1"
bitfld.long 0x0 30. "AR30,Add request" "0,1"
bitfld.long 0x0 29. "AR29,Add request" "0,1"
newline
bitfld.long 0x0 28. "AR28,Add request" "0,1"
bitfld.long 0x0 27. "AR27,Add request" "0,1"
bitfld.long 0x0 26. "AR26,Add request" "0,1"
newline
bitfld.long 0x0 25. "AR25,Add request" "0,1"
bitfld.long 0x0 24. "AR24,Add request" "0,1"
bitfld.long 0x0 23. "AR23,Add request" "0,1"
newline
bitfld.long 0x0 22. "AR22,Add request" "0,1"
bitfld.long 0x0 21. "AR21,Add request" "0,1"
bitfld.long 0x0 20. "AR20,Add request" "0,1"
newline
bitfld.long 0x0 19. "AR19,Add request" "0,1"
bitfld.long 0x0 18. "AR18,Add request" "0,1"
bitfld.long 0x0 17. "AR17,Add request" "0,1"
newline
bitfld.long 0x0 16. "AR16,Add request" "0,1"
bitfld.long 0x0 15. "AR15,Add request" "0,1"
bitfld.long 0x0 14. "AR14,Add request" "0,1"
newline
bitfld.long 0x0 13. "AR13,Add request" "0,1"
bitfld.long 0x0 12. "AR12,Add request" "0,1"
bitfld.long 0x0 11. "AR11,Add request" "0,1"
newline
bitfld.long 0x0 10. "AR10,Add request" "0,1"
bitfld.long 0x0 9. "AR9,Add request" "0,1"
bitfld.long 0x0 8. "AR8,Add request" "0,1"
newline
bitfld.long 0x0 7. "AR7,Add request" "0,1"
bitfld.long 0x0 6. "AR6,Add request" "0,1"
bitfld.long 0x0 5. "AR5,Add request" "0,1"
newline
bitfld.long 0x0 4. "AR4,Add request" "0,1"
bitfld.long 0x0 3. "AR3,Add request" "0,1"
bitfld.long 0x0 2. "AR2,Add request" "0,1"
newline
bitfld.long 0x0 1. "AR1,Add request" "0,1"
bitfld.long 0x0 0. "AR0,Add request" "0,1"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions"
bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1"
bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1"
bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1"
newline
bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1"
bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1"
bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1"
newline
bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1"
bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1"
bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1"
newline
bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1"
bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1"
bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1"
newline
bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1"
bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1"
bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1"
newline
bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1"
bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1"
bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1"
newline
bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1"
bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1"
bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1"
newline
bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1"
bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1"
bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1"
newline
bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1"
bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1"
bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1"
newline
bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1"
bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1"
bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1"
newline
bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1"
bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1"
rgroup.long 0xD8++0x7
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared"
bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1"
bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1"
bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1"
bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1"
bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1"
bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1"
bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1"
bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1"
bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1"
bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1"
bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1"
bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1"
bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1"
bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1"
bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1"
bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1"
bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1"
bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1"
bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1"
bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1"
bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1"
bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request"
bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1"
bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1"
bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1"
bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1"
bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1"
bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1"
bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1"
bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1"
bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1"
bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1"
bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1"
bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1"
bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1"
bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1"
bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1"
bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1"
bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1"
bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1"
bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1"
bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1"
bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1"
bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1"
group.long 0xE0++0x13
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers"
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers"
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field"
line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address"
hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark"
hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size"
hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address"
rgroup.long 0xF4++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level"
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
newline
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
group.long 0xF8++0xB
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field"
tree.end
tree "MCAN0_ECC_AGGR (MCAN0_ECC_AGGR)"
base ad:0x24018000
rgroup.long 0x0++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x7
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCAN0_SS (MCAN0_SS)"
base ad:0x20700000
rgroup.long 0x0++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
newline
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS"
bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
newline
bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend  1-Disregard debug suspend" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS"
bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress  1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done"
wgroup.long 0xC++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits"
bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1"
group.long 0x10++0xB
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits."
bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1"
line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits"
bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1"
line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable"
bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts"
bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register"
hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write  level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt"
group.long 0x24++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler"
hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1"
rgroup.long 0x28++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter"
hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt"
tree.end
tree.end
tree "MCAN1"
base ad:0x0
tree "MCAN1_CFG (MCAN1_CFG)"
base ad:0x20711000
rgroup.long 0x0++0x7
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)"
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release"
newline
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321"
hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value"
group.long 0x8++0x37
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable"
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1"
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler"
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point"
newline
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point"
hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection"
rbitfld.long 0x8 7. "RX,Receive Pin" "0,1"
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1"
line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM"
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration"
bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1"
newline
bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1"
bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1"
newline
bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1"
bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1"
newline
bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1"
newline
bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x10 0. "INIT,Initialization" "0,1"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing"
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
newline
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector"
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter"
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode"
hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter"
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter"
line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field"
line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field"
line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field"
line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field"
rgroup.long 0x40++0x7
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
newline
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1"
newline
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1"
bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1"
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
bitfld.long 0x4 5. "EP,Error Passive" "0,1"
newline
bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
group.long 0x48++0x4B
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags"
bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
newline
bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1"
bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x8 24. "EW,Warning Status" "0,1"
newline
bitfld.long 0x8 23. "EP,Error Passive" "0,1"
bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1"
bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1"
newline
bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1"
newline
bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1"
bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1"
newline
bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1"
newline
bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x8 9. "TC,Transmission Complete" "0,1"
bitfld.long 0x8 8. "HPM,High Priority Message" "0,1"
newline
bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1"
bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
newline
bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1"
newline
bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable"
bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
newline
bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1"
bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1"
newline
bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
newline
bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
newline
bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
newline
bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
newline
bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
newline
bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
newline
bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)"
bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
newline
bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1"
bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1"
newline
bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
newline
bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
newline
bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
newline
bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
newline
bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1"
newline
bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
newline
bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1"
bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field"
line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field"
line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field"
line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field"
line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field"
line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field"
line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames"
bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1"
newline
bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address"
line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address"
line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field"
line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939"
hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask"
rgroup.long 0x94++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages"
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
group.long 0x98++0xB
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31"
bitfld.long 0x0 31. "ND31,New Data" "0,1"
bitfld.long 0x0 30. "ND30,New Data" "0,1"
bitfld.long 0x0 29. "ND29,New Data" "0,1"
newline
bitfld.long 0x0 28. "ND28,New Data" "0,1"
bitfld.long 0x0 27. "ND27,New Data" "0,1"
bitfld.long 0x0 26. "ND26,New Data" "0,1"
newline
bitfld.long 0x0 25. "ND25,New Data" "0,1"
bitfld.long 0x0 24. "ND24,New Data" "0,1"
bitfld.long 0x0 23. "ND23,New Data" "0,1"
newline
bitfld.long 0x0 22. "ND22,New Data" "0,1"
bitfld.long 0x0 21. "ND21,New Data" "0,1"
bitfld.long 0x0 20. "ND20,New Data" "0,1"
newline
bitfld.long 0x0 19. "ND19,New Data" "0,1"
bitfld.long 0x0 18. "ND18,New Data" "0,1"
bitfld.long 0x0 17. "ND17,New Data" "0,1"
newline
bitfld.long 0x0 16. "ND16,New Data" "0,1"
bitfld.long 0x0 15. "ND15,New Data" "0,1"
bitfld.long 0x0 14. "ND14,New Data" "0,1"
newline
bitfld.long 0x0 13. "ND13,New Data" "0,1"
bitfld.long 0x0 12. "ND12,New Data" "0,1"
bitfld.long 0x0 11. "ND11,New Data" "0,1"
newline
bitfld.long 0x0 10. "ND10,New Data" "0,1"
bitfld.long 0x0 9. "ND9,New Data" "0,1"
bitfld.long 0x0 8. "ND8,New Data" "0,1"
newline
bitfld.long 0x0 7. "ND7,New Data" "0,1"
bitfld.long 0x0 6. "ND6,New Data" "0,1"
bitfld.long 0x0 5. "ND5,New Data" "0,1"
newline
bitfld.long 0x0 4. "ND4,New Data" "0,1"
bitfld.long 0x0 3. "ND3,New Data" "0,1"
bitfld.long 0x0 2. "ND2,New Data" "0,1"
newline
bitfld.long 0x0 1. "ND1,New Data" "0,1"
bitfld.long 0x0 0. "ND0,New Data" "0,1"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63"
bitfld.long 0x4 31. "ND63,New Data" "0,1"
bitfld.long 0x4 30. "ND62,New Data" "0,1"
bitfld.long 0x4 29. "ND61,New Data" "0,1"
newline
bitfld.long 0x4 28. "ND60,New Data" "0,1"
bitfld.long 0x4 27. "ND59,New Data" "0,1"
bitfld.long 0x4 26. "ND58,New Data" "0,1"
newline
bitfld.long 0x4 25. "ND57,New Data" "0,1"
bitfld.long 0x4 24. "ND56,New Data" "0,1"
bitfld.long 0x4 23. "ND55,New Data" "0,1"
newline
bitfld.long 0x4 22. "ND54,New Data" "0,1"
bitfld.long 0x4 21. "ND53,New Data" "0,1"
bitfld.long 0x4 20. "ND52,New Data" "0,1"
newline
bitfld.long 0x4 19. "ND51,New Data" "0,1"
bitfld.long 0x4 18. "ND50,New Data" "0,1"
bitfld.long 0x4 17. "ND49,New Data" "0,1"
newline
bitfld.long 0x4 16. "ND48,New Data" "0,1"
bitfld.long 0x4 15. "ND47,New Data" "0,1"
bitfld.long 0x4 14. "ND46,New Data" "0,1"
newline
bitfld.long 0x4 13. "ND45,New Data" "0,1"
bitfld.long 0x4 12. "ND44,New Data" "0,1"
bitfld.long 0x4 11. "ND43,New Data" "0,1"
newline
bitfld.long 0x4 10. "ND42,New Data" "0,1"
bitfld.long 0x4 9. "ND41,New Data" "0,1"
bitfld.long 0x4 8. "ND40,New Data" "0,1"
newline
bitfld.long 0x4 7. "ND39,New Data" "0,1"
bitfld.long 0x4 6. "ND38,New Data" "0,1"
bitfld.long 0x4 5. "ND37,New Data" "0,1"
newline
bitfld.long 0x4 4. "ND36,New Data" "0,1"
bitfld.long 0x4 3. "ND35,New Data" "0,1"
bitfld.long 0x4 2. "ND34,New Data" "0,1"
newline
bitfld.long 0x4 1. "ND33,New Data" "0,1"
bitfld.long 0x4 0. "ND32,New Data" "0,1"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address"
bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
newline
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
rgroup.long 0xA4++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level"
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
newline
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
group.long 0xA8++0xB
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level"
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section"
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address"
bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
newline
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
rgroup.long 0xB4++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level"
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1"
newline
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
group.long 0xB8++0xB
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames"
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address"
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
newline
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
rgroup.long 0xC4++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level"
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1"
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index"
newline
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
group.long 0xC8++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission"
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
rgroup.long 0xCC++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request"
bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1"
bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1"
bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1"
bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1"
bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1"
bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1"
bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1"
bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1"
bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1"
bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1"
bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1"
bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1"
bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1"
bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1"
bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1"
bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1"
bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1"
bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1"
bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1"
bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1"
bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1"
newline
bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1"
bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1"
group.long 0xD0++0x7
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests"
bitfld.long 0x0 31. "AR31,Add request" "0,1"
bitfld.long 0x0 30. "AR30,Add request" "0,1"
bitfld.long 0x0 29. "AR29,Add request" "0,1"
newline
bitfld.long 0x0 28. "AR28,Add request" "0,1"
bitfld.long 0x0 27. "AR27,Add request" "0,1"
bitfld.long 0x0 26. "AR26,Add request" "0,1"
newline
bitfld.long 0x0 25. "AR25,Add request" "0,1"
bitfld.long 0x0 24. "AR24,Add request" "0,1"
bitfld.long 0x0 23. "AR23,Add request" "0,1"
newline
bitfld.long 0x0 22. "AR22,Add request" "0,1"
bitfld.long 0x0 21. "AR21,Add request" "0,1"
bitfld.long 0x0 20. "AR20,Add request" "0,1"
newline
bitfld.long 0x0 19. "AR19,Add request" "0,1"
bitfld.long 0x0 18. "AR18,Add request" "0,1"
bitfld.long 0x0 17. "AR17,Add request" "0,1"
newline
bitfld.long 0x0 16. "AR16,Add request" "0,1"
bitfld.long 0x0 15. "AR15,Add request" "0,1"
bitfld.long 0x0 14. "AR14,Add request" "0,1"
newline
bitfld.long 0x0 13. "AR13,Add request" "0,1"
bitfld.long 0x0 12. "AR12,Add request" "0,1"
bitfld.long 0x0 11. "AR11,Add request" "0,1"
newline
bitfld.long 0x0 10. "AR10,Add request" "0,1"
bitfld.long 0x0 9. "AR9,Add request" "0,1"
bitfld.long 0x0 8. "AR8,Add request" "0,1"
newline
bitfld.long 0x0 7. "AR7,Add request" "0,1"
bitfld.long 0x0 6. "AR6,Add request" "0,1"
bitfld.long 0x0 5. "AR5,Add request" "0,1"
newline
bitfld.long 0x0 4. "AR4,Add request" "0,1"
bitfld.long 0x0 3. "AR3,Add request" "0,1"
bitfld.long 0x0 2. "AR2,Add request" "0,1"
newline
bitfld.long 0x0 1. "AR1,Add request" "0,1"
bitfld.long 0x0 0. "AR0,Add request" "0,1"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions"
bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1"
bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1"
bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1"
newline
bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1"
bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1"
bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1"
newline
bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1"
bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1"
bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1"
newline
bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1"
bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1"
bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1"
newline
bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1"
bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1"
bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1"
newline
bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1"
bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1"
bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1"
newline
bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1"
bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1"
bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1"
newline
bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1"
bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1"
bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1"
newline
bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1"
bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1"
bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1"
newline
bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1"
bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1"
bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1"
newline
bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1"
bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1"
rgroup.long 0xD8++0x7
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared"
bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1"
bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1"
bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1"
bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1"
bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1"
bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1"
bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1"
bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1"
bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1"
bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1"
bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1"
bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1"
bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1"
bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1"
bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1"
bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1"
bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1"
bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1"
bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1"
bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1"
bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1"
newline
bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1"
bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request"
bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1"
bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1"
bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1"
bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1"
bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1"
bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1"
bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1"
bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1"
bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1"
bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1"
bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1"
bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1"
bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1"
bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1"
bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1"
bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1"
bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1"
bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1"
bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1"
bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1"
bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1"
newline
bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1"
bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1"
group.long 0xE0++0x13
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers"
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1"
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers"
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field"
line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address"
hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark"
hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size"
hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address"
rgroup.long 0xF4++0x3
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level"
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
newline
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
group.long 0xF8++0xB
line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field"
line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field"
tree.end
tree "MCAN1_ECC_AGGR (MCAN1_ECC_AGGR)"
base ad:0x24019000
rgroup.long 0x0++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x7
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCAN1_SS (MCAN1_SS)"
base ad:0x20710000
rgroup.long 0x0++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
newline
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS"
bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
newline
bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend  1-Disregard debug suspend" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS"
bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress  1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done"
wgroup.long 0xC++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits"
bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1"
group.long 0x10++0xB
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits."
bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1"
line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits"
bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1"
line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable"
bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts"
bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register"
hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write  level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt"
group.long 0x24++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler"
hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1"
rgroup.long 0x28++0x3
line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter"
hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt"
tree.end
tree.end
tree "MCSPI"
base ad:0x0
tree "MCSPI0_CFG (MCSPI0_CFG)"
base ad:0x20100000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R]  maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.."
bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X]  maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y]  maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.."
line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)."
hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored"
bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter  only MSB bits from 8 down to 4 are taken into account"
bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x3
line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition  target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x3
line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10  0x21 for 21"
group.long 0x110++0x2B
line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface."
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
newline
bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
newline
bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
newline
bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis."
hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
newline
bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
newline
bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
newline
bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode."
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns the value on the CLKSPI line [high or low]  and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction]  the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction]  the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface."
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode  The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode  in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit"
rgroup.long 0x13C++0x3
line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data"
group.long 0x140++0xF
line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel."
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit"
rgroup.long 0x150++0x3
line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data"
group.long 0x154++0xF
line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit"
rgroup.long 0x164++0x3
line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data"
group.long 0x168++0xF
line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit"
rgroup.long 0x178++0x3
line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data"
group.long 0x17C++0x7
line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started  a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
rgroup.long 0x1A0++0x3
line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
tree.end
tree "MCSPI1_CFG (MCSPI1_CFG)"
base ad:0x20110000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R]  maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.."
bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X]  maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y]  maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.."
line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)."
hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored"
bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter  only MSB bits from 8 down to 4 are taken into account"
bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x3
line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition  target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x3
line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10  0x21 for 21"
group.long 0x110++0x2B
line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface."
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis."
hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode."
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns the value on the CLKSPI line [high or low]  and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction]  the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction]  the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface."
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode  The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode  in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit"
rgroup.long 0x13C++0x3
line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data"
group.long 0x140++0xF
line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel."
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit"
rgroup.long 0x150++0x3
line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data"
group.long 0x154++0xF
line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit"
rgroup.long 0x164++0x3
line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data"
group.long 0x168++0xF
line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit"
rgroup.long 0x178++0x3
line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data"
group.long 0x17C++0x7
line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started  a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
rgroup.long 0x1A0++0x3
line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
tree.end
tree "MCSPI2_CFG (MCSPI2_CFG)"
base ad:0x20120000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R]  maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.."
bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X]  maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y]  maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.."
line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)."
hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored"
bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter  only MSB bits from 8 down to 4 are taken into account"
bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x3
line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition  target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x3
line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10  0x21 for 21"
group.long 0x110++0x2B
line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface."
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis."
hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode."
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns the value on the CLKSPI line [high or low]  and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction]  the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction]  the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface."
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode  The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode  in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit"
rgroup.long 0x13C++0x3
line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data"
group.long 0x140++0xF
line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel."
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit"
rgroup.long 0x150++0x3
line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data"
group.long 0x154++0xF
line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit"
rgroup.long 0x164++0x3
line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data"
group.long 0x168++0xF
line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit"
rgroup.long 0x178++0x3
line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data"
group.long 0x17C++0x7
line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started  a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
rgroup.long 0x1A0++0x3
line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
tree.end
tree "MCSPI3_CFG (MCSPI3_CFG)"
base ad:0x20130000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R]  maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.."
bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X]  maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y]  maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.."
line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)."
hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored"
bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter  only MSB bits from 8 down to 4 are taken into account"
bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x3
line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition  target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x3
line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10  0x21 for 21"
group.long 0x110++0x2B
line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface."
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis."
hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode."
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns the value on the CLKSPI line [high or low]  and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction]  the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction]  the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface."
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode  The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode  in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit"
rgroup.long 0x13C++0x3
line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data"
group.long 0x140++0xF
line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel."
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit"
rgroup.long 0x150++0x3
line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data"
group.long 0x154++0xF
line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit"
rgroup.long 0x164++0x3
line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data"
group.long 0x168++0xF
line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit"
rgroup.long 0x178++0x3
line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data"
group.long 0x17C++0x7
line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started  a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
rgroup.long 0x1A0++0x3
line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
tree.end
tree "MCSPI4_CFG (MCSPI4_CFG)"
base ad:0x20140000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R]  maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.."
bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X]  maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y]  maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.."
line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)."
hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored"
bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter  only MSB bits from 8 down to 4 are taken into account"
bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x3
line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition  target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x3
line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10  0x21 for 21"
group.long 0x110++0x2B
line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface."
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis."
hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode."
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns the value on the CLKSPI line [high or low]  and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction]  the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction]  the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface."
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode  The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode  in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit"
rgroup.long 0x13C++0x3
line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data"
group.long 0x140++0xF
line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel."
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit"
rgroup.long 0x150++0x3
line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data"
group.long 0x154++0xF
line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
newline
bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
newline
bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit"
rgroup.long 0x164++0x3
line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data"
group.long 0x168++0xF
line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
newline
bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
newline
bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit"
rgroup.long 0x178++0x3
line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data"
group.long 0x17C++0x7
line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started  a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
rgroup.long 0x1A0++0x3
line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
tree.end
tree.end
tree "MCU"
base ad:0x0
tree "MCU_CBASS0"
tree "MCU_CBASS0_ERR (MCU_CBASS0_ERR)"
base ad:0x4720000
rgroup.long 0x0++0x3
line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
rgroup.long 0x24++0x17
line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error."
line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits."
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x50++0x13
line.long 0x0 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1"
line.long 0x4 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x8 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0xC "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "MCU_CBASS0_GLB (MCU_CBASS0_GLB)"
base ad:0x45B02000
rgroup.long 0x0++0x3
line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
tree.end
tree "MCU_CBASS0_ISC (MCU_CBASS0_ISC)"
base ad:0x45830000
group.long 0x0++0x3
line.long 0x0 "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iblazar_mcu_0.vbusp_m region 0 ISC."
bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3"
bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3"
bitfld.long 0x0 21. "PASS,No privID replacement  pass through value." "0,1"
newline
bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1"
hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables  others disable."
hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID."
newline
rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
group.long 0x10++0x13
line.long 0x0 "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iblazar_mcu_0.vbusp_m region 0 ISC."
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12."
hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode."
line.long 0x4 "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iblazar_mcu_0.vbusp_m region 0 ISC."
hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32."
line.long 0x8 "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iblazar_mcu_0.vbusp_m region 0 ISC."
hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match."
hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned."
line.long 0xC "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iblazar_mcu_0.vbusp_m region 0 ISC."
hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32."
line.long 0x10 "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iblazar_mcu_0.vbusp_m region 1 ISC."
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set  else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear  others do nothing. Do not set both sec and nonsec." "0,1"
hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set  others do nothing. Do not set both sec and nonsec."
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0."
newline
rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1"
bitfld.long 0x10 4. "LOCK,Lock region. Once set  the region values cannot be modified." "0,1"
newline
hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables  others disable."
tree.end
tree "MCU_CBASS0_QOS (MCU_CBASS0_QOS)"
base ad:0x45D30000
group.long 0x100++0x3
line.long 0x0 "QOS_REGS_Iblazar_mcu_0_vbusp_m_map0,The Map Register defines the fields for the master Iblazar_mcu_0.vbusp_m per channel."
bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address."
bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "MCU_CTRL_MMR0_CFG0 (MCU_CTRL_MMR0_CFG0)"
base ad:0x4500000
rgroup.long 0x0++0x3
line.long 0x0 "CFG0_PID,"
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
newline
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
newline
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
rgroup.long 0x8++0x3
line.long 0x0 "CFG0_MMR_CFG1,"
bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN,Proxy addressing actived" "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions"
group.long 0x1008++0x1B
line.long 0x0 "CFG0_LOCK0_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK0_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component"
line.long 0x8 "CFG0_intr_raw_status,"
bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
line.long 0xC "CFG0_intr_enabled_status_clear,"
bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
line.long 0x10 "CFG0_intr_enable,"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
line.long 0x14 "CFG0_intr_enable_clear,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
line.long 0x18 "CFG0_eoi,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip."
rgroup.long 0x1024++0xB
line.long 0x0 "CFG0_fault_address,"
hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address."
line.long 0x4 "CFG0_fault_type_status,"
bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1"
newline
hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
line.long 0x8 "CFG0_fault_attr_status,"
hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID."
newline
hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID."
newline
hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID."
wgroup.long 0x1030++0x3
line.long 0x0 "CFG0_fault_clear,"
bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
rgroup.long 0x1100++0x3
line.long 0x0 "CFG0_CLAIMREG_P0_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0_READONLY,Claim bits for Partition 0"
rgroup.long 0x2000++0x3
line.long 0x0 "CFG0_PID_PROXY,"
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY,"
newline
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY,"
newline
bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY,"
rgroup.long 0x2008++0x3
line.long 0x0 "CFG0_MMR_CFG1_PROXY,"
bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing actived" "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions"
group.long 0x3008++0x1B
line.long 0x0 "CFG0_LOCK0_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK0_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component"
line.long 0x8 "CFG0_intr_raw_status_PROXY,"
bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
line.long 0xC "CFG0_intr_enabled_status_clear_PROXY,"
bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
line.long 0x10 "CFG0_intr_enable_PROXY,"
bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
line.long 0x14 "CFG0_intr_enable_clear_PROXY,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
line.long 0x18 "CFG0_eoi_PROXY,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip."
rgroup.long 0x3024++0xB
line.long 0x0 "CFG0_fault_address_PROXY,"
hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address."
line.long 0x4 "CFG0_fault_type_status_PROXY,"
bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1"
newline
hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.."
line.long 0x8 "CFG0_fault_attr_status_PROXY,"
hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID."
newline
hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID."
newline
hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID."
wgroup.long 0x3030++0x3
line.long 0x0 "CFG0_fault_clear_PROXY,"
bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
group.long 0x3100++0x3
line.long 0x0 "CFG0_CLAIMREG_P0_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0,Claim bits for Partition 0"
group.long 0x4084++0x17
line.long 0x0 "CFG0_DBOUNCE_CFG1,"
hexmask.long.byte 0x0 0.--5. 1. "DBOUNCE_CFG1_DB_CFG,Configures the debounce period used for I/Os with debounce_sel1 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
line.long 0x4 "CFG0_DBOUNCE_CFG2,"
hexmask.long.byte 0x4 0.--5. 1. "DBOUNCE_CFG2_DB_CFG,Configures the debounce period used for I/Os with debounce_sel2 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
line.long 0x8 "CFG0_DBOUNCE_CFG3,"
hexmask.long.byte 0x8 0.--5. 1. "DBOUNCE_CFG3_DB_CFG,Configures the debounce period used for I/Os with debounce_sel3 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
line.long 0xC "CFG0_DBOUNCE_CFG4,"
hexmask.long.byte 0xC 0.--5. 1. "DBOUNCE_CFG4_DB_CFG,Configures the debounce period used for I/Os with debounce_sel4 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
line.long 0x10 "CFG0_DBOUNCE_CFG5,"
hexmask.long.byte 0x10 0.--5. 1. "DBOUNCE_CFG5_DB_CFG,Configures the debounce period used for I/Os with debounce_sel5 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
line.long 0x14 "CFG0_DBOUNCE_CFG6,"
hexmask.long.byte 0x14 0.--5. 1. "DBOUNCE_CFG6_DB_CFG,Configures the debounce period used for I/Os with debounce_sel6 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
rgroup.long 0x40A0++0x3
line.long 0x0 "CFG0_TEMP_DIODE_TRIM,"
hexmask.long.word 0x0 0.--13. 1. "TEMP_DIODE_TRIM_TRIM,Sets the diode non-ideality factor (n)  starting from 100th place decimal and going down"
rgroup.long 0x40B0++0x3
line.long 0x0 "CFG0_IO_VOLTAGE_STAT,"
bitfld.long 0x0 17. "IO_VOLTAGE_STAT_MAIN_GPMC,Indicates the voltage for the GPMC I/O group (VDDSHV3)" "0,1"
newline
bitfld.long 0x0 13. "IO_VOLTAGE_STAT_MAIN_PRG1,Indicates the voltage for the PRG1 I/O group (VDDSHV1)" "0,1"
newline
bitfld.long 0x0 12. "IO_VOLTAGE_STAT_MAIN_PRG0,Indicates the voltage for the PRG0 I/O group (VDDSHV2)" "0,1"
newline
bitfld.long 0x0 10. "IO_VOLTAGE_STAT_MAIN_MMC1,Indicates the voltage for the MMC1 I/O group (VDDSHV5)" "0,1"
newline
bitfld.long 0x0 8. "IO_VOLTAGE_STAT_MAIN_GEN,Indicates the voltage for the General I/O group (VDDSHV0)" "0,1"
newline
bitfld.long 0x0 1. "IO_VOLTAGE_STAT_MCU_FLASH,Indicates the voltage for the Flash I/O group (VDDSHV4)" "0,1"
newline
bitfld.long 0x0 0. "IO_VOLTAGE_STAT_MCU_GEN,Indicates the voltage for the MCU General I/O group (VDDSHV0_MCU)" "0,1"
group.long 0x4204++0x3
line.long 0x0 "CFG0_MCU_TIMER1_CTRL,"
bitfld.long 0x0 8. "MCU_TIMER1_CTRL_CASCADE_EN,Actives cascading of TIMER1 to TIMER0" "0,1"
group.long 0x420C++0x3
line.long 0x0 "CFG0_MCU_TIMER3_CTRL,"
bitfld.long 0x0 8. "MCU_TIMER3_CTRL_CASCADE_EN,Actives cascading of TIMER3 to TIMER2" "0,1"
group.long 0x42E0++0x3
line.long 0x0 "CFG0_MCU_I2C0_CTRL,"
bitfld.long 0x0 0. "MCU_I2C0_CTRL_HS_MCS_EN,HS Mode controller current source active." "0,1"
group.long 0x4600++0x3
line.long 0x0 "CFG0_MCU_MTOG_CTRL,"
rbitfld.long 0x0 31. "MCU_MTOG_CTRL_IDLE_STAT,Idle Status:" "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "MCU_MTOG_CTRL_FORCE_TIMEOUT,Force Timout"
newline
bitfld.long 0x0 15. "MCU_MTOG_CTRL_TIMEOUT_EN,Timeout Active" "0,1"
newline
bitfld.long 0x0 0.--2. "MCU_MTOG_CTRL_TIMEOUT_VAL,Gasket Timeout Value" "0,1,2,3,4,5,6,7"
group.long 0x5008++0x7
line.long 0x0 "CFG0_LOCK1_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK1_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component"
rgroup.long 0x5100++0x33
line.long 0x0 "CFG0_CLAIMREG_P1_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0_READONLY,Claim bits for Partition 1"
line.long 0x4 "CFG0_CLAIMREG_P1_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1_READONLY,Claim bits for Partition 1"
line.long 0x8 "CFG0_CLAIMREG_P1_R2_READONLY,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2_READONLY,Claim bits for Partition 1"
line.long 0xC "CFG0_CLAIMREG_P1_R3_READONLY,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3_READONLY,Claim bits for Partition 1"
line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4_READONLY,Claim bits for Partition 1"
line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5_READONLY,Claim bits for Partition 1"
line.long 0x18 "CFG0_CLAIMREG_P1_R6_READONLY,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6_READONLY,Claim bits for Partition 1"
line.long 0x1C "CFG0_CLAIMREG_P1_R7_READONLY,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P1_R7_READONLY,Claim bits for Partition 1"
line.long 0x20 "CFG0_CLAIMREG_P1_R8_READONLY,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P1_R8_READONLY,Claim bits for Partition 1"
line.long 0x24 "CFG0_CLAIMREG_P1_R9_READONLY,"
hexmask.long 0x24 0.--31. 1. "CLAIMREG_P1_R9_READONLY,Claim bits for Partition 1"
line.long 0x28 "CFG0_CLAIMREG_P1_R10_READONLY,"
hexmask.long 0x28 0.--31. 1. "CLAIMREG_P1_R10_READONLY,Claim bits for Partition 1"
line.long 0x2C "CFG0_CLAIMREG_P1_R11_READONLY,"
hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P1_R11_READONLY,Claim bits for Partition 1"
line.long 0x30 "CFG0_CLAIMREG_P1_R12_READONLY,"
hexmask.long 0x30 0.--31. 1. "CLAIMREG_P1_R12_READONLY,Claim bits for Partition 1"
group.long 0x6084++0x17
line.long 0x0 "CFG0_DBOUNCE_CFG1_PROXY,"
hexmask.long.byte 0x0 0.--5. 1. "DBOUNCE_CFG1_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel1 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
line.long 0x4 "CFG0_DBOUNCE_CFG2_PROXY,"
hexmask.long.byte 0x4 0.--5. 1. "DBOUNCE_CFG2_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel2 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
line.long 0x8 "CFG0_DBOUNCE_CFG3_PROXY,"
hexmask.long.byte 0x8 0.--5. 1. "DBOUNCE_CFG3_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel3 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
line.long 0xC "CFG0_DBOUNCE_CFG4_PROXY,"
hexmask.long.byte 0xC 0.--5. 1. "DBOUNCE_CFG4_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel4 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
line.long 0x10 "CFG0_DBOUNCE_CFG5_PROXY,"
hexmask.long.byte 0x10 0.--5. 1. "DBOUNCE_CFG5_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel5 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
line.long 0x14 "CFG0_DBOUNCE_CFG6_PROXY,"
hexmask.long.byte 0x14 0.--5. 1. "DBOUNCE_CFG6_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel6 actived. See the AM64xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=736&filtertitle=2622&filteritem=13912)"
rgroup.long 0x60A0++0x3
line.long 0x0 "CFG0_TEMP_DIODE_TRIM_PROXY,"
hexmask.long.word 0x0 0.--13. 1. "TEMP_DIODE_TRIM_TRIM_PROXY,Sets the diode non-ideality factor (n)  starting from 100th place decimal and going down"
rgroup.long 0x60B0++0x3
line.long 0x0 "CFG0_IO_VOLTAGE_STAT_PROXY,"
bitfld.long 0x0 17. "IO_VOLTAGE_STAT_MAIN_GPMC_PROXY,Indicates the voltage for the GPMC I/O group (VDDSHV3)" "0,1"
newline
bitfld.long 0x0 13. "IO_VOLTAGE_STAT_MAIN_PRG1_PROXY,Indicates the voltage for the PRG1 I/O group (VDDSHV1)" "0,1"
newline
bitfld.long 0x0 12. "IO_VOLTAGE_STAT_MAIN_PRG0_PROXY,Indicates the voltage for the PRG0 I/O group (VDDSHV2)" "0,1"
newline
bitfld.long 0x0 10. "IO_VOLTAGE_STAT_MAIN_MMC1_PROXY,Indicates the voltage for the MMC1 I/O group (VDDSHV5)" "0,1"
newline
bitfld.long 0x0 8. "IO_VOLTAGE_STAT_MAIN_GEN_PROXY,Indicates the voltage for the General I/O group (VDDSHV0)" "0,1"
newline
bitfld.long 0x0 1. "IO_VOLTAGE_STAT_MCU_FLASH_PROXY,Indicates the voltage for the Flash I/O group (VDDSHV4)" "0,1"
newline
bitfld.long 0x0 0. "IO_VOLTAGE_STAT_MCU_GEN_PROXY,Indicates the voltage for the MCU General I/O group (VDDSHV0_MCU)" "0,1"
group.long 0x6204++0x3
line.long 0x0 "CFG0_MCU_TIMER1_CTRL_PROXY,"
bitfld.long 0x0 8. "MCU_TIMER1_CTRL_CASCADE_EN_PROXY,Actives cascading of TIMER1 to TIMER0" "0,1"
group.long 0x620C++0x3
line.long 0x0 "CFG0_MCU_TIMER3_CTRL_PROXY,"
bitfld.long 0x0 8. "MCU_TIMER3_CTRL_CASCADE_EN_PROXY,Actives cascading of TIMER3 to TIMER2" "0,1"
group.long 0x62E0++0x3
line.long 0x0 "CFG0_MCU_I2C0_CTRL_PROXY,"
bitfld.long 0x0 0. "MCU_I2C0_CTRL_HS_MCS_EN_PROXY,HS Mode controller current source active." "0,1"
group.long 0x6600++0x3
line.long 0x0 "CFG0_MCU_MTOG_CTRL_PROXY,"
rbitfld.long 0x0 31. "MCU_MTOG_CTRL_IDLE_STAT_PROXY,Idle Status:" "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "MCU_MTOG_CTRL_FORCE_TIMEOUT_PROXY,Force Timout"
newline
bitfld.long 0x0 15. "MCU_MTOG_CTRL_TIMEOUT_EN_PROXY,Timeout Active" "0,1"
newline
bitfld.long 0x0 0.--2. "MCU_MTOG_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout Value" "0,1,2,3,4,5,6,7"
group.long 0x7008++0x7
line.long 0x0 "CFG0_LOCK1_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK1_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component"
group.long 0x7100++0x33
line.long 0x0 "CFG0_CLAIMREG_P1_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0,Claim bits for Partition 1"
line.long 0x4 "CFG0_CLAIMREG_P1_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1,Claim bits for Partition 1"
line.long 0x8 "CFG0_CLAIMREG_P1_R2,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2,Claim bits for Partition 1"
line.long 0xC "CFG0_CLAIMREG_P1_R3,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3,Claim bits for Partition 1"
line.long 0x10 "CFG0_CLAIMREG_P1_R4,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4,Claim bits for Partition 1"
line.long 0x14 "CFG0_CLAIMREG_P1_R5,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5,Claim bits for Partition 1"
line.long 0x18 "CFG0_CLAIMREG_P1_R6,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6,Claim bits for Partition 1"
line.long 0x1C "CFG0_CLAIMREG_P1_R7,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P1_R7,Claim bits for Partition 1"
line.long 0x20 "CFG0_CLAIMREG_P1_R8,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P1_R8,Claim bits for Partition 1"
line.long 0x24 "CFG0_CLAIMREG_P1_R9,"
hexmask.long 0x24 0.--31. 1. "CLAIMREG_P1_R9,Claim bits for Partition 1"
line.long 0x28 "CFG0_CLAIMREG_P1_R10,"
hexmask.long 0x28 0.--31. 1. "CLAIMREG_P1_R10,Claim bits for Partition 1"
line.long 0x2C "CFG0_CLAIMREG_P1_R11,"
hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P1_R11,Claim bits for Partition 1"
line.long 0x30 "CFG0_CLAIMREG_P1_R12,"
hexmask.long 0x30 0.--31. 1. "CLAIMREG_P1_R12,Claim bits for Partition 1"
group.long 0x8000++0x3
line.long 0x0 "CFG0_MCU_OBSCLK_CTRL,"
bitfld.long 0x0 24. "MCU_OBSCLK_CTRL_OUT_MUX_SEL,MCU_OBSCLK pin output mux selection." "0,1"
newline
bitfld.long 0x0 16. "MCU_OBSCLK_CTRL_CLK_DIV_LD,Load the output divider value" "0,1"
newline
hexmask.long.byte 0x0 8.--11. 1. "MCU_OBSCLK_CTRL_CLK_DIV,MCU_OBSCLK pin clock selection output divider"
newline
bitfld.long 0x0 0.--2. "MCU_OBSCLK_CTRL_CLK_SEL,MCU_OBSCLK pin clock selection" "0,1,2,3,4,5,6,7"
group.long 0x8010++0x3
line.long 0x0 "CFG0_HFOSC0_CTRL,"
bitfld.long 0x0 4. "HFOSC0_CTRL_BP_C,Oscillator bypass control. When set oscillator is in bypass mode" "0,1"
group.long 0x8018++0x3
line.long 0x0 "CFG0_HFOSC0_TRIM,"
bitfld.long 0x0 31. "HFOSC0_TRIM_TRIM_EN,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1"
newline
bitfld.long 0x0 20.--21. "HFOSC0_TRIM_HYST,Sets comparator hysterisis" "0,1,2,3"
newline
bitfld.long 0x0 16.--18. "HFOSC0_TRIM_I_MULT,AGC AMP current multiplication gain" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--13. 1. "HFOSC0_TRIM_R_REF,Sets the AMP AGC bias current"
newline
hexmask.long.byte 0x0 4.--7. 1. "HFOSC0_TRIM_I_IBIAS_COMP,Sets the COMP bias current"
newline
hexmask.long.byte 0x0 0.--3. 1. "HFOSC0_TRIM_R_IBIAS_REF,Sets the base IBIAS reference"
group.long 0x8024++0x3
line.long 0x0 "CFG0_RC12M_OSC_TRIM,"
bitfld.long 0x0 6. "RC12M_OSC_TRIM_TRIMOSC_COARSE_DIR,Coarse adjustment direction. If output is greater than 12.5" "0,1"
newline
bitfld.long 0x0 3.--5. "RC12M_OSC_TRIM_TRIMOSC_COARSE,Coarse adjustment. Frequency is decreased or increased by 1.25 MHz per value based on the trimosc_coarse_dir value." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "RC12M_OSC_TRIM_TRIMOSC_FINE,Fine adjustment. Decreases the frequency by 250 KHz per value." "0,1,2,3,4,5,6,7"
group.long 0x8030++0x3
line.long 0x0 "CFG0_HFOSC0_CLKOUT_32K_CTRL,"
bitfld.long 0x0 31. "HFOSC0_CLKOUT_32K_CTRL_RESET,Asynchronous Divider Reset" "0,1"
newline
bitfld.long 0x0 15. "HFOSC0_CLKOUT_32K_CTRL_CLKOUT_EN,HFOSC0_CLKOUT_32K active:" "0,1"
newline
bitfld.long 0x0 8. "HFOSC0_CLKOUT_32K_CTRL_SYNC_DIS,HFOSC0_CLKOUT_32K Synchronize Deactivate" "0,1"
newline
hexmask.long.byte 0x0 0.--6. 1. "HFOSC0_CLKOUT_32K_CTRL_HSDIV,HFOSC0_CLKOUT_32K divider:"
group.long 0x8040++0x7
line.long 0x0 "CFG0_MCU_M4FSS_CLKSEL,"
bitfld.long 0x0 0. "MCU_M4FSS_CLKSEL_M4FSS_CLKSEL,Selects the Clock Divider for M4FSS" "0,1"
line.long 0x4 "CFG0_MCU_M4FSS_SYSTICK,"
rbitfld.long 0x4 25. "MCU_M4FSS_SYSTICK_NOREF,No External Reference Clock for SysTick is available" "0,1"
newline
bitfld.long 0x4 24. "MCU_M4FSS_SYSTICK_SKEW,Indicates whether or not the M4FSS free running clock divided by TENMS produces a 100Hz tick exactly" "0,1"
newline
hexmask.long.tbyte 0x4 0.--23. 1. "MCU_M4FSS_SYSTICK_TENMS,Integer Divider Value that produces a 100Hz SysTick from the M4FSS Clock Frequency. Default is 3 999 999 (4M - 1) to produce a 100Hz clock from a 400 MHz M4FSS Clock."
group.long 0x8050++0x3
line.long 0x0 "CFG0_MCU_PLL_CLKSEL,"
bitfld.long 0x0 31. "MCU_PLL_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
newline
bitfld.long 0x0 23. "MCU_PLL_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset." "0,1"
newline
bitfld.long 0x0 8. "MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN,When set  actives automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected" "0,1"
group.long 0x8060++0xF
line.long 0x0 "CFG0_MCU_TIMER0_CLKSEL,"
bitfld.long 0x0 0.--2. "MCU_TIMER0_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
line.long 0x4 "CFG0_MCU_TIMER1_CLKSEL,"
bitfld.long 0x4 0.--2. "MCU_TIMER1_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
line.long 0x8 "CFG0_MCU_TIMER2_CLKSEL,"
bitfld.long 0x8 0.--2. "MCU_TIMER2_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
line.long 0xC "CFG0_MCU_TIMER3_CLKSEL,"
bitfld.long 0xC 0.--2. "MCU_TIMER3_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
group.long 0x80A0++0x7
line.long 0x0 "CFG0_MCU_SPI0_CLKSEL,"
bitfld.long 0x0 16. "MCU_SPI0_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "0,1"
line.long 0x4 "CFG0_MCU_SPI1_CLKSEL,"
bitfld.long 0x4 16. "MCU_SPI1_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "0,1"
group.long 0x80B0++0x3
line.long 0x0 "CFG0_MCU_WWD0_CLKSEL,"
bitfld.long 0x0 31. "MCU_WWD0_CLKSEL_WRTLOCK,When set  locks WWD0_CLKSEL from further writes until the next module reset." "0,1"
newline
bitfld.long 0x0 0.--1. "MCU_WWD0_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
group.long 0x80D0++0x3
line.long 0x0 "CFG0_DDR16SS_PMCTRL,"
hexmask.long.byte 0x0 0.--3. 1. "DDR16SS_PMCTRL_DATA_RETENTION,DDR16SS Retention:"
group.long 0x9008++0x7
line.long 0x0 "CFG0_LOCK2_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK2_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1,- KICK1 component"
rgroup.long 0x9100++0x7
line.long 0x0 "CFG0_CLAIMREG_P2_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0_READONLY,Claim bits for Partition 2"
line.long 0x4 "CFG0_CLAIMREG_P2_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1_READONLY,Claim bits for Partition 2"
group.long 0xA000++0x3
line.long 0x0 "CFG0_MCU_OBSCLK_CTRL_PROXY,"
bitfld.long 0x0 24. "MCU_OBSCLK_CTRL_OUT_MUX_SEL_PROXY,MCU_OBSCLK pin output mux selection." "0,1"
newline
bitfld.long 0x0 16. "MCU_OBSCLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value" "0,1"
newline
hexmask.long.byte 0x0 8.--11. 1. "MCU_OBSCLK_CTRL_CLK_DIV_PROXY,MCU_OBSCLK pin clock selection output divider"
newline
bitfld.long 0x0 0.--2. "MCU_OBSCLK_CTRL_CLK_SEL_PROXY,MCU_OBSCLK pin clock selection" "0,1,2,3,4,5,6,7"
group.long 0xA010++0x3
line.long 0x0 "CFG0_HFOSC0_CTRL_PROXY,"
bitfld.long 0x0 4. "HFOSC0_CTRL_BP_C_PROXY,Oscillator bypass control. When set oscillator is in bypass mode" "0,1"
group.long 0xA018++0x3
line.long 0x0 "CFG0_HFOSC0_TRIM_PROXY,"
bitfld.long 0x0 31. "HFOSC0_TRIM_TRIM_EN_PROXY,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1"
newline
bitfld.long 0x0 20.--21. "HFOSC0_TRIM_HYST_PROXY,Sets comparator hysterisis" "0,1,2,3"
newline
bitfld.long 0x0 16.--18. "HFOSC0_TRIM_I_MULT_PROXY,AGC AMP current multiplication gain" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--13. 1. "HFOSC0_TRIM_R_REF_PROXY,Sets the AMP AGC bias current"
newline
hexmask.long.byte 0x0 4.--7. 1. "HFOSC0_TRIM_I_IBIAS_COMP_PROXY,Sets the COMP bias current"
newline
hexmask.long.byte 0x0 0.--3. 1. "HFOSC0_TRIM_R_IBIAS_REF_PROXY,Sets the base IBIAS reference"
group.long 0xA024++0x3
line.long 0x0 "CFG0_RC12M_OSC_TRIM_PROXY,"
bitfld.long 0x0 6. "RC12M_OSC_TRIM_TRIMOSC_COARSE_DIR_PROXY,Coarse adjustment direction. If output is greater than 12.5" "0,1"
newline
bitfld.long 0x0 3.--5. "RC12M_OSC_TRIM_TRIMOSC_COARSE_PROXY,Coarse adjustment. Frequency is decreased or increased by 1.25 MHz per value based on the trimosc_coarse_dir value." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "RC12M_OSC_TRIM_TRIMOSC_FINE_PROXY,Fine adjustment. Decreases the frequency by 250 KHz per value." "0,1,2,3,4,5,6,7"
group.long 0xA030++0x3
line.long 0x0 "CFG0_HFOSC0_CLKOUT_32K_CTRL_PROXY,"
bitfld.long 0x0 31. "HFOSC0_CLKOUT_32K_CTRL_RESET_PROXY,Asynchronous Divider Reset" "0,1"
newline
bitfld.long 0x0 15. "HFOSC0_CLKOUT_32K_CTRL_CLKOUT_EN_PROXY,HFOSC0_CLKOUT_32K active:" "0,1"
newline
bitfld.long 0x0 8. "HFOSC0_CLKOUT_32K_CTRL_SYNC_DIS_PROXY,HFOSC0_CLKOUT_32K Synchronize Deactivate" "0,1"
newline
hexmask.long.byte 0x0 0.--6. 1. "HFOSC0_CLKOUT_32K_CTRL_HSDIV_PROXY,HFOSC0_CLKOUT_32K divider:"
group.long 0xA040++0x7
line.long 0x0 "CFG0_MCU_M4FSS_CLKSEL_PROXY,"
bitfld.long 0x0 0. "MCU_M4FSS_CLKSEL_M4FSS_CLKSEL_PROXY,Selects the Clock Divider for M4FSS" "0,1"
line.long 0x4 "CFG0_MCU_M4FSS_SYSTICK_PROXY,"
rbitfld.long 0x4 25. "MCU_M4FSS_SYSTICK_NOREF_PROXY,No External Reference Clock for SysTick is available" "0,1"
newline
bitfld.long 0x4 24. "MCU_M4FSS_SYSTICK_SKEW_PROXY,Indicates whether or not the M4FSS free running clock divided by TENMS produces a 100Hz tick exactly" "0,1"
newline
hexmask.long.tbyte 0x4 0.--23. 1. "MCU_M4FSS_SYSTICK_TENMS_PROXY,Integer Divider Value that produces a 100Hz SysTick from the M4FSS Clock Frequency. Default is 3 999 999 (4M - 1) to produce a 100Hz clock from a 400 MHz M4FSS Clock."
group.long 0xA050++0x3
line.long 0x0 "CFG0_MCU_PLL_CLKSEL_PROXY,"
bitfld.long 0x0 31. "MCU_PLL_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override" "0,1"
newline
bitfld.long 0x0 23. "MCU_PLL_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset." "0,1"
newline
bitfld.long 0x0 8. "MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN_PROXY,When set  actives automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected" "0,1"
group.long 0xA060++0xF
line.long 0x0 "CFG0_MCU_TIMER0_CLKSEL_PROXY,"
bitfld.long 0x0 0.--2. "MCU_TIMER0_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
line.long 0x4 "CFG0_MCU_TIMER1_CLKSEL_PROXY,"
bitfld.long 0x4 0.--2. "MCU_TIMER1_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
line.long 0x8 "CFG0_MCU_TIMER2_CLKSEL_PROXY,"
bitfld.long 0x8 0.--2. "MCU_TIMER2_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
line.long 0xC "CFG0_MCU_TIMER3_CLKSEL_PROXY,"
bitfld.long 0xC 0.--2. "MCU_TIMER3_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
group.long 0xA0A0++0x7
line.long 0x0 "CFG0_MCU_SPI0_CLKSEL_PROXY,"
bitfld.long 0x0 16. "MCU_SPI0_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "0,1"
line.long 0x4 "CFG0_MCU_SPI1_CLKSEL_PROXY,"
bitfld.long 0x4 16. "MCU_SPI1_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "0,1"
group.long 0xA0B0++0x3
line.long 0x0 "CFG0_MCU_WWD0_CLKSEL_PROXY,"
bitfld.long 0x0 31. "MCU_WWD0_CLKSEL_WRTLOCK_PROXY,When set  locks WWD0_CLKSEL from further writes until the next module reset." "0,1"
newline
bitfld.long 0x0 0.--1. "MCU_WWD0_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control" "0,1,2,3"
group.long 0xA0D0++0x3
line.long 0x0 "CFG0_DDR16SS_PMCTRL_PROXY,"
hexmask.long.byte 0x0 0.--3. 1. "DDR16SS_PMCTRL_DATA_RETENTION_PROXY,DDR16SS Retention:"
group.long 0xB008++0x7
line.long 0x0 "CFG0_LOCK2_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK2_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1_PROXY,- KICK1 component"
group.long 0xB100++0x7
line.long 0x0 "CFG0_CLAIMREG_P2_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0,Claim bits for Partition 2"
line.long 0x4 "CFG0_CLAIMREG_P2_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1,Claim bits for Partition 2"
group.long 0xC020++0x1B
line.long 0x0 "CFG0_MCU_M4FSS0_LBIST_CTRL,"
bitfld.long 0x0 31. "MCU_M4FSS0_LBIST_CTRL_BIST_RESET,This bitfield is not used. The bist_reset control for DMSC is generated by the POST state machine. The bitfield still reflects the efuse value." "0,1"
newline
hexmask.long.byte 0x0 24.--27. 1. "MCU_M4FSS0_LBIST_CTRL_BIST_RUN,This bitfield is not used. The bist_run control for DMSC is generated by the POST state machine. The bitfield still reflects the efuse value."
newline
hexmask.long.byte 0x0 16.--20. 1. "MCU_M4FSS0_LBIST_CTRL_SUBCHIP_ID,Specifies which sub-chip is to be tested"
newline
hexmask.long.byte 0x0 12.--15. 1. "MCU_M4FSS0_LBIST_CTRL_RUNBIST_MODE,Runbist mode active if all bits are 1"
newline
bitfld.long 0x0 8.--9. "MCU_M4FSS0_LBIST_CTRL_DC_DEF,Clock delay after scan_active switching" "0,1,2,3"
newline
bitfld.long 0x0 7. "MCU_M4FSS0_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "MCU_M4FSS0_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio"
line.long 0x4 "CFG0_MCU_M4FSS0_LBIST_PATCOUNT,"
hexmask.long.word 0x4 16.--29. 1. "MCU_M4FSS0_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run"
newline
hexmask.long.byte 0x4 8.--11. 1. "MCU_M4FSS0_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run"
newline
hexmask.long.byte 0x4 4.--7. 1. "MCU_M4FSS0_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run"
newline
hexmask.long.byte 0x4 0.--3. 1. "MCU_M4FSS0_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run"
line.long 0x8 "CFG0_MCU_M4FSS0_LBIST_SEED0,"
hexmask.long 0x8 0.--31. 1. "MCU_M4FSS0_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)"
line.long 0xC "CFG0_MCU_M4FSS0_LBIST_SEED1,"
hexmask.long.tbyte 0xC 0.--20. 1. "MCU_M4FSS0_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)"
line.long 0x10 "CFG0_MCU_M4FSS0_LBIST_SPARE0,"
hexmask.long 0x10 2.--31. 1. "MCU_M4FSS0_LBIST_SPARE0_SPARE0,LBIST spare bits"
newline
bitfld.long 0x10 1. "MCU_M4FSS0_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1"
newline
bitfld.long 0x10 0. "MCU_M4FSS0_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1"
line.long 0x14 "CFG0_MCU_M4FSS0_LBIST_SPARE1,"
hexmask.long 0x14 0.--31. 1. "MCU_M4FSS0_LBIST_SPARE1_SPARE1,LBIST spare bits"
line.long 0x18 "CFG0_MCU_M4FSS0_LBIST_STAT,"
rbitfld.long 0x18 31. "MCU_M4FSS0_LBIST_STAT_BIST_DONE,LBIST is done" "0,1"
newline
rbitfld.long 0x18 15. "MCU_M4FSS0_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1"
newline
bitfld.long 0x18 8.--9. "MCU_M4FSS0_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3"
newline
hexmask.long.byte 0x18 0.--7. 1. "MCU_M4FSS0_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR."
rgroup.long 0xC03C++0x3
line.long 0x0 "CFG0_MCU_M4FSS0_LBIST_MISR,"
hexmask.long 0x0 0.--31. 1. "MCU_M4FSS0_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl"
group.long 0xD008++0x7
line.long 0x0 "CFG0_LOCK3_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK3_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1,- KICK1 component"
rgroup.long 0xD100++0x3
line.long 0x0 "CFG0_CLAIMREG_P3_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0_READONLY,Claim bits for Partition 3"
group.long 0xE020++0x1B
line.long 0x0 "CFG0_MCU_M4FSS0_LBIST_CTRL_PROXY,"
bitfld.long 0x0 31. "MCU_M4FSS0_LBIST_CTRL_BIST_RESET_PROXY,This bitfield is not used. The bist_reset control for DMSC is generated by the POST state machine. The bitfield still reflects the efuse value." "0,1"
newline
hexmask.long.byte 0x0 24.--27. 1. "MCU_M4FSS0_LBIST_CTRL_BIST_RUN_PROXY,This bitfield is not used. The bist_run control for DMSC is generated by the POST state machine. The bitfield still reflects the efuse value."
newline
hexmask.long.byte 0x0 16.--20. 1. "MCU_M4FSS0_LBIST_CTRL_SUBCHIP_ID_PROXY,Specifies which sub-chip is to be tested"
newline
hexmask.long.byte 0x0 12.--15. 1. "MCU_M4FSS0_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode active if all bits are 1"
newline
bitfld.long 0x0 8.--9. "MCU_M4FSS0_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_active switching" "0,1,2,3"
newline
bitfld.long 0x0 7. "MCU_M4FSS0_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "MCU_M4FSS0_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio"
line.long 0x4 "CFG0_MCU_M4FSS0_LBIST_PATCOUNT_PROXY,"
hexmask.long.word 0x4 16.--29. 1. "MCU_M4FSS0_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run"
newline
hexmask.long.byte 0x4 8.--11. 1. "MCU_M4FSS0_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run"
newline
hexmask.long.byte 0x4 4.--7. 1. "MCU_M4FSS0_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run"
newline
hexmask.long.byte 0x4 0.--3. 1. "MCU_M4FSS0_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run"
line.long 0x8 "CFG0_MCU_M4FSS0_LBIST_SEED0_PROXY,"
hexmask.long 0x8 0.--31. 1. "MCU_M4FSS0_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)"
line.long 0xC "CFG0_MCU_M4FSS0_LBIST_SEED1_PROXY,"
hexmask.long.tbyte 0xC 0.--20. 1. "MCU_M4FSS0_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)"
line.long 0x10 "CFG0_MCU_M4FSS0_LBIST_SPARE0_PROXY,"
hexmask.long 0x10 2.--31. 1. "MCU_M4FSS0_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits"
newline
bitfld.long 0x10 1. "MCU_M4FSS0_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1"
newline
bitfld.long 0x10 0. "MCU_M4FSS0_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1"
line.long 0x14 "CFG0_MCU_M4FSS0_LBIST_SPARE1_PROXY,"
hexmask.long 0x14 0.--31. 1. "MCU_M4FSS0_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits"
line.long 0x18 "CFG0_MCU_M4FSS0_LBIST_STAT_PROXY,"
rbitfld.long 0x18 31. "MCU_M4FSS0_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1"
newline
rbitfld.long 0x18 15. "MCU_M4FSS0_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1"
newline
bitfld.long 0x18 8.--9. "MCU_M4FSS0_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output" "0,1,2,3"
newline
hexmask.long.byte 0x18 0.--7. 1. "MCU_M4FSS0_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR."
rgroup.long 0xE03C++0x3
line.long 0x0 "CFG0_MCU_M4FSS0_LBIST_MISR_PROXY,"
hexmask.long 0x0 0.--31. 1. "MCU_M4FSS0_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl"
group.long 0xF008++0x7
line.long 0x0 "CFG0_LOCK3_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK3_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1_PROXY,- KICK1 component"
group.long 0xF100++0x3
line.long 0x0 "CFG0_CLAIMREG_P3_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0,Claim bits for Partition 3"
group.long 0x11008++0x7
line.long 0x0 "CFG0_LOCK4_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK4_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1,- KICK1 component"
rgroup.long 0x11100++0x3B
line.long 0x0 "CFG0_CLAIMREG_P4_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0_READONLY,Claim bits for Partition 4"
line.long 0x4 "CFG0_CLAIMREG_P4_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1_READONLY,Claim bits for Partition 4"
line.long 0x8 "CFG0_CLAIMREG_P4_R2_READONLY,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2_READONLY,Claim bits for Partition 4"
line.long 0xC "CFG0_CLAIMREG_P4_R3_READONLY,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3_READONLY,Claim bits for Partition 4"
line.long 0x10 "CFG0_CLAIMREG_P4_R4_READONLY,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4_READONLY,Claim bits for Partition 4"
line.long 0x14 "CFG0_CLAIMREG_P4_R5_READONLY,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5_READONLY,Claim bits for Partition 4"
line.long 0x18 "CFG0_CLAIMREG_P4_R6_READONLY,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6_READONLY,Claim bits for Partition 4"
line.long 0x1C "CFG0_CLAIMREG_P4_R7_READONLY,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7_READONLY,Claim bits for Partition 4"
line.long 0x20 "CFG0_CLAIMREG_P4_R8_READONLY,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8_READONLY,Claim bits for Partition 4"
line.long 0x24 "CFG0_CLAIMREG_P4_R9_READONLY,"
hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9_READONLY,Claim bits for Partition 4"
line.long 0x28 "CFG0_CLAIMREG_P4_R10_READONLY,"
hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10_READONLY,Claim bits for Partition 4"
line.long 0x2C "CFG0_CLAIMREG_P4_R11_READONLY,"
hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P4_R11_READONLY,Claim bits for Partition 4"
line.long 0x30 "CFG0_CLAIMREG_P4_R12_READONLY,"
hexmask.long 0x30 0.--31. 1. "CLAIMREG_P4_R12_READONLY,Claim bits for Partition 4"
line.long 0x34 "CFG0_CLAIMREG_P4_R13_READONLY,"
hexmask.long 0x34 0.--31. 1. "CLAIMREG_P4_R13_READONLY,Claim bits for Partition 4"
line.long 0x38 "CFG0_CLAIMREG_P4_R14_READONLY,"
hexmask.long 0x38 0.--31. 1. "CLAIMREG_P4_R14_READONLY,Claim bits for Partition 4"
group.long 0x13008++0x7
line.long 0x0 "CFG0_LOCK4_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK4_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1_PROXY,- KICK1 component"
group.long 0x13100++0x3B
line.long 0x0 "CFG0_CLAIMREG_P4_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0,Claim bits for Partition 4"
line.long 0x4 "CFG0_CLAIMREG_P4_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1,Claim bits for Partition 4"
line.long 0x8 "CFG0_CLAIMREG_P4_R2,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2,Claim bits for Partition 4"
line.long 0xC "CFG0_CLAIMREG_P4_R3,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3,Claim bits for Partition 4"
line.long 0x10 "CFG0_CLAIMREG_P4_R4,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4,Claim bits for Partition 4"
line.long 0x14 "CFG0_CLAIMREG_P4_R5,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5,Claim bits for Partition 4"
line.long 0x18 "CFG0_CLAIMREG_P4_R6,"
hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6,Claim bits for Partition 4"
line.long 0x1C "CFG0_CLAIMREG_P4_R7,"
hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7,Claim bits for Partition 4"
line.long 0x20 "CFG0_CLAIMREG_P4_R8,"
hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8,Claim bits for Partition 4"
line.long 0x24 "CFG0_CLAIMREG_P4_R9,"
hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9,Claim bits for Partition 4"
line.long 0x28 "CFG0_CLAIMREG_P4_R10,"
hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10,Claim bits for Partition 4"
line.long 0x2C "CFG0_CLAIMREG_P4_R11,"
hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P4_R11,Claim bits for Partition 4"
line.long 0x30 "CFG0_CLAIMREG_P4_R12,"
hexmask.long 0x30 0.--31. 1. "CLAIMREG_P4_R12,Claim bits for Partition 4"
line.long 0x34 "CFG0_CLAIMREG_P4_R13,"
hexmask.long 0x34 0.--31. 1. "CLAIMREG_P4_R13,Claim bits for Partition 4"
line.long 0x38 "CFG0_CLAIMREG_P4_R14,"
hexmask.long 0x38 0.--31. 1. "CLAIMREG_P4_R14,Claim bits for Partition 4"
group.long 0x18000++0x3
line.long 0x0 "CFG0_POR_CTRL,"
bitfld.long 0x0 29. "POR_CTRL_OVRD_SET5,Reserved override set" "0,1"
newline
bitfld.long 0x0 28. "POR_CTRL_OVRD_SET4,POKLVB override set" "0,1"
newline
bitfld.long 0x0 27. "POR_CTRL_OVRD_SET3,POKLVA override set" "0,1"
newline
bitfld.long 0x0 26. "POR_CTRL_OVRD_SET2,POKHV override set" "0,1"
newline
bitfld.long 0x0 25. "POR_CTRL_OVRD_SET1,BGOK override set" "0,1"
newline
bitfld.long 0x0 24. "POR_CTRL_OVRD_SET0,PORHV override set" "0,1"
newline
bitfld.long 0x0 21. "POR_CTRL_OVRD5,Reserved override active" "0,1"
newline
bitfld.long 0x0 20. "POR_CTRL_OVRD4,POKLVB override active" "0,1"
newline
bitfld.long 0x0 19. "POR_CTRL_OVRD3,POKLVA override active" "0,1"
newline
bitfld.long 0x0 18. "POR_CTRL_OVRD2,POKHV override active" "0,1"
newline
bitfld.long 0x0 17. "POR_CTRL_OVRD1,BGOK override active" "0,1"
newline
bitfld.long 0x0 16. "POR_CTRL_OVRD0,PORHV override active" "0,1"
newline
bitfld.long 0x0 7. "POR_CTRL_TRIM_SEL,POR Trim Select" "0,1"
newline
bitfld.long 0x0 4. "POR_CTRL_MASK_HHV,Mask HHV/SOC_PORz outputs when applying new trim values" "0,1"
rgroup.long 0x18004++0x3
line.long 0x0 "CFG0_POR_STAT,"
bitfld.long 0x0 8. "POR_STAT_BGOK,Bandgap OK status" "0,1"
newline
bitfld.long 0x0 4. "POR_STAT_SOC_POR,POR module status" "0,1"
group.long 0x18100++0x3
line.long 0x0 "CFG0_POR_BANDGAP_CTRL,"
hexmask.long.byte 0x0 16.--19. 1. "POR_BANDGAP_CTRL_BGAPI,Bandgap output current trim bits"
newline
hexmask.long.byte 0x0 8.--15. 1. "POR_BANDGAP_CTRL_BGAPV,Bandgap output voltage magnitude trim bits"
newline
hexmask.long.byte 0x0 0.--7. 1. "POR_BANDGAP_CTRL_BGAPC,Bandgap slope trim bits. Bit7 is used to calculate the offset"
group.long 0x18110++0x47
line.long 0x0 "CFG0_POK_VDDA_MCU_UV_CTRL,"
bitfld.long 0x0 31. "POK_VDDA_MCU_UV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x0 7. "POK_VDDA_MCU_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x0 0.--6. 1. "POK_VDDA_MCU_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x4 "CFG0_POK_VDDA_MCU_OV_CTRL,"
bitfld.long 0x4 31. "POK_VDDA_MCU_OV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x4 7. "POK_VDDA_MCU_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x4 0.--6. 1. "POK_VDDA_MCU_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x8 "CFG0_POK_VDD_CORE_UV_CTRL,"
bitfld.long 0x8 31. "POK_VDD_CORE_UV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x8 7. "POK_VDD_CORE_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x8 0.--6. 1. "POK_VDD_CORE_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0xC "CFG0_POK_VDD_CORE_OV_CTRL,"
bitfld.long 0xC 31. "POK_VDD_CORE_OV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0xC 7. "POK_VDD_CORE_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0xC 0.--6. 1. "POK_VDD_CORE_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x10 "CFG0_POK_VDDR_CORE_UV_CTRL,"
bitfld.long 0x10 31. "POK_VDDR_CORE_UV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x10 7. "POK_VDDR_CORE_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x10 0.--6. 1. "POK_VDDR_CORE_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x14 "CFG0_POK_VDDR_CORE_OV_CTRL,"
bitfld.long 0x14 31. "POK_VDDR_CORE_OV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x14 7. "POK_VDDR_CORE_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x14 0.--6. 1. "POK_VDDR_CORE_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x18 "CFG0_POK_VDDSHV_MCU_1P8_UV_CTRL,"
bitfld.long 0x18 31. "POK_VDDSHV_MCU_1P8_UV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x18 7. "POK_VDDSHV_MCU_1P8_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x18 0.--6. 1. "POK_VDDSHV_MCU_1P8_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x1C "CFG0_POK_VDDSHV_MCU_1P8_OV_CTRL,"
bitfld.long 0x1C 31. "POK_VDDSHV_MCU_1P8_OV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x1C 7. "POK_VDDSHV_MCU_1P8_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x1C 0.--6. 1. "POK_VDDSHV_MCU_1P8_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x20 "CFG0_POK_VDDSHV_MCU_3P3_UV_CTRL,"
bitfld.long 0x20 31. "POK_VDDSHV_MCU_3P3_UV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x20 7. "POK_VDDSHV_MCU_3P3_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x20 0.--6. 1. "POK_VDDSHV_MCU_3P3_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x24 "CFG0_POK_VDDSHV_MCU_3P3_OV_CTRL,"
bitfld.long 0x24 31. "POK_VDDSHV_MCU_3P3_OV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x24 7. "POK_VDDSHV_MCU_3P3_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x24 0.--6. 1. "POK_VDDSHV_MCU_3P3_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x28 "CFG0_POK_VMON_CAP_MCU_GENERAL_UV_CTRL,"
bitfld.long 0x28 31. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x28 7. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x28 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x2C "CFG0_POK_VMON_CAP_MCU_GENERAL_OV_CTRL,"
bitfld.long 0x2C 31. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x2C 7. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x2C 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x30 "CFG0_POK_VDDSHV_MAIN_1P8_UV_CTRL,"
bitfld.long 0x30 31. "POK_VDDSHV_MAIN_1P8_UV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x30 7. "POK_VDDSHV_MAIN_1P8_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x30 0.--6. 1. "POK_VDDSHV_MAIN_1P8_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x34 "CFG0_POK_VDDSHV_MAIN_1P8_OV_CTRL,"
bitfld.long 0x34 31. "POK_VDDSHV_MAIN_1P8_OV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x34 7. "POK_VDDSHV_MAIN_1P8_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x34 0.--6. 1. "POK_VDDSHV_MAIN_1P8_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x38 "CFG0_POK_VDDSHV_MAIN_3P3_UV_CTRL,"
bitfld.long 0x38 31. "POK_VDDSHV_MAIN_3P3_UV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x38 7. "POK_VDDSHV_MAIN_3P3_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x38 0.--6. 1. "POK_VDDSHV_MAIN_3P3_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x3C "CFG0_POK_VDDSHV_MAIN_3P3_OV_CTRL,"
bitfld.long 0x3C 31. "POK_VDDSHV_MAIN_3P3_OV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x3C 7. "POK_VDDSHV_MAIN_3P3_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x3C 0.--6. 1. "POK_VDDSHV_MAIN_3P3_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x40 "CFG0_POK_VDDS_DDRIO_UV_CTRL,"
bitfld.long 0x40 31. "POK_VDDS_DDRIO_UV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x40 7. "POK_VDDS_DDRIO_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x40 0.--6. 1. "POK_VDDS_DDRIO_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x44 "CFG0_POK_VDDS_DDRIO_OV_CTRL,"
bitfld.long 0x44 31. "POK_VDDS_DDRIO_OV_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x44 7. "POK_VDDS_DDRIO_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x44 0.--6. 1. "POK_VDDS_DDRIO_OV_CTRL_POK_TRIM,POK Trim Bits"
group.long 0x18160++0x3
line.long 0x0 "CFG0_POK_VDDA_PMIC_IN_CTRL,"
bitfld.long 0x0 31. "POK_VDDA_PMIC_IN_CTRL_HYST_EN,Active POK hysteresis" "0,1"
newline
bitfld.long 0x0 15. "POK_VDDA_PMIC_IN_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
group.long 0x18170++0x3
line.long 0x0 "CFG0_RST_CTRL,"
bitfld.long 0x0 18. "RST_CTRL_MCU_RESET_ISO_DONE_Z,MCU can set this bit to block warm reset in the main domain which is useful when the MCU may be accessing" "0,1"
newline
bitfld.long 0x0 17. "RST_CTRL_MCU_ESM_ERROR_RST_EN_Z,Deactivate Reset of MCU by ESM" "0,1"
newline
bitfld.long 0x0 16. "RST_CTRL_DMSC_COLD_RESET_EN_Z,Deactivate Reset of MCU by DMSC" "0,1"
newline
hexmask.long.byte 0x0 8.--11. 1. "RST_CTRL_SW_MCU_WARMRST,This is a fault tolerant bitfield."
newline
hexmask.long.byte 0x0 4.--7. 1. "RST_CTRL_SW_MAIN_POR,This is a fault tolerant bitfield."
newline
hexmask.long.byte 0x0 0.--3. 1. "RST_CTRL_SW_MAIN_WARMRST,This is a fault tolerant bitfield."
rgroup.long 0x18174++0x3
line.long 0x0 "CFG0_RST_STAT,"
bitfld.long 0x0 0. "RST_STAT_MAIN_RESETSTATZ,Status of Main Domain Reset:" "0,1"
group.long 0x18178++0xB
line.long 0x0 "CFG0_RST_SRC,"
bitfld.long 0x0 31. "RST_SRC_SAFETY_ERROR,Reset Caused by MCU ESM Error" "0,1"
newline
bitfld.long 0x0 30. "RST_SRC_MAIN_ESM_ERROR,Reset Caused by Main ESM Error" "0,1"
newline
bitfld.long 0x0 25. "RST_SRC_SW_MAIN_POR_FROM_MAIN,Software Main Power On Reset From MAIN CTRL MMR" "0,1"
newline
bitfld.long 0x0 24. "RST_SRC_SW_MAIN_POR_FROM_MCU,Software Main Power On Reset From MCU CTRL MMR" "0,1"
newline
bitfld.long 0x0 21. "RST_SRC_SW_MAIN_WARMRST_FROM_MAIN,Software Main Warm Reset from MAIN CTRL MMR" "0,1"
newline
bitfld.long 0x0 20. "RST_SRC_SW_MAIN_WARMRST_FROM_MCU,Software Main Warm Reset From MCU CTRL MMR" "0,1"
newline
bitfld.long 0x0 16. "RST_SRC_SW_MCU_WARMRST,Software Warm Reset" "0,1"
newline
bitfld.long 0x0 13. "RST_SRC_WARM_OUT_RST,DMSC Warm Reset" "0,1"
newline
bitfld.long 0x0 12. "RST_SRC_COLD_OUT_RST,DMSC Cold Reset" "0,1"
newline
bitfld.long 0x0 8. "RST_SRC_DEBUG_RST,Debug Subsystem Initiated Reset" "0,1"
newline
bitfld.long 0x0 4. "RST_SRC_THERMAL_RST,Thermal Reset" "0,1"
newline
bitfld.long 0x0 2. "RST_SRC_MAIN_RESET_REQ,Main Reset Pin" "0,1"
newline
bitfld.long 0x0 0. "RST_SRC_MCU_RESET_PIN,Rest Caused by MCU Reset Pin" "0,1"
line.long 0x4 "CFG0_RST_MAGIC_WORD,"
hexmask.long 0x4 0.--31. 1. "RST_MAGIC_WORD_MCU_MAGIC_WORD,After a MCU_PORz reset this bit field resets to 0x00000000."
line.long 0x8 "CFG0_ISO_CTRL,"
bitfld.long 0x8 1. "ISO_CTRL_MCU_DBG_ISO_EN,Isolates the MCU domain from Debug" "0,1"
newline
bitfld.long 0x8 0. "ISO_CTRL_MCU_RST_ISO_EN,Isolates the MCU domain from Warm Reset initiated by Main" "0,1"
group.long 0x18190++0x3
line.long 0x0 "CFG0_VDD_CORE_GLDTC_CTRL,"
bitfld.long 0x0 31. "VDD_CORE_GLDTC_CTRL_PWDB,Power down - active low." "0,1"
newline
bitfld.long 0x0 30. "VDD_CORE_GLDTC_CTRL_RSTB,Reset - active low. To ensure proper operation  rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally  rstb must be toggled low at least 200 ns after any change in threshold or.." "0,1"
newline
bitfld.long 0x0 16.--18. "VDD_CORE_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--13. 1. "VDD_CORE_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage"
newline
hexmask.long.byte 0x0 0.--5. 1. "VDD_CORE_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage"
rgroup.long 0x181B0++0x3
line.long 0x0 "CFG0_VDD_CORE_GLDTC_STAT,"
bitfld.long 0x0 8. "VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit." "0,1"
newline
bitfld.long 0x0 0. "VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit." "0,1"
group.long 0x18200++0x3
line.long 0x0 "CFG0_PRG_PP_0_CTRL,"
bitfld.long 0x0 16.--17. "PRG_PP_0_CTRL_DEGLITCH_SEL,Deglitch period for PRG_PP0 POKs:" "0,1,2,3"
newline
bitfld.long 0x0 15. "PRG_PP_0_CTRL_POK_EN_SEL,Select POK active source" "0,1"
newline
bitfld.long 0x0 4. "PRG_PP_0_CTRL_POK_VDDA_PMIC_IN_UV_EN,Active VDDA_PMIC_IN undervoltage POK detection" "0,1"
newline
bitfld.long 0x0 3. "PRG_PP_0_CTRL_POK_VDD_MCU_OV_EN,Active VDD_MCU overvoltage POK detection" "0,1"
newline
bitfld.long 0x0 2. "PRG_PP_0_CTRL_POK_VDD_MCU_UV_EN,Active VDD_MCU undervoltage POK detection" "0,1"
newline
bitfld.long 0x0 1. "PRG_PP_0_CTRL_POK_VDDA_MCU_OV_EN,Active 1.8V VDDA_MCU overvoltage POK detection" "0,1"
newline
bitfld.long 0x0 0. "PRG_PP_0_CTRL_POK_VDDA_MCU_UV_EN,Active 1.8V VDDA_MCU undervoltage POK detection" "0,1"
group.long 0x18208++0x3
line.long 0x0 "CFG0_PRG_PP_1_CTRL,"
bitfld.long 0x0 19. "PRG_PP_1_CTRL_POK_PP_EN,POK ping-pong active. When set  activesautomatic switching between undervoltage andovervoltage detection on PRG_PP1 (POK_VDDR_CORE  POK_VDDSHV_MCU_1P8  POK_VDDSHV_MCU_3P3  POK_VMON_CAP_MCU_GENERAL  POK_VDDSHV_MAIN_1P8 .." "0,1"
newline
bitfld.long 0x0 16.--17. "PRG_PP_1_CTRL_DEGLITCH_SEL,Deglitch period for PRG_PP1 POKs:" "0,1,2,3"
newline
bitfld.long 0x0 15. "PRG_PP_1_CTRL_POK_EN_SEL,Select POK active source" "0,1"
newline
bitfld.long 0x0 14. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_OV_SEL,POK_VDDS_DDRIO mode:" "0,1"
newline
bitfld.long 0x0 13. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_OV_SEL,POK_VDDSHV_MAIN_3P3 mode:" "0,1"
newline
bitfld.long 0x0 12. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_OV_SEL,POK_VDDSHV_MAIN_1P8 mode:" "0,1"
newline
bitfld.long 0x0 11. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_OV_SEL,POK_VMON_CAP_MCU_GENERAL mode:" "0,1"
newline
bitfld.long 0x0 10. "PRG_PP_1_CTRL_POK_VDDSHV_MCU_3P3_OV_SEL,POK_VDDSHV_MCU_3P3 mode:" "0,1"
newline
bitfld.long 0x0 9. "PRG_PP_1_CTRL_POK_VDDSHV_MCU_1P8_OV_SEL,POK_VDDSHV_MCU_1P8 mode:" "0,1"
newline
bitfld.long 0x0 8. "PRG_PP_1_CTRL_POK_VDDR_CORE_OV_SEL,POK_VDDR_CORE Mode:" "0,1"
newline
bitfld.long 0x0 6. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_EN,Active POK_VDDS_DDRIO (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 5. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_EN,Active POK_VDDSHV_MAIN_3P3 (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 4. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_EN,Active POK_VDDSHV_MAIN_1P8 (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 3. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_EN,Active POK_VMON_CAP_MCU_GENERAL (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 2. "PRG_PP_1_CTRL_POK_VDDSHV_MCU_3P3_EN,Active POK_VDDSHV_MCU_3P3 (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 1. "PRG_PP_1_CTRL_POK_VDDSHV_MCU_1P8_EN,Active POK_VDDSHV_MCU_1P8 (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 0. "PRG_PP_1_CTRL_POK_VDDR_CORE_EN,Active POK_VDDR_CORE (if pok_en_sel = 1):" "0,1"
group.long 0x18284++0x7
line.long 0x0 "CFG0_MCU_CLKGATE_CTRL,"
bitfld.long 0x0 8. "MCU_CLKGATE_CTRL_MCU_M4FSS_NOGATE,MCU domain M4FSS0 clock gate deactivate." "0,1"
newline
bitfld.long 0x0 1. "MCU_CLKGATE_CTRL_MCU_CBA_ECC_AGGR_NOGATE,MCU domain Pulsar clock gate deactivate." "0,1"
newline
bitfld.long 0x0 0. "MCU_CLKGATE_CTRL_MCU_CBA_NOGATE,MCU domain Data bus (mcu_cbass) clock gate deactivate." "0,1"
line.long 0x4 "CFG0_MAIN_CLKGATE_CTRL0,"
bitfld.long 0x4 31. "MAIN_CLKGATE_CTRL0_MAIN_DMSC_NOGATE,MAIN domain DMSC (pwr_dis_nogate) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 28. "MAIN_CLKGATE_CTRL0_MAIN_DBG_CBA_NOGATE,MAIN domain Debug bus clock gate deactivate." "0,1"
newline
bitfld.long 0x4 26. "MAIN_CLKGATE_CTRL0_MAIN_R5FSS1_NOGATE,MAIN domain R5FSS1 clock gate deactivate." "0,1"
newline
bitfld.long 0x4 25. "MAIN_CLKGATE_CTRL0_MAIN_R5FSS0_NOGATE,MAIN domain R5FSS0 clock gate deactivate." "0,1"
newline
bitfld.long 0x4 24. "MAIN_CLKGATE_CTRL0_MAIN_TIMERMGR_NOGATE,MAIN domain TIMERMGR (pwr_dis_nogate) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 21. "MAIN_CLKGATE_CTRL0_MAIN_ICSSG1_NOGATE,MAIN domain ICSSG1 clock gate deactivate." "0,1"
newline
bitfld.long 0x4 20. "MAIN_CLKGATE_CTRL0_MAIN_ICSSG0_NOGATE,MAIN domain ICSSG0 clock gate deactivate." "0,1"
newline
bitfld.long 0x4 18. "MAIN_CLKGATE_CTRL0_MAIN_PDMA1_NOGATE,MAIN domain PDMA1 (pwr_dis_nogate) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 17. "MAIN_CLKGATE_CTRL0_MAIN_PDMA0_NOGATE,MAIN domain PDMA0 (pwr_dis_nogate) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 16. "MAIN_CLKGATE_CTRL0_MAIN_DMSS_NOGATE,MAIN domain DMSS (pwr_dis_nogate) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 15. "MAIN_CLKGATE_CTRL0_MAIN_GIC500_NOGATE,MAIN A53SS0 (gic500_1_2) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 10. "MAIN_CLKGATE_CTRL0_MAIN_A53_0_DBG_NOGATE,MAIN A53SS0 Debug Port clock gate deactivate." "0,1"
newline
bitfld.long 0x4 9. "MAIN_CLKGATE_CTRL0_MAIN_A53_0_CFG_NOGATE,MAIN A53SS0 Configuration Port clock gate deactivate." "0,1"
newline
bitfld.long 0x4 8. "MAIN_CLKGATE_CTRL0_MAIN_A53_0_ACP_NOGATE,MAIN A53SS0 ACP clock gate deactivate." "0,1"
newline
bitfld.long 0x4 7. "MAIN_CLKGATE_CTRL0_MAIN_A53_0_NOGATE,MAIN A53SS0 clock gate deactivate." "0,1"
newline
bitfld.long 0x4 6. "MAIN_CLKGATE_CTRL0_MAIN_CBA_ECC_AGG_NOGATE,MAIN domain data bus ECC aggragator (main_cba_ecc_aggr_main_0) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 5. "MAIN_CLKGATE_CTRL0_MAIN_FW_CBA_NOGATE,MAIN domain datal bus (main_fw_cbass) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 4. "MAIN_CLKGATE_CTRL0_MAIN_CBA_NOGATE,MAIN domain data bus (main_cbass) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 2. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_ECC_AGG_NOGATE,MAIN domain Infrastructure ECC aggragator (main_infra_ecc_aggr) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 0. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_CBA_NOGATE,MAIN domain Infrastructure bus (main_infra_cbass) clock gate deactivate." "0,1"
group.long 0x19008++0x7
line.long 0x0 "CFG0_LOCK6_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK6_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK6_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK6_KICK1,- KICK1 component"
rgroup.long 0x19100++0x17
line.long 0x0 "CFG0_CLAIMREG_P6_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0_READONLY,Claim bits for Partition 6"
line.long 0x4 "CFG0_CLAIMREG_P6_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1_READONLY,Claim bits for Partition 6"
line.long 0x8 "CFG0_CLAIMREG_P6_R2_READONLY,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P6_R2_READONLY,Claim bits for Partition 6"
line.long 0xC "CFG0_CLAIMREG_P6_R3_READONLY,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P6_R3_READONLY,Claim bits for Partition 6"
line.long 0x10 "CFG0_CLAIMREG_P6_R4_READONLY,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P6_R4_READONLY,Claim bits for Partition 6"
line.long 0x14 "CFG0_CLAIMREG_P6_R5_READONLY,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P6_R5_READONLY,Claim bits for Partition 6"
group.long 0x1A000++0x3
line.long 0x0 "CFG0_POR_CTRL_PROXY,"
bitfld.long 0x0 29. "POR_CTRL_OVRD_SET5_PROXY,Reserved override set" "0,1"
newline
bitfld.long 0x0 28. "POR_CTRL_OVRD_SET4_PROXY,POKLVB override set" "0,1"
newline
bitfld.long 0x0 27. "POR_CTRL_OVRD_SET3_PROXY,POKLVA override set" "0,1"
newline
bitfld.long 0x0 26. "POR_CTRL_OVRD_SET2_PROXY,POKHV override set" "0,1"
newline
bitfld.long 0x0 25. "POR_CTRL_OVRD_SET1_PROXY,BGOK override set" "0,1"
newline
bitfld.long 0x0 24. "POR_CTRL_OVRD_SET0_PROXY,PORHV override set" "0,1"
newline
bitfld.long 0x0 21. "POR_CTRL_OVRD5_PROXY,Reserved override active" "0,1"
newline
bitfld.long 0x0 20. "POR_CTRL_OVRD4_PROXY,POKLVB override active" "0,1"
newline
bitfld.long 0x0 19. "POR_CTRL_OVRD3_PROXY,POKLVA override active" "0,1"
newline
bitfld.long 0x0 18. "POR_CTRL_OVRD2_PROXY,POKHV override active" "0,1"
newline
bitfld.long 0x0 17. "POR_CTRL_OVRD1_PROXY,BGOK override active" "0,1"
newline
bitfld.long 0x0 16. "POR_CTRL_OVRD0_PROXY,PORHV override active" "0,1"
newline
bitfld.long 0x0 7. "POR_CTRL_TRIM_SEL_PROXY,POR Trim Select" "0,1"
newline
bitfld.long 0x0 4. "POR_CTRL_MASK_HHV_PROXY,Mask HHV/SOC_PORz outputs when applying new trim values" "0,1"
rgroup.long 0x1A004++0x3
line.long 0x0 "CFG0_POR_STAT_PROXY,"
bitfld.long 0x0 8. "POR_STAT_BGOK_PROXY,Bandgap OK status" "0,1"
newline
bitfld.long 0x0 4. "POR_STAT_SOC_POR_PROXY,POR module status" "0,1"
group.long 0x1A100++0x3
line.long 0x0 "CFG0_POR_BANDGAP_CTRL_PROXY,"
hexmask.long.byte 0x0 16.--19. 1. "POR_BANDGAP_CTRL_BGAPI_PROXY,Bandgap output current trim bits"
newline
hexmask.long.byte 0x0 8.--15. 1. "POR_BANDGAP_CTRL_BGAPV_PROXY,Bandgap output voltage magnitude trim bits"
newline
hexmask.long.byte 0x0 0.--7. 1. "POR_BANDGAP_CTRL_BGAPC_PROXY,Bandgap slope trim bits. Bit7 is used to calculate the offset"
group.long 0x1A110++0x47
line.long 0x0 "CFG0_POK_VDDA_MCU_UV_CTRL_PROXY,"
bitfld.long 0x0 31. "POK_VDDA_MCU_UV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x0 7. "POK_VDDA_MCU_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x0 0.--6. 1. "POK_VDDA_MCU_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x4 "CFG0_POK_VDDA_MCU_OV_CTRL_PROXY,"
bitfld.long 0x4 31. "POK_VDDA_MCU_OV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x4 7. "POK_VDDA_MCU_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x4 0.--6. 1. "POK_VDDA_MCU_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x8 "CFG0_POK_VDD_CORE_UV_CTRL_PROXY,"
bitfld.long 0x8 31. "POK_VDD_CORE_UV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x8 7. "POK_VDD_CORE_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x8 0.--6. 1. "POK_VDD_CORE_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0xC "CFG0_POK_VDD_CORE_OV_CTRL_PROXY,"
bitfld.long 0xC 31. "POK_VDD_CORE_OV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0xC 7. "POK_VDD_CORE_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0xC 0.--6. 1. "POK_VDD_CORE_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x10 "CFG0_POK_VDDR_CORE_UV_CTRL_PROXY,"
bitfld.long 0x10 31. "POK_VDDR_CORE_UV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x10 7. "POK_VDDR_CORE_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x10 0.--6. 1. "POK_VDDR_CORE_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x14 "CFG0_POK_VDDR_CORE_OV_CTRL_PROXY,"
bitfld.long 0x14 31. "POK_VDDR_CORE_OV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x14 7. "POK_VDDR_CORE_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x14 0.--6. 1. "POK_VDDR_CORE_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x18 "CFG0_POK_VDDSHV_MCU_1P8_UV_CTRL_PROXY,"
bitfld.long 0x18 31. "POK_VDDSHV_MCU_1P8_UV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x18 7. "POK_VDDSHV_MCU_1P8_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x18 0.--6. 1. "POK_VDDSHV_MCU_1P8_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x1C "CFG0_POK_VDDSHV_MCU_1P8_OV_CTRL_PROXY,"
bitfld.long 0x1C 31. "POK_VDDSHV_MCU_1P8_OV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x1C 7. "POK_VDDSHV_MCU_1P8_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x1C 0.--6. 1. "POK_VDDSHV_MCU_1P8_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x20 "CFG0_POK_VDDSHV_MCU_3P3_UV_CTRL_PROXY,"
bitfld.long 0x20 31. "POK_VDDSHV_MCU_3P3_UV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x20 7. "POK_VDDSHV_MCU_3P3_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x20 0.--6. 1. "POK_VDDSHV_MCU_3P3_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x24 "CFG0_POK_VDDSHV_MCU_3P3_OV_CTRL_PROXY,"
bitfld.long 0x24 31. "POK_VDDSHV_MCU_3P3_OV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x24 7. "POK_VDDSHV_MCU_3P3_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x24 0.--6. 1. "POK_VDDSHV_MCU_3P3_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x28 "CFG0_POK_VMON_CAP_MCU_GENERAL_UV_CTRL_PROXY,"
bitfld.long 0x28 31. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x28 7. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x28 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x2C "CFG0_POK_VMON_CAP_MCU_GENERAL_OV_CTRL_PROXY,"
bitfld.long 0x2C 31. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x2C 7. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x2C 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x30 "CFG0_POK_VDDSHV_MAIN_1P8_UV_CTRL_PROXY,"
bitfld.long 0x30 31. "POK_VDDSHV_MAIN_1P8_UV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x30 7. "POK_VDDSHV_MAIN_1P8_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x30 0.--6. 1. "POK_VDDSHV_MAIN_1P8_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x34 "CFG0_POK_VDDSHV_MAIN_1P8_OV_CTRL_PROXY,"
bitfld.long 0x34 31. "POK_VDDSHV_MAIN_1P8_OV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x34 7. "POK_VDDSHV_MAIN_1P8_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x34 0.--6. 1. "POK_VDDSHV_MAIN_1P8_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x38 "CFG0_POK_VDDSHV_MAIN_3P3_UV_CTRL_PROXY,"
bitfld.long 0x38 31. "POK_VDDSHV_MAIN_3P3_UV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x38 7. "POK_VDDSHV_MAIN_3P3_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x38 0.--6. 1. "POK_VDDSHV_MAIN_3P3_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x3C "CFG0_POK_VDDSHV_MAIN_3P3_OV_CTRL_PROXY,"
bitfld.long 0x3C 31. "POK_VDDSHV_MAIN_3P3_OV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x3C 7. "POK_VDDSHV_MAIN_3P3_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x3C 0.--6. 1. "POK_VDDSHV_MAIN_3P3_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x40 "CFG0_POK_VDDS_DDRIO_UV_CTRL_PROXY,"
bitfld.long 0x40 31. "POK_VDDS_DDRIO_UV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x40 7. "POK_VDDS_DDRIO_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x40 0.--6. 1. "POK_VDDS_DDRIO_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x44 "CFG0_POK_VDDS_DDRIO_OV_CTRL_PROXY,"
bitfld.long 0x44 31. "POK_VDDS_DDRIO_OV_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x44 7. "POK_VDDS_DDRIO_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x44 0.--6. 1. "POK_VDDS_DDRIO_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
group.long 0x1A160++0x3
line.long 0x0 "CFG0_POK_VDDA_PMIC_IN_CTRL_PROXY,"
bitfld.long 0x0 31. "POK_VDDA_PMIC_IN_CTRL_HYST_EN_PROXY,Active POK hysteresis" "0,1"
newline
bitfld.long 0x0 15. "POK_VDDA_PMIC_IN_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "0,1"
group.long 0x1A170++0x3
line.long 0x0 "CFG0_RST_CTRL_PROXY,"
bitfld.long 0x0 18. "RST_CTRL_MCU_RESET_ISO_DONE_Z_PROXY,MCU can set this bit to block warm reset in the main domain which is useful when the MCU may be accessing" "0,1"
newline
bitfld.long 0x0 17. "RST_CTRL_MCU_ESM_ERROR_RST_EN_Z_PROXY,Deactivate Reset of MCU by ESM" "0,1"
newline
bitfld.long 0x0 16. "RST_CTRL_DMSC_COLD_RESET_EN_Z_PROXY,Deactivate Reset of MCU by DMSC" "0,1"
newline
hexmask.long.byte 0x0 8.--11. 1. "RST_CTRL_SW_MCU_WARMRST_PROXY,This is a fault tolerant bitfield."
newline
hexmask.long.byte 0x0 4.--7. 1. "RST_CTRL_SW_MAIN_POR_PROXY,This is a fault tolerant bitfield."
newline
hexmask.long.byte 0x0 0.--3. 1. "RST_CTRL_SW_MAIN_WARMRST_PROXY,This is a fault tolerant bitfield."
rgroup.long 0x1A174++0x3
line.long 0x0 "CFG0_RST_STAT_PROXY,"
bitfld.long 0x0 0. "RST_STAT_MAIN_RESETSTATZ_PROXY,Status of Main Domain Reset:" "0,1"
group.long 0x1A178++0xB
line.long 0x0 "CFG0_RST_SRC_PROXY,"
bitfld.long 0x0 31. "RST_SRC_SAFETY_ERROR_PROXY,Reset Caused by MCU ESM Error" "0,1"
newline
bitfld.long 0x0 30. "RST_SRC_MAIN_ESM_ERROR_PROXY,Reset Caused by Main ESM Error" "0,1"
newline
bitfld.long 0x0 25. "RST_SRC_SW_MAIN_POR_FROM_MAIN_PROXY,Software Main Power On Reset From MAIN CTRL MMR" "0,1"
newline
bitfld.long 0x0 24. "RST_SRC_SW_MAIN_POR_FROM_MCU_PROXY,Software Main Power On Reset From MCU CTRL MMR" "0,1"
newline
bitfld.long 0x0 21. "RST_SRC_SW_MAIN_WARMRST_FROM_MAIN_PROXY,Software Main Warm Reset from MAIN CTRL MMR" "0,1"
newline
bitfld.long 0x0 20. "RST_SRC_SW_MAIN_WARMRST_FROM_MCU_PROXY,Software Main Warm Reset From MCU CTRL MMR" "0,1"
newline
bitfld.long 0x0 16. "RST_SRC_SW_MCU_WARMRST_PROXY,Software Warm Reset" "0,1"
newline
bitfld.long 0x0 13. "RST_SRC_WARM_OUT_RST_PROXY,DMSC Warm Reset" "0,1"
newline
bitfld.long 0x0 12. "RST_SRC_COLD_OUT_RST_PROXY,DMSC Cold Reset" "0,1"
newline
bitfld.long 0x0 8. "RST_SRC_DEBUG_RST_PROXY,Debug Subsystem Initiated Reset" "0,1"
newline
bitfld.long 0x0 4. "RST_SRC_THERMAL_RST_PROXY,Thermal Reset" "0,1"
newline
bitfld.long 0x0 2. "RST_SRC_MAIN_RESET_REQ_PROXY,Main Reset Pin" "0,1"
newline
bitfld.long 0x0 0. "RST_SRC_MCU_RESET_PIN_PROXY,Rest Caused by MCU Reset Pin" "0,1"
line.long 0x4 "CFG0_RST_MAGIC_WORD_PROXY,"
hexmask.long 0x4 0.--31. 1. "RST_MAGIC_WORD_MCU_MAGIC_WORD_PROXY,After a MCU_PORz reset this bit field resets to 0x00000000."
line.long 0x8 "CFG0_ISO_CTRL_PROXY,"
bitfld.long 0x8 1. "ISO_CTRL_MCU_DBG_ISO_EN_PROXY,Isolates the MCU domain from Debug" "0,1"
newline
bitfld.long 0x8 0. "ISO_CTRL_MCU_RST_ISO_EN_PROXY,Isolates the MCU domain from Warm Reset initiated by Main" "0,1"
group.long 0x1A190++0x3
line.long 0x0 "CFG0_VDD_CORE_GLDTC_CTRL_PROXY,"
bitfld.long 0x0 31. "VDD_CORE_GLDTC_CTRL_PWDB_PROXY,Power down - active low." "0,1"
newline
bitfld.long 0x0 30. "VDD_CORE_GLDTC_CTRL_RSTB_PROXY,Reset - active low. To ensure proper operation  rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally  rstb must be toggled low at least 200 ns after any change in threshold.." "0,1"
newline
bitfld.long 0x0 16.--18. "VDD_CORE_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--13. 1. "VDD_CORE_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage"
newline
hexmask.long.byte 0x0 0.--5. 1. "VDD_CORE_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage"
rgroup.long 0x1A1B0++0x3
line.long 0x0 "CFG0_VDD_CORE_GLDTC_STAT_PROXY,"
bitfld.long 0x0 8. "VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit." "0,1"
newline
bitfld.long 0x0 0. "VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit." "0,1"
group.long 0x1A200++0x3
line.long 0x0 "CFG0_PRG_PP_0_CTRL_PROXY,"
bitfld.long 0x0 16.--17. "PRG_PP_0_CTRL_DEGLITCH_SEL_PROXY,Deglitch period for PRG_PP0 POKs:" "0,1,2,3"
newline
bitfld.long 0x0 15. "PRG_PP_0_CTRL_POK_EN_SEL_PROXY,Select POK active source" "0,1"
newline
bitfld.long 0x0 4. "PRG_PP_0_CTRL_POK_VDDA_PMIC_IN_UV_EN_PROXY,Active VDDA_PMIC_IN undervoltage POK detection" "0,1"
newline
bitfld.long 0x0 3. "PRG_PP_0_CTRL_POK_VDD_MCU_OV_EN_PROXY,Active VDD_MCU overvoltage POK detection" "0,1"
newline
bitfld.long 0x0 2. "PRG_PP_0_CTRL_POK_VDD_MCU_UV_EN_PROXY,Active VDD_MCU undervoltage POK detection" "0,1"
newline
bitfld.long 0x0 1. "PRG_PP_0_CTRL_POK_VDDA_MCU_OV_EN_PROXY,Active 1.8V VDDA_MCU overvoltage POK detection" "0,1"
newline
bitfld.long 0x0 0. "PRG_PP_0_CTRL_POK_VDDA_MCU_UV_EN_PROXY,Active 1.8V VDDA_MCU undervoltage POK detection" "0,1"
group.long 0x1A208++0x3
line.long 0x0 "CFG0_PRG_PP_1_CTRL_PROXY,"
bitfld.long 0x0 19. "PRG_PP_1_CTRL_POK_PP_EN_PROXY,POK ping-pong active. When set  activesautomatic switching between undervoltage andovervoltage detection on PRG_PP1 (POK_VDDR_CORE  POK_VDDSHV_MCU_1P8  POK_VDDSHV_MCU_3P3  POK_VMON_CAP_MCU_GENERAL  POK_VDDSHV_MAIN_1P8 .." "0,1"
newline
bitfld.long 0x0 16.--17. "PRG_PP_1_CTRL_DEGLITCH_SEL_PROXY,Deglitch period for PRG_PP1 POKs:" "0,1,2,3"
newline
bitfld.long 0x0 15. "PRG_PP_1_CTRL_POK_EN_SEL_PROXY,Select POK active source" "0,1"
newline
bitfld.long 0x0 14. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_OV_SEL_PROXY,POK_VDDS_DDRIO mode:" "0,1"
newline
bitfld.long 0x0 13. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_OV_SEL_PROXY,POK_VDDSHV_MAIN_3P3 mode:" "0,1"
newline
bitfld.long 0x0 12. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_OV_SEL_PROXY,POK_VDDSHV_MAIN_1P8 mode:" "0,1"
newline
bitfld.long 0x0 11. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_OV_SEL_PROXY,POK_VMON_CAP_MCU_GENERAL mode:" "0,1"
newline
bitfld.long 0x0 10. "PRG_PP_1_CTRL_POK_VDDSHV_MCU_3P3_OV_SEL_PROXY,POK_VDDSHV_MCU_3P3 mode:" "0,1"
newline
bitfld.long 0x0 9. "PRG_PP_1_CTRL_POK_VDDSHV_MCU_1P8_OV_SEL_PROXY,POK_VDDSHV_MCU_1P8 mode:" "0,1"
newline
bitfld.long 0x0 8. "PRG_PP_1_CTRL_POK_VDDR_CORE_OV_SEL_PROXY,POK_VDDR_CORE Mode:" "0,1"
newline
bitfld.long 0x0 6. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_EN_PROXY,Active POK_VDDS_DDRIO (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 5. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_EN_PROXY,Active POK_VDDSHV_MAIN_3P3 (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 4. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_EN_PROXY,Active POK_VDDSHV_MAIN_1P8 (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 3. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_EN_PROXY,Active POK_VMON_CAP_MCU_GENERAL (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 2. "PRG_PP_1_CTRL_POK_VDDSHV_MCU_3P3_EN_PROXY,Active POK_VDDSHV_MCU_3P3 (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 1. "PRG_PP_1_CTRL_POK_VDDSHV_MCU_1P8_EN_PROXY,Active POK_VDDSHV_MCU_1P8 (if pok_en_sel = 1):" "0,1"
newline
bitfld.long 0x0 0. "PRG_PP_1_CTRL_POK_VDDR_CORE_EN_PROXY,Active POK_VDDR_CORE (if pok_en_sel = 1):" "0,1"
group.long 0x1A284++0x7
line.long 0x0 "CFG0_MCU_CLKGATE_CTRL_PROXY,"
bitfld.long 0x0 8. "MCU_CLKGATE_CTRL_MCU_M4FSS_NOGATE_PROXY,MCU domain M4FSS0 clock gate deactivate." "0,1"
newline
bitfld.long 0x0 1. "MCU_CLKGATE_CTRL_MCU_CBA_ECC_AGGR_NOGATE_PROXY,MCU domain Pulsar clock gate deactivate." "0,1"
newline
bitfld.long 0x0 0. "MCU_CLKGATE_CTRL_MCU_CBA_NOGATE_PROXY,MCU domain Data bus (mcu_cbass) clock gate deactivate." "0,1"
line.long 0x4 "CFG0_MAIN_CLKGATE_CTRL0_PROXY,"
bitfld.long 0x4 31. "MAIN_CLKGATE_CTRL0_MAIN_DMSC_NOGATE_PROXY,MAIN domain DMSC (pwr_dis_nogate) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 28. "MAIN_CLKGATE_CTRL0_MAIN_DBG_CBA_NOGATE_PROXY,MAIN domain Debug bus clock gate deactivate." "0,1"
newline
bitfld.long 0x4 26. "MAIN_CLKGATE_CTRL0_MAIN_R5FSS1_NOGATE_PROXY,MAIN domain R5FSS1 clock gate deactivate." "0,1"
newline
bitfld.long 0x4 25. "MAIN_CLKGATE_CTRL0_MAIN_R5FSS0_NOGATE_PROXY,MAIN domain R5FSS0 clock gate deactivate." "0,1"
newline
bitfld.long 0x4 24. "MAIN_CLKGATE_CTRL0_MAIN_TIMERMGR_NOGATE_PROXY,MAIN domain TIMERMGR (pwr_dis_nogate) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 21. "MAIN_CLKGATE_CTRL0_MAIN_ICSSG1_NOGATE_PROXY,MAIN domain ICSSG1 clock gate deactivate." "0,1"
newline
bitfld.long 0x4 20. "MAIN_CLKGATE_CTRL0_MAIN_ICSSG0_NOGATE_PROXY,MAIN domain ICSSG0 clock gate deactivate." "0,1"
newline
bitfld.long 0x4 18. "MAIN_CLKGATE_CTRL0_MAIN_PDMA1_NOGATE_PROXY,MAIN domain PDMA1 (pwr_dis_nogate) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 17. "MAIN_CLKGATE_CTRL0_MAIN_PDMA0_NOGATE_PROXY,MAIN domain PDMA0 (pwr_dis_nogate) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 16. "MAIN_CLKGATE_CTRL0_MAIN_DMSS_NOGATE_PROXY,MAIN domain DMSS (pwr_dis_nogate) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 15. "MAIN_CLKGATE_CTRL0_MAIN_GIC500_NOGATE_PROXY,MAIN A53SS0 (gic500_1_2) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 10. "MAIN_CLKGATE_CTRL0_MAIN_A53_0_DBG_NOGATE_PROXY,MAIN A53SS0 Debug Port clock gate deactivate." "0,1"
newline
bitfld.long 0x4 9. "MAIN_CLKGATE_CTRL0_MAIN_A53_0_CFG_NOGATE_PROXY,MAIN A53SS0 Configuration Port clock gate deactivate." "0,1"
newline
bitfld.long 0x4 8. "MAIN_CLKGATE_CTRL0_MAIN_A53_0_ACP_NOGATE_PROXY,MAIN A53SS0 ACP clock gate deactivate." "0,1"
newline
bitfld.long 0x4 7. "MAIN_CLKGATE_CTRL0_MAIN_A53_0_NOGATE_PROXY,MAIN A53SS0 clock gate deactivate." "0,1"
newline
bitfld.long 0x4 6. "MAIN_CLKGATE_CTRL0_MAIN_CBA_ECC_AGG_NOGATE_PROXY,MAIN domain data bus ECC aggragator (main_cba_ecc_aggr_main_0) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 5. "MAIN_CLKGATE_CTRL0_MAIN_FW_CBA_NOGATE_PROXY,MAIN domain datal bus (main_fw_cbass) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 4. "MAIN_CLKGATE_CTRL0_MAIN_CBA_NOGATE_PROXY,MAIN domain data bus (main_cbass) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 2. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_ECC_AGG_NOGATE_PROXY,MAIN domain Infrastructure ECC aggragator (main_infra_ecc_aggr) clock gate deactivate." "0,1"
newline
bitfld.long 0x4 0. "MAIN_CLKGATE_CTRL0_MAIN_INFRA_CBA_NOGATE_PROXY,MAIN domain Infrastructure bus (main_infra_cbass) clock gate deactivate." "0,1"
group.long 0x1B008++0x7
line.long 0x0 "CFG0_LOCK6_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK6_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK6_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK6_KICK1_PROXY,- KICK1 component"
group.long 0x1B100++0x17
line.long 0x0 "CFG0_CLAIMREG_P6_R0,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0,Claim bits for Partition 6"
line.long 0x4 "CFG0_CLAIMREG_P6_R1,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1,Claim bits for Partition 6"
line.long 0x8 "CFG0_CLAIMREG_P6_R2,"
hexmask.long 0x8 0.--31. 1. "CLAIMREG_P6_R2,Claim bits for Partition 6"
line.long 0xC "CFG0_CLAIMREG_P6_R3,"
hexmask.long 0xC 0.--31. 1. "CLAIMREG_P6_R3,Claim bits for Partition 6"
line.long 0x10 "CFG0_CLAIMREG_P6_R4,"
hexmask.long 0x10 0.--31. 1. "CLAIMREG_P6_R4,Claim bits for Partition 6"
line.long 0x14 "CFG0_CLAIMREG_P6_R5,"
hexmask.long 0x14 0.--31. 1. "CLAIMREG_P6_R5,Claim bits for Partition 6"
tree.end
tree "MCU_DCC0 (MCU_DCC0)"
base ad:0x4C00000
group.long 0x0++0x3
line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal."
hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal  but has no effect on the done status flag in DCCSTAT register. User  privilege  and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.."
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User  privilege  and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.."
newline
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User  privilege  and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.."
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User  privilege  and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.."
rgroup.long 0x4++0x3
line.long 0x0 "CFG_DCCREV,Specifies the module version."
bitfld.long 0x0 30.--31. "SCHEME,User  privilege  and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability  a unique func number is assigned; for compatible modules  the same number is maintained. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write):.."
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect."
bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User  privilege  and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User  privilege  and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User  privilege  and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect."
group.long 0x8++0xF
line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User  privilege  and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User  privilege  and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.."
line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User  privilege  and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.."
line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module."
bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag"
bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User  privilege  and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag"
rgroup.long 0x18++0xB
line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0."
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User  privilege  and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect."
line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0."
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User  privilege  and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect."
line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1."
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User  privilege  and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect."
group.long 0x24++0xB
line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1."
hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1  when the KEY field enables this feature. User  privilege  and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC."
line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0."
hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User  privilege  and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.."
hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User  privilege  and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0."
line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC."
hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.."
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hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User  privilege  and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.."
rgroup.long 0x30++0x3
line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs."
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User  privilege  and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full"
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User  privilege  and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full"
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bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User  privilege  and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full"
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User  privilege  and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
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bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User  privilege  and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User  privilege  and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
group.long 0x34++0x3
line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear."
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
tree.end
tree "MCU_ECC_AGGR0_ECC_AGGR (MCU_ECC_AGGR0_ECC_AGGR)"
base ad:0x4700000
rgroup.long 0x0++0x3
line.long 0x0 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
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hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
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bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
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bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
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hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 18. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
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bitfld.long 0x4 17. "AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_Iblazar_mcu_0_vbusp_s_p2p_bridge_Iblazar_mcu_0_vbusp_s_bridge_busecc_pend" "0,1"
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bitfld.long 0x4 16. "AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1"
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bitfld.long 0x4 15. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_1_pend" "0,1"
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bitfld.long 0x4 14. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_0_pend" "0,1"
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bitfld.long 0x4 13. "AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_err_scr_am64_mcu_cbass_cbass_err_scr_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x4 12. "AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1"
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bitfld.long 0x4 11. "AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_cbass_default_err_am64_mcu_cbass_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x4 10. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_3_pend" "0,1"
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bitfld.long 0x4 9. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x4 8. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x4 7. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x4 6. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 5. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 4. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 3. "AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 2. "AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_Islave_safety_gasket_mcu_0_cfg_p2p_bridge_Islave_safety_gasket_mcu_0_cfg_bridge_busecc_pend" "0,1"
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bitfld.long 0x4 1. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 0. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
group.long 0x80++0x3
line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 18. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
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bitfld.long 0x0 17. "AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_Iblazar_mcu_0_vbusp_s_p2p_bridge_Iblazar_mcu_0_vbusp_s_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 16. "AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 15. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_1_pend" "0,1"
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bitfld.long 0x0 14. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_0_pend" "0,1"
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bitfld.long 0x0 13. "AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_err_scr_am64_mcu_cbass_cbass_err_scr_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0 12. "AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 11. "AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_cbass_default_err_am64_mcu_cbass_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0 10. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_3_pend" "0,1"
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bitfld.long 0x0 9. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x0 8. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x0 7. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x0 6. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 5. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 4. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 3. "AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 2. "AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 1. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 0. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
group.long 0xC0++0x3
line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 18. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
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bitfld.long 0x0 17. "AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_Iblazar_mcu_0_vbusp_s_p2p_bridge_Iblazar_mcu_0_vbusp_s_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 16. "AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 15. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_1_pend" "0,1"
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bitfld.long 0x0 14. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_0_pend" "0,1"
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bitfld.long 0x0 13. "AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_err_scr_am64_mcu_cbass_cbass_err_scr_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0 12. "AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 11. "AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_cbass_default_err_am64_mcu_cbass_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0 10. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_3_pend" "0,1"
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bitfld.long 0x0 9. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x0 8. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x0 7. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x0 6. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 5. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 4. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x0 3. "AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x0 2. "AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 1. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 0. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
group.long 0x13C++0x7
line.long 0x0 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 18. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
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bitfld.long 0x4 17. "AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_Iblazar_mcu_0_vbusp_s_p2p_bridge_Iblazar_mcu_0_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x4 16. "AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x4 15. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_1_pend" "0,1"
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bitfld.long 0x4 14. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_0_pend" "0,1"
newline
bitfld.long 0x4 13. "AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_err_scr_am64_mcu_cbass_cbass_err_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 12. "AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x4 11. "AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_cbass_default_err_am64_mcu_cbass_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 10. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_3_pend" "0,1"
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bitfld.long 0x4 9. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x4 8. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x4 7. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x4 6. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 5. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 4. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
newline
bitfld.long 0x4 3. "AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 2. "AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_PEND,Interrupt Pending Status for am64_mcu_cbass_cbass_Islave_safety_gasket_mcu_0_cfg_p2p_bridge_Islave_safety_gasket_mcu_0_cfg_bridge_busecc_pend" "0,1"
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bitfld.long 0x4 1. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x4 0. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
group.long 0x180++0x3
line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 18. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
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bitfld.long 0x0 17. "AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_Iblazar_mcu_0_vbusp_s_p2p_bridge_Iblazar_mcu_0_vbusp_s_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 16. "AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 15. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_1_pend" "0,1"
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bitfld.long 0x0 14. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_0_pend" "0,1"
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bitfld.long 0x0 13. "AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_err_scr_am64_mcu_cbass_cbass_err_scr_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0 12. "AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 11. "AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_cbass_default_err_am64_mcu_cbass_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0 10. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_3_pend" "0,1"
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bitfld.long 0x0 9. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x0 8. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x0 7. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x0 6. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 5. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
newline
bitfld.long 0x0 4. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
newline
bitfld.long 0x0 3. "AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
newline
bitfld.long 0x0 2. "AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 1. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0 0. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
group.long 0x1C0++0x3
line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 18. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
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bitfld.long 0x0 17. "AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_Iblazar_mcu_0_vbusp_s_p2p_bridge_Iblazar_mcu_0_vbusp_s_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 16. "AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_dmsc_slv_p2p_bridge_dmsc_slv_bridge_busecc_pend" "0,1"
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bitfld.long 0x0 15. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_1_pend" "0,1"
newline
bitfld.long 0x0 14. "AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_MCU_SYSCLK0_4_clk_edc_ctrl_cbass_int_MCU_SYSCLK0_4_busecc_0_pend" "0,1"
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bitfld.long 0x0 13. "AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_err_scr_am64_mcu_cbass_cbass_err_scr_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0 12. "AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_err_slv_p2p_bridge_err_slv_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 11. "AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_cbass_default_err_am64_mcu_cbass_cbass_cbass_default_err_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 10. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_3_pend" "0,1"
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bitfld.long 0x0 9. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_2_pend" "0,1"
newline
bitfld.long 0x0 8. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_1_pend" "0,1"
newline
bitfld.long 0x0 7. "AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_am64_mcu_cbass_cbass_scrp_mcu_clk4_scr_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x0 6. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0 5. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x0 4. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_MCU_TOMAIN_0_SLV_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x0 3. "AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x0 2. "AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x0 1. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x0 0. "AM64_MCU_CBASS_CBASS_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_MCU_FROMMAIN_0_MST_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
group.long 0x200++0xF
line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_ESM0_CFG (MCU_ESM0_CFG)"
base ad:0x4100000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "CFG_INFO,The Info Register gives the configuration Inforrmation of this ESM."
bitfld.long 0x4 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1"
hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups"
hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Total number of Error Groups"
group.long 0x8++0x3
line.long 0x0 "CFG_EN,The Global Enable Register has the master interrupt mask"
hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Enable"
wgroup.long 0xC++0x3
line.long 0x0 "CFG_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables"
hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset"
group.long 0x10++0xF
line.long 0x0 "CFG_ERR_RAW,Raw Status/Set Register for Configuration Errors"
bitfld.long 0x0 0.--2. "STS,This is the raw status for config errors" "0,1,2,3,4,5,6,7"
line.long 0x4 "CFG_ERR_STS,Config Error Enable and Clear Register"
bitfld.long 0x4 0.--2. "MSK,This is the masked status/clear for config errors" "0,1,2,3,4,5,6,7"
line.long 0x8 "CFG_ERR_EN_SET,Config Error Enable Set Register"
bitfld.long 0x8 0.--2. "MSK,This is the mask enable set for config errors" "0,1,2,3,4,5,6,7"
line.long 0xC "CFG_ERR_EN_CLR,Config Error Interrupt Enabled Clear register"
bitfld.long 0xC 0.--2. "MSK,This is the mask enable clear for config errors" "0,1,2,3,4,5,6,7"
rgroup.long 0x20++0xF
line.long 0x0 "CFG_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt"
hexmask.long.word 0x0 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt"
hexmask.long.word 0x0 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt"
line.long 0x4 "CFG_HI_PRI,Shows which is the highest priority outstanding high priority interrupt"
hexmask.long.word 0x4 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt"
hexmask.long.word 0x4 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt"
line.long 0x8 "CFG_LOW,Shows which groups have oustanding low priority interrupts"
hexmask.long 0x8 0.--31. 1. "STS,This is the raw status for config errors"
line.long 0xC "CFG_HI,Shows which groups have oustanding high priority interrupts"
hexmask.long 0xC 0.--31. 1. "STS,This is the raw status for config errors"
wgroup.long 0x30++0x3
line.long 0x0 "CFG_EOI,End of Interrupt Register"
hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced"
group.long 0x40++0x3
line.long 0x0 "CFG_PIN_CTRL,This register controls the error_pin_n output"
hexmask.long.byte 0x0 4.--7. 1. "PWM_EN,PWM enable"
hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin Control Key"
rgroup.long 0x44++0x7
line.long 0x0 "CFG_PIN_STS,This register reflects the status of the error_pin_n output"
bitfld.long 0x0 0. "VAL,Value of the error_pin_n" "0,1"
line.long 0x4 "CFG_PIN_CNTR,This register shows the current value of the error pin counter"
hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Current Counter Value"
group.long 0x4C++0x3
line.long 0x0 "CFG_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_PWMH_PIN_CNTR,This register shows the current value of the error pin PWM high counter"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value"
group.long 0x54++0x3
line.long 0x0 "CFG_PWMH_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM High Counter"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_PWML_PIN_CNTR,This register shows the current value of the error pin PWM low counter"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value"
group.long 0x5C++0x3
line.long 0x0 "CFG_PWML_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM Low Counter"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value"
tree.end
tree "MCU_GPIO0 (MCU_GPIO0)"
base ad:0x4201000
rgroup.long 0x0++0x7
line.long 0x0 "MEM_pid,GPIO Periperal ID Register"
bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code"
bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code"
line.long 0x4 "MEM_PCR,Peripheral Control Register"
bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x4 0. "FREE,For GPIO  the FREE bit is fixed at 1  which means GPIO runs free in emulation suspend" "0,1"
group.long 0x8++0x3
line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register"
hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable 0 = disable  1 = enable"
group.long 0x10++0xF
line.long 0x0 "MEM_DIR01,Direction Register"
hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits  0 = output  1 = input"
hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits  0 = output  1 = input"
line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register"
hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x20++0x3
line.long 0x0 "MEM_IN_DATA01,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits"
hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits"
group.long 0x24++0x23
line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits"
line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits"
line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR23,Direction Register"
hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits  0 = output  1 = input"
hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x48++0x3
line.long 0x0 "MEM_IN_DATA23,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits"
hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits"
group.long 0x4C++0x23
line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits"
line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits"
line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR45,Direction Register"
hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits  0 = output  1 = input"
hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x70++0x3
line.long 0x0 "MEM_IN_DATA45,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits"
hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits"
group.long 0x74++0x23
line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits"
line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits"
line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR67,Direction Register"
hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits  0 = output  1 = input"
hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0x98++0x3
line.long 0x0 "MEM_IN_DATA67,Bank Status Register"
hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits"
hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits"
group.long 0x9C++0x23
line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits"
line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits"
line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register"
hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
line.long 0x14 "MEM_DIR8,Direction Register"
hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits  0 = output  1 = input"
line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits  does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register"
hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
rgroup.long 0xC0++0x3
line.long 0x0 "MEM_IN_DATA8,Bank Status Register"
hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits"
group.long 0xC4++0x13
line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits"
line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits"
line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits"
line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register"
hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back 1 = interrupt occurred 0 = interrupt hasnt occurred since last cleared Writing 1 clears the corresponding interrupt status"
tree.end
tree "MCU_I2C0_CFG (MCU_I2C0_CFG)"
base ad:0x4900000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix  and resets to"
bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix  or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix  or major feature change"
line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x0 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
group.long 0x24++0x2B
line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1"
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bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1"
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bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)."
bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x7
line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
rgroup.long 0x90++0x3
line.long 0x0 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1"
group.long 0x94++0xB
line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode"
bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode"
line.long 0x4 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count"
line.long 0x8 "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x1B
line.long 0x0 "CFG_I2C_CON,I2C configuration register."
bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x0 10. "MST,Master/slave mode" "0,1"
newline
bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1"
newline
bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x4 "CFG_I2C_OA,Own address register"
bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 0.--9. 1. "OA,Own address"
line.long 0x8 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x8 0.--9. 1. "SA,Slave address"
line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
newline
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status"
hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status"
group.long 0xC4++0xB
line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1"
line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2"
hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2"
line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1"
group.long 0xD4++0x3
line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "MCU_I2C1_CFG (MCU_I2C1_CFG)"
base ad:0x4910000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix  and resets to"
bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix  or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix  or major feature change"
line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x0 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
group.long 0x24++0x2B
line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1"
newline
bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)."
bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x7
line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode  a new data is able to be read When set to '1' by core  an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received  an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode  an interrupt is signaled to MPUSS During reads  it always returns 0" "0,1"
rgroup.long 0x90++0x3
line.long 0x0 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1"
group.long 0x94++0xB
line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode"
bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode"
line.long 0x4 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count"
line.long 0x8 "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x1B
line.long 0x0 "CFG_I2C_CON,I2C configuration register."
bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x0 10. "MST,Master/slave mode" "0,1"
newline
bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1"
newline
bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x4 "CFG_I2C_OA,Own address register"
bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 0.--9. 1. "OA,Own address"
line.long 0x8 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x8 0.--9. 1. "SA,Slave address"
line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
newline
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
rgroup.long 0xC0++0x3
line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status"
hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status"
group.long 0xC4++0xB
line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1"
line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2"
hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2"
line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1"
group.long 0xD4++0x3
line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
base ad:0x0
tree "MCU_M4FSS0"
tree "MCU_M4FSS0_DRAM_0_DRAM (MCU_M4FSS0_DRAM_0_DRAM)"
base ad:0x5040000
group.long 0x0++0x3
line.long 0x0 "IDRAM__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MCU_M4FSS0_ECC_AGGR_0_ECC_AGGR (MCU_M4FSS0_ECC_AGGR_0_ECC_AGGR)"
base ad:0x5FF1000
rgroup.long 0x0++0x3
line.long 0x0 "ECC__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 13. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
newline
bitfld.long 0x4 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_PEND,Interrupt Pending Status for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x4 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x4 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x4 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x4 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 3. "DRAM_BUSECC_PEND,Interrupt Pending Status for dram_busecc_pend" "0,1"
newline
bitfld.long 0x4 2. "IRAM_BUSECC_PEND,Interrupt Pending Status for iram_busecc_pend" "0,1"
newline
bitfld.long 0x4 1. "DRAM_RAMECC_PEND,Interrupt Pending Status for dram_ramecc_pend" "0,1"
newline
bitfld.long 0x4 0. "IRAM_RAMECC_PEND,Interrupt Pending Status for iram_ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 13. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
newline
bitfld.long 0x0 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x0 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x0 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 3. "DRAM_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dram_busecc_pend" "0,1"
newline
bitfld.long 0x0 2. "IRAM_BUSECC_ENABLE_SET,Interrupt Enable Set Register for iram_busecc_pend" "0,1"
newline
bitfld.long 0x0 1. "DRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dram_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "IRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for iram_ramecc_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 13. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
newline
bitfld.long 0x0 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x0 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x0 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 3. "DRAM_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dram_busecc_pend" "0,1"
newline
bitfld.long 0x0 2. "IRAM_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for iram_busecc_pend" "0,1"
newline
bitfld.long 0x0 1. "DRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dram_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "IRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for iram_ramecc_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 13. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
newline
bitfld.long 0x4 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_PEND,Interrupt Pending Status for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x4 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x4 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x4 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x4 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 3. "DRAM_BUSECC_PEND,Interrupt Pending Status for dram_busecc_pend" "0,1"
newline
bitfld.long 0x4 2. "IRAM_BUSECC_PEND,Interrupt Pending Status for iram_busecc_pend" "0,1"
newline
bitfld.long 0x4 1. "DRAM_RAMECC_PEND,Interrupt Pending Status for dram_ramecc_pend" "0,1"
newline
bitfld.long 0x4 0. "IRAM_RAMECC_PEND,Interrupt Pending Status for iram_ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 13. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
newline
bitfld.long 0x0 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x0 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x0 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 3. "DRAM_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dram_busecc_pend" "0,1"
newline
bitfld.long 0x0 2. "IRAM_BUSECC_ENABLE_SET,Interrupt Enable Set Register for iram_busecc_pend" "0,1"
newline
bitfld.long 0x0 1. "DRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dram_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "IRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for iram_ramecc_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 13. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
newline
bitfld.long 0x0 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x0 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x0 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 3. "DRAM_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dram_busecc_pend" "0,1"
newline
bitfld.long 0x0 2. "IRAM_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for iram_busecc_pend" "0,1"
newline
bitfld.long 0x0 1. "DRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dram_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "IRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for iram_ramecc_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_M4FSS0_IRAM_0_IRAM (MCU_M4FSS0_IRAM_0_IRAM)"
base ad:0x5000000
group.long 0x0++0x3
line.long 0x0 "BLAZAR_IRAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MCU_M4FSS0_RAT_0_RAT (MCU_M4FSS0_RAT_0_RAT)"
base ad:0x5FF0000
rgroup.long 0x0++0x7
line.long 0x0 "RAT__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "RAT__CFG__MMRS_config,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x3
line.long 0x0 "RAT__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
group.long 0x820++0x3
line.long 0x0 "RAT__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1"
bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1"
rgroup.long 0x824++0x17
line.long 0x0 "RAT__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 4 = RAT."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "RAT__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 1 = Boundary crossing error."
line.long 0x8 "RAT__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "RAT__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits."
line.long 0x10 "RAT__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
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bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "RAT__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x840++0x13
line.long 0x0 "RAT__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1"
line.long 0x4 "RAT__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1"
line.long 0x8 "RAT__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1"
line.long 0xC "RAT__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1"
line.long 0x10 "RAT__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
group.long 0x20++0xF
line.long 0x0 "RAT__CFG__MMRS_ctrl,The Control for Region a"
bitfld.long 0x0 31. "EN,Enable for the Region" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "SIZE,Size of the Region in Address Bits. 0 = 1 byte  1 = 2B  2 = 4B  3 = 8B  etc. up to 32 = 4GB."
line.long 0x4 "RAT__CFG__MMRS_base,The Base Address for Region a. This is the source address for matching to a region."
hexmask.long 0x4 0.--31. 1. "BASE,Base Address for the Region. It must be aligned to the programmed size."
line.long 0x8 "RAT__CFG__MMRS_trans_l,The Translated Lower Address Bits for Region a"
hexmask.long 0x8 0.--31. 1. "LOWER,Translated Lower Address Bits for the Region. It must be aligned to the programmed size."
line.long 0xC "RAT__CFG__MMRS_trans_u,The Translated Upper Address Bits for Region a"
hexmask.long.byte 0xC 0.--3. 1. "UPPER,Translated Upper Address Bits for the Region"
tree.end
tree.end
tree "MCU_MCRC64_0_REGS (MCU_MCRC64_0_REGS)"
base ad:0x4D00000
group.long 0x0++0x3
line.long 0x0 "MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0"
bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set  the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore  CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset"
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bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set  the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore  CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset"
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bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set  the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore  CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset"
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bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set  the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore  CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset"
group.long 0x8++0x3
line.long 0x0 "MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1"
bitfld.long 0x0 0. "PWDN,Power Down. When set  MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode"
group.long 0x10++0x3
line.long 0x0 "MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by writing a seed value into PSA.."
bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode  the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?"
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bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode  the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?"
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bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode  the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?"
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bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set  the channel is put into data trace mode. The channel snoops on the CPU VBUSM  ITCM  DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable"
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bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode  the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?"
group.long 0x18++0x3
line.long 0x0 "MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register"
bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
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bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
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bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
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bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable"
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bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable"
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bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
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bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
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bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
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bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable"
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bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable"
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bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
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bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
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bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
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bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable"
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bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable"
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bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
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bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
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bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
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bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable"
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bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable"
group.long 0x20++0x3
line.long 0x0 "MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register"
bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
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bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
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bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
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bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable"
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bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable"
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bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
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bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
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bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
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bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable"
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bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable"
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bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
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bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
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bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
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bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable"
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bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable"
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bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
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bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
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bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
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bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable"
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bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable"
group.long 0x28++0x3
line.long 0x0 "MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register"
bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active"
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bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active"
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bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active"
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bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active"
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bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.."
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bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active"
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bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active"
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bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active"
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bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active"
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bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.."
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bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active"
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bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active"
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bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active"
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bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active"
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bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.."
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bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active"
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bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active"
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bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active"
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bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active"
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bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.."
rgroup.long 0x30++0x3
line.long 0x0 "MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset"
hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag."
rgroup.long 0x38++0x3
line.long 0x0 "MCRC64_REGS_CRC_BUSY,CRC Busy Register"
bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode  the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1"
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bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode  the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1"
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bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode  the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1"
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bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode  the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1"
group.long 0x40++0x7
line.long 0x0 "MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1"
hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed."
line.long 0x4 "MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1"
hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory."
rgroup.long 0x48++0x3
line.long 0x0 "MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1"
hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode  this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails  the erroneous sector number.."
group.long 0x4C++0x7
line.long 0x0 "MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A"
hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."
line.long 0x4 "MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B"
hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."
group.long 0x60++0xF
line.long 0x0 "MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register"
hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register."
line.long 0x4 "MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register"
hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register."
line.long 0x8 "MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register"
hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register."
line.long 0xC "MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register"
hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register."
rgroup.long 0x70++0xF
line.long 0x0 "MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register"
hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register."
line.long 0x4 "MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register"
hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register."
line.long 0x8 "MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register"
hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data."
line.long 0xC "MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register"
hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data."
group.long 0x80++0x7
line.long 0x0 "MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2"
hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed."
line.long 0x4 "MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2"
hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory."
rgroup.long 0x88++0x3
line.long 0x0 "MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2"
hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode  this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails  the erroneous sector number.."
group.long 0x8C++0x7
line.long 0x0 "MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."
line.long 0x4 "MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated."
group.long 0xA0++0xF
line.long 0x0 "MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register"
hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register."
line.long 0x4 "MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register"
hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register."
line.long 0x8 "MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register"
hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register."
line.long 0xC "MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register"
hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register."
rgroup.long 0xB0++0xF
line.long 0x0 "MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register"
hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register."
line.long 0x4 "MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register"
hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register."
line.long 0x8 "MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register"
hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data."
line.long 0xC "MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register"
hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data."
group.long 0xC0++0x7
line.long 0x0 "MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3"
hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed."
line.long 0x4 "MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3"
hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory."
rgroup.long 0xC8++0x3
line.long 0x0 "MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3"
hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode  this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails  the erroneous sector number.."
group.long 0xCC++0x7
line.long 0x0 "MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."
line.long 0x4 "MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated."
group.long 0xE0++0xF
line.long 0x0 "MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register"
hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register."
line.long 0x4 "MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register"
hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register."
line.long 0x8 "MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register"
hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register."
line.long 0xC "MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register"
hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register."
rgroup.long 0xF0++0xF
line.long 0x0 "MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register"
hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register."
line.long 0x4 "MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register"
hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register."
line.long 0x8 "MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register"
hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data."
line.long 0xC "MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register"
hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data."
group.long 0x100++0x7
line.long 0x0 "MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4"
hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed."
line.long 0x4 "MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4"
hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory."
rgroup.long 0x108++0x3
line.long 0x0 "MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4"
hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode  this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails  the erroneous sector number is logged into current sector ID.."
group.long 0x10C++0x7
line.long 0x0 "MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."
line.long 0x4 "MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated."
group.long 0x120++0xF
line.long 0x0 "MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register"
hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register."
line.long 0x4 "MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register"
hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register."
line.long 0x8 "MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register"
hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register."
line.long 0xC "MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register"
hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register."
rgroup.long 0x130++0xF
line.long 0x0 "MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register"
hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register."
line.long 0x4 "MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register"
hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register."
line.long 0x8 "MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register"
hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data."
line.long 0xC "MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register"
hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data."
group.long 0x140++0x3
line.long 0x0 "MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection"
bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled"
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bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.."
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bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.."
wgroup.long 0x200++0x3
line.long 0x0 "MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems."
hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination  it is write only  the result can be found in the PSASIG1 register."
wgroup.long 0x280++0x3
line.long 0x0 "MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems."
hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination  it is write only  the result can be found in the PSASIG2 register."
wgroup.long 0x300++0x3
line.long 0x0 "MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems."
hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination  it is write only  the result can be found in the PSASIG3 register."
wgroup.long 0x380++0x3
line.long 0x0 "MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems."
hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination  it is write only  the result can be found in the PSASIG4 register."
tree.end
tree "MCU_MCSPI0_CFG (MCU_MCSPI0_CFG)"
base ad:0x4B00000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R]  maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.."
bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X]  maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y]  maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.."
line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)."
hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored"
bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter  only MSB bits from 8 down to 4 are taken into account"
bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x3
line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition  target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x3
line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10  0x21 for 21"
group.long 0x110++0x2B
line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface."
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis."
hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode."
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns the value on the CLKSPI line [high or low]  and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction]  the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction]  the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface."
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode  The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode  in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit"
rgroup.long 0x13C++0x3
line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data"
group.long 0x140++0xF
line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel."
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit"
rgroup.long 0x150++0x3
line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data"
group.long 0x154++0xF
line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit"
rgroup.long 0x164++0x3
line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data"
group.long 0x168++0xF
line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit"
rgroup.long 0x178++0x3
line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data"
group.long 0x17C++0x7
line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started  a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
rgroup.long 0x1A0++0x3
line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
tree.end
tree "MCU_MCSPI1_CFG (MCU_MCSPI1_CFG)"
base ad:0x4B10000
rgroup.long 0x0++0x7
line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R]  maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.."
bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X]  maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y]  maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.."
line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)."
hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero  and writes to them are ignored"
bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter  only MSB bits from 8 down to 4 are taken into account"
bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x3
line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition  target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x3
line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10  0x21 for 21"
group.long 0x110++0x2B
line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface."
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis."
hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis."
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode."
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns the value on the CLKSPI line [high or low]  and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction]  the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction]  the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction]  this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction]  the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction]  this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface."
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode  The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode  in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit"
rgroup.long 0x13C++0x3
line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data"
group.long 0x140++0xF
line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel."
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit"
rgroup.long 0x150++0x3
line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data"
group.long 0x154++0xF
line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
newline
bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
newline
bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit"
rgroup.long 0x164++0x3
line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data"
group.long 0x168++0xF
line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
newline
bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x0 18. "IS,Input Select" "0,1"
bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length"
bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value  and results in a new clock SPICLK available to shift-in and shift-out data By.."
bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1"
newline
bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1"
line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes  Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x8 0. "EN,Channel Enable" "0,1"
line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is."
hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit"
rgroup.long 0x178++0x3
line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is."
hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data"
group.long 0x17C++0x7
line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started  a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
rgroup.long 0x1A0++0x3
line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled."
hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.."
tree.end
tree "MCU_MCU_GPIOMUX_INTROUTER0_CFG (MCU_MCU_GPIOMUX_INTROUTER0_CFG)"
base ad:0x4210000
rgroup.long 0x0++0x3
line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register"
bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function"
hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version"
bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version"
group.long 0x4++0x3
line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register"
bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1"
hexmask.long.byte 0x0 0.--4. 1. "MUX_CNTL,Mux control for interrupt N"
tree.end
tree "MCU_PADCFG_CTRL0_CFG0 (MCU_PADCFG_CTRL0_CFG0)"
base ad:0x4080000
rgroup.long 0x0++0x3
line.long 0x0 "CFG0_PID,"
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
rgroup.long 0x8++0x3
line.long 0x0 "CFG0_MMR_CFG1,"
bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN,Proxy addressing enabled" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions"
group.long 0x1008++0x1B
line.long 0x0 "CFG0_LOCK0_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK0_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component"
line.long 0x8 "CFG0_intr_raw_status,"
bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
line.long 0xC "CFG0_intr_enabled_status_clear,"
bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
line.long 0x10 "CFG0_intr_enable,"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
line.long 0x14 "CFG0_intr_enable_clear,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
line.long 0x18 "CFG0_eoi,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip."
rgroup.long 0x1024++0xB
line.long 0x0 "CFG0_fault_address,"
hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address."
line.long 0x4 "CFG0_fault_type_status,"
bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1"
hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
line.long 0x8 "CFG0_fault_attr_status,"
hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID."
hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID."
hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID."
wgroup.long 0x1030++0x3
line.long 0x0 "CFG0_fault_clear,"
bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
rgroup.long 0x2000++0x3
line.long 0x0 "CFG0_PID_PROXY,"
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY,"
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY,"
bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY,"
rgroup.long 0x2008++0x3
line.long 0x0 "CFG0_MMR_CFG1_PROXY,"
bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing enabled" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions"
group.long 0x3008++0x1B
line.long 0x0 "CFG0_LOCK0_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK0_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component"
line.long 0x8 "CFG0_intr_raw_status_PROXY,"
bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
line.long 0xC "CFG0_intr_enabled_status_clear_PROXY,"
bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
line.long 0x10 "CFG0_intr_enable_PROXY,"
bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
line.long 0x14 "CFG0_intr_enable_clear_PROXY,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
line.long 0x18 "CFG0_eoi_PROXY,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip."
rgroup.long 0x3024++0xB
line.long 0x0 "CFG0_fault_address_PROXY,"
hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address."
line.long 0x4 "CFG0_fault_type_status_PROXY,"
bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1"
hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.."
line.long 0x8 "CFG0_fault_attr_status_PROXY,"
hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID."
hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID."
hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID."
wgroup.long 0x3030++0x3
line.long 0x0 "CFG0_fault_clear_PROXY,"
bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
group.long 0x4000++0x83
line.long 0x0 "CFG0_PADCONFIG0,"
bitfld.long 0x0 31. "PADCONFIG0_LOCK,Lock" "0,1"
bitfld.long 0x0 21. "PADCONFIG0_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x0 19.--20. "PADCONFIG0_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x0 17. "PADCONFIG0_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x0 16. "PADCONFIG0_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x0 14. "PADCONFIG0_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE,Pad functional signal mux selection"
line.long 0x4 "CFG0_PADCONFIG1,"
bitfld.long 0x4 31. "PADCONFIG1_LOCK,Lock" "0,1"
bitfld.long 0x4 21. "PADCONFIG1_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x4 14. "PADCONFIG1_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE,Pad functional signal mux selection"
line.long 0x8 "CFG0_PADCONFIG2,"
bitfld.long 0x8 31. "PADCONFIG2_LOCK,Lock" "0,1"
bitfld.long 0x8 21. "PADCONFIG2_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x8 14. "PADCONFIG2_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE,Pad functional signal mux selection"
line.long 0xC "CFG0_PADCONFIG3,"
bitfld.long 0xC 31. "PADCONFIG3_LOCK,Lock" "0,1"
bitfld.long 0xC 21. "PADCONFIG3_TX_DIS,Driver Disable" "0,1"
bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0xC 14. "PADCONFIG3_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE,Pad functional signal mux selection"
line.long 0x10 "CFG0_PADCONFIG4,"
bitfld.long 0x10 31. "PADCONFIG4_LOCK,Lock" "0,1"
bitfld.long 0x10 21. "PADCONFIG4_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x10 14. "PADCONFIG4_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE,Pad functional signal mux selection"
line.long 0x14 "CFG0_PADCONFIG5,"
bitfld.long 0x14 31. "PADCONFIG5_LOCK,Lock" "0,1"
bitfld.long 0x14 21. "PADCONFIG5_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x14 14. "PADCONFIG5_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE,Pad functional signal mux selection"
line.long 0x18 "CFG0_PADCONFIG6,"
bitfld.long 0x18 31. "PADCONFIG6_LOCK,Lock" "0,1"
bitfld.long 0x18 21. "PADCONFIG6_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x18 14. "PADCONFIG6_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE,Pad functional signal mux selection"
line.long 0x1C "CFG0_PADCONFIG7,"
bitfld.long 0x1C 31. "PADCONFIG7_LOCK,Lock" "0,1"
bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x1C 14. "PADCONFIG7_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE,Pad functional signal mux selection"
line.long 0x20 "CFG0_PADCONFIG8,"
bitfld.long 0x20 31. "PADCONFIG8_LOCK,Lock" "0,1"
bitfld.long 0x20 21. "PADCONFIG8_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x20 14. "PADCONFIG8_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE,Pad functional signal mux selection"
line.long 0x24 "CFG0_PADCONFIG9,"
bitfld.long 0x24 31. "PADCONFIG9_LOCK,Lock" "0,1"
bitfld.long 0x24 21. "PADCONFIG9_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x24 14. "PADCONFIG9_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE,Pad functional signal mux selection"
line.long 0x28 "CFG0_PADCONFIG10,"
bitfld.long 0x28 31. "PADCONFIG10_LOCK,Lock" "0,1"
bitfld.long 0x28 21. "PADCONFIG10_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x28 14. "PADCONFIG10_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE,Pad functional signal mux selection"
line.long 0x2C "CFG0_PADCONFIG11,"
bitfld.long 0x2C 31. "PADCONFIG11_LOCK,Lock" "0,1"
bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x2C 14. "PADCONFIG11_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE,Pad functional signal mux selection"
line.long 0x30 "CFG0_PADCONFIG12,"
bitfld.long 0x30 31. "PADCONFIG12_LOCK,Lock" "0,1"
bitfld.long 0x30 21. "PADCONFIG12_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x30 14. "PADCONFIG12_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE,Pad functional signal mux selection"
line.long 0x34 "CFG0_PADCONFIG13,"
bitfld.long 0x34 31. "PADCONFIG13_LOCK,Lock" "0,1"
bitfld.long 0x34 21. "PADCONFIG13_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x34 14. "PADCONFIG13_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG13_MUXMODE,Pad functional signal mux selection"
line.long 0x38 "CFG0_PADCONFIG14,"
bitfld.long 0x38 31. "PADCONFIG14_LOCK,Lock" "0,1"
bitfld.long 0x38 21. "PADCONFIG14_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x38 14. "PADCONFIG14_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG14_MUXMODE,Pad functional signal mux selection"
line.long 0x3C "CFG0_PADCONFIG15,"
bitfld.long 0x3C 31. "PADCONFIG15_LOCK,Lock" "0,1"
bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x3C 14. "PADCONFIG15_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG15_MUXMODE,Pad functional signal mux selection"
line.long 0x40 "CFG0_PADCONFIG16,"
bitfld.long 0x40 31. "PADCONFIG16_LOCK,Lock" "0,1"
bitfld.long 0x40 21. "PADCONFIG16_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x40 14. "PADCONFIG16_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG16_MUXMODE,Pad functional signal mux selection"
line.long 0x44 "CFG0_PADCONFIG17,"
bitfld.long 0x44 31. "PADCONFIG17_LOCK,Lock" "0,1"
bitfld.long 0x44 21. "PADCONFIG17_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x44 14. "PADCONFIG17_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG17_MUXMODE,Pad functional signal mux selection"
line.long 0x48 "CFG0_PADCONFIG18,"
bitfld.long 0x48 31. "PADCONFIG18_LOCK,Lock" "0,1"
bitfld.long 0x48 21. "PADCONFIG18_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x48 14. "PADCONFIG18_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG18_MUXMODE,Pad functional signal mux selection"
line.long 0x4C "CFG0_PADCONFIG19,"
bitfld.long 0x4C 31. "PADCONFIG19_LOCK,Lock" "0,1"
bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x4C 14. "PADCONFIG19_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG19_MUXMODE,Pad functional signal mux selection"
line.long 0x50 "CFG0_PADCONFIG20,"
bitfld.long 0x50 31. "PADCONFIG20_LOCK,Lock" "0,1"
bitfld.long 0x50 21. "PADCONFIG20_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x50 14. "PADCONFIG20_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG20_MUXMODE,Pad functional signal mux selection"
line.long 0x54 "CFG0_PADCONFIG21,"
bitfld.long 0x54 31. "PADCONFIG21_LOCK,Lock" "0,1"
bitfld.long 0x54 21. "PADCONFIG21_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x54 14. "PADCONFIG21_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG21_MUXMODE,Pad functional signal mux selection"
line.long 0x58 "CFG0_PADCONFIG22,"
bitfld.long 0x58 31. "PADCONFIG22_LOCK,Lock" "0,1"
bitfld.long 0x58 21. "PADCONFIG22_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x58 14. "PADCONFIG22_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG22_MUXMODE,Pad functional signal mux selection"
line.long 0x5C "CFG0_PADCONFIG23,"
bitfld.long 0x5C 31. "PADCONFIG23_LOCK,Lock" "0,1"
bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x5C 14. "PADCONFIG23_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG23_MUXMODE,Pad functional signal mux selection"
line.long 0x60 "CFG0_PADCONFIG24,"
bitfld.long 0x60 31. "PADCONFIG24_LOCK,Lock" "0,1"
bitfld.long 0x60 21. "PADCONFIG24_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x60 14. "PADCONFIG24_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG24_MUXMODE,Pad functional signal mux selection"
line.long 0x64 "CFG0_PADCONFIG25,"
bitfld.long 0x64 31. "PADCONFIG25_LOCK,Lock" "0,1"
bitfld.long 0x64 21. "PADCONFIG25_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x64 14. "PADCONFIG25_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG25_MUXMODE,Pad functional signal mux selection"
line.long 0x68 "CFG0_PADCONFIG26,"
bitfld.long 0x68 31. "PADCONFIG26_LOCK,Lock" "0,1"
bitfld.long 0x68 21. "PADCONFIG26_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x68 14. "PADCONFIG26_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG26_MUXMODE,Pad functional signal mux selection"
line.long 0x6C "CFG0_PADCONFIG27,"
bitfld.long 0x6C 31. "PADCONFIG27_LOCK,Lock" "0,1"
bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x6C 14. "PADCONFIG27_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG27_MUXMODE,Pad functional signal mux selection"
line.long 0x70 "CFG0_PADCONFIG28,"
bitfld.long 0x70 31. "PADCONFIG28_LOCK,Lock" "0,1"
bitfld.long 0x70 21. "PADCONFIG28_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x70 14. "PADCONFIG28_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG28_MUXMODE,Pad functional signal mux selection"
line.long 0x74 "CFG0_PADCONFIG29,"
bitfld.long 0x74 31. "PADCONFIG29_LOCK,Lock" "0,1"
bitfld.long 0x74 21. "PADCONFIG29_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x74 14. "PADCONFIG29_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG29_MUXMODE,Pad functional signal mux selection"
line.long 0x78 "CFG0_PADCONFIG30,"
bitfld.long 0x78 31. "PADCONFIG30_LOCK,Lock" "0,1"
bitfld.long 0x78 21. "PADCONFIG30_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x78 14. "PADCONFIG30_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG30_MUXMODE,Pad functional signal mux selection"
line.long 0x7C "CFG0_PADCONFIG31,"
bitfld.long 0x7C 31. "PADCONFIG31_LOCK,Lock" "0,1"
bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x7C 14. "PADCONFIG31_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG31_MUXMODE,Pad functional signal mux selection"
line.long 0x80 "CFG0_PADCONFIG32,"
bitfld.long 0x80 31. "PADCONFIG32_LOCK,Lock" "0,1"
bitfld.long 0x80 21. "PADCONFIG32_TX_DIS,Driver Disable" "0,1"
bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x80 14. "PADCONFIG32_ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG32_MUXMODE,Pad functional signal mux selection"
group.long 0x5008++0x7
line.long 0x0 "CFG0_LOCK1_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK1_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component"
rgroup.long 0x5100++0x7
line.long 0x0 "CFG0_CLAIMREG_P1_R0_READONLY,"
hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0_READONLY,Claim bits for Partition 1"
line.long 0x4 "CFG0_CLAIMREG_P1_R1_READONLY,"
hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1_READONLY,Claim bits for Partition 1"
group.long 0x6000++0x83
line.long 0x0 "CFG0_PADCONFIG0_PROXY,"
bitfld.long 0x0 31. "PADCONFIG0_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x0 21. "PADCONFIG0_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x0 19.--20. "PADCONFIG0_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x0 17. "PADCONFIG0_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x0 16. "PADCONFIG0_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x0 14. "PADCONFIG0_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x4 "CFG0_PADCONFIG1_PROXY,"
bitfld.long 0x4 31. "PADCONFIG1_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x4 21. "PADCONFIG1_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x4 14. "PADCONFIG1_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x8 "CFG0_PADCONFIG2_PROXY,"
bitfld.long 0x8 31. "PADCONFIG2_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x8 21. "PADCONFIG2_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x8 14. "PADCONFIG2_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0xC "CFG0_PADCONFIG3_PROXY,"
bitfld.long 0xC 31. "PADCONFIG3_LOCK_PROXY,Lock" "0,1"
bitfld.long 0xC 21. "PADCONFIG3_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0xC 14. "PADCONFIG3_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x10 "CFG0_PADCONFIG4_PROXY,"
bitfld.long 0x10 31. "PADCONFIG4_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x10 21. "PADCONFIG4_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x10 14. "PADCONFIG4_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x14 "CFG0_PADCONFIG5_PROXY,"
bitfld.long 0x14 31. "PADCONFIG5_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x14 21. "PADCONFIG5_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x14 14. "PADCONFIG5_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x18 "CFG0_PADCONFIG6_PROXY,"
bitfld.long 0x18 31. "PADCONFIG6_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x18 21. "PADCONFIG6_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x18 14. "PADCONFIG6_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x1C "CFG0_PADCONFIG7_PROXY,"
bitfld.long 0x1C 31. "PADCONFIG7_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x1C 14. "PADCONFIG7_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x20 "CFG0_PADCONFIG8_PROXY,"
bitfld.long 0x20 31. "PADCONFIG8_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x20 21. "PADCONFIG8_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x20 14. "PADCONFIG8_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x24 "CFG0_PADCONFIG9_PROXY,"
bitfld.long 0x24 31. "PADCONFIG9_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x24 21. "PADCONFIG9_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x24 14. "PADCONFIG9_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x28 "CFG0_PADCONFIG10_PROXY,"
bitfld.long 0x28 31. "PADCONFIG10_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x28 21. "PADCONFIG10_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x28 14. "PADCONFIG10_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x2C "CFG0_PADCONFIG11_PROXY,"
bitfld.long 0x2C 31. "PADCONFIG11_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x2C 14. "PADCONFIG11_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x30 "CFG0_PADCONFIG12_PROXY,"
bitfld.long 0x30 31. "PADCONFIG12_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x30 21. "PADCONFIG12_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x30 14. "PADCONFIG12_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x34 "CFG0_PADCONFIG13_PROXY,"
bitfld.long 0x34 31. "PADCONFIG13_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x34 21. "PADCONFIG13_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x34 14. "PADCONFIG13_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG13_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x38 "CFG0_PADCONFIG14_PROXY,"
bitfld.long 0x38 31. "PADCONFIG14_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x38 21. "PADCONFIG14_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x38 14. "PADCONFIG14_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG14_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x3C "CFG0_PADCONFIG15_PROXY,"
bitfld.long 0x3C 31. "PADCONFIG15_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x3C 14. "PADCONFIG15_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG15_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x40 "CFG0_PADCONFIG16_PROXY,"
bitfld.long 0x40 31. "PADCONFIG16_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x40 21. "PADCONFIG16_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x40 14. "PADCONFIG16_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG16_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x44 "CFG0_PADCONFIG17_PROXY,"
bitfld.long 0x44 31. "PADCONFIG17_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x44 21. "PADCONFIG17_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x44 14. "PADCONFIG17_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG17_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x48 "CFG0_PADCONFIG18_PROXY,"
bitfld.long 0x48 31. "PADCONFIG18_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x48 21. "PADCONFIG18_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x48 14. "PADCONFIG18_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG18_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x4C "CFG0_PADCONFIG19_PROXY,"
bitfld.long 0x4C 31. "PADCONFIG19_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x4C 14. "PADCONFIG19_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG19_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x50 "CFG0_PADCONFIG20_PROXY,"
bitfld.long 0x50 31. "PADCONFIG20_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x50 21. "PADCONFIG20_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x50 14. "PADCONFIG20_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG20_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x54 "CFG0_PADCONFIG21_PROXY,"
bitfld.long 0x54 31. "PADCONFIG21_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x54 21. "PADCONFIG21_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x54 14. "PADCONFIG21_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG21_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x58 "CFG0_PADCONFIG22_PROXY,"
bitfld.long 0x58 31. "PADCONFIG22_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x58 21. "PADCONFIG22_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x58 14. "PADCONFIG22_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG22_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x5C "CFG0_PADCONFIG23_PROXY,"
bitfld.long 0x5C 31. "PADCONFIG23_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x5C 14. "PADCONFIG23_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG23_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x60 "CFG0_PADCONFIG24_PROXY,"
bitfld.long 0x60 31. "PADCONFIG24_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x60 21. "PADCONFIG24_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x60 14. "PADCONFIG24_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG24_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x64 "CFG0_PADCONFIG25_PROXY,"
bitfld.long 0x64 31. "PADCONFIG25_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x64 21. "PADCONFIG25_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x64 14. "PADCONFIG25_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG25_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x68 "CFG0_PADCONFIG26_PROXY,"
bitfld.long 0x68 31. "PADCONFIG26_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x68 21. "PADCONFIG26_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x68 14. "PADCONFIG26_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG26_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x6C "CFG0_PADCONFIG27_PROXY,"
bitfld.long 0x6C 31. "PADCONFIG27_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x6C 14. "PADCONFIG27_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG27_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x70 "CFG0_PADCONFIG28_PROXY,"
bitfld.long 0x70 31. "PADCONFIG28_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x70 21. "PADCONFIG28_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x70 14. "PADCONFIG28_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG28_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x74 "CFG0_PADCONFIG29_PROXY,"
bitfld.long 0x74 31. "PADCONFIG29_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x74 21. "PADCONFIG29_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x74 14. "PADCONFIG29_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG29_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x78 "CFG0_PADCONFIG30_PROXY,"
bitfld.long 0x78 31. "PADCONFIG30_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x78 21. "PADCONFIG30_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x78 14. "PADCONFIG30_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG30_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x7C "CFG0_PADCONFIG31_PROXY,"
bitfld.long 0x7C 31. "PADCONFIG31_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x7C 14. "PADCONFIG31_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG31_MUXMODE_PROXY,Pad functional signal mux selection"
line.long 0x80 "CFG0_PADCONFIG32_PROXY,"
bitfld.long 0x80 31. "PADCONFIG32_LOCK_PROXY,Lock" "0,1"
bitfld.long 0x80 21. "PADCONFIG32_TX_DIS_PROXY,Driver Disable" "0,1"
bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE_PROXY,Input enable for the Pad" "0,1"
bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
newline
bitfld.long 0x80 14. "PADCONFIG32_ST_EN_PROXY,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG32_MUXMODE_PROXY,Pad functional signal mux selection"
group.long 0x7008++0x7
line.long 0x0 "CFG0_LOCK1_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK1_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component"
tree.end
tree "MCU_PLL0_CFG (MCU_PLL0_CFG)"
base ad:0x4040000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_pll0_PID,"
bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier"
hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number"
bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number"
rgroup.long 0x8++0x3
line.long 0x0 "CFG_pll0_CFG,"
hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3"
bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1"
bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3"
group.long 0x10++0x7
line.long 0x0 "CFG_pll0_LOCKKEY0,"
hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set  indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
line.long 0x4 "CFG_pll0_LOCKKEY1,"
hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers"
group.long 0x20++0x3
line.long 0x0 "CFG_pll0_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1"
bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1"
bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1"
bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1"
bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2  FOUT3  FOUT4 clocks are enabled." "0,1"
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bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV  4-phase and synchronous clocks are enabled." "0,1"
bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1"
bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "CFG_pll0_STAT,"
bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1"
group.long 0x30++0xB
line.long 0x0 "CFG_pll0_FREQ_CTRL0,"
hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.."
line.long 0x4 "CFG_pll0_FREQ_CTRL1,"
hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.."
line.long 0x8 "CFG_pll0_DIV_CTRL,"
bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation  post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63"
group.long 0x40++0x7
line.long 0x0 "CFG_pll0_SS_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1"
hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0"
bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1"
bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1"
line.long 0x4 "CFG_pll0_SS_SPREAD,"
hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63"
hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%"
group.long 0x60++0x3
line.long 0x0 "CFG_pll0_CAL_CTRL,"
bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1"
bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1"
bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0  this represents the initial condition for calibration. When cal_byp is 1'b1  this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.."
rgroup.long 0x64++0x3
line.long 0x0 "CFG_pll0_CAL_STAT,"
bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use"
hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration"
group.long 0x80++0x13
line.long 0x0 "CFG_pll0_HSDIV_CTRL0,"
bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x4 "CFG_pll0_HSDIV_CTRL1,"
bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x8 "CFG_pll0_HSDIV_CTRL2,"
bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0xC "CFG_pll0_HSDIV_CTRL3,"
bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x10 "CFG_pll0_HSDIV_CTRL4,"
bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
tree.end
tree "MCU_PSC0 (MCU_PSC0)"
base ad:0x4000000
rgroup.long 0x0++0x3
line.long 0x0 "VBUS_PID,The peripheral identification register is a constant register that contains the ID and ID revision number for that module. The PID stores version information used to identify the module. All bits within this register are read-only (writes have.."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
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hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release"
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
rgroup.long 0x10++0x7
line.long 0x0 "VBUS_GBLCTL,This register contains global control to PSC."
hexmask.long.byte 0x0 8.--15. 1. "IO_ANA_CTL,General purpose IO/Analog PowerDown control. Directly drives io_ana_pdctl_po[7:0] outputs."
line.long 0x4 "VBUS_GBLSTAT,This register shows the PSC global status."
hexmask.long.word 0x4 16.--27. 1. "EF_SMRFLEX,Smart reflex class0 bits"
bitfld.long 0x4 0. "OVRIDE,PSC Override Status" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "VBUS_INTEVAL,This register has no storage. Read from this register returns 0."
bitfld.long 0x0 19. "GOSET,GOSTAT Interrupt Set" "0,1"
bitfld.long 0x0 18. "EPCSET,External Power Control Interrupt Set" "0,1"
bitfld.long 0x0 17. "ERRSET,Combined Interrupt Set" "0,1"
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bitfld.long 0x0 2. "EPCEV,External Power Control Interrupt Set" "0,1"
bitfld.long 0x0 1. "ERREV,Re_evaluate Error Interrupt" "0,1"
bitfld.long 0x0 0. "ALLEV,Re_evaluate combined PSC interrupt" "0,1"
rgroup.long 0x40++0x3
line.long 0x0 "VBUS_MERRPR,This register records pending error conditions for all modules. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "M,Records pending error conditions. Each bit n represents a module."
group.long 0x50++0x3
line.long 0x0 "VBUS_MERRCR,This register has no storage. Read from this register returns 0. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "M,Write of 1 clears the corresponding MERRPR bit."
rgroup.long 0x60++0x3
line.long 0x0 "VBUS_PERRPR,This register records pending error conditions for each power domain. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "P,Power Domain n Error Condition. Each bit n represents a power domain."
group.long 0x68++0x3
line.long 0x0 "VBUS_PERRCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "P,Write of 1 clears the corresponding PERRPR bit."
rgroup.long 0x70++0x3
line.long 0x0 "VBUS_EPCPR,This register records pending external power control conditions. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "EPC,External Power Control Intervention Request for Power Domain n"
group.long 0x78++0x3
line.long 0x0 "VBUS_EPCCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "EPC,Write of 1 clears the corresponding EPCPR bit"
rgroup.long 0x100++0x3
line.long 0x0 "VBUS_RAILSTAT,This register is a read-only and shows the current rail requestor whose request is being granted and the current value of the counter associated with this requestor."
hexmask.long.byte 0x0 24.--28. 1. "RAILNUM,Indicates Current Rail Requestor being processed by GPSC"
hexmask.long.byte 0x0 0.--7. 1. "RAILCNT,Indicates the current rail counter value"
group.long 0x104++0x7
line.long 0x0 "VBUS_RAILCTL,This register is user programmable. It holds the counter values for rail counter. User can select one of the two counter values to be used for each power domain (see RAILSEL register)."
hexmask.long.byte 0x0 8.--15. 1. "RAILCTR1,Rail Counter Value 1"
hexmask.long.byte 0x0 0.--7. 1. "RAILCTR0,Rail Counter Value 0"
line.long 0x4 "VBUS_RAILSEL,User can use this register to select the counter value (RAILCTL) for each power domain."
hexmask.long 0x4 0.--31. 1. "P,Rail Counter Select for Power Domain"
group.long 0x120++0x3
line.long 0x0 "VBUS_PTCMD,This is a pseudo-command register with no actual storage. Reads return 0. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "GO,Power Domain n GO Transition"
rgroup.long 0x128++0x3
line.long 0x0 "VBUS_PTSTAT,This is a status register. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "GOSTAT,Power Domain n Transition Command Status"
rgroup.long 0x200++0x3
line.long 0x0 "VBUS_PDSTAT,This is a status register. One register per power domain. Each register contains the status for the given power domain."
bitfld.long 0x0 11. "EMUIHB,Emulation Alters Domain State" "0,1"
bitfld.long 0x0 10. "PWRBAD,Power Bad error" "0,1"
bitfld.long 0x0 9. "PORDONE,POR Done Input Status" "0,1"
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bitfld.long 0x0 8. "PORZ,PORz output actual status" "0,1"
hexmask.long.byte 0x0 0.--4. 1. "STATE,Current Power Domain State"
group.long 0x300++0x3
line.long 0x0 "VBUS_PDCTL,This is a control register. One register per power domain."
bitfld.long 0x0 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x0 29. "PWRSW,Power shorting Switch Control" "0,1"
bitfld.long 0x0 28. "ISO,Isolation Cell control" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "WAKECNT,RAM wake count delay value"
bitfld.long 0x0 12.--14. "PDMODE,Power Down mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 9. "EMUIHBIE,Emulation alters domain state" "0,1"
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bitfld.long 0x0 8. "EPCGOOD,External Power Control Power Good Indication" "0,1"
bitfld.long 0x0 0. "NEXT,User_Desired Next Power Domain State" "0,1"
rgroup.long 0x400++0x3
line.long 0x0 "VBUS_PDCFG,This is a status register. It shows PSC settings for easy debug."
bitfld.long 0x0 3. "ICEPICK,Icepick support" "0,1"
bitfld.long 0x0 1. "MEMSLPKWK,Memory sleep-wake domain" "0,1"
bitfld.long 0x0 0. "ALWAYSON,Always on power domain" "0,1"
rgroup.long 0x600++0x3
line.long 0x0 "VBUS_MDCFG,This is a constant register showing some PSC settings for easy debug. This register is read only."
hexmask.long.byte 0x0 16.--20. 1. "PWRDOM,Indicates which power domain this module belongs to"
bitfld.long 0x0 15. "AUTOONLY,0: This LPSC supports all modes  1: This LPSC supports Enable  AutoSleep or AutoWake only" "0: This LPSC supports all modes,1: This LPSC supports Enable"
bitfld.long 0x0 14. "RESETISO,0: This LPSC does not support Reset Isolation  1: This LPSC supports Reset Isolation" "0: This LPSC does not support Reset Isolation,1: This LPSC supports Reset Isolation"
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bitfld.long 0x0 13. "NEXTLOCK,0: MDCTL.NEXT field is writable  1: MDCTL.NEXT field is locked" "0: MDCTL,1: MDCTL"
bitfld.long 0x0 12. "ASYNC,Async Lpsc" "0,1"
bitfld.long 0x0 11. "ICEPICK,IcePick support" "0,1"
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bitfld.long 0x0 10. "PERMDIS,Permanently disable" "0,1"
bitfld.long 0x0 9. "PLLHANDSHAKE,RTL parameter PLL_HANDSHAKE" "0,1"
bitfld.long 0x0 6.--8. "NUMSCRDISBALE,Number of PWR_SCR_DISABLE interfaces required on LPSC" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 3.--5. "NUMCLKEN,Number of PWR_CLK_EN interfaces required on LPSC" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "NUMCLK,Number of PWR_CLKSTOP interfaces required on LPSC" "0,1,2,3,4,5,6,7"
rgroup.long 0x800++0x3
line.long 0x0 "VBUS_MDSTAT,This register shows the status of each module. Requires one register per module on the device."
bitfld.long 0x0 17. "EMUIHB,Emulation Alters Module State. Inhibits Module Inactive or Force Module Active." "0,1"
bitfld.long 0x0 16. "EMURST,Emulation Alters Reset" "0,1"
bitfld.long 0x0 12. "MCKOUT,Actual modclk output to module" "0,1"
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bitfld.long 0x0 11. "MRSTDONE,Module reset initialization done status" "0,1"
bitfld.long 0x0 10. "MRSTZ,Module reset actual status" "0,1"
bitfld.long 0x0 9. "LRSTDONE,Module local reset initialization done status" "0,1"
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bitfld.long 0x0 8. "LRSTZ,Module local reset actual status" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "STATE,These bits indicate the current module state"
group.long 0xA00++0x3
line.long 0x0 "VBUS_MDCTL,This register provides specific control for the individual module. One register per module on the device."
bitfld.long 0x0 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x0 12. "RESETISO,Reset Isolation" "0,1"
bitfld.long 0x0 11. "BLKCHIP1RST,Block Chip_1_Reset" "0,1"
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bitfld.long 0x0 10. "EMUIHBIE,Emulation Alters Module State. Inhibits Module Inactive or Force Module Active." "0,1"
bitfld.long 0x0 9. "EMURSTIE,Emulation Alter Reset Interrupt Enable" "0,1"
bitfld.long 0x0 8. "LRSTZ,Module local reset control" "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "NEXT,Module Next State"
tree.end
tree "MCU_RTI0_CFG (MCU_RTI0_CFG)"
base ad:0x4880000
group.long 0x0++0x1B
line.long 0x0 "CFG_GCTRL,"
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.."
bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode"
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bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
line.long 0x4 "CFG_TBCTRL,"
bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0  Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
line.long 0x8 "CFG_CAPCTRL,"
bitfld.long 0x8 1. "CAPCNTR1,This bit determines  which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
bitfld.long 0x8 0. "CAPCNTR0,This bit determines  which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
line.long 0xC "CFG_COMPCTRL,"
bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register."
line.long 0x14 "CFG_UC0,"
hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x18 "CFG_CPUC0,"
hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value  which is compared with the Up Counter 0. When the compare matches  Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
rgroup.long 0x20++0x7
line.long 0x0 "CFG_CAFRC0,"
hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
line.long 0x4 "CFG_CAUC0,"
hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.."
group.long 0x30++0xB
line.long 0x0 "CFG_FRC1,"
hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register."
line.long 0x4 "CFG_UC1,"
hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x8 "CFG_CPUC1,"
hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value  which is compared with the Up Counter 1. When the compare matches  Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
rgroup.long 0x40++0x7
line.long 0x0 "CFG_CAFRC1,"
hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
line.long 0x4 "CFG_CAUC1,"
hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.."
group.long 0x50++0x27
line.long 0x0 "CFG_COMP0,"
hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x4 "CFG_UDCP0,"
hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value  which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x8 "CFG_COMP1,"
hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0xC "CFG_UDCP1,"
hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value  which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x10 "CFG_COMP2,"
hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x14 "CFG_UDCP2,"
hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value  which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x18 "CFG_COMP3,"
hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x1C "CFG_UDCP3,"
hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value  which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x20 "CFG_TBLCOMP,"
hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.."
line.long 0x24 "CFG_TBHCOMP,"
hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0  since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.."
group.long 0x80++0xB
line.long 0x0 "CFG_SETINT,"
bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
line.long 0x4 "CFG_CLEARINT,"
bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
line.long 0x8 "CFG_INTFLAG,"
bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
group.long 0x90++0xF
line.long 0x0 "CFG_DWDCTRL,"
hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.."
line.long 0x4 "CFG_DWDPRLD,"
hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.."
line.long 0x8 "CFG_WDSTATUS,"
bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated  or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
line.long 0xC "CFG_WDKEY,"
hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.."
rgroup.long 0xA0++0x3
line.long 0x0 "CFG_DWDCNTR,"
hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz  a watchdog reset will be generated in 1 second. User and.."
group.long 0xA4++0x1B
line.long 0x0 "CFG_WWDRXNCTRL,"
hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read)  privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration  or if the watchdog is not.."
line.long 0x4 "CFG_WWDSIZECTRL,"
hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read)  privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).."
line.long 0x8 "CFG_INTCLRENABLE,"
hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.."
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hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.."
line.long 0xC "CFG_COMP0CLR,"
hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 0 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x10 "CFG_COMP1CLR,"
hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 1 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x14 "CFG_COMP2CLR,"
hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 2 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x18 "CFG_COMP3CLR,"
hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 3 interrupt or DMA request line is cleared. User and privilege.."
tree.end
tree "MCU_TIMEOUT0_CFG (MCU_TIMEOUT0_CFG)"
base ad:0x4300000
rgroup.long 0x0++0xB
line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket."
hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard"
hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard"
line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket."
hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard"
hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard"
group.long 0xC++0xF
line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable."
hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled  All other values - Enabled."
line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control."
rbitfld.long 0x4 31. "EXT_FL,External Flush Value" "0,1"
hexmask.long.byte 0x4 0.--3. 1. "FL,Enable. 4'b1111 - Flush  All other values - Normal."
line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions."
hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon."
line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer."
rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3"
hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer"
group.long 0x20++0x17
line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits"
bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1"
bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1"
bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1"
line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits"
bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1"
bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1"
bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1"
line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits"
bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1"
bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1"
bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1"
line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits"
bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1"
bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1"
bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1"
line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts"
bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3"
line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts"
bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3"
rgroup.long 0x38++0x13
line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt"
hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator"
hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator"
bitfld.long 0x0 2. "DIR,Direction Indicator" "0,1"
bitfld.long 0x0 1. "TYP,Type Indicator" "0,1"
bitfld.long 0x0 0. "VAL,Valid Indicator" "0,1"
line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt"
hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator"
hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator"
line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt"
hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt"
hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt"
line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt"
hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the Address"
line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt"
hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the Address"
tree.end
tree "MCU_TIMER0_CFG (MCU_TIMER0_CFG)"
base ad:0x4800000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_TIMER1_CFG (MCU_TIMER1_CFG)"
base ad:0x4810000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_TIMER2_CFG (MCU_TIMER2_CFG)"
base ad:0x4820000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_TIMER3_CFG (MCU_TIMER3_CFG)"
base ad:0x4830000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_UART0 (MCU_UART0)"
base ad:0x4A00000
group.long 0x0++0x3
line.long 0x0 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register"
group.long 0x0++0x7
line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x4 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.."
bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x7
line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "CTS_IT," "0,1"
newline
bitfld.long 0x0 6. "RTS_IT," "0,1"
newline
bitfld.long 0x0 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x0 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x0 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x0 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
line.long 0x4 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i"
newline
bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level  TCR[3:0]  is reached  and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i"
newline
bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable"
newline
bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7. 1: Enables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7"
newline
hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options"
group.long 0x8++0x3
line.long 0x0 "MEM_FCR,Notes:"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000  RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?"
newline
bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000  TX_FIFO_TRIG is not considered. If SCR[6]=1  TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?"
newline
bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1"
newline
bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 0. "FIFO_EN," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3"
newline
hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,"
newline
bitfld.long 0x0 0. "IT_PENDING," "0,1"
group.long 0xC++0x7
line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "DIV_EN," "0,1"
newline
bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1"
newline
bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0  the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1  the parity bit is forced to 0 in the transmitted and received.." "0,1"
newline
bitfld.long 0x0 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x0 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1"
newline
bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3"
line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x4 7. "RESERVED," "0,1"
newline
bitfld.long 0x4 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x4 5. "XON_EN," "0,1"
newline
bitfld.long 0x4 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x4 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x4 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1"
newline
bitfld.long 0x4 0. "DTR," "0,1"
group.long 0x10++0x3
line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes."
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_CIR,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "RESERVED," "0,1"
newline
bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_IRDA,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x0 3. "ABORT," "0,1"
newline
bitfld.long 0x0 2. "CRC," "0,1"
newline
bitfld.long 0x0 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_UART,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x0 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x0 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x0 4. "RX_BI," "0,1"
newline
bitfld.long 0x0 3. "RX_FE," "0,1"
newline
bitfld.long 0x0 2. "RX_PE," "0,1"
newline
bitfld.long 0x0 1. "RX_OE," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x3
line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes."
rgroup.long 0x18++0x3
line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1"
newline
bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1"
newline
bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode  it is equivalent to MCR[0]" "0,1"
newline
bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1"
newline
bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1"
newline
bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1"
newline
bitfld.long 0x0 1. "DSR_STS," "0,1"
newline
bitfld.long 0x0 0. "CTS_STS," "0,1"
group.long 0x18++0x3
line.long 0x0 "MEM_TCR,Transmission Control Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)"
newline
hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)"
group.long 0x18++0x7
line.long 0x0 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes."
line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x3
line.long 0x0 "MEM_TLR,Trigger Level Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level"
group.long 0x1C++0xB
line.long 0x0 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes."
line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1"
newline
bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1"
newline
bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1"
newline
bitfld.long 0x4 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1"
newline
bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3"
newline
bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1"
newline
bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3"
newline
rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs  the meaning of the interrupt is :" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "MEM_SFLSR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0 0. "RESERVED0," "0,1"
group.long 0x28++0x3
line.long 0x0 "MEM_TXFLL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x7
line.long 0x0 "MEM_TXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length"
line.long 0x4 "MEM_RXFLL,IrDA modes only."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x0 "MEM_SFREGL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length"
group.long 0x34++0x3
line.long 0x0 "MEM_RXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception"
rgroup.long 0x34++0x3
line.long 0x0 "MEM_SFREGH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length"
group.long 0x38++0x3
line.long 0x0 "MEM_BLR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1"
newline
bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1"
newline
hexmask.long.byte 0x0 0.--5. 1. "RESERVED,"
rgroup.long 0x38++0x3
line.long 0x0 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?"
newline
bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified"
newline
hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.."
group.long 0x3C++0xF
line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1"
newline
bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1"
newline
bitfld.long 0x0 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1  garbage data is sent over TX line." "0,1"
newline
bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission  the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1"
newline
bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1"
newline
bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1  UART IrDA will start a new transfer.." "0,1"
newline
bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1"
line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 5. "DSR_IT," "0,1"
newline
bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1"
line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x8 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1"
line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs  the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.."
rgroup.long 0x50++0x3
line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned"
bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module"
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module."
group.long 0x54++0x3
line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1"
newline
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "MEM_SYSS,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1"
group.long 0x5C++0x7
line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.."
rgroup.long 0x64++0x7
line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,"
line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,"
group.long 0x6C++0xB
line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x0 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1"
newline
bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1"
line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x4 2.--7. 1. "RESERVED,"
newline
bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6."
rgroup.long 0x78++0x7
line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused"
hexmask.long 0x0 0.--31. 1. "RESERVED,"
line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused"
hexmask.long 0x4 0.--31. 1. "RESERVED,"
group.long 0x80++0x23
line.long 0x0 "MEM_MDR3,Mode definition register 3."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0  RX: RTS=1. 1 => TX: RTS=1  RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1"
newline
bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
line.long 0x8 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x8 7. "RESERVED," "0,1"
newline
bitfld.long 0x8 6. "MODE9,9-bit character length. When '1'  overrides character length setting in LCR" "0,1"
newline
bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values  as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "MODE,New modes [when set  overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0xC "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode  when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set  signaling an address" "0,1"
line.long 0x14 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes  useful when comunicating with slower devices"
line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Lower byte of the 16 bit value]"
line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Higher byte of the 16 bit value]"
line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned  the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving  even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character  if the receiver did not acknowledge. If not acknowledged after the max value is reached  the USART transmitter will set parity error  stop and not continue until it is cleared." "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x0 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0xF
line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x4 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x8 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree "MCU_UART1 (MCU_UART1)"
base ad:0x4A10000
group.long 0x0++0x3
line.long 0x0 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register"
group.long 0x0++0x7
line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x4 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.."
bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x7
line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "CTS_IT," "0,1"
newline
bitfld.long 0x0 6. "RTS_IT," "0,1"
newline
bitfld.long 0x0 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x0 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x0 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x0 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
line.long 0x4 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i"
newline
bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level  TCR[3:0]  is reached  and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i"
newline
bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable"
newline
bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7. 1: Enables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7"
newline
hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options"
group.long 0x8++0x3
line.long 0x0 "MEM_FCR,Notes:"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000  RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?"
newline
bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000  TX_FIFO_TRIG is not considered. If SCR[6]=1  TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?"
newline
bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1"
newline
bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 0. "FIFO_EN," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3"
newline
hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,"
newline
bitfld.long 0x0 0. "IT_PENDING," "0,1"
group.long 0xC++0x7
line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "DIV_EN," "0,1"
newline
bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1"
newline
bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0  the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1  the parity bit is forced to 0 in the transmitted and received.." "0,1"
newline
bitfld.long 0x0 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x0 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1"
newline
bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3"
line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x4 7. "RESERVED," "0,1"
newline
bitfld.long 0x4 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x4 5. "XON_EN," "0,1"
newline
bitfld.long 0x4 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x4 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x4 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1"
newline
bitfld.long 0x4 0. "DTR," "0,1"
group.long 0x10++0x3
line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes."
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_CIR,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "RESERVED," "0,1"
newline
bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_IRDA,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x0 3. "ABORT," "0,1"
newline
bitfld.long 0x0 2. "CRC," "0,1"
newline
bitfld.long 0x0 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_UART,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x0 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x0 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x0 4. "RX_BI," "0,1"
newline
bitfld.long 0x0 3. "RX_FE," "0,1"
newline
bitfld.long 0x0 2. "RX_PE," "0,1"
newline
bitfld.long 0x0 1. "RX_OE," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x3
line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes."
rgroup.long 0x18++0x3
line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1"
newline
bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1"
newline
bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode  it is equivalent to MCR[0]" "0,1"
newline
bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1"
newline
bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1"
newline
bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1"
newline
bitfld.long 0x0 1. "DSR_STS," "0,1"
newline
bitfld.long 0x0 0. "CTS_STS," "0,1"
group.long 0x18++0x3
line.long 0x0 "MEM_TCR,Transmission Control Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)"
newline
hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)"
group.long 0x18++0x7
line.long 0x0 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes."
line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x3
line.long 0x0 "MEM_TLR,Trigger Level Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level"
group.long 0x1C++0xB
line.long 0x0 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes."
line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1"
newline
bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1"
newline
bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1"
newline
bitfld.long 0x4 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1"
newline
bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3"
newline
bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1"
newline
bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3"
newline
rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs  the meaning of the interrupt is :" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "MEM_SFLSR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0 0. "RESERVED0," "0,1"
group.long 0x28++0x3
line.long 0x0 "MEM_TXFLL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x7
line.long 0x0 "MEM_TXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length"
line.long 0x4 "MEM_RXFLL,IrDA modes only."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x0 "MEM_SFREGL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length"
group.long 0x34++0x3
line.long 0x0 "MEM_RXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception"
rgroup.long 0x34++0x3
line.long 0x0 "MEM_SFREGH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length"
group.long 0x38++0x3
line.long 0x0 "MEM_BLR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1"
newline
bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1"
newline
hexmask.long.byte 0x0 0.--5. 1. "RESERVED,"
rgroup.long 0x38++0x3
line.long 0x0 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?"
newline
bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified"
newline
hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.."
group.long 0x3C++0xF
line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1"
newline
bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1"
newline
bitfld.long 0x0 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1  garbage data is sent over TX line." "0,1"
newline
bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission  the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1"
newline
bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1"
newline
bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1  UART IrDA will start a new transfer.." "0,1"
newline
bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1"
line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 5. "DSR_IT," "0,1"
newline
bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1"
line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x8 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1"
line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs  the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.."
rgroup.long 0x50++0x3
line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned"
bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module"
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module."
group.long 0x54++0x3
line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1"
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bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "MEM_SYSS,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1"
group.long 0x5C++0x7
line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
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bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
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bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1"
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bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1"
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bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.."
rgroup.long 0x64++0x7
line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,"
line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,"
group.long 0x6C++0xB
line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x0 3.--7. 1. "RESERVED,"
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bitfld.long 0x0 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1"
newline
bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1"
line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x4 2.--7. 1. "RESERVED,"
newline
bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6."
rgroup.long 0x78++0x7
line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused"
hexmask.long 0x0 0.--31. 1. "RESERVED,"
line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused"
hexmask.long 0x4 0.--31. 1. "RESERVED,"
group.long 0x80++0x23
line.long 0x0 "MEM_MDR3,Mode definition register 3."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0  RX: RTS=1. 1 => TX: RTS=1  RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1"
newline
bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
line.long 0x8 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x8 7. "RESERVED," "0,1"
newline
bitfld.long 0x8 6. "MODE9,9-bit character length. When '1'  overrides character length setting in LCR" "0,1"
newline
bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values  as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "MODE,New modes [when set  overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0xC "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode  when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set  signaling an address" "0,1"
line.long 0x14 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes  useful when comunicating with slower devices"
line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Lower byte of the 16 bit value]"
line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Higher byte of the 16 bit value]"
line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned  the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving  even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character  if the receiver did not acknowledge. If not acknowledged after the max value is reached  the USART transmitter will set parity error  stop and not continue until it is cleared." "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x0 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0xF
line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x4 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x8 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree.end
tree "MMCSD0"
base ad:0x0
tree "MMCSD0_CTL_CFG (MMCSD0_CTL_CFG)"
base ad:0xFA10000
group.word 0x0++0xF
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_lo,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
hexmask.word 0x0 0.--15. 1. "SDMA_ADDRESS,When Host Version 4 Enable is set to 0 in the Host Control 2 register DMA uses this register as system address in only 32-bit addressing mode. Auto CMD23 cannot be used with SDMA. When Host Version 4 Enable is set to 1  SDMA uses ADMA System.."
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_hi,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
hexmask.word 0x2 0.--15. 1. "SDMA_ADDRESS,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_block_size,This register is used to configure the number of bytes in a data block"
bitfld.word 0x4 12.--14. "SDMA_BUF_SIZE,To perform long DMA transfer  System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary.." "0,1,2,3,4,5,6,7"
newline
hexmask.word 0x4 0.--11. 1. "XFER_BLK_SIZE,This field specifies the block size for block data transfers for CMD17  CMD18  CMD24  CMD25 and CMD53. It can be accessed only if no transaction is executing [i.e after a transaction has stopped]. Read operations during transfer return an.."
line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_block_count,This register is used to configure the number of data blocks"
hexmask.word 0x6 0.--15. 1. "XFER_BLK_CNT,Host Controller Version 4.10 extends block count to 32-bit [Refer to Section 1.15].Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: [1] If Host Version 4 Enable in the Host Control 2.."
line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_lo,This register contains Lower bits of SD Command Argument"
hexmask.word 0x8 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit23-8 of Command-Format."
line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_hi,This register contains higher bits of SD Command Argument"
hexmask.word 0xA 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit39-24 of Command-Format."
line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_transfer_mode,This register is used to control the operations of data transfers"
bitfld.word 0xC 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command Complete.." "0,1"
newline
bitfld.word 0xC 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.If Host Driver checks response error  this bit is set to 0 and Response Interrupt.." "0,1"
newline
bitfld.word 0xC 6. "RESP_TYPE,When response error check is enabled  this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO." "0,1"
newline
bitfld.word 0xC 5. "MULTI_BLK_SEL,This bit enables multiple block data transfers." "0,1"
newline
bitfld.word 0xC 4. "DATA_XFER_DIR,This bit defines the direction of data transfers." "0,1"
newline
bitfld.word 0xC 2.--3. "AUTO_CMD_ENA,There are three methods to stop Multiple-block read and write operation. [1] Auto CMD12 Enable: Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 01b  the Host.." "0,1,2,3"
newline
bitfld.word 0xC 1. "BLK_CNT_ENA,This bit is used to enable the Block count register  which is only relevant for multiple block transfers. When this bit is 0  the Block Count register is disabled  which is useful in executing an infinite transfer." "0,1"
newline
bitfld.word 0xC 0. "DMA_ENA,DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1  a DMA operation shall begin when the HD writes to the upper byte of Command register [00Fh]." "0,1"
line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_command,This register is used to program the Command for host controller"
hexmask.word.byte 0xE 8.--13. 1. "CMD_INDEX,This bit shall be set to the command number [CMD0-63  ACMD0-63]."
newline
bitfld.word 0xE 6.--7. "CMD_TYPE,There are three types of special commands. Suspend  Resume andAbort. These bits shall bet set to 00b for all other commands. Suspend Command: If the Suspend command succeeds  the HC shall assume the SD Bus has been released and that it is.." "0,1,2,3"
newline
bitfld.word 0xE 5. "DATA_PRESENT,This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 1. Commands using only CMD line [ex. CMD52]. 2. Commands with no data transferbut using busy.." "0,1"
newline
bitfld.word 0xE 4. "CMD_INDEX_CHK_ENA,If this bit is set to 1  the HC shall check the index field in the response to see if it has the same value as the command index. If it is not  it is reported as a Command Index Error. If this bit is set to 0  the Index field is not.." "0,1"
newline
bitfld.word 0xE 3. "CMD_CRC_CHK_ENA,If this bit is set to 1  the HC shall check the CRC field in the response. If an error is detected  it is reported as a Command CRC Error. If this bit is set to 0  the CRC field is not checked." "0,1"
newline
bitfld.word 0xE 2. "SUB_CMD,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]. When issuing a main com-mand  this bit is set to 0 and when issuing a sub command  this bit is set to 1. Setting of this bit is checked.." "0,1"
newline
bitfld.word 0xE 0.--1. "RESP_TYPE_SEL,Response Type Select." "0,1,2,3"
rgroup.word 0x10++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_response,This register is used to store responses from SD Cards"
hexmask.word 0x0 0.--15. 1. "CMD_RESP,R[] refers to a bit range within the response data as transmitted on the SD Bus  REP[] refers to a bit range within the Response register."
group.long 0x20++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_data_port,This register is used to access internal buffer"
hexmask.long 0x0 0.--31. 1. "BUF_RD_DATA,The Host Controller Buffer can be accessed through this 32-bit Data Port Register."
rgroup.long 0x24++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_presentstate,The Host Driver can get status of the Host Controller from this 32-bit read-only register"
bitfld.long 0x0 31. "UHS2_IF_DETECTION,This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 regis-ter. UHS-II interface initialization is activated by setting SD Clock Enable in the.." "0,1"
newline
bitfld.long 0x0 30. "UHS2_IF_LANE_SYNC,This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On detecting UHS-II Interface [D31=1]  Host Controller provides SYN.." "0,1"
newline
bitfld.long 0x0 29. "UHS2_DORMANT,This status indicates whether UHS-II Ianes enterDormant state. This function is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On issuing GO_DORMAT_STATE com-mand  Go Dormant Command [111b]; is set to Command.." "0,1"
newline
bitfld.long 0x0 28. "SUB_COMMAND_STS,The Command register and Response register are commonly used for main command and sub command. This status is used to distinguish which response error statuses  main command or sub command  indicated in the Error Interrupt Status.." "0,1"
newline
bitfld.long 0x0 27. "CMD_NOT_ISS_BY_ERR,Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error. [Equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the Auto CMD Error.." "0,1"
newline
bitfld.long 0x0 24. "SDIF_CMDIN,This status is used to check DAT line level to recover from errors  and for debugging." "0,1"
newline
bitfld.long 0x0 23. "SDIF_DAT3IN,This status is used to check DAT line level to recover from errors  and for debugging. This is especially useful in detecting the busy signal level from DAT[3]." "0,1"
newline
bitfld.long 0x0 22. "SDIF_DAT2IN,This status is used to check DAT line level to recover from errors  and for debugging. This is especially useful in detecting the busy signal level from DAT[2]." "0,1"
newline
bitfld.long 0x0 21. "SDIF_DAT1IN,This status is used to check DAT line level to recover from errors  and for debugging. This is especially useful in detecting the busy signal level from DAT[1]." "0,1"
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bitfld.long 0x0 20. "SDIF_DAT0IN,This status is used to check DAT line level to recover from errors  and for debugging. This is especially useful in detecting the busy signal level from DAT[0]." "0,1"
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bitfld.long 0x0 19. "WRITE_PROTECT,The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin." "0,1"
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bitfld.long 0x0 18. "CARD_DETECT,This bit reflects the inverse value of the SDCD# pin. '0' No Card present [SDCD# = 1] '1' Card present [SDCD# = 0]" "0,1"
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bitfld.long 0x0 17. "CARD_STATE_STABLE,This bit is used for testing. If it is 0  the Card Detect Pin Level is not stable. If this bit is set to 1 it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this.." "0,1"
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bitfld.long 0x0 16. "CARD_INSERTED,This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt.." "0,1"
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bitfld.long 0x0 11. "BUF_RD_ENA,This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1  readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the.." "0,1"
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bitfld.long 0x0 10. "BUF_WR_ENA,This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data. If this bit is 1  data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written.." "0,1"
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bitfld.long 0x0 9. "RD_XFER_ACTIVE,This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: After the end bit of the read command. When writing a 1 to continue Request in the Block.." "0,1"
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bitfld.long 0x0 8. "WR_XFER_ACTIVE,This status indicates a write transfer is active. If this bit is 0  it means no valid write data exists in the HC. This bit is set in either of the following cases: After the end bit of the write command. When writing a.." "0,1"
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bitfld.long 0x0 7. "SDIF_DAT7IN,This status is used to check DAT line level to recover from errors  and for debugging." "0,1"
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bitfld.long 0x0 6. "SDIF_DAT6IN,This status is used to check DAT line level to recover from errors  and for debugging." "0,1"
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bitfld.long 0x0 5. "SDIF_DAT5IN,This status is used to check DAT line level to recover from errors  and for debugging." "0,1"
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bitfld.long 0x0 4. "SDIF_DAT4IN,This status is used to check DAT line level to recover from errors  and for debugging." "0,1"
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bitfld.long 0x0 3. "RETUNING_REQ,Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is.." "0,1"
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bitfld.long 0x0 2. "DATA_LINE_ACTIVE,This bit indicates whether one of the DAT line on SD bus is in use." "0,1"
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bitfld.long 0x0 1. "INHIBIT_DAT,This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0  it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit [DAT] [ex. R1b  R5b.." "0,1"
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bitfld.long 0x0 0. "INHIBIT_CMD,SD Mode If this bit is 0  it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register [00Fh] is written. This bit is cleared when the command response is.." "0,1"
group.byte 0x28++0x3
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control1,This register is used to program DMA modes. LED Control. Data Transfer Width. High Speed Enable. Card detect test level and signal selection"
bitfld.byte 0x0 7. "CD_SIG_SEL,This bit selects source for card detection. '0' SDCD# is selected [for normal use] '1' The card detect test level is selected" "0,1"
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bitfld.byte 0x0 6. "CD_TEST_LEVEL,This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates [card ins or card removal] interrupt when the normal int sts enable bit is set. '0' No Card '1' Card Inserted" "0,1"
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bitfld.byte 0x0 5. "EXT_DATA_WIDTH,This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode  this bit may be set to 1. If this bit.." "0,1"
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bitfld.byte 0x0 3.--4. "DMA_SELECT,This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the Capabilities register. Selected DMA is enabled by DMA Enable of the Transfer Mode register in SD mode and DMA Enable of UHS-II Transfer.." "0,1,2,3"
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bitfld.byte 0x0 2. "HIGH_SPEED_ENA,This bit is optional. Before setting this bit  the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 [default]  the HC outputs CMD line and DAT lines at the falling edge of the SD clock [up to.." "0,1"
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bitfld.byte 0x0 1. "DATA_WIDTH,This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode." "0,1"
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bitfld.byte 0x0 0. "LED_CONTROL,This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands  this bit can be set during all transactions. It is not necessary to change for each.." "0,1"
line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_power_control,This register is used to program the SD Bus power and voltage level"
bitfld.byte 0x1 5.--7. "UHS2_VOLTAGE,This field determines supply voltage range to VDD2. This field can be set to 101b if 1.8V VDD2 Support in the Capabilities register is set to 1. '000' VDD2 Not supported '001'- '011' Reserved '100' Reserved for 1.2V.." "0,1,2,3,4,5,6,7"
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bitfld.byte 0x1 4. "UHS2_POWER,Setting this bit enables providing VDD2. '0' Power Off '1' Power On" "0,1"
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bitfld.byte 0x1 1.--3. "SD_BUS_VOLTAGE,By setting these bits  the HD selects the voltage level for the SD card. Before setting this register  the HD shall check the voltage support bits in the capabilities register. If an unsupported voltage is selected  the Host System shall.." "0,1,2,3,4,5,6,7"
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bitfld.byte 0x1 0. "SD_BUS_POWER,Before setting this bit  the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State  this bit shall be cleared. If this bit is cleared  the Host Control-ler should immediately stop driving CMD and DAT[3:0].." "0,1"
line.byte 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_block_gap_control,This register is used to program the block gap request. read wait control and interrupt at block gap"
bitfld.byte 0x2 7. "BOOT_ACK_ENA,To check for the boot acknowledge in boot operation." "0,1"
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bitfld.byte 0x2 6. "ALT_BOOT_MODE,To start boot code access in alternative mode." "0,1"
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bitfld.byte 0x2 5. "BOOT_ENABLE,To start boot code access." "0,1"
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bitfld.byte 0x2 4. "SPI_MODE,SPI mode enable bit." "0,1"
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bitfld.byte 0x2 3. "INTRPT_AT_BLK_GAP,This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt.." "0,1"
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bitfld.byte 0x2 2. "RDWAIT_CTRL,The read wait function is optional for SDIO cards. If the card supports read wait  set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data  which.." "0,1"
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bitfld.byte 0x2 1. "CONTINUE,This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap  set Stop At block Gap Request to 0 and set this bit to restart the transfer. The Host Controller automatically.." "0,1"
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bitfld.byte 0x2 0. "STOP_AT_BLK_GAP,This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers. Until the transfer complete is set to 1  indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the.." "0,1"
line.byte 0x3 "SDHC_WRAP__CTL_CFG__CTLCFG_wakeup_control,This register is used to program the wakeup functionality"
bitfld.byte 0x3 2. "CARD_REMOVAL,This bit enables wakeup event via Card removal assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1"
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bitfld.byte 0x3 1. "CARD_INSERTION,This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1"
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bitfld.byte 0x3 0. "CARD_INTERRUPT,This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS [Wake Up Support] in CIS is set to 1." "0,1"
group.word 0x2C++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_clock_control,This register is used to program the Clock frequency select. generator select. Clock enable. Internal Clock state fields"
hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FRQSEL,This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following.."
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bitfld.word 0x0 6.--7. "SDCLK_FRQSEL_UPBITS,Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select." "0,1,2,3"
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bitfld.word 0x0 5. "CLKGEN_SEL,This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported [non-zero value is set to Clock Multiplier in the Capabilities register]  this bit attribute is RW  and if not.." "0,1"
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bitfld.word 0x0 3. "PLL_ENA,This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable and PLL Enable and to minimize output latency [ex. SDCLK/RCLK  D0lane].." "0,1"
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bitfld.word 0x0 2. "SD_CLK_ENA,The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then  the HC shall maintain the same clock frequency until SDCLK is stopped [Stop at SDCLK = 0]. If the HC detects the No Card state .." "0,1"
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rbitfld.word 0x0 1. "INT_CLK_STABLE,This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock.." "0,1"
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bitfld.word 0x0 0. "INT_CLK_ENA,This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still  registers shall be able to be read and written. Clock starts to oscillate when this.." "0,1"
group.byte 0x2E++0x1
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_timeout_control,The register sets the Data Timeout counter value"
hexmask.byte 0x0 0.--3. 1. "COUNTER_VALUE,This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will.."
line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_software_reset,This register is used to program the software reset for data. command and for all"
bitfld.byte 0x1 2. "SWRST_FOR_DAT,Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register: Buffer is cleared and Initialized. Present State register: Buffer read Enable  Buffer write.." "0,1"
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bitfld.byte 0x1 1. "SWRST_FOR_CMD,Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command. From Version 4.10  this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit [including.." "0,1"
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bitfld.byte 0x1 0. "SWRST_FOR_ALL,This reset affects the entire HC except for the card detection circuit. Register bits of type ROC  RW  RW1C  RWAC are cleared to 0. During its initialization  the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0.." "0,1"
group.word 0x30++0xB
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts,This register gives the status of all the interrupts"
rbitfld.word 0x0 15. "ERROR_INTR,If any of the bits in the Error Interrupt Status Register are set  then this bit is set. Therefore the HD can test for an error by checking this bit first. In UHS-II mode is enabled  if any of the bits in the UHS-II Error.." "0,1"
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bitfld.word 0x0 14. "BOOT_COMPLETE,This status is set if the boot operation gets terminated. '0' Boot operation is not terminated '1' Boot operation is terminated" "0,1"
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bitfld.word 0x0 13. "RCV_BOOT_ACK,This status is set if the boot acknowledge is received from device. '0' Boot ack not recieved '1' Boot ack is recieved" "0,1"
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rbitfld.word 0x0 12. "RETUNING_EVENT,This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer [not large block count] can be completed.." "0,1"
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rbitfld.word 0x0 11. "INTC,This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor." "0,1"
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rbitfld.word 0x0 10. "INTB,This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor." "0,1"
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rbitfld.word 0x0 9. "INTA,This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor. NOTE : INT_A  INT_B  and INT_C are to be implemented based on the.." "0,1"
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rbitfld.word 0x0 8. "CARD_INTR,When this status has been set and the Host Driver needs to start this interrupt service  Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the Host.." "0,1"
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bitfld.word 0x0 7. "CARD_REM,This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1"
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bitfld.word 0x0 6. "CARD_INS,This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1"
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bitfld.word 0x0 5. "BUF_RD_READY,This status is set if the Buffer Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure.In UHS-II mode  this bit is set at FC [Flow Control] unit basis. '0' Not ready to.." "0,1"
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bitfld.word 0x0 4. "BUF_WR_READY,This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode  this bit is set at FC [Flow Control] unit basis. '0' Not ready to write to buffer  '1' Ready to write to buffer" "0,1"
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bitfld.word 0x0 3. "DMA_INTERRUPT,This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser. '0' No DMA Interrupt '1' DMA Interrupt is generated" "0,1"
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bitfld.word 0x0 2. "BLK_GAP_EVENT,If the Stop At Block Gap Request in the BlockGap Control Register is set  this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status [When the transaction is stopped at SD Bus timing. The Read.." "0,1"
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bitfld.word 0x0 1. "XFER_COMPLETE,This bit is set when a read / write transaction is completed. SD Mode Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is.." "0,1"
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bitfld.word 0x0 0. "CMD_COMPLETE,SD Mode This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23] Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1  it can be considered that the.." "0,1"
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts,This register gives the status of the error interrupts"
bitfld.word 0x2 12. "HOST,Occurs when detecting ERROR in m_hresp[dma transaction]" "0,1"
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bitfld.word 0x2 11. "RESP,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register  Host Controller Checks R1 or.." "0,1"
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bitfld.word 0x2 10. "TUNING,This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]. By detecting Tuning Error  Host Driver needs to abort a.." "0,1"
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bitfld.word 0x2 9. "ADMA,This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register." "0,1"
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bitfld.word 0x2 8. "AUTO_CMD,Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto CMD12. Auto CMD Error Status register is.." "0,1"
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bitfld.word 0x2 7. "CURR_LIMIT,By setting the SD Bus Power bit in the Power Control Register  the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function  it can be protected from an Illegal card by stopping power supply to the card in.." "0,1"
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bitfld.word 0x2 6. "DATA_ENDBIT,Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status." "0,1"
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bitfld.word 0x2 5. "DATA_CRC,Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010." "0,1"
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bitfld.word 0x2 4. "DATA_TIMEOUT,Occurs when detecting one of following timeout conditions: 1. Busy Timeout for R1b  R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout." "0,1"
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bitfld.word 0x2 3. "CMD_INDEX,Occurs if a Command Index error occurs in the Command Response." "0,1"
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bitfld.word 0x2 2. "CMD_ENDBIT,Occurs when detecting that the end bit of a command response is 0." "0,1"
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bitfld.word 0x2 1. "CMD_CRC,Command CRC Error is generated in two cases. 1. If a response is returned and the Command Time-out Error is set to 0  this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by.." "0,1"
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bitfld.word 0x2 0. "CMD_TIMEOUT,Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict  in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK.." "0,1"
line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts_ena,This register is used to enable the normal interrupt status register fields"
rbitfld.word 0x4 15. "BIT15_FIXED0,The HC shall control error Interrupts using the Error Interrupt Status Enable register." "0,1"
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bitfld.word 0x4 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 12. "RETUNING_EVENT,0 - Masked 1 - Enabled" "0,1"
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bitfld.word 0x4 11. "INTC,If this bit is set to 0  the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent.." "0,1"
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bitfld.word 0x4 10. "INTB,If this bit is set to 0  the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent.." "0,1"
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bitfld.word 0x4 9. "INTA,If this bit is set to 0  the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent.." "0,1"
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bitfld.word 0x4 8. "CARD_INTERRUPT,If this bit is set to 0  the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before.." "0,1"
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bitfld.word 0x4 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 3. "DMA_INTERRUPT,'0' Masked  '1' Enabled" "0,1"
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bitfld.word 0x4 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1"
line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts_ena,This register is used to enable the Error Interrupt Status register fields"
bitfld.word 0x6 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3"
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bitfld.word 0x6 12. "HOST,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 11. "RESP,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 10. "TUNING,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 9. "ADMA,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1"
line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sig_ena,This register is used to enable the Normal Interrupt Signal register"
rbitfld.word 0x8 15. "BIT15_FIXED0,The HD shall control error Interrupts using the Error Interrupt Signal Enable register." "0,1"
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bitfld.word 0x8 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 12. "RETUNING_EVENT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 11. "INTC,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 10. "INTB,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 9. "INTA,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 8. "CARD_INTERRUPT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1"
line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sig_ena,This register is used to enable Error Interrupt Signal register"
bitfld.word 0xA 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3"
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bitfld.word 0xA 12. "HOST,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 11. "RESP,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 10. "TUNING,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 9. "ADMA,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1"
rgroup.word 0x3C++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_autocmd_err_sts,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23"
bitfld.word 0x0 7. "CMD_NOT_ISSUED,Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1"
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bitfld.word 0x0 5. "RESP,This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23. This status should be ignored if any bit of D00 to D04 is set to 1." "0,1"
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bitfld.word 0x0 4. "INDEX,Occurs if the Command Index error occurs in response to a command." "0,1"
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bitfld.word 0x0 3. "ENDBIT,Occurs when detecting that the end bit of command response is 0." "0,1"
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bitfld.word 0x0 2. "CRC,Occurs when detecting a CRC error in the command response." "0,1"
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bitfld.word 0x0 1. "TIMEOUT,Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1  the other error status bits [D04 - D02] are meaningless." "0,1"
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bitfld.word 0x0 0. "ACMD12_NOT_EXEC,If memory multiple block data transfer is not started due to command error  this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block.." "0,1"
group.word 0x3E++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control2,This register is used to program UHS Select Mode.UHS Select Mode.Driver Strength Select.Execute Tuning.Sampling Clock Select.Asynchronous Interrupt Enable and Preset value enable"
bitfld.word 0x0 15. "PRESET_VALUE_ENA,Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation  it is difficult to determine these parameters in the Standard Host Driver. When Preset.." "0,1"
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bitfld.word 0x0 14. "ASYNCH_INTR_ENA,This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode [and zero is.." "0,1"
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bitfld.word 0x0 13. "BIT64_ADDRESSING,This field is effective when Host Version 4.00 Enable is set to 1. Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host.." "0,1"
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bitfld.word 0x0 12. "HOST_VER40_ENA,This bit selects either Version 3.00 compatible mode or Ver4.mode. In Version 4.00  support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit. In Version.." "0,1"
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bitfld.word 0x0 11. "CMD23_ENA,In memory card initialization  Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 [SCR[33]=1]  this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3.." "0,1"
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bitfld.word 0x0 10. "ADMA2_LEN_MODE,This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit." "0,1"
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bitfld.word 0x0 9. "DRIVER_STRENGTH2,This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value." "0,1"
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bitfld.word 0x0 8. "UHS2_INTF_ENABLE,This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization  this bit shall be set to 1. Before trying to start SD mode initialization  this bit shall be set to 0. This bit is used to enable UHS-II IF.." "0,1"
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bitfld.word 0x0 7. "SAMPLING_CLK_SELECT,This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller.." "0,1"
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bitfld.word 0x0 6. "EXECUTE_TUNING,This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning.." "0,1"
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bitfld.word 0x0 4.--5. "DRIVER_STRENGTH1,Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling  this field is not effective. This field can be set depends on Driver Type A  C and D support bits in the Capabilities register. This bit depends.." "0,1,2,3"
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bitfld.word 0x0 3. "V1P8_SIGNAL_ENA,This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within.." "?,1: SDR50"
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bitfld.word 0x0 0.--2. "UHS_MODE_SELECT,This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode  this field is effective when 1.8V Signal-ing Enable is set to 1. In case of UHS-II mode  1.8V Signaling Enable shall be set to 0. Setting of this field.." "0,1,2,3,4,5,6,7"
rgroup.quad 0x40++0xF
line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_capabilities,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initializa-tion."
bitfld.quad 0x0 63. "HS400_SUPPORT,1 HS400 is Supported 0 HS400 is Not Supported" "0,1"
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bitfld.quad 0x0 60. "VDD2_1P8_SUPPORT,This field indicates that support of VDD2 on Host system." "0,1"
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bitfld.quad 0x0 59. "ADMA3_SUPPORT,This field indicates that support of ADMA3 on Host Controller." "0,1"
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bitfld.quad 0x0 57. "SPI_BLK_MODE,This field indicates whether SPI Block Mode is supported or not." "0,1"
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bitfld.quad 0x0 56. "SPI_SUPPORT,This field indicates whether SPI Mode is supported or not." "0,1"
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hexmask.quad.byte 0x0 48.--55. 1. "CLOCK_MULTIPLIER,This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. 'FF' Clock Multiplier M = 256.."
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bitfld.quad 0x0 46.--47. "RETUNING_MODES,This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. '00' Mode 1 '01' Mode 2 '10' Mode 3 '11' Reserved. There are two.." "0,1,2,3"
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bitfld.quad 0x0 45. "TUNING_FOR_SDR50,If this bit is set to 1  this Host Controller requires tuning to operate SDR50. [Tuning is always required to operate SDR104]. '0' '1'" "0,1"
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hexmask.quad.byte 0x0 40.--43. 1. "RETUNING_TIMER_CNT,This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ------.."
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bitfld.quad 0x0 38. "DRIVERD_SUPPORT,This bit indicates support of Driver Type D for 1.8 Signaling. '0' Driver Type D is Not supported  '1' Driver Type D is supported" "0,1"
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bitfld.quad 0x0 37. "DRIVERC_SUPPORT,This bit indicates support of Driver Type C for 1.8 Signaling. '0' Driver Type C is Not supported  '1' Driver Type C is supported" "0,1"
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bitfld.quad 0x0 36. "DRIVERA_SUPPORT,This bit indicates support of Driver Type A for 1.8 Signaling. '0' Driver Type A is Not supported  '1' Driver Type A is supported" "0,1"
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bitfld.quad 0x0 35. "UHS2_SUPPORT,This bit indicates whether Host controller supports UHS-II. If this bit is set to 1  1.8V VDD2 Support shall be set to 1 [Host Sys- tem shall support VDD2 power supply]. 1 UHS-II is Supported 0 UHS-II is Not Supported" "0,1"
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bitfld.quad 0x0 34. "DDR50_SUPPORT,This bit indicates whether DDR50 is supported or not." "0,1"
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bitfld.quad 0x0 33. "SDR104_SUPPORT,This bit indicates whether SDR104 is supported or not.SDR104 requires tuning." "0,1"
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bitfld.quad 0x0 32. "SDR50_SUPPORT,If SDR104 is supported  this bit shall be set to 1. Bit 40 indicates whether SDR50 requires tuning or not." "0,1"
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bitfld.quad 0x0 30.--31. "SLOT_TYPE,This field indicates usage of a slot by a specific Host System. [A host controller register set is defined perslot.] Embedded slot for one device [01b] means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot.." "0,1,2,3"
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bitfld.quad 0x0 29. "ASYNCH_INTR_SUPPORT,Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1"
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bitfld.quad 0x0 28. "ADDR_64BIT_SUPPORT_V3,IMeaning of this bit is different depends on Versions [Refer to Table 2-35 for more details]. Host Controller Version 3.00 and Ver4.10 use this bit as 64-bit System Address support for V3 mode. Host Con- troller Version 4.00 uses.." "0,1"
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bitfld.quad 0x0 27. "ADDR_64BIT_SUPPORT_V4,This bit is added from Version 4.10. Set-ting 1 to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode [Refer to Table 2-35 for the summary of 64-bit sys-tem address support].. When.." "0,1"
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bitfld.quad 0x0 26. "VOLT_1P8_SUPPORT,This bit indicates whether the HC supports 1.8V." "0,1"
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bitfld.quad 0x0 25. "VOLT_3P0_SUPPORT,This bit indicates whether the HC supports 3.0V." "0,1"
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bitfld.quad 0x0 24. "VOLT_3P3_SUPPORT,This bit indicates whether the HC supports 3.3V." "0,1"
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bitfld.quad 0x0 23. "SUSP_RES_SUPPORT,This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0  the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands." "0,1"
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bitfld.quad 0x0 22. "SDMA_SUPPORT,This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.Version 4.10 Host Controller shall support SDMA if ADMA2 is supported." "0,1"
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bitfld.quad 0x0 21. "HIGH_SPEED_SUPPORT,This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz [for SD]/ 20MHz to 52MHz [for MMC]." "0,1"
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bitfld.quad 0x0 19. "ADMA2_SUPPORT,'0' ADMA2 Not Supported '1' ADMA2 Supported" "0,1"
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bitfld.quad 0x0 18. "BUS_8BIT_SUPPORT,This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case  refer to Bus Width Preset in the Shared Bus resister." "0,1"
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bitfld.quad 0x0 16.--17. "MAX_BLK_LENGTH,This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below." "0,1,2,3"
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hexmask.quad.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,[1]6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. '11xx xxxxb' Not.."
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bitfld.quad 0x0 7. "TIMEOUT_CLK_UNIT,This bit shows the unit of base clock frequency used to detect Data Timeout Error." "0,1"
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hexmask.quad.byte 0x0 0.--5. 1. "TIMEOUT_CLK_FREQ,This bit shows the base clock frequency used to detect Data Timeout Error. '000000' Get Information via another method  'not 0' 1KHz to 63KHz/1MHz to 63MHz"
line.quad 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_max_current_cap,This register indicates maximum current capability for each voltage"
hexmask.quad.byte 0x8 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8V VDD2"
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hexmask.quad.byte 0x8 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8V VDD1"
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hexmask.quad.byte 0x8 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0V VDD1"
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hexmask.quad.byte 0x8 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3V VDD1"
wgroup.word 0x50++0x3
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_ACMD_Err_Sts,This register is not physically implemented. rather it is an address where Auto CMD Error Status register can be written."
bitfld.word 0x0 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error." "0,1"
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bitfld.word 0x0 5. "RESP,Force Event for AUTO CMD Response Error.." "0,1"
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bitfld.word 0x0 4. "INDEX,Force Event for AUTO CMD Index Error.." "0,1"
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bitfld.word 0x0 3. "ENDBIT,Force Event for AUTO CMD End Bit Error." "0,1"
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bitfld.word 0x0 2. "CRC,Force Event for AUTO CMD Timeout Error." "0,1"
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bitfld.word 0x0 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error." "0,1"
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bitfld.word 0x0 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed." "0,1"
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_Err_Int_Sts,This register is not physically implemented. rather it is an address where Error Interrupt Status register can be written."
bitfld.word 0x2 12. "HOST,Force Event for Host Error" "0,1"
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bitfld.word 0x2 11. "RESP,Force Event for Response Error" "0,1"
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bitfld.word 0x2 10. "TUNING,Force Event for Tuning Error." "0,1"
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bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error." "0,1"
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bitfld.word 0x2 8. "AUTO_CMD,Force Event for Auto CMD Error." "0,1"
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bitfld.word 0x2 7. "CURR_LIM,Force Event for Current Limit Error." "0,1"
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bitfld.word 0x2 6. "DAT_ENDBIT,Force Event for Data End Bit Error." "0,1"
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bitfld.word 0x2 5. "DAT_CRC,Force Event for Data CRC Error." "0,1"
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bitfld.word 0x2 4. "DAT_TIMEOUT,Force Event for Data Timeout Error." "0,1"
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bitfld.word 0x2 3. "CMD_INDEX,Force Event for Command Index Error" "0,1"
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bitfld.word 0x2 2. "CMD_ENDBIT,Force Event for Command End Bit Error." "0,1"
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bitfld.word 0x2 1. "CMD_CRC,Force Event for Command CRC Error." "0,1"
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bitfld.word 0x2 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error." "0,1"
rgroup.byte 0x54++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_err_status,When the ADMA Error interrupt occur. this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor"
bitfld.byte 0x0 2. "ADMA_LENGTH_ERR,This error occurs in the following 2 cases. While Block Count Enable being set  the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be.." "0,1"
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bitfld.byte 0x0 0.--1. "ADMA_ERR_STATE,This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state. D01 D00 : ADMA Error State when error occurred Contents of SYS_SDR.." "0,1,2,3"
group.quad 0x58++0x7
line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_sys_address,This register contains the physical address used for ADMA data transfer"
hexmask.quad 0x0 0.--63. 1. "ADMA_ADDR,The 32-bit addressing Host Driver uses lower 32-bit of this register [upper 32-bit should be set to 0] and shall program Descriptor Table on 32-bit boundary andset 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this.."
rgroup.word 0x60++0xF
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value0,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value1,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value2,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x4 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x4 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x4 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value3,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x6 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x6 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x6 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value4,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x8 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x8 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x8 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value5,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0xA 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0xA 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0xA 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value6,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0xC 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0xC 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0xC 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value7,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0xE 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0xE 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0xE 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
rgroup.word 0x72++0x3
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value8,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value10,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
group.quad 0x78++0x7
line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma3_desc_address,The start address of Integrated DMA Descriptor is set to this register."
hexmask.quad 0x0 0.--63. 1. "INTG_DESC_ADDR,The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the.."
group.word 0x80++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_size,This register is used to configure the number of bytes in a data block"
bitfld.word 0x0 12.--14. "SDMA_BUF_BOUNDARY,When system memory is managed by paging  SDMA data transfer is performed in unit of paging. A page size of sys-tem memory management is set to this field. Host Controller generates the DMA Interrupt at the page boundary and.." "0,1,2,3,4,5,6,7"
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hexmask.word 0x0 0.--11. 1. "XFER_BLK_SIZE,This register specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Vari-able block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This register is.."
group.long 0x84++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_count,This register is used to configure the number of data blocks"
hexmask.long 0x0 0.--31. 1. "XFER_BLK_COUNT,This register is effective when Data Present is set to 1 in UHS-II Command register and is enabled when Block Count Enable is set to 1 and Block / Byte Mode is set to 0 in the UHS-II Transfer Mode register. Data transfer stops when the.."
group.byte 0x88++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command_pkt,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes. The command length varies depends on a Command Packet type. The length is specified by the UHS-II Command register."
hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,UHS-II Command Packet image is set to this register.The command length varies depends on a Command Packet type."
group.word 0x9C++0x3
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_xfer_mode,This register is used to control the operations of data transfers"
bitfld.word 0x0 15. "DUPLEX_SELECT,Use of 2 lane half duplex mode is determined by Host Driver." "0,1"
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bitfld.word 0x0 14. "EBSY_WAIT,This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer.If this bit is set to 1  Host Controller waits receiving of.." "0,1"
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bitfld.word 0x0 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error  sets this bit to 0 and waits Command.." "0,1"
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bitfld.word 0x0 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked. If Host Driver checks response error  this bit is set to 0 and Response.." "0,1"
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bitfld.word 0x0 6. "RESP_TYPE,When response error check is enabled  this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1 Bit31 OUT_OF_RANGE.." "0,1"
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bitfld.word 0x0 5. "BYTE_MODE,This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1. This bit is effective to a command with data trans-fer." "0,1"
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bitfld.word 0x0 4. "DATA_XFER_DIR,This bit specifies direction of data trans-fer when Data Present is set to 1. This bit is effective to a command with data transfer. 0 - Read [Card to Host] 1 - Write [Host to Card]" "0,1"
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bitfld.word 0x0 1. "BLK_CNT_ENA,This bit specifies whether data transfer usesUHS-II Block Count register. If this bit is set to 1  data transfer is terminated by Block Count. Setting to UHS-II Block Count register shall be equivalent to TLEN in UHS-II Command Packet.." "0,1"
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bitfld.word 0x0 0. "DMA_ENA,This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by DMA Select in the Host Control 1 register." "0,1"
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command,This register is used to program the Command for host controller"
hexmask.word.byte 0x2 8.--12. 1. "PKT_LENGTH,A command packet length  which is set in the UHS-II Command Packet register  is set to this register. 00011b - 00000b - 3-0 Bytes [Not used] 00100b - 4 Bytes .......... ...... 10100b - 20 Bytes.."
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bitfld.word 0x2 6.--7. "CMD_TYPE,This field is used to distinguish a spe-cific command like abort command. If this field is set to 00b  the UHS-II RES Packet is stored in UHS-II Response register [0B3h-0A0h]. To avoid overwrit-ing the UHS-II Response register  when this filed.." "0,1,2,3"
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bitfld.word 0x2 5. "DATA_PRESENT,This bit specifies whether the command is accompanied by data packet." "0,1"
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bitfld.word 0x2 2. "SUB_COMMAND,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command  this bit is set to 0 and when issuing a sub com-mand  this bit is set to 1. Setting of this bit is checked.." "0,1"
rgroup.byte 0xA0++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_response,This register is used to store received UHS-II RES Packet image"
hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command."
group.byte 0xB4++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message_select,This register is used to access internal buffer"
bitfld.byte 0x0 0.--1. "MSG_SEL,Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs.." "0,1,2,3"
rgroup.long 0xB8++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message,This register is used to access internal buffer"
hexmask.long.byte 0x0 24.--31. 1. "MSG_BYTE3,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.."
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hexmask.long.byte 0x0 16.--23. 1. "MSG_BYTE2,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.."
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hexmask.long.byte 0x0 8.--15. 1. "MSG_BYTE1,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.."
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hexmask.long.byte 0x0 0.--7. 1. "MSG_BYTE0,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.."
group.word 0xBC++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_intr_status,This register shows receipt of INT MSG from which device"
hexmask.word 0x0 0.--15. 1. "DEV_INT_STS,This register shows receipt of INT MSG from which device and is effective when INT MSG Enable is set to 1 in the UHS- II Device Select register. On receiving INT MSG from a device  Host Controller saves the INT MSG to UHS-II Device Interrupt.."
group.byte 0xBE++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_select,UHS-II Device Select Register"
bitfld.byte 0x0 7. "INT_MSG_ENA,This bit enables receipt of INT MSG. If this bit is set to 1 receipt of INT MSG is informed by Card Interrupt in the Nor-mal Interrupt Status register. If this bit is set to 0  Host Con-troller ignores receipt of INT MSG and may not set the.." "0,1"
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hexmask.byte 0x0 0.--3. 1. "DEV_SEL,Host Controller holds an INT MSG packet per device. One of INT MSGs [up to 15] can be selected by this field and read from the UHS-II Device Interrupt Code Register [0BFh]. This field is effective when INT MSG Enable is set to 1. The.."
rgroup.byte 0xBF++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_int_code,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register."
hexmask.byte 0x0 0.--7. 1. "DEV_INTR,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register. Host Controller holds an INT MSG packet per device. One of INT MSGs [Code length is 1 byte] up to 15 can be read from this register by.."
group.word 0xC0++0x3
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_software_reset,UHS-II Software Reset Register"
bitfld.word 0x0 1. "HOST_SDTRAN_RESET,Host Driver set this bit to 1 to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completionof SD-TRAN reset. If CMD0 is issued  SD-TRAN Initial- ization sequence from.." "0,1"
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bitfld.word 0x0 0. "HOST_FULL_RESET,On issuing FULL_RESET CCMD  Host Driver set this bit to 1 to reset Host Controller. This bit is cleared auto-matically at completion of Host Controller reset. Initial- ization sequence from PHY Initialization is required to use UHS-II.." "0,1"
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_timer_control,UHS-II Timeout Control Register"
hexmask.word.byte 0x2 4.--7. 1. "DEADLOCK_TIMEOUT_CTR,This value determines the deadlock period while host expecting to receive a packet [1 second]. Tim-eout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register  prevent.."
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hexmask.word.byte 0x2 0.--3. 1. "CMDRESP_TIMEOUT_CTR,This value determines the interval between com-mand packet and response packet [5ms]. Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When set-ting this register  prevent inadvertent.."
group.long 0xC4++0xB
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts,This register gives the status of all UHS-II interrupts"
hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC_ERR,Vendor may use this field for vendor specific error status. '0' Interrupt is not generated '1' Vendor Specific Error"
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bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout [1 second]. Timeout value is determined by the setting of Timeout Counter Value for Deadlock in UHS-II Timer.." "0,1"
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bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout [5ms]. Timeout value is determined by the setting of Timeout Counter Value for CMD_RES in UHS-II Timer.." "0,1"
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bitfld.long 0x0 15. "ADMA2_ADMA3,Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the ADMA Error Status [054h]  which is defined in the Host spec 3.00." "0,1"
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bitfld.long 0x0 8. "EBSY,On receiving EBSY packet  if the packet indicates an error  this bit is set to 1. Setting of this bit also sets Error Interrupt and Transfer Completer together in the Normal Interrupt Status register. This error check is effective for a command with.." "0,1"
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bitfld.long 0x0 7. "UNRECOVERABLE,Setting of this bit means that Unrecoverable Error is set in a packet from a device." "0,1"
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bitfld.long 0x0 5. "TID,Setting of this bit means that TID Error occurs." "0,1"
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bitfld.long 0x0 4. "FRAMING,Setting of this bit means that Framing Error occurs during a packet receiving." "0,1"
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bitfld.long 0x0 3. "CRC,Setting of this bit means that CRC Error occurs during a packet receiving." "0,1"
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bitfld.long 0x0 2. "RETRY_EXPIRED,Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set either Framing Error or CRC Error in this register shall be set." "0,1"
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bitfld.long 0x0 1. "RESP_PKT,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to1 in the UHS- II Transfer Mode register  Host Controller.." "0,1"
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bitfld.long 0x0 0. "HEADER,Setting of this bit means that Header Error occurs in a received packet." "0,1"
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts_ena,This register is used to enable the UHS-II Error Interrupt Status register fields"
hexmask.long.byte 0x4 27.--31. 1. "VENDOR_SPECFIC,Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register. 0h - Status is Disabled 1h - Status is Enabled"
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bitfld.long 0x4 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 15. "ADMA2_ADMA3,Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 8. "EBSY,Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 7. "UNRECOVERABLE,Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 5. "TID,Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 4. "FRAMING,Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 3. "CRC,Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 2. "RETRY_EXPIRED,Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 1. "RESP_PKT,Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 0. "HEADER,Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register." "0,1"
line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sig_ena,This register is used to generate UHS-II Interrupt signals"
hexmask.long.byte 0x8 27.--31. 1. "VENDOR_SPECFIC,Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register. 0h - Interrupt Signal is Disabled 1h -.."
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bitfld.long 0x8 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 15. "ADMA2_ADMA3,Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 8. "EBSY,Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 7. "UNRECOVERABLE,Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 5. "TID,Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 4. "FRAMING,Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 3. "CRC,Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 2. "RETRY_EXPIRED_SIG_ENA,Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 1. "RESP_PKT,Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 0. "HEADER,Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register." "0,1"
rgroup.word 0xE0++0x9
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_settings_ptr,This register is pointer for UHS-II settings."
hexmask.word 0x0 0.--15. 1. "UHS2_SETTINGS_PTR,Pointer for UHS-II Settings Register"
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_capabilities_ptr,This register is pointer for UHS-II Capabilities Register."
hexmask.word 0x2 0.--15. 1. "UHS2_CAPABILITIES_PTR,Pointer for UHS-II Capabilities Register"
line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_test_ptr,This register is pointer for UHS-II Test Register."
hexmask.word 0x4 0.--15. 1. "UHS2_TEST_PTR,Pointer for UHS-II Test Register"
line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_shared_bus_ctrl_ptr,This register is pointer for UHS-II Shared Bus Control Register."
hexmask.word 0x6 0.--15. 1. "SHARED_BUS_CTRL_PTR,Pointer for Shared Bus Control Register"
line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_specfic_ptr,This register is pointer for UHS-II Vendor Specific Pointer Register."
hexmask.word 0x8 0.--15. 1. "VENDOR_SPECFIC_PTR,Pointer for Vendor Specific Area"
group.long 0xF4++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_boot_timeout_control,This is used to program the boot timeout value counter"
hexmask.long 0x0 0.--31. 1. "DATA_TIMEOUT_CNT,This value determines the interval by which DAT line time-outs are detected during boot operation for eMMC4.4 card.The value is in number of sd clock."
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_register,Vendor register added for autogate sdclk. cmd11 power down timer. enhancedstrobe and eMMC hardware reset"
bitfld.long 0x4 16. "AUTOGATE_SDCLK,If this bit is set  SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device" "0,1"
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hexmask.long.word 0x4 2.--15. 1. "CMD11_PD_TIMER,cmd11 power-down timer value"
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bitfld.long 0x4 1. "EMMC_HW_RESET,Hardware reset signal is generared for eMMC card when this bit is set" "0,1"
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bitfld.long 0x4 0. "ENHANCED_STROBE,This bit enables the enhanced strobe logic of the Host Controller" "0,1"
rgroup.word 0xFC++0x3
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_slot_int_sts,This register is used to read the interrupt signal for each slot."
hexmask.word.byte 0x0 0.--7. 1. "INTR_SIG,These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot."
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_host_controller_ver,This register is used to read the vendor version number and specification version number"
hexmask.word.byte 0x2 8.--15. 1. "VEN_VER_NUM,The Vendor Version Number is set to 0x10 [1.0]"
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hexmask.word.byte 0x2 0.--7. 1. "SPEC_VER_NUM,This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 00h - SD Host Controller Specification Version 1.00 01h - SD Host Controller Specification Version 2.00 Including the.."
group.long 0x100++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_settings,Start Address of General settings is pointed by Pointer for UHS-II Setting Register."
hexmask.long.byte 0x0 8.--13. 1. "NUMLANES,The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0000b - 2 Lanes FD or 2L-HD 0001b -.."
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bitfld.long 0x0 0. "POWER_MODE,This field determines either Fast mode or Low Power mode.Host and all devices connected to the host shall be set to the same mode." "0,1"
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_settings,Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register."
hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h - 8 x16 LSS 1h - 8 x 1 LSS 2h - 8 x 2 LSS 3h - 8 x 3 LSS ...... ......"
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hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ......"
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bitfld.long 0x4 15. "HIBERNATE_ENA,After checking card capability of Hibernate mode  if all devices support Hibernate mode  this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode  VDD1 Power may be off." "0,1"
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bitfld.long 0x4 6.--7. "SPEED_RANGE,PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. '00' Range A [Default] '01' Range B '10' Reserved '11' Reserved" "0,1,2,3"
group.quad 0x108++0x7
line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_settings,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Setting Register."
hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255.."
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bitfld.quad 0x0 16.--17. "RETRY_COUNT,Data Burst retry count is set to this field. '00' Retry Disabled '01' 1 time '10' 2 times '11' 3 times" "0,1,2,3"
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hexmask.quad.byte 0x0 8.--15. 1. "HOST_NFCU,Host Driver sets the number of blocks in Data Burst [Flow Control] to this field.The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended.."
rgroup.long 0x110++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_cap,Start Address of General Capabilities is pointed by Pointer for UHS-II Host Capabilities Register."
bitfld.long 0x0 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,This field indicates one of bus topologies configured by a Host system. '00' P2P Connection '01' Ring Connection '10' HUB Connection '11' HUB is connected in Ring" "0,1,2,3"
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hexmask.long.byte 0x0 18.--21. 1. "CORECFG_UHS2_MAX_DEVICES,This field indicates the maximum number of devices supported by the Host Controller. 0h - Not used 1h - 1 Devices 2h - 2 Devices ..... ....... Fh - 15 Devices"
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bitfld.long 0x0 16.--17. "DEVICE_TYPE,This field indicates device type configured by a Host system. '00' Removable Card[P2P] '01' Embedded Devices '10' Embedded Devices+Removable Card '11' Reserved" "0,1,2,3"
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bitfld.long 0x0 14. "CFG_64BIT_ADDRESSING,This field indicates support of 64-bit addressing by the Host Controller. '0' 32-bit Addressing is supported '1' 32-bit and 64-bit Addressing is supported" "0,1"
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hexmask.long.byte 0x0 8.--13. 1. "NUM_LANES,This field indicates support of lanes by the Host Controller.0 mean not supported and 1 means supported. D08 - 2L-HD D09 - 2D1U-FD D10 - 1D2U-FD D11 - 2D2U-FD D12 - Reserved D13 - Reserved"
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hexmask.long.byte 0x0 4.--7. 1. "GAP,This field indicates the maximum capability of host power supply for a group configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -Not used 1h - 360 mW 2h - 720 mW ....."
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hexmask.long.byte 0x0 0.--3. 1. "DAP,This field indicates the maximum capability of host power supply for a device configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -360 mW [Default] 1h - 360 mW 2h - 720 mW.."
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_cap,Start Address of PHY Capabilities is pointed by Pointer for UHS-II Host Capabilities Register."
hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS"
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hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS"
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bitfld.long 0x4 6.--7. "SPEED_RANGE,This field indicates supported Speed Range by the Host Controller '00' Range A [Default] '01' Range A and Range B '10' Reserved '11' Reserved" "0,1,2,3"
rgroup.quad 0x118++0x7
line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_cap,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Capabilities Register."
hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,This field indicates the minimum number of data gap[DIDL] supported by the Host Controller. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255 LSS"
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hexmask.quad.word 0x0 20.--31. 1. "MAX_BLK_LENGTH,This field indicates maximum block length by the Host Controller. 000h - Not Used 001h - 1 byte 002h - 2 bytes ...... ...... 200h - 512 bytes ...... ......"
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hexmask.quad.byte 0x0 8.--15. 1. "N_FCU,This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller.This value is determined by supported buffer size. 00h - 256 Blocks 01h - 1 Block 02h - 2 Block 03h - 3 Block.."
wgroup.long 0x120++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_UHSII_Err_Int_Sts,This register is not physically implemented. rather it is an address where UHS-II Error Interrupt Status register can be written."
hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error 0h - Not Affected 1h - Vendor Specific Error Status is set"
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bitfld.long 0x0 17. "TIMEOUT_DEADLOCK,Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 16. "TIMEOUT_CMD_RES,Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 15. "ADMA,Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 8. "EBSY,Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 7. "UNRECOVERABLE,Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 5. "TID,Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 4. "FRAMING,Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 3. "CRC,Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 2. "RETRY_EXPIRED,Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 1. "RES_PKT,Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 0. "HEADER,Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register." "0,1"
rgroup.long 0x200++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_version,This register provides information about the version of the eMMC CQ standard which is 285 implemented by the CQE. in BCD format. The current version is rev 5.1"
hexmask.long.byte 0x0 8.--11. 1. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number [digit left of decimal point] in BCD format"
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hexmask.long.byte 0x0 4.--7. 1. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number [digit right of decimal point]  in BCD format"
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hexmask.long.byte 0x0 0.--3. 1. "EMMC_VERSION_SUFFIX,eMMC Version Suffix [2nd digit right of decimal point]  in BCD format"
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_capabilities,This register is reserved for capability indication."
hexmask.long.byte 0x4 12.--15. 1. "CF_MUL,Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period. See ITCFVAL definition for details."
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hexmask.long.word 0x4 0.--9. 1. "CF_VAL,Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling."
group.long 0x208++0x27
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_config,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time."
bitfld.long 0x0 12. "DCMD_ENA,Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor  or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot.." "0: Task descriptor in slot #31 is a Data Transfer..,1: Task descriptor in slot #31 is a DCMD Task.."
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bitfld.long 0x0 8. "TASK_DESC_SIZE,Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section. This bit can only be configured when Command Queueing Enable bit is 0 [command queueing is.." "0: Task descriptor size is 64 bits,1: Task descriptor size is 128 bits"
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bitfld.long 0x0 0. "CQ_ENABLE,Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE]. When this bit is 0  CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller." "0,1"
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_control,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time."
bitfld.long 0x4 8. "CLEAR_ALL_TASKS,Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state [i.e.Halt bit is 1]. When software writes 1  the value of the.." "0,1"
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bitfld.long 0x4 0. "HALT_BIT,Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example  issuing a Discard Task command [CMDQ_TASK_MGMT] When software writes 1 .." "0,1"
line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event. only if the respective bit is set in CQ ISTE register."
bitfld.long 0x8 4. "TASK_ERROR,Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor" "0,1"
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bitfld.long 0x8 3. "TASK_CLEARED,Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE. The com-pleted task clear operation is either an individual task clear [CQTCLR] or clearing of all tasks [CQCTL]." "0,1"
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bitfld.long 0x8 2. "RESP_ERR_DET,Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field. The contents of the device status field are listed in Section.." "0,1"
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bitfld.long 0x8 1. "TASK_COMPLETE,Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met: [1] A task is completed and the INT bit is set in its Task Descriptor [2] Interrupt caused by.." "0,1"
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bitfld.long 0x8 0. "HALT_COMPLETE,Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating that host controller has completed its current ongoing task and has entered halt state." "0,1"
line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts_ena,This register enables and disables the reporting of the corresponding interrupt to host soft-ware in 299 CQIS register. When a bit is set ( 1 ) and the corresponding interrupt c -ondition is active. then.."
bitfld.long 0xC 4. "TASK_ERROR,Task Error Interrupt Status Enable 1 = CQIS.TERR will be set when its interrupt condition is active 0 = CQIS.TERR is disabled" "0: CQIS,1: CQIS"
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bitfld.long 0xC 3. "TASK_CLEARED,Task Cleared Status Enable [TCL] 1 = CQIS.TCL will be set when its interrupt condition is active 0 = CQIS.TCL is disabled" "0: CQIS,1: CQIS"
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bitfld.long 0xC 2. "RESP_ERR_DET,Response Error Detected Status Enable [RED] 1 = CQIS.RED will be set when its interrupt condition is active 0 = CQIS.RED is disabled" "0: CQIS,1: CQIS"
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bitfld.long 0xC 1. "TASK_COMPLETE,Task Complete Status Enable [TCC] 1 = CQIS.TCC will be set when its interrupt condition is active 0 = CQIS.TCC is disabled" "0: CQIS,1: CQIS"
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bitfld.long 0xC 0. "HALT_COMPLETE,Halt Complete Status Enable [HAC] 1 = CQIS.HAC will be set when its interrupt condition is active 0 = CQIS.HAC is disabled" "0: CQIS,1: CQIS"
line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sig_ena,This register enables and disables the generation of interrupts to host software. When a bit is set 304 ( 1 ) and the corresponding bit in CQIS is set. then an interrupt is gene -rated. Interrupt sources.."
bitfld.long 0x10 4. "TASK_ERROR,Task Error Interrupt Signal Enable [TERR] When set and CQIS.TERR is asserted  the CQE shall generate an interrupt" "0,1"
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bitfld.long 0x10 3. "TASK_CLEARED,Task Cleared Signal Enable [TCL] When set and CQIS.TCL is asserted  the CQE shall generate an interrupt" "0,1"
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bitfld.long 0x10 2. "RESP_ERR_DET,Response Error Detected Signal Enable [TCC] When set and CQIS.RED is asserted  the CQE shall generate an interrupt" "0,1"
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bitfld.long 0x10 1. "TASK_COMPLETE,Task Complete Signal Enable [TCC] When set and CQIS.TCC is asserted  the CQE shall generate an interrupt" "0,1"
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bitfld.long 0x10 0. "HALT_COMPLETE,Halt Complete Signal Enable [HAC] When set and CQIS.HAC is asserted  the CQE shall generate an interrupt" "0,1"
line.long 0x14 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_coalescing,This register controls the interrupt coalescing feature."
bitfld.long 0x14 31. "CQINTCOALESC_ENABLE,When set to 0 by software  command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT=1 in the Task Descriptor. When set to 1  the interrupt coalescing mechanism is enabled.." "0,1"
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rbitfld.long 0x14 20. "IC_STATUS,This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e.  ICSB is set if and only if IC counter > 0]. Bit Value Description 1 = At least one task completion has been.." "0: No task completions have occurred since last..,1: At least one task completion has been counted.."
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hexmask.long.byte 0x14 8.--12. 1. "CTR_THRESHOLD,Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt. Counter.."
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hexmask.long.byte 0x14 0.--6. 1. "TIMEOUT_VAL,Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by.."
line.long 0x18 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory."
hexmask.long 0x18 0.--31. 1. "CQTDLBA_LO,Task Descriptor List Base Address [TDLBA] This register stores the LSB bits [bits 31:0] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.."
line.long 0x1C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr_upbits,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory."
hexmask.long 0x1C 0.--31. 1. "CQTDLBA_HI,Task Descriptor List Base Address [TDLBA] This register stores the MSB bits [bits 63:32] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.."
line.long 0x20 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_door_bell,Using this register. software triggers CQE to process a new task."
hexmask.long 0x20 0.--31. 1. "CQTDB_VAL,Command Queueing Task Doorbell Software shall configure TDLBA and TDLBAU  and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start pro-cessing the task encoded in slot n of the TDL."
line.long 0x24 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_comp_notif,This register is used by CQE to notify software about completed tasks."
hexmask.long 0x24 0.--31. 1. "CQTCN_VAL,CQE shall set bit n of this register [at the same time it clears bit n of CQTDBR] when a task execution is com-pleted [with success or error]. When receiving interrupt for task completion  software may read this register to know which tasks.."
rgroup.long 0x230++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_queue_status,This register stores the most recent value of the device s queue status."
hexmask.long 0x0 0.--31. 1. "CQDQ_STS,Every time the Host controller receives a queue status register [QSR] from the device  it updates this register with the response of status command  i.e. the devices queue status."
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_pending_tasks,This register indicates to software which tasks are queued in the device. awaiting execution."
hexmask.long 0x4 0.--31. 1. "CQDP_TSKS,Bit n of this register is set if and only if QUEUED_TASK_PARAMS [CMD44] and QUEUED_TASK_ADDRESS [CMD45] were sent for this specific task and if this task hasnt been executed yet.CQE shall set this bit after receiving a successful response for.."
group.long 0x238++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_clear,This register is used for removing an outstanding task in the CQE. 327. The register should be used only when CQE is in Halt state."
hexmask.long 0x0 0.--31. 1. "CQTCLR,Writing 1 to bit n of this register orders CQE to clear a task which software has previously issued.This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit.When software writes 1 to a bit in this.."
group.long 0x240++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config1,The register controls the when SEND_QUEUE_STATUS commands are sent."
hexmask.long.byte 0x0 16.--19. 1. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS [CMD13] command to inquire the status of the devices task queue.A value of n means CQE shall send status command on the CMD line  during the transfer of data block BLOCK_CNT-n  on.."
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hexmask.long.word 0x0 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS [CMD13] polling.Periodic polling is used when tasks are pending in the device  but no data transfer is in progress. When a SEND_QUEUE_STATUS.."
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argu-ment."
hexmask.long.word 0x4 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_ STATUS [CMD13] com-mand. argument. CQE shall copy this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS [CMD13] command."
rgroup.long 0x248++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dcmd_response,This register is used for passing the response of a DCMD task to software."
hexmask.long 0x0 0.--31. 1. "LAST_RESP,This register contains the response of the command generated by the last direct-command [DCMD] task which was sent.CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit 31.."
group.long 0x250++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_resp_err_mask,This register controls the generation of Response Error Detection (RED) interrupt."
hexmask.long 0x0 0.--31. 1. "CQRMEM,This bit is used as in interrupt mask on the device status filed which is received in R1/R1b responses.Bit Value Description [for any bit i]:1 = When a R1/R1b response is received  with bit i in the device status set  a RED interrupt is generated.."
rgroup.long 0x254++0xF
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_err_info,This register is updated by CQE when an error occurs on data or command related to a task activity."
bitfld.long 0x0 31. "DATERR_VALID,Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE  or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated  the bit is set to 1. If a no.." "0,1"
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hexmask.long.byte 0x0 24.--28. 1. "DATERR_TASK_ID,Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE  or.."
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hexmask.long.byte 0x0 16.--21. 1. "DATERR_CMD_INDEX,Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK[CMD46] or EXECUTE_WRITE_TASK [CMD47].."
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bitfld.long 0x0 15. "RESP_MODE_VALID,Response Mode Error Fields Valid This bit is updated when an error is detected by CQE  or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated  the bit is set to 1." "0,1"
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hexmask.long.byte 0x0 8.--12. 1. "RESP_MODE_TASK_ID,Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by.."
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hexmask.long.byte 0x0 0.--5. 1. "RESP_MODE_CMD_INDEX,Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is.."
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_index,This register stores the index of the last received command response."
hexmask.long.byte 0x4 0.--5. 1. "LAST_CRI,This field stores the index of the last received command response. CQE shall update the value every time a com-mand response is received."
line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_arg,This register stores the index of the last received command response."
hexmask.long 0x8 0.--31. 1. "LAST_CRA,This field stores the argument of the last received com-mand. CQE shall update the value every time a com-mand response is received."
line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_error_task_id,CQ Error Task ID Register"
hexmask.long.byte 0xC 0.--4. 1. "TERR_ID,Task Error ID"
tree.end
base ad:0x0
tree "MMCSD0_ECC_AGGR"
tree "MMCSD0_ECC_AGGR_RXMEM (MMCSD0_ECC_AGGR_RXMEM)"
base ad:0x706000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
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bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MMCSD0_ECC_AGGR_TXMEM (MMCSD0_ECC_AGGR_TXMEM)"
base ad:0x707000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
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bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "MMCSD0_SS_CFG (MMCSD0_SS_CFG)"
base ad:0xFA18000
rgroup.long 0x0++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem"
hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version"
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bitfld.long 0x0 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor revision"
group.long 0x10++0x37
line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.byte 0x0 24.--29. 1. "TUNINGCOUNT,Configures the Number of Taps (Phases) of the RX clock that is supported. The Tuning State machine uses this information to select one of the Taps (Phases) of the RX clock during the Tuning Procedure."
bitfld.long 0x0 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode. 0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated." "0: Synchronous Wakeup Mode: The xin_clk has to be..,1: Asyncrhonous Wakeup Mode: The xin_clk and the.."
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hexmask.long.byte 0x0 12.--15. 1. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency"
hexmask.long.word 0x0 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency"
line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
bitfld.long 0x4 30.--31. "SLOTTYPE,Slot Type. Should be set based on the final product usage. 00 - Removable SCard Slot  01 - Embedded Slot for One Device  10 - Shared Bus Slot  11 - Reserved." "0,1,2,3"
bitfld.long 0x4 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support. Suggested Value is 1'b1 (The Core supports monitoring of Asynchronous Interrupt)." "0,1"
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bitfld.long 0x4 26. "SUPPORT1P8VOLT,1.8V Support. Suggested Value is 1'b1 (The 1.8 Volt Switching is supported by Core). Optionally can be set to 1'b0 if the application doesn't want 1.8V switching (SD3.0)." "0,1"
bitfld.long 0x4 25. "SUPPORT3P0VOLT,3.0V Support. Should be set based on whether 3.0V is supported on the SD Interface." "0,1"
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bitfld.long 0x4 24. "SUPPORT3P3VOLT,3.3V Support. Suggested Value is 1'b1 as the 3.3 V is the default voltage on the SD Interface." "0,1"
bitfld.long 0x4 23. "SUSPRESSUPPORT,Suspend/Resume Support. Suggested Value is 1'b1 (The Suspend/Resume is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support Suspend/Resume Mode." "0,1"
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bitfld.long 0x4 22. "SDMASUPPORT,SDMA Support. Suggested Value is 1'b1 (The SDMA is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support SDMA Mode." "0,1"
bitfld.long 0x4 21. "HIGHSPEEDSUPPORT,High Speed Support. Suggested Value is 1'b1 (The High Speed mode is supported by Core)." "0,1"
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bitfld.long 0x4 19. "ADMA2SUPPORT,ADMA2 Support. Suggested Value is 1'b1 (The ADMA2 is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support ADMA2 Mode." "0,1"
bitfld.long 0x4 18. "SUPPORT8BIT,8-bit Support for Embedded Device. Suggested Value is 1'b1 (The Core supports 8-bit Interface). Optionally an be set to 1'b0 if the Application supports only 4-bit SD Interface." "0,1"
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bitfld.long 0x4 16.--17. "MAXBLKLENGTH,Max Block Length. Maximum Block Length supported by the Core/Device. 00: 512 (Bytes)  01: 1024  10: 2048  11: Reserved." "0: 512,1: 1024,?,?"
hexmask.long.byte 0x4 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock. This is the frequency of the xin_clk."
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bitfld.long 0x4 7. "TIMEOUTCLKUNIT,Timeout Clock Unit. Suggested Value is 1'b0 (KHz)." "0,1"
hexmask.long.byte 0x4 0.--5. 1. "TIMEOUTCLKFREQ,Timeout Clock Frequency. Suggested Value is 1 KHz. Internally the 1msec Timer is used for Timeout Detection. The 1msec Timer is generated from the xin_clk."
line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
bitfld.long 0x8 31. "HS400SUPPORT,HS400 Support. Suggested Value is 1'b1 (The Core supports HS400 Mode). This applies only to eMMC5.0 mode. This should be set to 1'b0 for SD3.0 mode Optionally can be set to 1'b0 if the application doesn't want to support HS400." "0,1"
bitfld.long 0x8 28. "SUPPORT1P8VDD2,1.8V VDD2 Support." "0,1"
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bitfld.long 0x8 27. "ADMA3SUPPORT,ADMA3 Support." "0,1"
hexmask.long.byte 0x8 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier. This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. FFh Clock Multiplier M =.."
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bitfld.long 0x8 14.--15. "RETUNINGMODES,Re-Tuning Modes. Should be set to 2'b00 as the Core supports only the Software Timer based Re-Tuning." "0,1,2,3"
bitfld.long 0x8 13. "TUNINGFORSDR50,Use Tuning for SDR50. This bit should be set if the Application wants Tuning be used for SDR50 Modes. The Core operates with or with out tuning for SDR50 mode as long as the Clock can be manually tuned using tap delay." "0,1"
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hexmask.long.byte 0x8 8.--11. 1. "RETUNINGTIMERCNT,Timer Count for Re-Tuning. This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer."
bitfld.long 0x8 7. "TYPE4SUPPORT,Driver Type 4 Support. This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not." "0,1"
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bitfld.long 0x8 6. "DDRIVERSUPPORT,Driver Type D Support. This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not." "0,1"
bitfld.long 0x8 5. "CDRIVERSUPPORT,Driver Type C Support. This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not." "0,1"
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bitfld.long 0x8 4. "ADRIVERSUPPORT,Driver Type A Support. This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not." "0,1"
bitfld.long 0x8 2. "DDR50SUPPORT,DDR50 Support. Suggested Value is 1'b1 (The Core supports DDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support DDR50." "0,1"
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bitfld.long 0x8 1. "SDR104SUPPORT,SDR104 Support. Suggested Value is 1'b1 (The Core supports SDR104 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR104." "0,1"
bitfld.long 0x8 0. "SDR50SUPPORT,SDR50 Support. Suggested Value is 1'b1 (The Core supports SDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR50." "0,1"
line.long 0xC "REGS__SS_CFG__SSCFG_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.byte 0xC 16.--23. 1. "MAXCURRENT1P8V,Maximum Current for 1.8V."
hexmask.long.byte 0xC 8.--15. 1. "MAXCURRENT3P0V,Maximum Current for 3.0V."
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hexmask.long.byte 0xC 0.--7. 1. "MAXCURRENT3P3V,Maximum Current for 3.3V."
line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current for 1.8 V (VDD2)."
line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value for Initialization."
line.long 0x18 "REGS__SS_CFG__SSCFG_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value for Default Speed."
line.long 0x1C "REGS__SS_CFG__SSCFG_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value for High Speed."
line.long 0x20 "REGS__SS_CFG__SSCFG_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value for SDR12."
line.long 0x24 "REGS__SS_CFG__SSCFG_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value for SDR25."
line.long 0x28 "REGS__SS_CFG__SSCFG_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value for SDR50."
line.long 0x2C "REGS__SS_CFG__SSCFG_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value for SDR104."
line.long 0x30 "REGS__SS_CFG__SSCFG_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value for DDR50."
line.long 0x34 "REGS__SS_CFG__SSCFG_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x34 0.--12. 1. "HS400PRESETVAL,Preset Value for HS400."
rgroup.long 0x60++0x17
line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
bitfld.long 0x0 31. "SDHC_CMDIDLE,Idle signal to enable S/W to gate off the clocks." "0,1"
hexmask.long.word 0x0 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus."
line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
hexmask.long.word 0x4 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus."
line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
hexmask.long.word 0x8 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus."
line.long 0xC "REGS__SS_CFG__SSCFG_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
hexmask.long.word 0xC 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)."
line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)."
line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus."
group.long 0x100++0x17
line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
bitfld.long 0x0 20.--22. "DR_TY,Drive Source/Sink impedance programming. 0 => 50 Ohms  1 => 33 Ohms  2 => 66 Ohms  3 => 100 Ohms  4 => 40 Ohms." "0: 50 Ohms,1: 33 Ohms,2: 66 Ohms,3: 100 Ohms,4: 40 Ohms,?,?,?"
bitfld.long 0x0 17. "RETRIM,Start CALIO calibration cycle. At positive edge initiates CALIO calibration cycle." "0,1"
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bitfld.long 0x0 16. "EN_RTRIM,CALIO enable. Enables CALIO  If enabled CALIO will start calibration cycle at phyctrl_pdb positive edge." "0,1"
hexmask.long.byte 0x0 4.--7. 1. "DLL_TRM_ICP,Analog DLL's Charge Pump Current Trim. Programs the analog DLL loop gain."
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bitfld.long 0x0 1. "ENDLL,Enable DLL. Enables the analog DLL circuits." "0,1"
bitfld.long 0x0 0. "PDB,CALIO S/M power down bar. SOC asserts after power up sequence is completed." "0,1"
line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
bitfld.long 0x4 29. "OD_RELEASE_STRB,Disable an internal 4.7K pull up resistor on STRB line in open drain mode." "0,1"
bitfld.long 0x4 28. "OD_RELEASE_CMD,Disable an internal 4.7K pull up resistor on CMD line in open drain mode." "0,1"
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hexmask.long.byte 0x4 16.--23. 1. "OD_RELEASE_DAT,Disable an internal 4.7K pull up resistor on data lines in open drain mode."
bitfld.long 0x4 13. "ODEN_STRB,Open Drain Enable on STRB line." "0,1"
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bitfld.long 0x4 12. "ODEN_CMD,Open Drain Enable on CMD line." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "ODEN_DAT,Open Drain Enable on DAT lines."
line.long 0x8 "REGS__SS_CFG__SSCFG_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
bitfld.long 0x8 29. "PU_STRB,Enable pull up on STRB line. If ren_strb is high week pull up is enabled on STRB line." "0,1"
bitfld.long 0x8 28. "PU_CMD,Enable pull up on CMD line. If ren_cmd is high week pull up is enabled on CMD line." "0,1"
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hexmask.long.byte 0x8 16.--23. 1. "PU_DAT,Enable pull up on DAT lines. If ren_dat is high week pull up is enabled on DATA lines."
bitfld.long 0x8 13. "REN_STRB,Enable pull up/down on the STRB line. If pu_strb is high a week pull up is enabled on STRB line  if low week pull down is enabled on STRB line." "0,1"
newline
bitfld.long 0x8 12. "REN_CMD,Enable pull up/down on the CMD line. If pu_cmd is high a week pull up is enabled on CMD line  if low week pull down is enabled on CMD line." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "REN_DAT,Enable pull up/down on the DAT lines. If pu_dat is high a week pull up is enabled on DATA lines  if low week pull down is enabled on DATA lines."
line.long 0xC "REGS__SS_CFG__SSCFG_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
hexmask.long.byte 0xC 24.--31. 1. "STRBSEL,Select the Four Taps for each of STRB_90 and STRB_180 Outputs. strbsel[3:2] selects one of the four for STRB_180 and strbsel[1:0] selects the four taps for STRB_90."
bitfld.long 0xC 20. "OTAPDLYENA,Output Tap Delay Enable. Enables manual control of the TX clock tap delay  for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." "0,1"
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hexmask.long.byte 0xC 12.--15. 1. "OTAPDLYSEL,Output Tap Delay Select. Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface."
bitfld.long 0xC 9. "ITAPCHGWIN,Input Tap Change Window. It gets asserted by the controller while changing the itapdlysel. Used to gate of the RX clock during switching the clock source while tap is changing to avoid clock glitches." "0,1"
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bitfld.long 0xC 8. "ITAPDLYENA,Input Tap Delay Enable. This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes." "0,1"
hexmask.long.byte 0xC 0.--4. 1. "ITAPDLYSEL,Input Tap Delay Select. Manual control of the RX clock Tap Delay in the non HS200/HS400 modes."
line.long 0x10 "REGS__SS_CFG__SSCFG_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
bitfld.long 0x10 17. "SELDLYTXCLK,Select the Delay chain based txclk. Enables the TX clock based delay chain rather than analog DLL based delay chain." "0,1"
bitfld.long 0x10 16. "SELDLYRXCLK,Select the Delay chain based rxclk. Enables the RX clock based delay chain rather than analog DLL based delay chain." "0,1"
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bitfld.long 0x10 8.--10. "FRQSEL,Select the frequency range of DLL operation: 0 => 200MHz to 170 MHz  1 => 170MHz to 140 MHz  2 => 140MHz to 110 MHz  3 => 110MHz to 80MHz  4 => 80MHz to 50 MHz  5 => 275Mhz to 250MHz  6 => 250MHz to 225MHz  7 => 225MHz to 200MHz." "0: 200MHz to 170 MHz,1: 170MHz to 140 MHz,2: 140MHz to 110 MHz,3: 110MHz to 80MHz,4: 80MHz to 50 MHz,5: 275Mhz to 250MHz,6: 250MHz to 225MHz,7: 225MHz to 200MHz"
bitfld.long 0x10 0.--2. "CLKBUFSEL,Clock Delay Buffer Select. Selects one of the eight taps in the CLK Delay Buffer based on PVT variation." "0,1,2,3,4,5,6,7"
line.long 0x14 "REGS__SS_CFG__SSCFG_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
bitfld.long 0x14 31. "BISTENABLE,Internal BIST operation enable. Enables the embedded BIST." "0,1"
bitfld.long 0x14 30. "BISTSTART,Internal BIST start. Starts the embedded BIST operation." "0,1"
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hexmask.long.byte 0x14 24.--27. 1. "BISTMODE,Internal BIST mode Select. Select the embedded BIST mode of operation."
hexmask.long.byte 0x14 0.--7. 1. "TESTCTRL,PHY test control: 8'b00010000 => Test EMMC IOs sink impedance  8'b00010001 => Test EMMC IOs source impedance  8'b00100000 => Test RX clock phases on data lines  8'b00110000 => Test TX clock phases on data lines  8'b01000000 => Test STRB clock.."
rgroup.long 0x130++0x7
line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.."
hexmask.long.byte 0x0 4.--7. 1. "RTRIM,CALIO Calibration Result. Holds the content of CALIO Impedance Calibration Result."
bitfld.long 0x0 3. "BISTDONE,Internal BIST completed test cycle. Indicates that the embedded BIST has completed the test cycle." "0,1"
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bitfld.long 0x0 2. "EXR_NINST,External Resistor on CALIO absent. Indicates trim cycle started and external resistor is absent." "0,1"
bitfld.long 0x0 1. "CALDONE,STATUS  indicate that CALIO Calibration is completed successfully." "0,1"
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bitfld.long 0x0 0. "DLLRDY,DLL ready. Indicates that DLL loop is locked." "0,1"
line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.."
hexmask.long 0x4 0.--31. 1. "BISTSTATUS,Internal BIST data compare results. BIST cycle data comparison results."
tree.end
tree.end
tree "MMCSD1"
base ad:0x0
tree "MMCSD1_CTL_CFG (MMCSD1_CTL_CFG)"
base ad:0xFA00000
group.word 0x0++0xF
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_lo,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
hexmask.word 0x0 0.--15. 1. "SDMA_ADDRESS,When Host Version 4 Enable is set to 0 in the Host Control 2 register DMA uses this register as system address in only 32-bit addressing mode. Auto CMD23 cannot be used with SDMA. When Host Version 4 Enable is set to 1  SDMA uses ADMA System.."
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_hi,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
hexmask.word 0x2 0.--15. 1. "SDMA_ADDRESS,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_block_size,This register is used to configure the number of bytes in a data block"
bitfld.word 0x4 12.--14. "SDMA_BUF_SIZE,To perform long DMA transfer  System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary.." "0,1,2,3,4,5,6,7"
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hexmask.word 0x4 0.--11. 1. "XFER_BLK_SIZE,This field specifies the block size for block data transfers for CMD17  CMD18  CMD24  CMD25 and CMD53. It can be accessed only if no transaction is executing [i.e after a transaction has stopped]. Read operations during transfer return an.."
line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_block_count,This register is used to configure the number of data blocks"
hexmask.word 0x6 0.--15. 1. "XFER_BLK_CNT,Host Controller Version 4.10 extends block count to 32-bit [Refer to Section 1.15].Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: [1] If Host Version 4 Enable in the Host Control 2.."
line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_lo,This register contains Lower bits of SD Command Argument"
hexmask.word 0x8 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit23-8 of Command-Format."
line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_hi,This register contains higher bits of SD Command Argument"
hexmask.word 0xA 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit39-24 of Command-Format."
line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_transfer_mode,This register is used to control the operations of data transfers"
bitfld.word 0xC 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command Complete.." "0,1"
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bitfld.word 0xC 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.If Host Driver checks response error  this bit is set to 0 and Response Interrupt.." "0,1"
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bitfld.word 0xC 6. "RESP_TYPE,When response error check is enabled  this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO." "0,1"
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bitfld.word 0xC 5. "MULTI_BLK_SEL,This bit enables multiple block data transfers." "0,1"
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bitfld.word 0xC 4. "DATA_XFER_DIR,This bit defines the direction of data transfers." "0,1"
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bitfld.word 0xC 2.--3. "AUTO_CMD_ENA,There are three methods to stop Multiple-block read and write operation. [1] Auto CMD12 Enable: Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 01b  the Host.." "0,1,2,3"
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bitfld.word 0xC 1. "BLK_CNT_ENA,This bit is used to enable the Block count register  which is only relevant for multiple block transfers. When this bit is 0  the Block Count register is disabled  which is useful in executing an infinite transfer." "0,1"
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bitfld.word 0xC 0. "DMA_ENA,DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1  a DMA operation shall begin when the HD writes to the upper byte of Command register [00Fh]." "0,1"
line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_command,This register is used to program the Command for host controller"
hexmask.word.byte 0xE 8.--13. 1. "CMD_INDEX,This bit shall be set to the command number [CMD0-63  ACMD0-63]."
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bitfld.word 0xE 6.--7. "CMD_TYPE,There are three types of special commands. Suspend  Resume andAbort. These bits shall bet set to 00b for all other commands. Suspend Command: If the Suspend command succeeds  the HC shall assume the SD Bus has been released and that it is.." "0,1,2,3"
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bitfld.word 0xE 5. "DATA_PRESENT,This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 1. Commands using only CMD line [ex. CMD52]. 2. Commands with no data transferbut using busy.." "0,1"
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bitfld.word 0xE 4. "CMD_INDEX_CHK_ENA,If this bit is set to 1  the HC shall check the index field in the response to see if it has the same value as the command index. If it is not  it is reported as a Command Index Error. If this bit is set to 0  the Index field is not.." "0,1"
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bitfld.word 0xE 3. "CMD_CRC_CHK_ENA,If this bit is set to 1  the HC shall check the CRC field in the response. If an error is detected  it is reported as a Command CRC Error. If this bit is set to 0  the CRC field is not checked." "0,1"
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bitfld.word 0xE 2. "SUB_CMD,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]. When issuing a main com-mand  this bit is set to 0 and when issuing a sub command  this bit is set to 1. Setting of this bit is checked.." "0,1"
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bitfld.word 0xE 0.--1. "RESP_TYPE_SEL,Response Type Select." "0,1,2,3"
rgroup.word 0x10++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_response,This register is used to store responses from SD Cards"
hexmask.word 0x0 0.--15. 1. "CMD_RESP,R[] refers to a bit range within the response data as transmitted on the SD Bus  REP[] refers to a bit range within the Response register."
group.long 0x20++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_data_port,This register is used to access internal buffer"
hexmask.long 0x0 0.--31. 1. "BUF_RD_DATA,The Host Controller Buffer can be accessed through this 32-bit Data Port Register."
rgroup.long 0x24++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_presentstate,The Host Driver can get status of the Host Controller from this 32-bit read-only register"
bitfld.long 0x0 31. "UHS2_IF_DETECTION,This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 regis-ter. UHS-II interface initialization is activated by setting SD Clock Enable in the.." "0,1"
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bitfld.long 0x0 30. "UHS2_IF_LANE_SYNC,This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On detecting UHS-II Interface [D31=1]  Host Controller provides SYN.." "0,1"
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bitfld.long 0x0 29. "UHS2_DORMANT,This status indicates whether UHS-II Ianes enterDormant state. This function is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On issuing GO_DORMAT_STATE com-mand  Go Dormant Command [111b]; is set to Command.." "0,1"
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bitfld.long 0x0 28. "SUB_COMMAND_STS,The Command register and Response register are commonly used for main command and sub command. This status is used to distinguish which response error statuses  main command or sub command  indicated in the Error Interrupt Status.." "0,1"
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bitfld.long 0x0 27. "CMD_NOT_ISS_BY_ERR,Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error. [Equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the Auto CMD Error.." "0,1"
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bitfld.long 0x0 24. "SDIF_CMDIN,This status is used to check DAT line level to recover from errors  and for debugging." "0,1"
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bitfld.long 0x0 23. "SDIF_DAT3IN,This status is used to check DAT line level to recover from errors  and for debugging. This is especially useful in detecting the busy signal level from DAT[3]." "0,1"
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bitfld.long 0x0 22. "SDIF_DAT2IN,This status is used to check DAT line level to recover from errors  and for debugging. This is especially useful in detecting the busy signal level from DAT[2]." "0,1"
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bitfld.long 0x0 21. "SDIF_DAT1IN,This status is used to check DAT line level to recover from errors  and for debugging. This is especially useful in detecting the busy signal level from DAT[1]." "0,1"
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bitfld.long 0x0 20. "SDIF_DAT0IN,This status is used to check DAT line level to recover from errors  and for debugging. This is especially useful in detecting the busy signal level from DAT[0]." "0,1"
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bitfld.long 0x0 19. "WRITE_PROTECT,The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin." "0,1"
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bitfld.long 0x0 18. "CARD_DETECT,This bit reflects the inverse value of the SDCD# pin. '0' No Card present [SDCD# = 1] '1' Card present [SDCD# = 0]" "0,1"
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bitfld.long 0x0 17. "CARD_STATE_STABLE,This bit is used for testing. If it is 0  the Card Detect Pin Level is not stable. If this bit is set to 1 it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this.." "0,1"
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bitfld.long 0x0 16. "CARD_INSERTED,This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt.." "0,1"
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bitfld.long 0x0 11. "BUF_RD_ENA,This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1  readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the.." "0,1"
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bitfld.long 0x0 10. "BUF_WR_ENA,This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data. If this bit is 1  data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written.." "0,1"
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bitfld.long 0x0 9. "RD_XFER_ACTIVE,This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: After the end bit of the read command. When writing a 1 to continue Request in the Block.." "0,1"
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bitfld.long 0x0 8. "WR_XFER_ACTIVE,This status indicates a write transfer is active. If this bit is 0  it means no valid write data exists in the HC. This bit is set in either of the following cases: After the end bit of the write command. When writing a.." "0,1"
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bitfld.long 0x0 7. "SDIF_DAT7IN,This status is used to check DAT line level to recover from errors  and for debugging." "0,1"
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bitfld.long 0x0 6. "SDIF_DAT6IN,This status is used to check DAT line level to recover from errors  and for debugging." "0,1"
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bitfld.long 0x0 5. "SDIF_DAT5IN,This status is used to check DAT line level to recover from errors  and for debugging." "0,1"
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bitfld.long 0x0 4. "SDIF_DAT4IN,This status is used to check DAT line level to recover from errors  and for debugging." "0,1"
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bitfld.long 0x0 3. "RETUNING_REQ,Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is.." "0,1"
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bitfld.long 0x0 2. "DATA_LINE_ACTIVE,This bit indicates whether one of the DAT line on SD bus is in use." "0,1"
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bitfld.long 0x0 1. "INHIBIT_DAT,This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0  it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit [DAT] [ex. R1b  R5b.." "0,1"
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bitfld.long 0x0 0. "INHIBIT_CMD,SD Mode If this bit is 0  it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register [00Fh] is written. This bit is cleared when the command response is.." "0,1"
group.byte 0x28++0x3
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control1,This register is used to program DMA modes. LED Control. Data Transfer Width. High Speed Enable. Card detect test level and signal selection"
bitfld.byte 0x0 7. "CD_SIG_SEL,This bit selects source for card detection. '0' SDCD# is selected [for normal use] '1' The card detect test level is selected" "0,1"
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bitfld.byte 0x0 6. "CD_TEST_LEVEL,This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates [card ins or card removal] interrupt when the normal int sts enable bit is set. '0' No Card '1' Card Inserted" "0,1"
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bitfld.byte 0x0 5. "EXT_DATA_WIDTH,This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode  this bit may be set to 1. If this bit.." "0,1"
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bitfld.byte 0x0 3.--4. "DMA_SELECT,This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the Capabilities register. Selected DMA is enabled by DMA Enable of the Transfer Mode register in SD mode and DMA Enable of UHS-II Transfer.." "0,1,2,3"
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bitfld.byte 0x0 2. "HIGH_SPEED_ENA,This bit is optional. Before setting this bit  the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 [default]  the HC outputs CMD line and DAT lines at the falling edge of the SD clock [up to.." "0,1"
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bitfld.byte 0x0 1. "DATA_WIDTH,This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode." "0,1"
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bitfld.byte 0x0 0. "LED_CONTROL,This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands  this bit can be set during all transactions. It is not necessary to change for each.." "0,1"
line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_power_control,This register is used to program the SD Bus power and voltage level"
bitfld.byte 0x1 5.--7. "UHS2_VOLTAGE,This field determines supply voltage range to VDD2. This field can be set to 101b if 1.8V VDD2 Support in the Capabilities register is set to 1. '000' VDD2 Not supported '001'- '011' Reserved '100' Reserved for 1.2V.." "0,1,2,3,4,5,6,7"
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bitfld.byte 0x1 4. "UHS2_POWER,Setting this bit enables providing VDD2. '0' Power Off '1' Power On" "0,1"
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bitfld.byte 0x1 1.--3. "SD_BUS_VOLTAGE,By setting these bits  the HD selects the voltage level for the SD card. Before setting this register  the HD shall check the voltage support bits in the capabilities register. If an unsupported voltage is selected  the Host System shall.." "0,1,2,3,4,5,6,7"
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bitfld.byte 0x1 0. "SD_BUS_POWER,Before setting this bit  the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State  this bit shall be cleared. If this bit is cleared  the Host Control-ler should immediately stop driving CMD and DAT[3:0].." "0,1"
line.byte 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_block_gap_control,This register is used to program the block gap request. read wait control and interrupt at block gap"
bitfld.byte 0x2 7. "BOOT_ACK_ENA,To check for the boot acknowledge in boot operation." "0,1"
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bitfld.byte 0x2 6. "ALT_BOOT_MODE,To start boot code access in alternative mode." "0,1"
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bitfld.byte 0x2 5. "BOOT_ENABLE,To start boot code access." "0,1"
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bitfld.byte 0x2 4. "SPI_MODE,SPI mode enable bit." "0,1"
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bitfld.byte 0x2 3. "INTRPT_AT_BLK_GAP,This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt.." "0,1"
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bitfld.byte 0x2 2. "RDWAIT_CTRL,The read wait function is optional for SDIO cards. If the card supports read wait  set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data  which.." "0,1"
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bitfld.byte 0x2 1. "CONTINUE,This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap  set Stop At block Gap Request to 0 and set this bit to restart the transfer. The Host Controller automatically.." "0,1"
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bitfld.byte 0x2 0. "STOP_AT_BLK_GAP,This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers. Until the transfer complete is set to 1  indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the.." "0,1"
line.byte 0x3 "SDHC_WRAP__CTL_CFG__CTLCFG_wakeup_control,This register is used to program the wakeup functionality"
bitfld.byte 0x3 2. "CARD_REMOVAL,This bit enables wakeup event via Card removal assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1"
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bitfld.byte 0x3 1. "CARD_INSERTION,This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1"
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bitfld.byte 0x3 0. "CARD_INTERRUPT,This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS [Wake Up Support] in CIS is set to 1." "0,1"
group.word 0x2C++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_clock_control,This register is used to program the Clock frequency select. generator select. Clock enable. Internal Clock state fields"
hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FRQSEL,This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following.."
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bitfld.word 0x0 6.--7. "SDCLK_FRQSEL_UPBITS,Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select." "0,1,2,3"
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bitfld.word 0x0 5. "CLKGEN_SEL,This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported [non-zero value is set to Clock Multiplier in the Capabilities register]  this bit attribute is RW  and if not.." "0,1"
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bitfld.word 0x0 3. "PLL_ENA,This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable and PLL Enable and to minimize output latency [ex. SDCLK/RCLK  D0lane].." "0,1"
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bitfld.word 0x0 2. "SD_CLK_ENA,The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then  the HC shall maintain the same clock frequency until SDCLK is stopped [Stop at SDCLK = 0]. If the HC detects the No Card state .." "0,1"
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rbitfld.word 0x0 1. "INT_CLK_STABLE,This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock.." "0,1"
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bitfld.word 0x0 0. "INT_CLK_ENA,This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still  registers shall be able to be read and written. Clock starts to oscillate when this.." "0,1"
group.byte 0x2E++0x1
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_timeout_control,The register sets the Data Timeout counter value"
hexmask.byte 0x0 0.--3. 1. "COUNTER_VALUE,This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will.."
line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_software_reset,This register is used to program the software reset for data. command and for all"
bitfld.byte 0x1 2. "SWRST_FOR_DAT,Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register: Buffer is cleared and Initialized. Present State register: Buffer read Enable  Buffer write.." "0,1"
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bitfld.byte 0x1 1. "SWRST_FOR_CMD,Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command. From Version 4.10  this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit [including.." "0,1"
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bitfld.byte 0x1 0. "SWRST_FOR_ALL,This reset affects the entire HC except for the card detection circuit. Register bits of type ROC  RW  RW1C  RWAC are cleared to 0. During its initialization  the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0.." "0,1"
group.word 0x30++0xB
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts,This register gives the status of all the interrupts"
rbitfld.word 0x0 15. "ERROR_INTR,If any of the bits in the Error Interrupt Status Register are set  then this bit is set. Therefore the HD can test for an error by checking this bit first. In UHS-II mode is enabled  if any of the bits in the UHS-II Error.." "0,1"
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bitfld.word 0x0 14. "BOOT_COMPLETE,This status is set if the boot operation gets terminated. '0' Boot operation is not terminated '1' Boot operation is terminated" "0,1"
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bitfld.word 0x0 13. "RCV_BOOT_ACK,This status is set if the boot acknowledge is received from device. '0' Boot ack not recieved '1' Boot ack is recieved" "0,1"
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rbitfld.word 0x0 12. "RETUNING_EVENT,This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer [not large block count] can be completed.." "0,1"
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rbitfld.word 0x0 11. "INTC,This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor." "0,1"
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rbitfld.word 0x0 10. "INTB,This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor." "0,1"
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rbitfld.word 0x0 9. "INTA,This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor. NOTE : INT_A  INT_B  and INT_C are to be implemented based on the.." "0,1"
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rbitfld.word 0x0 8. "CARD_INTR,When this status has been set and the Host Driver needs to start this interrupt service  Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the Host.." "0,1"
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bitfld.word 0x0 7. "CARD_REM,This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1"
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bitfld.word 0x0 6. "CARD_INS,This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1"
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bitfld.word 0x0 5. "BUF_RD_READY,This status is set if the Buffer Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure.In UHS-II mode  this bit is set at FC [Flow Control] unit basis. '0' Not ready to.." "0,1"
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bitfld.word 0x0 4. "BUF_WR_READY,This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode  this bit is set at FC [Flow Control] unit basis. '0' Not ready to write to buffer  '1' Ready to write to buffer" "0,1"
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bitfld.word 0x0 3. "DMA_INTERRUPT,This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser. '0' No DMA Interrupt '1' DMA Interrupt is generated" "0,1"
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bitfld.word 0x0 2. "BLK_GAP_EVENT,If the Stop At Block Gap Request in the BlockGap Control Register is set  this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status [When the transaction is stopped at SD Bus timing. The Read.." "0,1"
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bitfld.word 0x0 1. "XFER_COMPLETE,This bit is set when a read / write transaction is completed. SD Mode Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is.." "0,1"
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bitfld.word 0x0 0. "CMD_COMPLETE,SD Mode This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23] Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1  it can be considered that the.." "0,1"
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts,This register gives the status of the error interrupts"
bitfld.word 0x2 12. "HOST,Occurs when detecting ERROR in m_hresp[dma transaction]" "0,1"
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bitfld.word 0x2 11. "RESP,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register  Host Controller Checks R1 or.." "0,1"
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bitfld.word 0x2 10. "TUNING,This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]. By detecting Tuning Error  Host Driver needs to abort a.." "0,1"
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bitfld.word 0x2 9. "ADMA,This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register." "0,1"
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bitfld.word 0x2 8. "AUTO_CMD,Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto CMD12. Auto CMD Error Status register is.." "0,1"
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bitfld.word 0x2 7. "CURR_LIMIT,By setting the SD Bus Power bit in the Power Control Register  the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function  it can be protected from an Illegal card by stopping power supply to the card in.." "0,1"
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bitfld.word 0x2 6. "DATA_ENDBIT,Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status." "0,1"
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bitfld.word 0x2 5. "DATA_CRC,Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010." "0,1"
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bitfld.word 0x2 4. "DATA_TIMEOUT,Occurs when detecting one of following timeout conditions: 1. Busy Timeout for R1b  R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout." "0,1"
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bitfld.word 0x2 3. "CMD_INDEX,Occurs if a Command Index error occurs in the Command Response." "0,1"
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bitfld.word 0x2 2. "CMD_ENDBIT,Occurs when detecting that the end bit of a command response is 0." "0,1"
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bitfld.word 0x2 1. "CMD_CRC,Command CRC Error is generated in two cases. 1. If a response is returned and the Command Time-out Error is set to 0  this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by.." "0,1"
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bitfld.word 0x2 0. "CMD_TIMEOUT,Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict  in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK.." "0,1"
line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts_ena,This register is used to enable the normal interrupt status register fields"
rbitfld.word 0x4 15. "BIT15_FIXED0,The HC shall control error Interrupts using the Error Interrupt Status Enable register." "0,1"
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bitfld.word 0x4 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 12. "RETUNING_EVENT,0 - Masked 1 - Enabled" "0,1"
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bitfld.word 0x4 11. "INTC,If this bit is set to 0  the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent.." "0,1"
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bitfld.word 0x4 10. "INTB,If this bit is set to 0  the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent.." "0,1"
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bitfld.word 0x4 9. "INTA,If this bit is set to 0  the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent.." "0,1"
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bitfld.word 0x4 8. "CARD_INTERRUPT,If this bit is set to 0  the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before.." "0,1"
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bitfld.word 0x4 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 3. "DMA_INTERRUPT,'0' Masked  '1' Enabled" "0,1"
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bitfld.word 0x4 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x4 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1"
line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts_ena,This register is used to enable the Error Interrupt Status register fields"
bitfld.word 0x6 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3"
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bitfld.word 0x6 12. "HOST,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 11. "RESP,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 10. "TUNING,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 9. "ADMA,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x6 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1"
line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sig_ena,This register is used to enable the Normal Interrupt Signal register"
rbitfld.word 0x8 15. "BIT15_FIXED0,The HD shall control error Interrupts using the Error Interrupt Signal Enable register." "0,1"
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bitfld.word 0x8 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 12. "RETUNING_EVENT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 11. "INTC,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 10. "INTB,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 9. "INTA,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 8. "CARD_INTERRUPT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0x8 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1"
line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sig_ena,This register is used to enable Error Interrupt Signal register"
bitfld.word 0xA 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3"
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bitfld.word 0xA 12. "HOST,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 11. "RESP,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 10. "TUNING,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 9. "ADMA,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1"
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bitfld.word 0xA 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1"
rgroup.word 0x3C++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_autocmd_err_sts,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23"
bitfld.word 0x0 7. "CMD_NOT_ISSUED,Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1"
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bitfld.word 0x0 5. "RESP,This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23. This status should be ignored if any bit of D00 to D04 is set to 1." "0,1"
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bitfld.word 0x0 4. "INDEX,Occurs if the Command Index error occurs in response to a command." "0,1"
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bitfld.word 0x0 3. "ENDBIT,Occurs when detecting that the end bit of command response is 0." "0,1"
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bitfld.word 0x0 2. "CRC,Occurs when detecting a CRC error in the command response." "0,1"
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bitfld.word 0x0 1. "TIMEOUT,Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1  the other error status bits [D04 - D02] are meaningless." "0,1"
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bitfld.word 0x0 0. "ACMD12_NOT_EXEC,If memory multiple block data transfer is not started due to command error  this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block.." "0,1"
group.word 0x3E++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control2,This register is used to program UHS Select Mode.UHS Select Mode.Driver Strength Select.Execute Tuning.Sampling Clock Select.Asynchronous Interrupt Enable and Preset value enable"
bitfld.word 0x0 15. "PRESET_VALUE_ENA,Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation  it is difficult to determine these parameters in the Standard Host Driver. When Preset.." "0,1"
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bitfld.word 0x0 14. "ASYNCH_INTR_ENA,This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode [and zero is.." "0,1"
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bitfld.word 0x0 13. "BIT64_ADDRESSING,This field is effective when Host Version 4.00 Enable is set to 1. Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host.." "0,1"
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bitfld.word 0x0 12. "HOST_VER40_ENA,This bit selects either Version 3.00 compatible mode or Ver4.mode. In Version 4.00  support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit. In Version.." "0,1"
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bitfld.word 0x0 11. "CMD23_ENA,In memory card initialization  Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 [SCR[33]=1]  this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3.." "0,1"
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bitfld.word 0x0 10. "ADMA2_LEN_MODE,This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit." "0,1"
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bitfld.word 0x0 9. "DRIVER_STRENGTH2,This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value." "0,1"
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bitfld.word 0x0 8. "UHS2_INTF_ENABLE,This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization  this bit shall be set to 1. Before trying to start SD mode initialization  this bit shall be set to 0. This bit is used to enable UHS-II IF.." "0,1"
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bitfld.word 0x0 7. "SAMPLING_CLK_SELECT,This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller.." "0,1"
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bitfld.word 0x0 6. "EXECUTE_TUNING,This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning.." "0,1"
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bitfld.word 0x0 4.--5. "DRIVER_STRENGTH1,Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling  this field is not effective. This field can be set depends on Driver Type A  C and D support bits in the Capabilities register. This bit depends.." "0,1,2,3"
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bitfld.word 0x0 3. "V1P8_SIGNAL_ENA,This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within.." "?,1: SDR50"
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bitfld.word 0x0 0.--2. "UHS_MODE_SELECT,This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode  this field is effective when 1.8V Signal-ing Enable is set to 1. In case of UHS-II mode  1.8V Signaling Enable shall be set to 0. Setting of this field.." "0,1,2,3,4,5,6,7"
rgroup.quad 0x40++0xF
line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_capabilities,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initializa-tion."
bitfld.quad 0x0 63. "HS400_SUPPORT,1 HS400 is Supported 0 HS400 is Not Supported" "0,1"
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bitfld.quad 0x0 60. "VDD2_1P8_SUPPORT,This field indicates that support of VDD2 on Host system." "0,1"
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bitfld.quad 0x0 59. "ADMA3_SUPPORT,This field indicates that support of ADMA3 on Host Controller." "0,1"
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bitfld.quad 0x0 57. "SPI_BLK_MODE,This field indicates whether SPI Block Mode is supported or not." "0,1"
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bitfld.quad 0x0 56. "SPI_SUPPORT,This field indicates whether SPI Mode is supported or not." "0,1"
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hexmask.quad.byte 0x0 48.--55. 1. "CLOCK_MULTIPLIER,This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. 'FF' Clock Multiplier M = 256.."
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bitfld.quad 0x0 46.--47. "RETUNING_MODES,This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. '00' Mode 1 '01' Mode 2 '10' Mode 3 '11' Reserved. There are two.." "0,1,2,3"
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bitfld.quad 0x0 45. "TUNING_FOR_SDR50,If this bit is set to 1  this Host Controller requires tuning to operate SDR50. [Tuning is always required to operate SDR104]. '0' '1'" "0,1"
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hexmask.quad.byte 0x0 40.--43. 1. "RETUNING_TIMER_CNT,This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ------.."
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bitfld.quad 0x0 38. "DRIVERD_SUPPORT,This bit indicates support of Driver Type D for 1.8 Signaling. '0' Driver Type D is Not supported  '1' Driver Type D is supported" "0,1"
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bitfld.quad 0x0 37. "DRIVERC_SUPPORT,This bit indicates support of Driver Type C for 1.8 Signaling. '0' Driver Type C is Not supported  '1' Driver Type C is supported" "0,1"
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bitfld.quad 0x0 36. "DRIVERA_SUPPORT,This bit indicates support of Driver Type A for 1.8 Signaling. '0' Driver Type A is Not supported  '1' Driver Type A is supported" "0,1"
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bitfld.quad 0x0 35. "UHS2_SUPPORT,This bit indicates whether Host controller supports UHS-II. If this bit is set to 1  1.8V VDD2 Support shall be set to 1 [Host Sys- tem shall support VDD2 power supply]. 1 UHS-II is Supported 0 UHS-II is Not Supported" "0,1"
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bitfld.quad 0x0 34. "DDR50_SUPPORT,This bit indicates whether DDR50 is supported or not." "0,1"
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bitfld.quad 0x0 33. "SDR104_SUPPORT,This bit indicates whether SDR104 is supported or not.SDR104 requires tuning." "0,1"
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bitfld.quad 0x0 32. "SDR50_SUPPORT,If SDR104 is supported  this bit shall be set to 1. Bit 40 indicates whether SDR50 requires tuning or not." "0,1"
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bitfld.quad 0x0 30.--31. "SLOT_TYPE,This field indicates usage of a slot by a specific Host System. [A host controller register set is defined perslot.] Embedded slot for one device [01b] means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot.." "0,1,2,3"
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bitfld.quad 0x0 29. "ASYNCH_INTR_SUPPORT,Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1"
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bitfld.quad 0x0 28. "ADDR_64BIT_SUPPORT_V3,IMeaning of this bit is different depends on Versions [Refer to Table 2-35 for more details]. Host Controller Version 3.00 and Ver4.10 use this bit as 64-bit System Address support for V3 mode. Host Con- troller Version 4.00 uses.." "0,1"
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bitfld.quad 0x0 27. "ADDR_64BIT_SUPPORT_V4,This bit is added from Version 4.10. Set-ting 1 to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode [Refer to Table 2-35 for the summary of 64-bit sys-tem address support].. When.." "0,1"
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bitfld.quad 0x0 26. "VOLT_1P8_SUPPORT,This bit indicates whether the HC supports 1.8V." "0,1"
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bitfld.quad 0x0 25. "VOLT_3P0_SUPPORT,This bit indicates whether the HC supports 3.0V." "0,1"
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bitfld.quad 0x0 24. "VOLT_3P3_SUPPORT,This bit indicates whether the HC supports 3.3V." "0,1"
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bitfld.quad 0x0 23. "SUSP_RES_SUPPORT,This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0  the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands." "0,1"
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bitfld.quad 0x0 22. "SDMA_SUPPORT,This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.Version 4.10 Host Controller shall support SDMA if ADMA2 is supported." "0,1"
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bitfld.quad 0x0 21. "HIGH_SPEED_SUPPORT,This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz [for SD]/ 20MHz to 52MHz [for MMC]." "0,1"
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bitfld.quad 0x0 19. "ADMA2_SUPPORT,'0' ADMA2 Not Supported '1' ADMA2 Supported" "0,1"
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bitfld.quad 0x0 18. "BUS_8BIT_SUPPORT,This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case  refer to Bus Width Preset in the Shared Bus resister." "0,1"
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bitfld.quad 0x0 16.--17. "MAX_BLK_LENGTH,This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below." "0,1,2,3"
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hexmask.quad.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,[1]6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. '11xx xxxxb' Not.."
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bitfld.quad 0x0 7. "TIMEOUT_CLK_UNIT,This bit shows the unit of base clock frequency used to detect Data Timeout Error." "0,1"
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hexmask.quad.byte 0x0 0.--5. 1. "TIMEOUT_CLK_FREQ,This bit shows the base clock frequency used to detect Data Timeout Error. '000000' Get Information via another method  'not 0' 1KHz to 63KHz/1MHz to 63MHz"
line.quad 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_max_current_cap,This register indicates maximum current capability for each voltage"
hexmask.quad.byte 0x8 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8V VDD2"
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hexmask.quad.byte 0x8 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8V VDD1"
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hexmask.quad.byte 0x8 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0V VDD1"
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hexmask.quad.byte 0x8 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3V VDD1"
wgroup.word 0x50++0x3
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_ACMD_Err_Sts,This register is not physically implemented. rather it is an address where Auto CMD Error Status register can be written."
bitfld.word 0x0 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error." "0,1"
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bitfld.word 0x0 5. "RESP,Force Event for AUTO CMD Response Error.." "0,1"
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bitfld.word 0x0 4. "INDEX,Force Event for AUTO CMD Index Error.." "0,1"
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bitfld.word 0x0 3. "ENDBIT,Force Event for AUTO CMD End Bit Error." "0,1"
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bitfld.word 0x0 2. "CRC,Force Event for AUTO CMD Timeout Error." "0,1"
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bitfld.word 0x0 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error." "0,1"
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bitfld.word 0x0 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed." "0,1"
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_Err_Int_Sts,This register is not physically implemented. rather it is an address where Error Interrupt Status register can be written."
bitfld.word 0x2 12. "HOST,Force Event for Host Error" "0,1"
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bitfld.word 0x2 11. "RESP,Force Event for Response Error" "0,1"
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bitfld.word 0x2 10. "TUNING,Force Event for Tuning Error." "0,1"
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bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error." "0,1"
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bitfld.word 0x2 8. "AUTO_CMD,Force Event for Auto CMD Error." "0,1"
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bitfld.word 0x2 7. "CURR_LIM,Force Event for Current Limit Error." "0,1"
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bitfld.word 0x2 6. "DAT_ENDBIT,Force Event for Data End Bit Error." "0,1"
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bitfld.word 0x2 5. "DAT_CRC,Force Event for Data CRC Error." "0,1"
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bitfld.word 0x2 4. "DAT_TIMEOUT,Force Event for Data Timeout Error." "0,1"
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bitfld.word 0x2 3. "CMD_INDEX,Force Event for Command Index Error" "0,1"
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bitfld.word 0x2 2. "CMD_ENDBIT,Force Event for Command End Bit Error." "0,1"
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bitfld.word 0x2 1. "CMD_CRC,Force Event for Command CRC Error." "0,1"
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bitfld.word 0x2 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error." "0,1"
rgroup.byte 0x54++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_err_status,When the ADMA Error interrupt occur. this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor"
bitfld.byte 0x0 2. "ADMA_LENGTH_ERR,This error occurs in the following 2 cases. While Block Count Enable being set  the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be.." "0,1"
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bitfld.byte 0x0 0.--1. "ADMA_ERR_STATE,This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state. D01 D00 : ADMA Error State when error occurred Contents of SYS_SDR.." "0,1,2,3"
group.quad 0x58++0x7
line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_sys_address,This register contains the physical address used for ADMA data transfer"
hexmask.quad 0x0 0.--63. 1. "ADMA_ADDR,The 32-bit addressing Host Driver uses lower 32-bit of this register [upper 32-bit should be set to 0] and shall program Descriptor Table on 32-bit boundary andset 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this.."
rgroup.word 0x60++0xF
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value0,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value1,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value2,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x4 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x4 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x4 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value3,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x6 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x6 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x6 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value4,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x8 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x8 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x8 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value5,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0xA 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0xA 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0xA 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value6,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0xC 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0xC 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0xC 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value7,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0xE 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0xE 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0xE 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
rgroup.word 0x72++0x3
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value8,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value10,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value"
bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3"
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bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1"
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hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system."
group.quad 0x78++0x7
line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma3_desc_address,The start address of Integrated DMA Descriptor is set to this register."
hexmask.quad 0x0 0.--63. 1. "INTG_DESC_ADDR,The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the.."
group.word 0x80++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_size,This register is used to configure the number of bytes in a data block"
bitfld.word 0x0 12.--14. "SDMA_BUF_BOUNDARY,When system memory is managed by paging  SDMA data transfer is performed in unit of paging. A page size of sys-tem memory management is set to this field. Host Controller generates the DMA Interrupt at the page boundary and.." "0,1,2,3,4,5,6,7"
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hexmask.word 0x0 0.--11. 1. "XFER_BLK_SIZE,This register specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Vari-able block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This register is.."
group.long 0x84++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_count,This register is used to configure the number of data blocks"
hexmask.long 0x0 0.--31. 1. "XFER_BLK_COUNT,This register is effective when Data Present is set to 1 in UHS-II Command register and is enabled when Block Count Enable is set to 1 and Block / Byte Mode is set to 0 in the UHS-II Transfer Mode register. Data transfer stops when the.."
group.byte 0x88++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command_pkt,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes. The command length varies depends on a Command Packet type. The length is specified by the UHS-II Command register."
hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,UHS-II Command Packet image is set to this register.The command length varies depends on a Command Packet type."
group.word 0x9C++0x3
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_xfer_mode,This register is used to control the operations of data transfers"
bitfld.word 0x0 15. "DUPLEX_SELECT,Use of 2 lane half duplex mode is determined by Host Driver." "0,1"
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bitfld.word 0x0 14. "EBSY_WAIT,This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer.If this bit is set to 1  Host Controller waits receiving of.." "0,1"
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bitfld.word 0x0 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error  sets this bit to 0 and waits Command.." "0,1"
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bitfld.word 0x0 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked. If Host Driver checks response error  this bit is set to 0 and Response.." "0,1"
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bitfld.word 0x0 6. "RESP_TYPE,When response error check is enabled  this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1 Bit31 OUT_OF_RANGE.." "0,1"
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bitfld.word 0x0 5. "BYTE_MODE,This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1. This bit is effective to a command with data trans-fer." "0,1"
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bitfld.word 0x0 4. "DATA_XFER_DIR,This bit specifies direction of data trans-fer when Data Present is set to 1. This bit is effective to a command with data transfer. 0 - Read [Card to Host] 1 - Write [Host to Card]" "0,1"
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bitfld.word 0x0 1. "BLK_CNT_ENA,This bit specifies whether data transfer usesUHS-II Block Count register. If this bit is set to 1  data transfer is terminated by Block Count. Setting to UHS-II Block Count register shall be equivalent to TLEN in UHS-II Command Packet.." "0,1"
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bitfld.word 0x0 0. "DMA_ENA,This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by DMA Select in the Host Control 1 register." "0,1"
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command,This register is used to program the Command for host controller"
hexmask.word.byte 0x2 8.--12. 1. "PKT_LENGTH,A command packet length  which is set in the UHS-II Command Packet register  is set to this register. 00011b - 00000b - 3-0 Bytes [Not used] 00100b - 4 Bytes .......... ...... 10100b - 20 Bytes.."
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bitfld.word 0x2 6.--7. "CMD_TYPE,This field is used to distinguish a spe-cific command like abort command. If this field is set to 00b  the UHS-II RES Packet is stored in UHS-II Response register [0B3h-0A0h]. To avoid overwrit-ing the UHS-II Response register  when this filed.." "0,1,2,3"
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bitfld.word 0x2 5. "DATA_PRESENT,This bit specifies whether the command is accompanied by data packet." "0,1"
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bitfld.word 0x2 2. "SUB_COMMAND,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command  this bit is set to 0 and when issuing a sub com-mand  this bit is set to 1. Setting of this bit is checked.." "0,1"
rgroup.byte 0xA0++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_response,This register is used to store received UHS-II RES Packet image"
hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command."
group.byte 0xB4++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message_select,This register is used to access internal buffer"
bitfld.byte 0x0 0.--1. "MSG_SEL,Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs.." "0,1,2,3"
rgroup.long 0xB8++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message,This register is used to access internal buffer"
hexmask.long.byte 0x0 24.--31. 1. "MSG_BYTE3,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.."
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hexmask.long.byte 0x0 16.--23. 1. "MSG_BYTE2,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.."
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hexmask.long.byte 0x0 8.--15. 1. "MSG_BYTE1,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.."
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hexmask.long.byte 0x0 0.--7. 1. "MSG_BYTE0,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.."
group.word 0xBC++0x1
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_intr_status,This register shows receipt of INT MSG from which device"
hexmask.word 0x0 0.--15. 1. "DEV_INT_STS,This register shows receipt of INT MSG from which device and is effective when INT MSG Enable is set to 1 in the UHS- II Device Select register. On receiving INT MSG from a device  Host Controller saves the INT MSG to UHS-II Device Interrupt.."
group.byte 0xBE++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_select,UHS-II Device Select Register"
bitfld.byte 0x0 7. "INT_MSG_ENA,This bit enables receipt of INT MSG. If this bit is set to 1 receipt of INT MSG is informed by Card Interrupt in the Nor-mal Interrupt Status register. If this bit is set to 0  Host Con-troller ignores receipt of INT MSG and may not set the.." "0,1"
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hexmask.byte 0x0 0.--3. 1. "DEV_SEL,Host Controller holds an INT MSG packet per device. One of INT MSGs [up to 15] can be selected by this field and read from the UHS-II Device Interrupt Code Register [0BFh]. This field is effective when INT MSG Enable is set to 1. The.."
rgroup.byte 0xBF++0x0
line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_int_code,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register."
hexmask.byte 0x0 0.--7. 1. "DEV_INTR,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register. Host Controller holds an INT MSG packet per device. One of INT MSGs [Code length is 1 byte] up to 15 can be read from this register by.."
group.word 0xC0++0x3
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_software_reset,UHS-II Software Reset Register"
bitfld.word 0x0 1. "HOST_SDTRAN_RESET,Host Driver set this bit to 1 to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completionof SD-TRAN reset. If CMD0 is issued  SD-TRAN Initial- ization sequence from.." "0,1"
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bitfld.word 0x0 0. "HOST_FULL_RESET,On issuing FULL_RESET CCMD  Host Driver set this bit to 1 to reset Host Controller. This bit is cleared auto-matically at completion of Host Controller reset. Initial- ization sequence from PHY Initialization is required to use UHS-II.." "0,1"
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_timer_control,UHS-II Timeout Control Register"
hexmask.word.byte 0x2 4.--7. 1. "DEADLOCK_TIMEOUT_CTR,This value determines the deadlock period while host expecting to receive a packet [1 second]. Tim-eout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register  prevent.."
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hexmask.word.byte 0x2 0.--3. 1. "CMDRESP_TIMEOUT_CTR,This value determines the interval between com-mand packet and response packet [5ms]. Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When set-ting this register  prevent inadvertent.."
group.long 0xC4++0xB
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts,This register gives the status of all UHS-II interrupts"
hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC_ERR,Vendor may use this field for vendor specific error status. '0' Interrupt is not generated '1' Vendor Specific Error"
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bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout [1 second]. Timeout value is determined by the setting of Timeout Counter Value for Deadlock in UHS-II Timer.." "0,1"
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bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout [5ms]. Timeout value is determined by the setting of Timeout Counter Value for CMD_RES in UHS-II Timer.." "0,1"
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bitfld.long 0x0 15. "ADMA2_ADMA3,Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the ADMA Error Status [054h]  which is defined in the Host spec 3.00." "0,1"
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bitfld.long 0x0 8. "EBSY,On receiving EBSY packet  if the packet indicates an error  this bit is set to 1. Setting of this bit also sets Error Interrupt and Transfer Completer together in the Normal Interrupt Status register. This error check is effective for a command with.." "0,1"
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bitfld.long 0x0 7. "UNRECOVERABLE,Setting of this bit means that Unrecoverable Error is set in a packet from a device." "0,1"
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bitfld.long 0x0 5. "TID,Setting of this bit means that TID Error occurs." "0,1"
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bitfld.long 0x0 4. "FRAMING,Setting of this bit means that Framing Error occurs during a packet receiving." "0,1"
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bitfld.long 0x0 3. "CRC,Setting of this bit means that CRC Error occurs during a packet receiving." "0,1"
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bitfld.long 0x0 2. "RETRY_EXPIRED,Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set either Framing Error or CRC Error in this register shall be set." "0,1"
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bitfld.long 0x0 1. "RESP_PKT,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to1 in the UHS- II Transfer Mode register  Host Controller.." "0,1"
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bitfld.long 0x0 0. "HEADER,Setting of this bit means that Header Error occurs in a received packet." "0,1"
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts_ena,This register is used to enable the UHS-II Error Interrupt Status register fields"
hexmask.long.byte 0x4 27.--31. 1. "VENDOR_SPECFIC,Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register. 0h - Status is Disabled 1h - Status is Enabled"
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bitfld.long 0x4 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 15. "ADMA2_ADMA3,Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 8. "EBSY,Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 7. "UNRECOVERABLE,Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 5. "TID,Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 4. "FRAMING,Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 3. "CRC,Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 2. "RETRY_EXPIRED,Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 1. "RESP_PKT,Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x4 0. "HEADER,Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register." "0,1"
line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sig_ena,This register is used to generate UHS-II Interrupt signals"
hexmask.long.byte 0x8 27.--31. 1. "VENDOR_SPECFIC,Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register. 0h - Interrupt Signal is Disabled 1h -.."
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bitfld.long 0x8 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 15. "ADMA2_ADMA3,Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 8. "EBSY,Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 7. "UNRECOVERABLE,Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 5. "TID,Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 4. "FRAMING,Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 3. "CRC,Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 2. "RETRY_EXPIRED_SIG_ENA,Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 1. "RESP_PKT,Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register." "0,1"
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bitfld.long 0x8 0. "HEADER,Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register." "0,1"
rgroup.word 0xE0++0x9
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_settings_ptr,This register is pointer for UHS-II settings."
hexmask.word 0x0 0.--15. 1. "UHS2_SETTINGS_PTR,Pointer for UHS-II Settings Register"
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_capabilities_ptr,This register is pointer for UHS-II Capabilities Register."
hexmask.word 0x2 0.--15. 1. "UHS2_CAPABILITIES_PTR,Pointer for UHS-II Capabilities Register"
line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_test_ptr,This register is pointer for UHS-II Test Register."
hexmask.word 0x4 0.--15. 1. "UHS2_TEST_PTR,Pointer for UHS-II Test Register"
line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_shared_bus_ctrl_ptr,This register is pointer for UHS-II Shared Bus Control Register."
hexmask.word 0x6 0.--15. 1. "SHARED_BUS_CTRL_PTR,Pointer for Shared Bus Control Register"
line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_specfic_ptr,This register is pointer for UHS-II Vendor Specific Pointer Register."
hexmask.word 0x8 0.--15. 1. "VENDOR_SPECFIC_PTR,Pointer for Vendor Specific Area"
group.long 0xF4++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_boot_timeout_control,This is used to program the boot timeout value counter"
hexmask.long 0x0 0.--31. 1. "DATA_TIMEOUT_CNT,This value determines the interval by which DAT line time-outs are detected during boot operation for eMMC4.4 card.The value is in number of sd clock."
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_register,Vendor register added for autogate sdclk. cmd11 power down timer. enhancedstrobe and eMMC hardware reset"
bitfld.long 0x4 16. "AUTOGATE_SDCLK,If this bit is set  SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device" "0,1"
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hexmask.long.word 0x4 2.--15. 1. "CMD11_PD_TIMER,cmd11 power-down timer value"
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bitfld.long 0x4 1. "EMMC_HW_RESET,Hardware reset signal is generared for eMMC card when this bit is set" "0,1"
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bitfld.long 0x4 0. "ENHANCED_STROBE,This bit enables the enhanced strobe logic of the Host Controller" "0,1"
rgroup.word 0xFC++0x3
line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_slot_int_sts,This register is used to read the interrupt signal for each slot."
hexmask.word.byte 0x0 0.--7. 1. "INTR_SIG,These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot."
line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_host_controller_ver,This register is used to read the vendor version number and specification version number"
hexmask.word.byte 0x2 8.--15. 1. "VEN_VER_NUM,The Vendor Version Number is set to 0x10 [1.0]"
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hexmask.word.byte 0x2 0.--7. 1. "SPEC_VER_NUM,This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 00h - SD Host Controller Specification Version 1.00 01h - SD Host Controller Specification Version 2.00 Including the.."
group.long 0x100++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_settings,Start Address of General settings is pointed by Pointer for UHS-II Setting Register."
hexmask.long.byte 0x0 8.--13. 1. "NUMLANES,The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0000b - 2 Lanes FD or 2L-HD 0001b -.."
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bitfld.long 0x0 0. "POWER_MODE,This field determines either Fast mode or Low Power mode.Host and all devices connected to the host shall be set to the same mode." "0,1"
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_settings,Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register."
hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h - 8 x16 LSS 1h - 8 x 1 LSS 2h - 8 x 2 LSS 3h - 8 x 3 LSS ...... ......"
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hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ......"
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bitfld.long 0x4 15. "HIBERNATE_ENA,After checking card capability of Hibernate mode  if all devices support Hibernate mode  this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode  VDD1 Power may be off." "0,1"
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bitfld.long 0x4 6.--7. "SPEED_RANGE,PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. '00' Range A [Default] '01' Range B '10' Reserved '11' Reserved" "0,1,2,3"
group.quad 0x108++0x7
line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_settings,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Setting Register."
hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255.."
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bitfld.quad 0x0 16.--17. "RETRY_COUNT,Data Burst retry count is set to this field. '00' Retry Disabled '01' 1 time '10' 2 times '11' 3 times" "0,1,2,3"
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hexmask.quad.byte 0x0 8.--15. 1. "HOST_NFCU,Host Driver sets the number of blocks in Data Burst [Flow Control] to this field.The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended.."
rgroup.long 0x110++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_cap,Start Address of General Capabilities is pointed by Pointer for UHS-II Host Capabilities Register."
bitfld.long 0x0 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,This field indicates one of bus topologies configured by a Host system. '00' P2P Connection '01' Ring Connection '10' HUB Connection '11' HUB is connected in Ring" "0,1,2,3"
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hexmask.long.byte 0x0 18.--21. 1. "CORECFG_UHS2_MAX_DEVICES,This field indicates the maximum number of devices supported by the Host Controller. 0h - Not used 1h - 1 Devices 2h - 2 Devices ..... ....... Fh - 15 Devices"
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bitfld.long 0x0 16.--17. "DEVICE_TYPE,This field indicates device type configured by a Host system. '00' Removable Card[P2P] '01' Embedded Devices '10' Embedded Devices+Removable Card '11' Reserved" "0,1,2,3"
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bitfld.long 0x0 14. "CFG_64BIT_ADDRESSING,This field indicates support of 64-bit addressing by the Host Controller. '0' 32-bit Addressing is supported '1' 32-bit and 64-bit Addressing is supported" "0,1"
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hexmask.long.byte 0x0 8.--13. 1. "NUM_LANES,This field indicates support of lanes by the Host Controller.0 mean not supported and 1 means supported. D08 - 2L-HD D09 - 2D1U-FD D10 - 1D2U-FD D11 - 2D2U-FD D12 - Reserved D13 - Reserved"
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hexmask.long.byte 0x0 4.--7. 1. "GAP,This field indicates the maximum capability of host power supply for a group configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -Not used 1h - 360 mW 2h - 720 mW ....."
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hexmask.long.byte 0x0 0.--3. 1. "DAP,This field indicates the maximum capability of host power supply for a device configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -360 mW [Default] 1h - 360 mW 2h - 720 mW.."
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_cap,Start Address of PHY Capabilities is pointed by Pointer for UHS-II Host Capabilities Register."
hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS"
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hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS"
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bitfld.long 0x4 6.--7. "SPEED_RANGE,This field indicates supported Speed Range by the Host Controller '00' Range A [Default] '01' Range A and Range B '10' Reserved '11' Reserved" "0,1,2,3"
rgroup.quad 0x118++0x7
line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_cap,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Capabilities Register."
hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,This field indicates the minimum number of data gap[DIDL] supported by the Host Controller. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255 LSS"
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hexmask.quad.word 0x0 20.--31. 1. "MAX_BLK_LENGTH,This field indicates maximum block length by the Host Controller. 000h - Not Used 001h - 1 byte 002h - 2 bytes ...... ...... 200h - 512 bytes ...... ......"
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hexmask.quad.byte 0x0 8.--15. 1. "N_FCU,This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller.This value is determined by supported buffer size. 00h - 256 Blocks 01h - 1 Block 02h - 2 Block 03h - 3 Block.."
wgroup.long 0x120++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_UHSII_Err_Int_Sts,This register is not physically implemented. rather it is an address where UHS-II Error Interrupt Status register can be written."
hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error 0h - Not Affected 1h - Vendor Specific Error Status is set"
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bitfld.long 0x0 17. "TIMEOUT_DEADLOCK,Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 16. "TIMEOUT_CMD_RES,Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 15. "ADMA,Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 8. "EBSY,Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 7. "UNRECOVERABLE,Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 5. "TID,Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 4. "FRAMING,Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 3. "CRC,Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 2. "RETRY_EXPIRED,Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 1. "RES_PKT,Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register." "0,1"
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bitfld.long 0x0 0. "HEADER,Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register." "0,1"
rgroup.long 0x200++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_version,This register provides information about the version of the eMMC CQ standard which is 285 implemented by the CQE. in BCD format. The current version is rev 5.1"
hexmask.long.byte 0x0 8.--11. 1. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number [digit left of decimal point] in BCD format"
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hexmask.long.byte 0x0 4.--7. 1. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number [digit right of decimal point]  in BCD format"
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hexmask.long.byte 0x0 0.--3. 1. "EMMC_VERSION_SUFFIX,eMMC Version Suffix [2nd digit right of decimal point]  in BCD format"
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_capabilities,This register is reserved for capability indication."
hexmask.long.byte 0x4 12.--15. 1. "CF_MUL,Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period. See ITCFVAL definition for details."
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hexmask.long.word 0x4 0.--9. 1. "CF_VAL,Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling."
group.long 0x208++0x27
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_config,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time."
bitfld.long 0x0 12. "DCMD_ENA,Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor  or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot.." "0: Task descriptor in slot #31 is a Data Transfer..,1: Task descriptor in slot #31 is a DCMD Task.."
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bitfld.long 0x0 8. "TASK_DESC_SIZE,Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section. This bit can only be configured when Command Queueing Enable bit is 0 [command queueing is.." "0: Task descriptor size is 64 bits,1: Task descriptor size is 128 bits"
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bitfld.long 0x0 0. "CQ_ENABLE,Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE]. When this bit is 0  CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller." "0,1"
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_control,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time."
bitfld.long 0x4 8. "CLEAR_ALL_TASKS,Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state [i.e.Halt bit is 1]. When software writes 1  the value of the.." "0,1"
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bitfld.long 0x4 0. "HALT_BIT,Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example  issuing a Discard Task command [CMDQ_TASK_MGMT] When software writes 1 .." "0,1"
line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event. only if the respective bit is set in CQ ISTE register."
bitfld.long 0x8 4. "TASK_ERROR,Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor" "0,1"
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bitfld.long 0x8 3. "TASK_CLEARED,Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE. The com-pleted task clear operation is either an individual task clear [CQTCLR] or clearing of all tasks [CQCTL]." "0,1"
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bitfld.long 0x8 2. "RESP_ERR_DET,Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field. The contents of the device status field are listed in Section.." "0,1"
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bitfld.long 0x8 1. "TASK_COMPLETE,Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met: [1] A task is completed and the INT bit is set in its Task Descriptor [2] Interrupt caused by.." "0,1"
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bitfld.long 0x8 0. "HALT_COMPLETE,Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating that host controller has completed its current ongoing task and has entered halt state." "0,1"
line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts_ena,This register enables and disables the reporting of the corresponding interrupt to host soft-ware in 299 CQIS register. When a bit is set ( 1 ) and the corresponding interrupt c -ondition is active. then.."
bitfld.long 0xC 4. "TASK_ERROR,Task Error Interrupt Status Enable 1 = CQIS.TERR will be set when its interrupt condition is active 0 = CQIS.TERR is disabled" "0: CQIS,1: CQIS"
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bitfld.long 0xC 3. "TASK_CLEARED,Task Cleared Status Enable [TCL] 1 = CQIS.TCL will be set when its interrupt condition is active 0 = CQIS.TCL is disabled" "0: CQIS,1: CQIS"
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bitfld.long 0xC 2. "RESP_ERR_DET,Response Error Detected Status Enable [RED] 1 = CQIS.RED will be set when its interrupt condition is active 0 = CQIS.RED is disabled" "0: CQIS,1: CQIS"
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bitfld.long 0xC 1. "TASK_COMPLETE,Task Complete Status Enable [TCC] 1 = CQIS.TCC will be set when its interrupt condition is active 0 = CQIS.TCC is disabled" "0: CQIS,1: CQIS"
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bitfld.long 0xC 0. "HALT_COMPLETE,Halt Complete Status Enable [HAC] 1 = CQIS.HAC will be set when its interrupt condition is active 0 = CQIS.HAC is disabled" "0: CQIS,1: CQIS"
line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sig_ena,This register enables and disables the generation of interrupts to host software. When a bit is set 304 ( 1 ) and the corresponding bit in CQIS is set. then an interrupt is gene -rated. Interrupt sources.."
bitfld.long 0x10 4. "TASK_ERROR,Task Error Interrupt Signal Enable [TERR] When set and CQIS.TERR is asserted  the CQE shall generate an interrupt" "0,1"
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bitfld.long 0x10 3. "TASK_CLEARED,Task Cleared Signal Enable [TCL] When set and CQIS.TCL is asserted  the CQE shall generate an interrupt" "0,1"
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bitfld.long 0x10 2. "RESP_ERR_DET,Response Error Detected Signal Enable [TCC] When set and CQIS.RED is asserted  the CQE shall generate an interrupt" "0,1"
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bitfld.long 0x10 1. "TASK_COMPLETE,Task Complete Signal Enable [TCC] When set and CQIS.TCC is asserted  the CQE shall generate an interrupt" "0,1"
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bitfld.long 0x10 0. "HALT_COMPLETE,Halt Complete Signal Enable [HAC] When set and CQIS.HAC is asserted  the CQE shall generate an interrupt" "0,1"
line.long 0x14 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_coalescing,This register controls the interrupt coalescing feature."
bitfld.long 0x14 31. "CQINTCOALESC_ENABLE,When set to 0 by software  command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT=1 in the Task Descriptor. When set to 1  the interrupt coalescing mechanism is enabled.." "0,1"
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rbitfld.long 0x14 20. "IC_STATUS,This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e.  ICSB is set if and only if IC counter > 0]. Bit Value Description 1 = At least one task completion has been.." "0: No task completions have occurred since last..,1: At least one task completion has been counted.."
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hexmask.long.byte 0x14 8.--12. 1. "CTR_THRESHOLD,Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt. Counter.."
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hexmask.long.byte 0x14 0.--6. 1. "TIMEOUT_VAL,Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by.."
line.long 0x18 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory."
hexmask.long 0x18 0.--31. 1. "CQTDLBA_LO,Task Descriptor List Base Address [TDLBA] This register stores the LSB bits [bits 31:0] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.."
line.long 0x1C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr_upbits,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory."
hexmask.long 0x1C 0.--31. 1. "CQTDLBA_HI,Task Descriptor List Base Address [TDLBA] This register stores the MSB bits [bits 63:32] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.."
line.long 0x20 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_door_bell,Using this register. software triggers CQE to process a new task."
hexmask.long 0x20 0.--31. 1. "CQTDB_VAL,Command Queueing Task Doorbell Software shall configure TDLBA and TDLBAU  and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start pro-cessing the task encoded in slot n of the TDL."
line.long 0x24 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_comp_notif,This register is used by CQE to notify software about completed tasks."
hexmask.long 0x24 0.--31. 1. "CQTCN_VAL,CQE shall set bit n of this register [at the same time it clears bit n of CQTDBR] when a task execution is com-pleted [with success or error]. When receiving interrupt for task completion  software may read this register to know which tasks.."
rgroup.long 0x230++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_queue_status,This register stores the most recent value of the device s queue status."
hexmask.long 0x0 0.--31. 1. "CQDQ_STS,Every time the Host controller receives a queue status register [QSR] from the device  it updates this register with the response of status command  i.e. the devices queue status."
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_pending_tasks,This register indicates to software which tasks are queued in the device. awaiting execution."
hexmask.long 0x4 0.--31. 1. "CQDP_TSKS,Bit n of this register is set if and only if QUEUED_TASK_PARAMS [CMD44] and QUEUED_TASK_ADDRESS [CMD45] were sent for this specific task and if this task hasnt been executed yet.CQE shall set this bit after receiving a successful response for.."
group.long 0x238++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_clear,This register is used for removing an outstanding task in the CQE. 327. The register should be used only when CQE is in Halt state."
hexmask.long 0x0 0.--31. 1. "CQTCLR,Writing 1 to bit n of this register orders CQE to clear a task which software has previously issued.This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit.When software writes 1 to a bit in this.."
group.long 0x240++0x7
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config1,The register controls the when SEND_QUEUE_STATUS commands are sent."
hexmask.long.byte 0x0 16.--19. 1. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS [CMD13] command to inquire the status of the devices task queue.A value of n means CQE shall send status command on the CMD line  during the transfer of data block BLOCK_CNT-n  on.."
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hexmask.long.word 0x0 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS [CMD13] polling.Periodic polling is used when tasks are pending in the device  but no data transfer is in progress. When a SEND_QUEUE_STATUS.."
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argu-ment."
hexmask.long.word 0x4 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_ STATUS [CMD13] com-mand. argument. CQE shall copy this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS [CMD13] command."
rgroup.long 0x248++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dcmd_response,This register is used for passing the response of a DCMD task to software."
hexmask.long 0x0 0.--31. 1. "LAST_RESP,This register contains the response of the command generated by the last direct-command [DCMD] task which was sent.CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit 31.."
group.long 0x250++0x3
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_resp_err_mask,This register controls the generation of Response Error Detection (RED) interrupt."
hexmask.long 0x0 0.--31. 1. "CQRMEM,This bit is used as in interrupt mask on the device status filed which is received in R1/R1b responses.Bit Value Description [for any bit i]:1 = When a R1/R1b response is received  with bit i in the device status set  a RED interrupt is generated.."
rgroup.long 0x254++0xF
line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_err_info,This register is updated by CQE when an error occurs on data or command related to a task activity."
bitfld.long 0x0 31. "DATERR_VALID,Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE  or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated  the bit is set to 1. If a no.." "0,1"
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hexmask.long.byte 0x0 24.--28. 1. "DATERR_TASK_ID,Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE  or.."
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hexmask.long.byte 0x0 16.--21. 1. "DATERR_CMD_INDEX,Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK[CMD46] or EXECUTE_WRITE_TASK [CMD47].."
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bitfld.long 0x0 15. "RESP_MODE_VALID,Response Mode Error Fields Valid This bit is updated when an error is detected by CQE  or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated  the bit is set to 1." "0,1"
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hexmask.long.byte 0x0 8.--12. 1. "RESP_MODE_TASK_ID,Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by.."
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hexmask.long.byte 0x0 0.--5. 1. "RESP_MODE_CMD_INDEX,Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is.."
line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_index,This register stores the index of the last received command response."
hexmask.long.byte 0x4 0.--5. 1. "LAST_CRI,This field stores the index of the last received command response. CQE shall update the value every time a com-mand response is received."
line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_arg,This register stores the index of the last received command response."
hexmask.long 0x8 0.--31. 1. "LAST_CRA,This field stores the argument of the last received com-mand. CQE shall update the value every time a com-mand response is received."
line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_error_task_id,CQ Error Task ID Register"
hexmask.long.byte 0xC 0.--4. 1. "TERR_ID,Task Error ID"
tree.end
base ad:0x0
tree "MMCSD1_ECC_AGGR"
tree "MMCSD1_ECC_AGGR_RXMEM (MMCSD1_ECC_AGGR_RXMEM)"
base ad:0x708000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
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bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MMCSD1_ECC_AGGR_TXMEM (MMCSD1_ECC_AGGR_TXMEM)"
base ad:0x709000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
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bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "MMCSD1_SS_CFG (MMCSD1_SS_CFG)"
base ad:0xFA08000
rgroup.long 0x0++0x3
line.long 0x0 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem"
hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version"
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bitfld.long 0x0 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor revision"
group.long 0x10++0x33
line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.byte 0x0 24.--29. 1. "TUNINGCOUNT,Configures the Number of Taps (Phases) of the RX clock that is supported. The Tuning State machine uses this information to select one of the Taps (Phases) of the RX clock during the Tuning Procedure."
bitfld.long 0x0 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode. 0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated." "0: Synchronous Wakeup Mode: The xin_clk has to be..,1: Asyncrhonous Wakeup Mode: The xin_clk and the.."
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hexmask.long.byte 0x0 12.--15. 1. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency"
hexmask.long.word 0x0 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency"
line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
bitfld.long 0x4 30.--31. "SLOTTYPE,Slot Type. Should be set based on the final product usage. 00 - Removable SCard Slot  01 - Embedded Slot for One Device  10 - Shared Bus Slot  11 - Reserved." "0,1,2,3"
bitfld.long 0x4 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support. Suggested Value is 1'b1 (The Core supports monitoring of Asynchronous Interrupt)." "0,1"
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bitfld.long 0x4 26. "SUPPORT1P8VOLT,1.8V Support. Suggested Value is 1'b1 (The 1.8 Volt Switching is supported by Core). Optionally can be set to 1'b0 if the application doesn't want 1.8V switching (SD3.0)." "0,1"
bitfld.long 0x4 25. "SUPPORT3P0VOLT,3.0V Support. Should be set based on whether 3.0V is supported on the SD Interface." "0,1"
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bitfld.long 0x4 24. "SUPPORT3P3VOLT,3.3V Support. Suggested Value is 1'b1 as the 3.3 V is the default voltage on the SD Interface." "0,1"
bitfld.long 0x4 23. "SUSPRESSUPPORT,Suspend/Resume Support. Suggested Value is 1'b1 (The Suspend/Resume is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support Suspend/Resume Mode." "0,1"
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bitfld.long 0x4 22. "SDMASUPPORT,SDMA Support. Suggested Value is 1'b1 (The SDMA is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support SDMA Mode." "0,1"
bitfld.long 0x4 21. "HIGHSPEEDSUPPORT,High Speed Support. Suggested Value is 1'b1 (The High Speed mode is supported by Core)." "0,1"
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bitfld.long 0x4 19. "ADMA2SUPPORT,ADMA2 Support. Suggested Value is 1'b1 (The ADMA2 is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support ADMA2 Mode." "0,1"
bitfld.long 0x4 18. "SUPPORT8BIT,8-bit Support for Embedded Device. Suggested Value is 1'b1 (The Core supports 8-bit Interface). Optionally an be set to 1'b0 if the Application supports only 4-bit SD Interface." "0,1"
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bitfld.long 0x4 16.--17. "MAXBLKLENGTH,Max Block Length. Maximum Block Length supported by the Core/Device. 00: 512 (Bytes)  01: 1024  10: 2048  11: Reserved." "0: 512,1: 1024,?,?"
hexmask.long.byte 0x4 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock. This is the frequency of the xin_clk."
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bitfld.long 0x4 7. "TIMEOUTCLKUNIT,Timeout Clock Unit. Suggested Value is 1'b0 (KHz)." "0,1"
hexmask.long.byte 0x4 0.--5. 1. "TIMEOUTCLKFREQ,Timeout Clock Frequency. Suggested Value is 1 KHz. Internally the 1msec Timer is used for Timeout Detection. The 1msec Timer is generated from the xin_clk."
line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
bitfld.long 0x8 28. "SUPPORT1P8VDD2,1.8V VDD2 Support." "0,1"
bitfld.long 0x8 27. "ADMA3SUPPORT,ADMA3 Support." "0,1"
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hexmask.long.byte 0x8 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier. This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. FFh Clock Multiplier M =.."
bitfld.long 0x8 14.--15. "RETUNINGMODES,Re-Tuning Modes. Should be set to 2'b00 as the Core supports only the Software Timer based Re-Tuning." "0,1,2,3"
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bitfld.long 0x8 13. "TUNINGFORSDR50,Use Tuning for SDR50. This bit should be set if the Application wants Tuning be used for SDR50 Modes. The Core operates with or with out tuning for SDR50 mode as long as the Clock can be manually tuned using tap delay." "0,1"
hexmask.long.byte 0x8 8.--11. 1. "RETUNINGTIMERCNT,Timer Count for Re-Tuning. This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer."
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bitfld.long 0x8 7. "TYPE4SUPPORT,Driver Type 4 Support. This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not." "0,1"
bitfld.long 0x8 6. "DDRIVERSUPPORT,Driver Type D Support. This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not." "0,1"
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bitfld.long 0x8 5. "CDRIVERSUPPORT,Driver Type C Support. This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not." "0,1"
bitfld.long 0x8 4. "ADRIVERSUPPORT,Driver Type A Support. This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not." "0,1"
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bitfld.long 0x8 2. "DDR50SUPPORT,DDR50 Support. Suggested Value is 1'b1 (The Core supports DDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support DDR50." "0,1"
bitfld.long 0x8 1. "SDR104SUPPORT,SDR104 Support. Suggested Value is 1'b1 (The Core supports SDR104 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR104." "0,1"
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bitfld.long 0x8 0. "SDR50SUPPORT,SDR50 Support. Suggested Value is 1'b1 (The Core supports SDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR50." "0,1"
line.long 0xC "REGS__SS_CFG__SSCFG_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.byte 0xC 16.--23. 1. "MAXCURRENT1P8V,Maximum Current for 1.8V."
hexmask.long.byte 0xC 8.--15. 1. "MAXCURRENT3P0V,Maximum Current for 3.0V."
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hexmask.long.byte 0xC 0.--7. 1. "MAXCURRENT3P3V,Maximum Current for 3.3V."
line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current for 1.8 V (VDD2)."
line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value for Initialization."
line.long 0x18 "REGS__SS_CFG__SSCFG_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value for Default Speed."
line.long 0x1C "REGS__SS_CFG__SSCFG_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value for High Speed."
line.long 0x20 "REGS__SS_CFG__SSCFG_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value for SDR12."
line.long 0x24 "REGS__SS_CFG__SSCFG_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value for SDR25."
line.long 0x28 "REGS__SS_CFG__SSCFG_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value for SDR50."
line.long 0x2C "REGS__SS_CFG__SSCFG_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value for SDR104."
line.long 0x30 "REGS__SS_CFG__SSCFG_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.."
hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value for DDR50."
rgroup.long 0x60++0x17
line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
bitfld.long 0x0 31. "SDHC_CMDIDLE,Idle signal to enable S/W to gate off the clocks." "0,1"
hexmask.long.word 0x0 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus."
line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
hexmask.long.word 0x4 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus."
line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
hexmask.long.word 0x8 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus."
line.long 0xC "REGS__SS_CFG__SSCFG_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
hexmask.long.word 0xC 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)."
line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)."
line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.."
hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus."
group.long 0x100++0x17
line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
bitfld.long 0x0 31. "IOMUX_ENABLE,IO mux enable. Set 1 for GPIO. Set 0 for eMMC/SD" "0,1"
line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
line.long 0x8 "REGS__SS_CFG__SSCFG_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
line.long 0xC "REGS__SS_CFG__SSCFG_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
bitfld.long 0xC 20. "OTAPDLYENA,Output Tap Delay Enable. Enables manual control of the TX clock tap delay  for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." "0,1"
hexmask.long.byte 0xC 12.--15. 1. "OTAPDLYSEL,Output Tap Delay Select. Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface."
newline
bitfld.long 0xC 9. "ITAPCHGWIN,Input Tap Change Window. It gets asserted by the controller while changing the itapdlysel. Used to gate of the RX clock during switching the clock source while tap is changing to avoid clock glitches." "0,1"
bitfld.long 0xC 8. "ITAPDLYENA,Input Tap Delay Enable. This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes." "0,1"
newline
hexmask.long.byte 0xC 0.--4. 1. "ITAPDLYSEL,Input Tap Delay Select. Manual control of the RX clock Tap Delay in the non HS200/HS400 modes."
line.long 0x10 "REGS__SS_CFG__SSCFG_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
bitfld.long 0x10 0.--2. "CLKBUFSEL,Clock Delay Buffer Select. Selects one of the eight taps in the CLK Delay Buffer based on PVT variation." "0,1,2,3,4,5,6,7"
line.long 0x14 "REGS__SS_CFG__SSCFG_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.."
group.long 0x130++0x7
line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.."
line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.."
tree.end
tree.end
tree "MSRAM"
base ad:0x0
tree "MSRAM_256K0"
tree "MSRAM_256K0_ECC_AGGR_REGS (MSRAM_256K0_ECC_AGGR_REGS)"
base ad:0x3F001000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MSRAM_256K0_RAM (MSRAM_256K0_RAM)"
base ad:0x70000000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree "MSRAM_256K1"
tree "MSRAM_256K1_ECC_AGGR_REGS (MSRAM_256K1_ECC_AGGR_REGS)"
base ad:0x3F002000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MSRAM_256K1_RAM (MSRAM_256K1_RAM)"
base ad:0x70040000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree "MSRAM_256K2"
tree "MSRAM_256K2_ECC_AGGR_REGS (MSRAM_256K2_ECC_AGGR_REGS)"
base ad:0x3F003000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MSRAM_256K2_RAM (MSRAM_256K2_RAM)"
base ad:0x70080000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree "MSRAM_256K3"
tree "MSRAM_256K3_ECC_AGGR_REGS (MSRAM_256K3_ECC_AGGR_REGS)"
base ad:0x3F008000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MSRAM_256K3_RAM (MSRAM_256K3_RAM)"
base ad:0x700C0000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree "MSRAM_256K4"
tree "MSRAM_256K4_ECC_AGGR_REGS (MSRAM_256K4_ECC_AGGR_REGS)"
base ad:0x3F007000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MSRAM_256K4_RAM (MSRAM_256K4_RAM)"
base ad:0x70100000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree "MSRAM_256K5"
tree "MSRAM_256K5_ECC_AGGR_REGS (MSRAM_256K5_ECC_AGGR_REGS)"
base ad:0x3F006000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MSRAM_256K5_RAM (MSRAM_256K5_RAM)"
base ad:0x70140000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree "MSRAM_256K6"
tree "MSRAM_256K6_ECC_AGGR_REGS (MSRAM_256K6_ECC_AGGR_REGS)"
base ad:0x3F010000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MSRAM_256K6_RAM (MSRAM_256K6_RAM)"
base ad:0x70180000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MSRAM_256K6_RAM_1 (MSRAM_256K6_RAM)"
base ad:0x440A0000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MSRAM_256K6_RAM_2 (MSRAM_256K6_RAM)"
base ad:0x440C0000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree "MSRAM_256K7"
tree "MSRAM_256K7_ECC_AGGR_REGS (MSRAM_256K7_ECC_AGGR_REGS)"
base ad:0x3F011000
rgroup.long 0x0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MSRAM_256K7_RAM (MSRAM_256K7_RAM)"
base ad:0x701C0000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MSRAM_256K7_RAM_1 (MSRAM_256K7_RAM)"
base ad:0x44060000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MSRAM_256K7_RAM_2 (MSRAM_256K7_RAM)"
base ad:0x44080000
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree.end
tree "PADCFG_CTRL0_CFG0 (PADCFG_CTRL0_CFG0)"
base ad:0xF0000
rgroup.long 0x0++0x3
line.long 0x0 "CFG0_PID,"
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
rgroup.long 0x8++0x3
line.long 0x0 "CFG0_MMR_CFG1,"
bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN,Proxy addressing enabled" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions"
group.long 0x1008++0x1B
line.long 0x0 "CFG0_LOCK0_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK0_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component"
line.long 0x8 "CFG0_intr_raw_status,"
bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
line.long 0xC "CFG0_intr_enabled_status_clear,"
bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
line.long 0x10 "CFG0_intr_enable,"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
line.long 0x14 "CFG0_intr_enable_clear,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
line.long 0x18 "CFG0_eoi,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip."
rgroup.long 0x1024++0xB
line.long 0x0 "CFG0_fault_address,"
hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address."
line.long 0x4 "CFG0_fault_type_status,"
bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1"
hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
line.long 0x8 "CFG0_fault_attr_status,"
hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID."
hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID."
hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID."
wgroup.long 0x1030++0x3
line.long 0x0 "CFG0_fault_clear,"
bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
rgroup.long 0x2000++0x3
line.long 0x0 "CFG0_PID_PROXY,"
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY,"
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY,"
bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY,"
rgroup.long 0x2008++0x3
line.long 0x0 "CFG0_MMR_CFG1_PROXY,"
bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing enabled" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions"
group.long 0x3008++0x1B
line.long 0x0 "CFG0_LOCK0_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK0_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component"
line.long 0x8 "CFG0_intr_raw_status_PROXY,"
bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
line.long 0xC "CFG0_intr_enabled_status_clear_PROXY,"
bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
line.long 0x10 "CFG0_intr_enable_PROXY,"
bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
line.long 0x14 "CFG0_intr_enable_clear_PROXY,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
line.long 0x18 "CFG0_eoi_PROXY,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip."
rgroup.long 0x3024++0xB
line.long 0x0 "CFG0_fault_address_PROXY,"
hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address."
line.long 0x4 "CFG0_fault_type_status_PROXY,"
bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1"
hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.."
line.long 0x8 "CFG0_fault_attr_status_PROXY,"
hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID."
hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID."
hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID."
wgroup.long 0x3030++0x3
line.long 0x0 "CFG0_fault_clear_PROXY,"
bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
group.long 0x4000++0x2CF
line.long 0x0 "CFG0_PADCONFIG0,"
bitfld.long 0x0 31. "PADCONFIG0_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x0 21. "PADCONFIG0_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x0 19.--20. "PADCONFIG0_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x0 17. "PADCONFIG0_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x0 16. "PADCONFIG0_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x0 14. "PADCONFIG0_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x4 "CFG0_PADCONFIG1,"
bitfld.long 0x4 31. "PADCONFIG1_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x4 21. "PADCONFIG1_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x4 14. "PADCONFIG1_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x8 "CFG0_PADCONFIG2,"
bitfld.long 0x8 31. "PADCONFIG2_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x8 21. "PADCONFIG2_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x8 14. "PADCONFIG2_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xC "CFG0_PADCONFIG3,"
bitfld.long 0xC 31. "PADCONFIG3_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xC 21. "PADCONFIG3_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0xC 14. "PADCONFIG3_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x10 "CFG0_PADCONFIG4,"
bitfld.long 0x10 31. "PADCONFIG4_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x10 21. "PADCONFIG4_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x10 14. "PADCONFIG4_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x14 "CFG0_PADCONFIG5,"
bitfld.long 0x14 31. "PADCONFIG5_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x14 21. "PADCONFIG5_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x14 14. "PADCONFIG5_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x18 "CFG0_PADCONFIG6,"
bitfld.long 0x18 31. "PADCONFIG6_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x18 21. "PADCONFIG6_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x18 14. "PADCONFIG6_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1C "CFG0_PADCONFIG7,"
bitfld.long 0x1C 31. "PADCONFIG7_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1C 14. "PADCONFIG7_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x20 "CFG0_PADCONFIG8,"
bitfld.long 0x20 31. "PADCONFIG8_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x20 21. "PADCONFIG8_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x20 14. "PADCONFIG8_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x24 "CFG0_PADCONFIG9,"
bitfld.long 0x24 31. "PADCONFIG9_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x24 21. "PADCONFIG9_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x24 14. "PADCONFIG9_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x28 "CFG0_PADCONFIG10,"
bitfld.long 0x28 31. "PADCONFIG10_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x28 21. "PADCONFIG10_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x28 14. "PADCONFIG10_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2C "CFG0_PADCONFIG11,"
bitfld.long 0x2C 31. "PADCONFIG11_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2C 14. "PADCONFIG11_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x30 "CFG0_PADCONFIG12,"
bitfld.long 0x30 31. "PADCONFIG12_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x30 21. "PADCONFIG12_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x30 14. "PADCONFIG12_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x34 "CFG0_PADCONFIG13,"
bitfld.long 0x34 31. "PADCONFIG13_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x34 21. "PADCONFIG13_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x34 14. "PADCONFIG13_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG13_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x38 "CFG0_PADCONFIG14,"
bitfld.long 0x38 31. "PADCONFIG14_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x38 21. "PADCONFIG14_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x38 14. "PADCONFIG14_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG14_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x3C "CFG0_PADCONFIG15,"
bitfld.long 0x3C 31. "PADCONFIG15_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x3C 14. "PADCONFIG15_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG15_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x40 "CFG0_PADCONFIG16,"
bitfld.long 0x40 31. "PADCONFIG16_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x40 21. "PADCONFIG16_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x40 14. "PADCONFIG16_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG16_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x44 "CFG0_PADCONFIG17,"
bitfld.long 0x44 31. "PADCONFIG17_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x44 21. "PADCONFIG17_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x44 14. "PADCONFIG17_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG17_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x48 "CFG0_PADCONFIG18,"
bitfld.long 0x48 31. "PADCONFIG18_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x48 21. "PADCONFIG18_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x48 14. "PADCONFIG18_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG18_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x4C "CFG0_PADCONFIG19,"
bitfld.long 0x4C 31. "PADCONFIG19_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x4C 14. "PADCONFIG19_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG19_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x50 "CFG0_PADCONFIG20,"
bitfld.long 0x50 31. "PADCONFIG20_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x50 21. "PADCONFIG20_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x50 14. "PADCONFIG20_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG20_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x54 "CFG0_PADCONFIG21,"
bitfld.long 0x54 31. "PADCONFIG21_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x54 21. "PADCONFIG21_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x54 14. "PADCONFIG21_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG21_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x58 "CFG0_PADCONFIG22,"
bitfld.long 0x58 31. "PADCONFIG22_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x58 21. "PADCONFIG22_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x58 14. "PADCONFIG22_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG22_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x5C "CFG0_PADCONFIG23,"
bitfld.long 0x5C 31. "PADCONFIG23_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x5C 14. "PADCONFIG23_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG23_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x60 "CFG0_PADCONFIG24,"
bitfld.long 0x60 31. "PADCONFIG24_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x60 21. "PADCONFIG24_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x60 14. "PADCONFIG24_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG24_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x64 "CFG0_PADCONFIG25,"
bitfld.long 0x64 31. "PADCONFIG25_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x64 21. "PADCONFIG25_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x64 14. "PADCONFIG25_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG25_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x68 "CFG0_PADCONFIG26,"
bitfld.long 0x68 31. "PADCONFIG26_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x68 21. "PADCONFIG26_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x68 14. "PADCONFIG26_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG26_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x6C "CFG0_PADCONFIG27,"
bitfld.long 0x6C 31. "PADCONFIG27_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x6C 14. "PADCONFIG27_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG27_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x70 "CFG0_PADCONFIG28,"
bitfld.long 0x70 31. "PADCONFIG28_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x70 21. "PADCONFIG28_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x70 14. "PADCONFIG28_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG28_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x74 "CFG0_PADCONFIG29,"
bitfld.long 0x74 31. "PADCONFIG29_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x74 21. "PADCONFIG29_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x74 14. "PADCONFIG29_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG29_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x78 "CFG0_PADCONFIG30,"
bitfld.long 0x78 31. "PADCONFIG30_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x78 21. "PADCONFIG30_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x78 14. "PADCONFIG30_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG30_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x7C "CFG0_PADCONFIG31,"
bitfld.long 0x7C 31. "PADCONFIG31_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x7C 14. "PADCONFIG31_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG31_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x80 "CFG0_PADCONFIG32,"
bitfld.long 0x80 31. "PADCONFIG32_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x80 21. "PADCONFIG32_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x80 14. "PADCONFIG32_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG32_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x84 "CFG0_PADCONFIG33,"
bitfld.long 0x84 31. "PADCONFIG33_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x84 21. "PADCONFIG33_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x84 14. "PADCONFIG33_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x84 0.--3. 1. "PADCONFIG33_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x88 "CFG0_PADCONFIG34,"
bitfld.long 0x88 31. "PADCONFIG34_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x88 21. "PADCONFIG34_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x88 19.--20. "PADCONFIG34_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x88 18. "PADCONFIG34_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x88 17. "PADCONFIG34_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x88 16. "PADCONFIG34_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x88 14. "PADCONFIG34_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x88 11.--13. "PADCONFIG34_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x88 0.--3. 1. "PADCONFIG34_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x8C "CFG0_PADCONFIG35,"
bitfld.long 0x8C 31. "PADCONFIG35_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x8C 21. "PADCONFIG35_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x8C 19.--20. "PADCONFIG35_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x8C 18. "PADCONFIG35_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x8C 17. "PADCONFIG35_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x8C 16. "PADCONFIG35_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x8C 14. "PADCONFIG35_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x8C 11.--13. "PADCONFIG35_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8C 0.--3. 1. "PADCONFIG35_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x90 "CFG0_PADCONFIG36,"
bitfld.long 0x90 31. "PADCONFIG36_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x90 21. "PADCONFIG36_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x90 19.--20. "PADCONFIG36_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x90 18. "PADCONFIG36_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x90 17. "PADCONFIG36_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x90 16. "PADCONFIG36_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x90 14. "PADCONFIG36_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x90 11.--13. "PADCONFIG36_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x90 0.--3. 1. "PADCONFIG36_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x94 "CFG0_PADCONFIG37,"
bitfld.long 0x94 31. "PADCONFIG37_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x94 21. "PADCONFIG37_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x94 19.--20. "PADCONFIG37_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x94 18. "PADCONFIG37_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x94 17. "PADCONFIG37_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x94 16. "PADCONFIG37_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x94 14. "PADCONFIG37_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x94 11.--13. "PADCONFIG37_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x94 0.--3. 1. "PADCONFIG37_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x98 "CFG0_PADCONFIG38,"
bitfld.long 0x98 31. "PADCONFIG38_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x98 21. "PADCONFIG38_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x98 19.--20. "PADCONFIG38_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x98 18. "PADCONFIG38_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x98 17. "PADCONFIG38_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x98 16. "PADCONFIG38_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x98 14. "PADCONFIG38_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x98 11.--13. "PADCONFIG38_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x98 0.--3. 1. "PADCONFIG38_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x9C "CFG0_PADCONFIG39,"
bitfld.long 0x9C 31. "PADCONFIG39_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x9C 21. "PADCONFIG39_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x9C 19.--20. "PADCONFIG39_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x9C 18. "PADCONFIG39_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x9C 17. "PADCONFIG39_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x9C 16. "PADCONFIG39_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x9C 14. "PADCONFIG39_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x9C 11.--13. "PADCONFIG39_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x9C 0.--3. 1. "PADCONFIG39_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xA0 "CFG0_PADCONFIG40,"
bitfld.long 0xA0 31. "PADCONFIG40_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xA0 21. "PADCONFIG40_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xA0 19.--20. "PADCONFIG40_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xA0 18. "PADCONFIG40_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xA0 17. "PADCONFIG40_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xA0 16. "PADCONFIG40_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xA0 14. "PADCONFIG40_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xA0 11.--13. "PADCONFIG40_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xA0 0.--3. 1. "PADCONFIG40_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xA4 "CFG0_PADCONFIG41,"
bitfld.long 0xA4 31. "PADCONFIG41_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xA4 21. "PADCONFIG41_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xA4 19.--20. "PADCONFIG41_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xA4 18. "PADCONFIG41_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xA4 17. "PADCONFIG41_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xA4 16. "PADCONFIG41_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xA4 14. "PADCONFIG41_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xA4 11.--13. "PADCONFIG41_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xA4 0.--3. 1. "PADCONFIG41_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xA8 "CFG0_PADCONFIG42,"
bitfld.long 0xA8 31. "PADCONFIG42_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xA8 21. "PADCONFIG42_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xA8 19.--20. "PADCONFIG42_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xA8 18. "PADCONFIG42_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xA8 17. "PADCONFIG42_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xA8 16. "PADCONFIG42_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xA8 14. "PADCONFIG42_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xA8 11.--13. "PADCONFIG42_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xA8 0.--3. 1. "PADCONFIG42_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xAC "CFG0_PADCONFIG43,"
bitfld.long 0xAC 31. "PADCONFIG43_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xAC 21. "PADCONFIG43_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xAC 19.--20. "PADCONFIG43_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xAC 18. "PADCONFIG43_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xAC 17. "PADCONFIG43_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xAC 16. "PADCONFIG43_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xAC 14. "PADCONFIG43_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xAC 11.--13. "PADCONFIG43_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xAC 0.--3. 1. "PADCONFIG43_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xB0 "CFG0_PADCONFIG44,"
bitfld.long 0xB0 31. "PADCONFIG44_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xB0 21. "PADCONFIG44_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xB0 19.--20. "PADCONFIG44_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xB0 18. "PADCONFIG44_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xB0 17. "PADCONFIG44_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xB0 16. "PADCONFIG44_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xB0 14. "PADCONFIG44_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xB0 11.--13. "PADCONFIG44_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xB0 0.--3. 1. "PADCONFIG44_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xB4 "CFG0_PADCONFIG45,"
bitfld.long 0xB4 31. "PADCONFIG45_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xB4 21. "PADCONFIG45_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xB4 19.--20. "PADCONFIG45_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xB4 18. "PADCONFIG45_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xB4 17. "PADCONFIG45_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xB4 16. "PADCONFIG45_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xB4 14. "PADCONFIG45_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xB4 11.--13. "PADCONFIG45_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xB4 0.--3. 1. "PADCONFIG45_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xB8 "CFG0_PADCONFIG46,"
bitfld.long 0xB8 31. "PADCONFIG46_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xB8 21. "PADCONFIG46_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xB8 19.--20. "PADCONFIG46_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xB8 18. "PADCONFIG46_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xB8 17. "PADCONFIG46_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xB8 16. "PADCONFIG46_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xB8 14. "PADCONFIG46_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xB8 11.--13. "PADCONFIG46_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xB8 0.--3. 1. "PADCONFIG46_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xBC "CFG0_PADCONFIG47,"
bitfld.long 0xBC 31. "PADCONFIG47_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xBC 21. "PADCONFIG47_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xBC 19.--20. "PADCONFIG47_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xBC 18. "PADCONFIG47_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xBC 17. "PADCONFIG47_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xBC 16. "PADCONFIG47_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xBC 14. "PADCONFIG47_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xBC 11.--13. "PADCONFIG47_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xBC 0.--3. 1. "PADCONFIG47_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xC0 "CFG0_PADCONFIG48,"
bitfld.long 0xC0 31. "PADCONFIG48_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xC0 21. "PADCONFIG48_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xC0 19.--20. "PADCONFIG48_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xC0 18. "PADCONFIG48_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xC0 17. "PADCONFIG48_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xC0 16. "PADCONFIG48_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xC0 14. "PADCONFIG48_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xC0 11.--13. "PADCONFIG48_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC0 0.--3. 1. "PADCONFIG48_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xC4 "CFG0_PADCONFIG49,"
bitfld.long 0xC4 31. "PADCONFIG49_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xC4 21. "PADCONFIG49_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xC4 19.--20. "PADCONFIG49_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xC4 18. "PADCONFIG49_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xC4 17. "PADCONFIG49_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xC4 16. "PADCONFIG49_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xC4 14. "PADCONFIG49_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xC4 11.--13. "PADCONFIG49_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC4 0.--3. 1. "PADCONFIG49_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xC8 "CFG0_PADCONFIG50,"
bitfld.long 0xC8 31. "PADCONFIG50_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xC8 21. "PADCONFIG50_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xC8 19.--20. "PADCONFIG50_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xC8 18. "PADCONFIG50_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xC8 17. "PADCONFIG50_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xC8 16. "PADCONFIG50_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xC8 14. "PADCONFIG50_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xC8 11.--13. "PADCONFIG50_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC8 0.--3. 1. "PADCONFIG50_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xCC "CFG0_PADCONFIG51,"
bitfld.long 0xCC 31. "PADCONFIG51_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xCC 21. "PADCONFIG51_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xCC 19.--20. "PADCONFIG51_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xCC 18. "PADCONFIG51_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xCC 17. "PADCONFIG51_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xCC 16. "PADCONFIG51_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xCC 14. "PADCONFIG51_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xCC 11.--13. "PADCONFIG51_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xCC 0.--3. 1. "PADCONFIG51_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xD0 "CFG0_PADCONFIG52,"
bitfld.long 0xD0 31. "PADCONFIG52_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xD0 21. "PADCONFIG52_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xD0 19.--20. "PADCONFIG52_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xD0 18. "PADCONFIG52_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xD0 17. "PADCONFIG52_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xD0 16. "PADCONFIG52_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xD0 14. "PADCONFIG52_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xD0 11.--13. "PADCONFIG52_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xD0 0.--3. 1. "PADCONFIG52_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xD4 "CFG0_PADCONFIG53,"
bitfld.long 0xD4 31. "PADCONFIG53_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xD4 21. "PADCONFIG53_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xD4 19.--20. "PADCONFIG53_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xD4 18. "PADCONFIG53_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xD4 17. "PADCONFIG53_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xD4 16. "PADCONFIG53_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xD4 14. "PADCONFIG53_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xD4 11.--13. "PADCONFIG53_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xD4 0.--3. 1. "PADCONFIG53_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xD8 "CFG0_PADCONFIG54,"
bitfld.long 0xD8 31. "PADCONFIG54_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xD8 21. "PADCONFIG54_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xD8 19.--20. "PADCONFIG54_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xD8 18. "PADCONFIG54_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xD8 17. "PADCONFIG54_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xD8 16. "PADCONFIG54_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xD8 14. "PADCONFIG54_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xD8 11.--13. "PADCONFIG54_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xD8 0.--3. 1. "PADCONFIG54_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xDC "CFG0_PADCONFIG55,"
bitfld.long 0xDC 31. "PADCONFIG55_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xDC 21. "PADCONFIG55_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xDC 19.--20. "PADCONFIG55_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xDC 18. "PADCONFIG55_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xDC 17. "PADCONFIG55_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xDC 16. "PADCONFIG55_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xDC 14. "PADCONFIG55_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xDC 11.--13. "PADCONFIG55_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xDC 0.--3. 1. "PADCONFIG55_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xE0 "CFG0_PADCONFIG56,"
bitfld.long 0xE0 31. "PADCONFIG56_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xE0 21. "PADCONFIG56_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xE0 19.--20. "PADCONFIG56_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xE0 18. "PADCONFIG56_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xE0 17. "PADCONFIG56_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xE0 16. "PADCONFIG56_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xE0 14. "PADCONFIG56_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xE0 11.--13. "PADCONFIG56_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xE0 0.--3. 1. "PADCONFIG56_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xE4 "CFG0_PADCONFIG57,"
bitfld.long 0xE4 31. "PADCONFIG57_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xE4 21. "PADCONFIG57_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xE4 19.--20. "PADCONFIG57_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xE4 18. "PADCONFIG57_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xE4 17. "PADCONFIG57_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xE4 16. "PADCONFIG57_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xE4 14. "PADCONFIG57_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xE4 11.--13. "PADCONFIG57_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xE4 0.--3. 1. "PADCONFIG57_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xE8 "CFG0_PADCONFIG58,"
bitfld.long 0xE8 31. "PADCONFIG58_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xE8 21. "PADCONFIG58_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xE8 19.--20. "PADCONFIG58_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xE8 18. "PADCONFIG58_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xE8 17. "PADCONFIG58_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xE8 16. "PADCONFIG58_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xE8 14. "PADCONFIG58_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xE8 11.--13. "PADCONFIG58_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xE8 0.--3. 1. "PADCONFIG58_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xEC "CFG0_PADCONFIG59,"
bitfld.long 0xEC 31. "PADCONFIG59_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xEC 21. "PADCONFIG59_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xEC 19.--20. "PADCONFIG59_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xEC 18. "PADCONFIG59_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xEC 17. "PADCONFIG59_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xEC 16. "PADCONFIG59_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xEC 14. "PADCONFIG59_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xEC 11.--13. "PADCONFIG59_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xEC 0.--3. 1. "PADCONFIG59_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xF0 "CFG0_PADCONFIG60,"
bitfld.long 0xF0 31. "PADCONFIG60_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xF0 21. "PADCONFIG60_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xF0 19.--20. "PADCONFIG60_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xF0 18. "PADCONFIG60_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xF0 17. "PADCONFIG60_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xF0 16. "PADCONFIG60_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xF0 14. "PADCONFIG60_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xF0 11.--13. "PADCONFIG60_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xF0 0.--3. 1. "PADCONFIG60_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xF4 "CFG0_PADCONFIG61,"
bitfld.long 0xF4 31. "PADCONFIG61_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xF4 21. "PADCONFIG61_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xF4 19.--20. "PADCONFIG61_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xF4 18. "PADCONFIG61_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xF4 17. "PADCONFIG61_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xF4 16. "PADCONFIG61_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xF4 14. "PADCONFIG61_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xF4 11.--13. "PADCONFIG61_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xF4 0.--3. 1. "PADCONFIG61_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xF8 "CFG0_PADCONFIG62,"
bitfld.long 0xF8 31. "PADCONFIG62_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xF8 21. "PADCONFIG62_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xF8 19.--20. "PADCONFIG62_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xF8 18. "PADCONFIG62_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xF8 17. "PADCONFIG62_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xF8 16. "PADCONFIG62_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xF8 14. "PADCONFIG62_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xF8 11.--13. "PADCONFIG62_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xF8 0.--3. 1. "PADCONFIG62_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0xFC "CFG0_PADCONFIG63,"
bitfld.long 0xFC 31. "PADCONFIG63_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xFC 21. "PADCONFIG63_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xFC 19.--20. "PADCONFIG63_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xFC 18. "PADCONFIG63_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xFC 17. "PADCONFIG63_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xFC 16. "PADCONFIG63_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xFC 14. "PADCONFIG63_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xFC 11.--13. "PADCONFIG63_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xFC 0.--3. 1. "PADCONFIG63_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x100 "CFG0_PADCONFIG64,"
bitfld.long 0x100 31. "PADCONFIG64_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x100 21. "PADCONFIG64_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x100 19.--20. "PADCONFIG64_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x100 18. "PADCONFIG64_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x100 17. "PADCONFIG64_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x100 16. "PADCONFIG64_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x100 14. "PADCONFIG64_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x100 11.--13. "PADCONFIG64_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x100 0.--3. 1. "PADCONFIG64_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x104 "CFG0_PADCONFIG65,"
bitfld.long 0x104 31. "PADCONFIG65_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x104 21. "PADCONFIG65_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x104 19.--20. "PADCONFIG65_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x104 18. "PADCONFIG65_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x104 17. "PADCONFIG65_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x104 16. "PADCONFIG65_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x104 14. "PADCONFIG65_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x104 11.--13. "PADCONFIG65_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x104 0.--3. 1. "PADCONFIG65_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x108 "CFG0_PADCONFIG66,"
bitfld.long 0x108 31. "PADCONFIG66_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x108 21. "PADCONFIG66_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x108 19.--20. "PADCONFIG66_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x108 18. "PADCONFIG66_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x108 17. "PADCONFIG66_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x108 16. "PADCONFIG66_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x108 14. "PADCONFIG66_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x108 11.--13. "PADCONFIG66_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x108 0.--3. 1. "PADCONFIG66_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x10C "CFG0_PADCONFIG67,"
bitfld.long 0x10C 31. "PADCONFIG67_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x10C 21. "PADCONFIG67_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x10C 19.--20. "PADCONFIG67_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x10C 18. "PADCONFIG67_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x10C 17. "PADCONFIG67_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x10C 16. "PADCONFIG67_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x10C 14. "PADCONFIG67_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x10C 11.--13. "PADCONFIG67_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10C 0.--3. 1. "PADCONFIG67_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x110 "CFG0_PADCONFIG68,"
bitfld.long 0x110 31. "PADCONFIG68_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x110 21. "PADCONFIG68_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x110 19.--20. "PADCONFIG68_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x110 18. "PADCONFIG68_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x110 17. "PADCONFIG68_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x110 16. "PADCONFIG68_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x110 14. "PADCONFIG68_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x110 11.--13. "PADCONFIG68_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x110 0.--3. 1. "PADCONFIG68_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x114 "CFG0_PADCONFIG69,"
bitfld.long 0x114 31. "PADCONFIG69_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x114 21. "PADCONFIG69_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x114 19.--20. "PADCONFIG69_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x114 18. "PADCONFIG69_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x114 17. "PADCONFIG69_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x114 16. "PADCONFIG69_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x114 14. "PADCONFIG69_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x114 11.--13. "PADCONFIG69_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x114 0.--3. 1. "PADCONFIG69_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x118 "CFG0_PADCONFIG70,"
bitfld.long 0x118 31. "PADCONFIG70_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x118 21. "PADCONFIG70_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x118 19.--20. "PADCONFIG70_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x118 18. "PADCONFIG70_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x118 17. "PADCONFIG70_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x118 16. "PADCONFIG70_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x118 14. "PADCONFIG70_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x118 11.--13. "PADCONFIG70_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x118 0.--3. 1. "PADCONFIG70_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x11C "CFG0_PADCONFIG71,"
bitfld.long 0x11C 31. "PADCONFIG71_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x11C 21. "PADCONFIG71_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x11C 19.--20. "PADCONFIG71_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x11C 18. "PADCONFIG71_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x11C 17. "PADCONFIG71_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x11C 16. "PADCONFIG71_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x11C 14. "PADCONFIG71_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x11C 11.--13. "PADCONFIG71_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x11C 0.--3. 1. "PADCONFIG71_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x120 "CFG0_PADCONFIG72,"
bitfld.long 0x120 31. "PADCONFIG72_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x120 21. "PADCONFIG72_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x120 19.--20. "PADCONFIG72_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x120 18. "PADCONFIG72_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x120 17. "PADCONFIG72_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x120 16. "PADCONFIG72_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x120 14. "PADCONFIG72_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x120 11.--13. "PADCONFIG72_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x120 0.--3. 1. "PADCONFIG72_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x124 "CFG0_PADCONFIG73,"
bitfld.long 0x124 31. "PADCONFIG73_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x124 21. "PADCONFIG73_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x124 19.--20. "PADCONFIG73_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x124 18. "PADCONFIG73_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x124 17. "PADCONFIG73_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x124 16. "PADCONFIG73_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x124 14. "PADCONFIG73_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x124 11.--13. "PADCONFIG73_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x124 0.--3. 1. "PADCONFIG73_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x128 "CFG0_PADCONFIG74,"
bitfld.long 0x128 31. "PADCONFIG74_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x128 21. "PADCONFIG74_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x128 19.--20. "PADCONFIG74_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x128 18. "PADCONFIG74_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x128 17. "PADCONFIG74_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x128 16. "PADCONFIG74_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x128 14. "PADCONFIG74_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x128 11.--13. "PADCONFIG74_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x128 0.--3. 1. "PADCONFIG74_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x12C "CFG0_PADCONFIG75,"
bitfld.long 0x12C 31. "PADCONFIG75_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x12C 21. "PADCONFIG75_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x12C 19.--20. "PADCONFIG75_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x12C 18. "PADCONFIG75_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x12C 17. "PADCONFIG75_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x12C 16. "PADCONFIG75_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x12C 14. "PADCONFIG75_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x12C 11.--13. "PADCONFIG75_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x12C 0.--3. 1. "PADCONFIG75_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x130 "CFG0_PADCONFIG76,"
bitfld.long 0x130 31. "PADCONFIG76_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x130 21. "PADCONFIG76_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x130 19.--20. "PADCONFIG76_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x130 18. "PADCONFIG76_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x130 17. "PADCONFIG76_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x130 16. "PADCONFIG76_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x130 14. "PADCONFIG76_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x130 11.--13. "PADCONFIG76_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x130 0.--3. 1. "PADCONFIG76_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x134 "CFG0_PADCONFIG77,"
bitfld.long 0x134 31. "PADCONFIG77_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x134 21. "PADCONFIG77_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x134 19.--20. "PADCONFIG77_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x134 18. "PADCONFIG77_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x134 17. "PADCONFIG77_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x134 16. "PADCONFIG77_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x134 14. "PADCONFIG77_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x134 11.--13. "PADCONFIG77_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x134 0.--3. 1. "PADCONFIG77_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x138 "CFG0_PADCONFIG78,"
bitfld.long 0x138 31. "PADCONFIG78_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x138 21. "PADCONFIG78_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x138 19.--20. "PADCONFIG78_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x138 18. "PADCONFIG78_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x138 17. "PADCONFIG78_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x138 16. "PADCONFIG78_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x138 14. "PADCONFIG78_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x138 11.--13. "PADCONFIG78_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x138 0.--3. 1. "PADCONFIG78_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x13C "CFG0_PADCONFIG79,"
bitfld.long 0x13C 31. "PADCONFIG79_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x13C 21. "PADCONFIG79_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x13C 19.--20. "PADCONFIG79_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x13C 18. "PADCONFIG79_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x13C 17. "PADCONFIG79_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x13C 16. "PADCONFIG79_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x13C 14. "PADCONFIG79_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x13C 11.--13. "PADCONFIG79_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x13C 0.--3. 1. "PADCONFIG79_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x140 "CFG0_PADCONFIG80,"
bitfld.long 0x140 31. "PADCONFIG80_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x140 21. "PADCONFIG80_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x140 19.--20. "PADCONFIG80_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x140 18. "PADCONFIG80_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x140 17. "PADCONFIG80_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x140 16. "PADCONFIG80_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x140 14. "PADCONFIG80_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x140 11.--13. "PADCONFIG80_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x140 0.--3. 1. "PADCONFIG80_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x144 "CFG0_PADCONFIG81,"
bitfld.long 0x144 31. "PADCONFIG81_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x144 21. "PADCONFIG81_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x144 19.--20. "PADCONFIG81_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x144 18. "PADCONFIG81_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x144 17. "PADCONFIG81_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x144 16. "PADCONFIG81_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x144 14. "PADCONFIG81_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x144 11.--13. "PADCONFIG81_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x144 0.--3. 1. "PADCONFIG81_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x148 "CFG0_PADCONFIG82,"
bitfld.long 0x148 31. "PADCONFIG82_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x148 21. "PADCONFIG82_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x148 19.--20. "PADCONFIG82_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x148 18. "PADCONFIG82_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x148 17. "PADCONFIG82_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x148 16. "PADCONFIG82_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x148 14. "PADCONFIG82_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x148 11.--13. "PADCONFIG82_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x148 0.--3. 1. "PADCONFIG82_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x14C "CFG0_PADCONFIG83,"
bitfld.long 0x14C 31. "PADCONFIG83_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x14C 21. "PADCONFIG83_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x14C 19.--20. "PADCONFIG83_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x14C 18. "PADCONFIG83_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x14C 17. "PADCONFIG83_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x14C 16. "PADCONFIG83_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x14C 14. "PADCONFIG83_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x14C 11.--13. "PADCONFIG83_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14C 0.--3. 1. "PADCONFIG83_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x150 "CFG0_PADCONFIG84,"
bitfld.long 0x150 31. "PADCONFIG84_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x150 21. "PADCONFIG84_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x150 19.--20. "PADCONFIG84_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x150 18. "PADCONFIG84_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x150 17. "PADCONFIG84_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x150 16. "PADCONFIG84_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x150 14. "PADCONFIG84_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x150 11.--13. "PADCONFIG84_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x150 0.--3. 1. "PADCONFIG84_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x154 "CFG0_PADCONFIG85,"
bitfld.long 0x154 31. "PADCONFIG85_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x154 21. "PADCONFIG85_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x154 19.--20. "PADCONFIG85_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x154 18. "PADCONFIG85_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x154 17. "PADCONFIG85_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x154 16. "PADCONFIG85_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x154 14. "PADCONFIG85_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x154 11.--13. "PADCONFIG85_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x154 0.--3. 1. "PADCONFIG85_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x158 "CFG0_PADCONFIG86,"
bitfld.long 0x158 31. "PADCONFIG86_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x158 21. "PADCONFIG86_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x158 19.--20. "PADCONFIG86_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x158 18. "PADCONFIG86_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x158 17. "PADCONFIG86_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x158 16. "PADCONFIG86_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x158 14. "PADCONFIG86_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x158 11.--13. "PADCONFIG86_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x158 0.--3. 1. "PADCONFIG86_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x15C "CFG0_PADCONFIG87,"
bitfld.long 0x15C 31. "PADCONFIG87_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x15C 21. "PADCONFIG87_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x15C 19.--20. "PADCONFIG87_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x15C 18. "PADCONFIG87_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x15C 17. "PADCONFIG87_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x15C 16. "PADCONFIG87_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x15C 14. "PADCONFIG87_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x15C 11.--13. "PADCONFIG87_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x15C 0.--3. 1. "PADCONFIG87_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x160 "CFG0_PADCONFIG88,"
bitfld.long 0x160 31. "PADCONFIG88_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x160 21. "PADCONFIG88_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x160 19.--20. "PADCONFIG88_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x160 18. "PADCONFIG88_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x160 17. "PADCONFIG88_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x160 16. "PADCONFIG88_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x160 14. "PADCONFIG88_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x160 11.--13. "PADCONFIG88_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x160 0.--3. 1. "PADCONFIG88_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x164 "CFG0_PADCONFIG89,"
bitfld.long 0x164 31. "PADCONFIG89_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x164 21. "PADCONFIG89_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x164 19.--20. "PADCONFIG89_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x164 18. "PADCONFIG89_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x164 17. "PADCONFIG89_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x164 16. "PADCONFIG89_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x164 14. "PADCONFIG89_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x164 11.--13. "PADCONFIG89_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x164 0.--3. 1. "PADCONFIG89_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x168 "CFG0_PADCONFIG90,"
bitfld.long 0x168 31. "PADCONFIG90_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x168 21. "PADCONFIG90_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x168 19.--20. "PADCONFIG90_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x168 18. "PADCONFIG90_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x168 17. "PADCONFIG90_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x168 16. "PADCONFIG90_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x168 14. "PADCONFIG90_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x168 11.--13. "PADCONFIG90_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x168 0.--3. 1. "PADCONFIG90_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x16C "CFG0_PADCONFIG91,"
bitfld.long 0x16C 31. "PADCONFIG91_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x16C 21. "PADCONFIG91_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x16C 19.--20. "PADCONFIG91_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x16C 18. "PADCONFIG91_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x16C 17. "PADCONFIG91_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x16C 16. "PADCONFIG91_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x16C 14. "PADCONFIG91_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x16C 11.--13. "PADCONFIG91_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x16C 0.--3. 1. "PADCONFIG91_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x170 "CFG0_PADCONFIG92,"
bitfld.long 0x170 31. "PADCONFIG92_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x170 21. "PADCONFIG92_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x170 19.--20. "PADCONFIG92_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x170 18. "PADCONFIG92_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x170 17. "PADCONFIG92_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x170 16. "PADCONFIG92_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x170 14. "PADCONFIG92_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x170 11.--13. "PADCONFIG92_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x170 0.--3. 1. "PADCONFIG92_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x174 "CFG0_PADCONFIG93,"
bitfld.long 0x174 31. "PADCONFIG93_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x174 21. "PADCONFIG93_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x174 19.--20. "PADCONFIG93_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x174 18. "PADCONFIG93_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x174 17. "PADCONFIG93_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x174 16. "PADCONFIG93_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x174 14. "PADCONFIG93_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x174 11.--13. "PADCONFIG93_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x174 0.--3. 1. "PADCONFIG93_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x178 "CFG0_PADCONFIG94,"
bitfld.long 0x178 31. "PADCONFIG94_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x178 21. "PADCONFIG94_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x178 19.--20. "PADCONFIG94_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x178 18. "PADCONFIG94_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x178 17. "PADCONFIG94_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x178 16. "PADCONFIG94_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x178 14. "PADCONFIG94_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x178 11.--13. "PADCONFIG94_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x178 0.--3. 1. "PADCONFIG94_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x17C "CFG0_PADCONFIG95,"
bitfld.long 0x17C 31. "PADCONFIG95_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x17C 21. "PADCONFIG95_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x17C 19.--20. "PADCONFIG95_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x17C 18. "PADCONFIG95_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x17C 17. "PADCONFIG95_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x17C 16. "PADCONFIG95_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x17C 14. "PADCONFIG95_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x17C 11.--13. "PADCONFIG95_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x17C 0.--3. 1. "PADCONFIG95_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x180 "CFG0_PADCONFIG96,"
bitfld.long 0x180 31. "PADCONFIG96_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x180 21. "PADCONFIG96_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x180 19.--20. "PADCONFIG96_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x180 18. "PADCONFIG96_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x180 17. "PADCONFIG96_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x180 16. "PADCONFIG96_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x180 14. "PADCONFIG96_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x180 11.--13. "PADCONFIG96_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x180 0.--3. 1. "PADCONFIG96_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x184 "CFG0_PADCONFIG97,"
bitfld.long 0x184 31. "PADCONFIG97_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x184 21. "PADCONFIG97_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x184 19.--20. "PADCONFIG97_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x184 18. "PADCONFIG97_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x184 17. "PADCONFIG97_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x184 16. "PADCONFIG97_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x184 14. "PADCONFIG97_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x184 11.--13. "PADCONFIG97_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x184 0.--3. 1. "PADCONFIG97_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x188 "CFG0_PADCONFIG98,"
bitfld.long 0x188 31. "PADCONFIG98_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x188 21. "PADCONFIG98_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x188 19.--20. "PADCONFIG98_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x188 18. "PADCONFIG98_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x188 17. "PADCONFIG98_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x188 16. "PADCONFIG98_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x188 14. "PADCONFIG98_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x188 11.--13. "PADCONFIG98_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x188 0.--3. 1. "PADCONFIG98_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x18C "CFG0_PADCONFIG99,"
bitfld.long 0x18C 31. "PADCONFIG99_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x18C 21. "PADCONFIG99_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x18C 19.--20. "PADCONFIG99_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x18C 18. "PADCONFIG99_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x18C 17. "PADCONFIG99_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x18C 16. "PADCONFIG99_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x18C 14. "PADCONFIG99_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x18C 11.--13. "PADCONFIG99_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18C 0.--3. 1. "PADCONFIG99_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x190 "CFG0_PADCONFIG100,"
bitfld.long 0x190 31. "PADCONFIG100_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x190 21. "PADCONFIG100_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x190 19.--20. "PADCONFIG100_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x190 18. "PADCONFIG100_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x190 17. "PADCONFIG100_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x190 16. "PADCONFIG100_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x190 14. "PADCONFIG100_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x190 11.--13. "PADCONFIG100_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x190 0.--3. 1. "PADCONFIG100_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x194 "CFG0_PADCONFIG101,"
bitfld.long 0x194 31. "PADCONFIG101_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x194 21. "PADCONFIG101_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x194 19.--20. "PADCONFIG101_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x194 18. "PADCONFIG101_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x194 17. "PADCONFIG101_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x194 16. "PADCONFIG101_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x194 14. "PADCONFIG101_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x194 11.--13. "PADCONFIG101_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x194 0.--3. 1. "PADCONFIG101_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x198 "CFG0_PADCONFIG102,"
bitfld.long 0x198 31. "PADCONFIG102_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x198 21. "PADCONFIG102_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x198 19.--20. "PADCONFIG102_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x198 18. "PADCONFIG102_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x198 17. "PADCONFIG102_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x198 16. "PADCONFIG102_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x198 14. "PADCONFIG102_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x198 11.--13. "PADCONFIG102_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x198 0.--3. 1. "PADCONFIG102_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x19C "CFG0_PADCONFIG103,"
bitfld.long 0x19C 31. "PADCONFIG103_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x19C 21. "PADCONFIG103_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x19C 19.--20. "PADCONFIG103_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x19C 18. "PADCONFIG103_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x19C 17. "PADCONFIG103_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x19C 16. "PADCONFIG103_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x19C 14. "PADCONFIG103_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x19C 11.--13. "PADCONFIG103_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x19C 0.--3. 1. "PADCONFIG103_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1A0 "CFG0_PADCONFIG104,"
bitfld.long 0x1A0 31. "PADCONFIG104_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1A0 21. "PADCONFIG104_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1A0 19.--20. "PADCONFIG104_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1A0 18. "PADCONFIG104_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1A0 17. "PADCONFIG104_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1A0 16. "PADCONFIG104_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1A0 14. "PADCONFIG104_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1A0 11.--13. "PADCONFIG104_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1A0 0.--3. 1. "PADCONFIG104_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1A4 "CFG0_PADCONFIG105,"
bitfld.long 0x1A4 31. "PADCONFIG105_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1A4 21. "PADCONFIG105_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1A4 19.--20. "PADCONFIG105_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1A4 18. "PADCONFIG105_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1A4 17. "PADCONFIG105_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1A4 16. "PADCONFIG105_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x1A4 14. "PADCONFIG105_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1A4 11.--13. "PADCONFIG105_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1A4 0.--3. 1. "PADCONFIG105_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1A8 "CFG0_PADCONFIG106,"
bitfld.long 0x1A8 31. "PADCONFIG106_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1A8 21. "PADCONFIG106_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1A8 19.--20. "PADCONFIG106_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1A8 18. "PADCONFIG106_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1A8 17. "PADCONFIG106_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1A8 16. "PADCONFIG106_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x1A8 14. "PADCONFIG106_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1A8 11.--13. "PADCONFIG106_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1A8 0.--3. 1. "PADCONFIG106_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1AC "CFG0_PADCONFIG107,"
bitfld.long 0x1AC 31. "PADCONFIG107_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1AC 21. "PADCONFIG107_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1AC 19.--20. "PADCONFIG107_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1AC 18. "PADCONFIG107_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1AC 17. "PADCONFIG107_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1AC 16. "PADCONFIG107_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x1AC 14. "PADCONFIG107_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1AC 11.--13. "PADCONFIG107_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1AC 0.--3. 1. "PADCONFIG107_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1B0 "CFG0_PADCONFIG108,"
bitfld.long 0x1B0 31. "PADCONFIG108_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1B0 21. "PADCONFIG108_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1B0 19.--20. "PADCONFIG108_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1B0 18. "PADCONFIG108_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1B0 17. "PADCONFIG108_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1B0 16. "PADCONFIG108_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x1B0 14. "PADCONFIG108_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1B0 11.--13. "PADCONFIG108_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1B0 0.--3. 1. "PADCONFIG108_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1B4 "CFG0_PADCONFIG109,"
bitfld.long 0x1B4 31. "PADCONFIG109_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1B4 21. "PADCONFIG109_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1B4 19.--20. "PADCONFIG109_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x1B4 18. "PADCONFIG109_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1B4 17. "PADCONFIG109_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1B4 16. "PADCONFIG109_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x1B4 14. "PADCONFIG109_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1B4 11.--13. "PADCONFIG109_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1B4 0.--3. 1. "PADCONFIG109_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1B8 "CFG0_PADCONFIG110,"
bitfld.long 0x1B8 31. "PADCONFIG110_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1B8 21. "PADCONFIG110_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1B8 19.--20. "PADCONFIG110_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1B8 18. "PADCONFIG110_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1B8 17. "PADCONFIG110_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1B8 16. "PADCONFIG110_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x1B8 14. "PADCONFIG110_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1B8 11.--13. "PADCONFIG110_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1B8 0.--3. 1. "PADCONFIG110_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1BC "CFG0_PADCONFIG111,"
bitfld.long 0x1BC 31. "PADCONFIG111_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1BC 21. "PADCONFIG111_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1BC 19.--20. "PADCONFIG111_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1BC 18. "PADCONFIG111_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1BC 17. "PADCONFIG111_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1BC 16. "PADCONFIG111_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1BC 14. "PADCONFIG111_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1BC 11.--13. "PADCONFIG111_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1BC 0.--3. 1. "PADCONFIG111_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1C0 "CFG0_PADCONFIG112,"
bitfld.long 0x1C0 31. "PADCONFIG112_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1C0 21. "PADCONFIG112_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1C0 19.--20. "PADCONFIG112_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1C0 18. "PADCONFIG112_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1C0 17. "PADCONFIG112_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1C0 16. "PADCONFIG112_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1C0 14. "PADCONFIG112_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1C0 11.--13. "PADCONFIG112_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C0 0.--3. 1. "PADCONFIG112_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1C4 "CFG0_PADCONFIG113,"
bitfld.long 0x1C4 31. "PADCONFIG113_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1C4 21. "PADCONFIG113_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1C4 19.--20. "PADCONFIG113_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1C4 18. "PADCONFIG113_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1C4 17. "PADCONFIG113_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1C4 16. "PADCONFIG113_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1C4 14. "PADCONFIG113_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1C4 11.--13. "PADCONFIG113_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C4 0.--3. 1. "PADCONFIG113_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1C8 "CFG0_PADCONFIG114,"
bitfld.long 0x1C8 31. "PADCONFIG114_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1C8 21. "PADCONFIG114_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1C8 19.--20. "PADCONFIG114_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1C8 18. "PADCONFIG114_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1C8 17. "PADCONFIG114_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1C8 16. "PADCONFIG114_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1C8 14. "PADCONFIG114_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1C8 11.--13. "PADCONFIG114_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C8 0.--3. 1. "PADCONFIG114_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1CC "CFG0_PADCONFIG115,"
bitfld.long 0x1CC 31. "PADCONFIG115_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1CC 21. "PADCONFIG115_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1CC 19.--20. "PADCONFIG115_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1CC 18. "PADCONFIG115_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1CC 17. "PADCONFIG115_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1CC 16. "PADCONFIG115_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1CC 14. "PADCONFIG115_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1CC 11.--13. "PADCONFIG115_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1CC 0.--3. 1. "PADCONFIG115_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1D0 "CFG0_PADCONFIG116,"
bitfld.long 0x1D0 31. "PADCONFIG116_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1D0 21. "PADCONFIG116_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1D0 19.--20. "PADCONFIG116_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1D0 18. "PADCONFIG116_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1D0 17. "PADCONFIG116_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1D0 16. "PADCONFIG116_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1D0 14. "PADCONFIG116_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1D0 11.--13. "PADCONFIG116_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1D0 0.--3. 1. "PADCONFIG116_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1D4 "CFG0_PADCONFIG117,"
bitfld.long 0x1D4 31. "PADCONFIG117_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1D4 21. "PADCONFIG117_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1D4 19.--20. "PADCONFIG117_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1D4 18. "PADCONFIG117_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1D4 17. "PADCONFIG117_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1D4 16. "PADCONFIG117_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1D4 14. "PADCONFIG117_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1D4 11.--13. "PADCONFIG117_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1D4 0.--3. 1. "PADCONFIG117_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1D8 "CFG0_PADCONFIG118,"
bitfld.long 0x1D8 31. "PADCONFIG118_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1D8 21. "PADCONFIG118_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1D8 19.--20. "PADCONFIG118_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1D8 18. "PADCONFIG118_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1D8 17. "PADCONFIG118_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1D8 16. "PADCONFIG118_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1D8 14. "PADCONFIG118_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1D8 11.--13. "PADCONFIG118_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1D8 0.--3. 1. "PADCONFIG118_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1DC "CFG0_PADCONFIG119,"
bitfld.long 0x1DC 31. "PADCONFIG119_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1DC 21. "PADCONFIG119_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1DC 19.--20. "PADCONFIG119_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1DC 18. "PADCONFIG119_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1DC 17. "PADCONFIG119_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1DC 16. "PADCONFIG119_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1DC 14. "PADCONFIG119_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1DC 11.--13. "PADCONFIG119_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1DC 0.--3. 1. "PADCONFIG119_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1E0 "CFG0_PADCONFIG120,"
bitfld.long 0x1E0 31. "PADCONFIG120_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1E0 21. "PADCONFIG120_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1E0 19.--20. "PADCONFIG120_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1E0 18. "PADCONFIG120_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1E0 17. "PADCONFIG120_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1E0 16. "PADCONFIG120_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1E0 14. "PADCONFIG120_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1E0 11.--13. "PADCONFIG120_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1E0 0.--3. 1. "PADCONFIG120_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1E4 "CFG0_PADCONFIG121,"
bitfld.long 0x1E4 31. "PADCONFIG121_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1E4 21. "PADCONFIG121_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1E4 19.--20. "PADCONFIG121_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1E4 18. "PADCONFIG121_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1E4 17. "PADCONFIG121_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1E4 16. "PADCONFIG121_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1E4 14. "PADCONFIG121_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1E4 11.--13. "PADCONFIG121_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1E4 0.--3. 1. "PADCONFIG121_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1E8 "CFG0_PADCONFIG122,"
bitfld.long 0x1E8 31. "PADCONFIG122_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1E8 21. "PADCONFIG122_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1E8 19.--20. "PADCONFIG122_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1E8 18. "PADCONFIG122_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1E8 17. "PADCONFIG122_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1E8 16. "PADCONFIG122_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1E8 14. "PADCONFIG122_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1E8 11.--13. "PADCONFIG122_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1E8 0.--3. 1. "PADCONFIG122_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1EC "CFG0_PADCONFIG123,"
bitfld.long 0x1EC 31. "PADCONFIG123_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1EC 21. "PADCONFIG123_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1EC 19.--20. "PADCONFIG123_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1EC 18. "PADCONFIG123_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1EC 17. "PADCONFIG123_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1EC 16. "PADCONFIG123_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1EC 14. "PADCONFIG123_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1EC 11.--13. "PADCONFIG123_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1EC 0.--3. 1. "PADCONFIG123_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1F0 "CFG0_PADCONFIG124,"
bitfld.long 0x1F0 31. "PADCONFIG124_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1F0 21. "PADCONFIG124_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1F0 19.--20. "PADCONFIG124_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1F0 18. "PADCONFIG124_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1F0 17. "PADCONFIG124_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1F0 16. "PADCONFIG124_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1F0 14. "PADCONFIG124_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1F0 11.--13. "PADCONFIG124_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1F0 0.--3. 1. "PADCONFIG124_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1F4 "CFG0_PADCONFIG125,"
bitfld.long 0x1F4 31. "PADCONFIG125_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1F4 21. "PADCONFIG125_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1F4 19.--20. "PADCONFIG125_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1F4 18. "PADCONFIG125_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1F4 17. "PADCONFIG125_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1F4 16. "PADCONFIG125_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1F4 14. "PADCONFIG125_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1F4 11.--13. "PADCONFIG125_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1F4 0.--3. 1. "PADCONFIG125_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1F8 "CFG0_PADCONFIG126,"
bitfld.long 0x1F8 31. "PADCONFIG126_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1F8 21. "PADCONFIG126_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1F8 19.--20. "PADCONFIG126_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1F8 18. "PADCONFIG126_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1F8 17. "PADCONFIG126_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1F8 16. "PADCONFIG126_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1F8 14. "PADCONFIG126_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1F8 11.--13. "PADCONFIG126_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1F8 0.--3. 1. "PADCONFIG126_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x1FC "CFG0_PADCONFIG127,"
bitfld.long 0x1FC 31. "PADCONFIG127_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1FC 21. "PADCONFIG127_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1FC 19.--20. "PADCONFIG127_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1FC 18. "PADCONFIG127_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1FC 17. "PADCONFIG127_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1FC 16. "PADCONFIG127_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1FC 14. "PADCONFIG127_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1FC 11.--13. "PADCONFIG127_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1FC 0.--3. 1. "PADCONFIG127_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x200 "CFG0_PADCONFIG128,"
bitfld.long 0x200 31. "PADCONFIG128_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x200 21. "PADCONFIG128_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x200 19.--20. "PADCONFIG128_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x200 18. "PADCONFIG128_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x200 17. "PADCONFIG128_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x200 16. "PADCONFIG128_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x200 14. "PADCONFIG128_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x200 11.--13. "PADCONFIG128_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x200 0.--3. 1. "PADCONFIG128_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x204 "CFG0_PADCONFIG129,"
bitfld.long 0x204 31. "PADCONFIG129_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x204 21. "PADCONFIG129_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x204 19.--20. "PADCONFIG129_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x204 18. "PADCONFIG129_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x204 17. "PADCONFIG129_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x204 16. "PADCONFIG129_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x204 14. "PADCONFIG129_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x204 11.--13. "PADCONFIG129_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x204 0.--3. 1. "PADCONFIG129_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x208 "CFG0_PADCONFIG130,"
bitfld.long 0x208 31. "PADCONFIG130_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x208 21. "PADCONFIG130_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x208 19.--20. "PADCONFIG130_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x208 18. "PADCONFIG130_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x208 17. "PADCONFIG130_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x208 16. "PADCONFIG130_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x208 14. "PADCONFIG130_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x208 11.--13. "PADCONFIG130_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x208 0.--3. 1. "PADCONFIG130_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x20C "CFG0_PADCONFIG131,"
bitfld.long 0x20C 31. "PADCONFIG131_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x20C 21. "PADCONFIG131_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x20C 19.--20. "PADCONFIG131_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x20C 18. "PADCONFIG131_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x20C 17. "PADCONFIG131_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x20C 16. "PADCONFIG131_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x20C 14. "PADCONFIG131_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x20C 11.--13. "PADCONFIG131_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20C 0.--3. 1. "PADCONFIG131_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x210 "CFG0_PADCONFIG132,"
bitfld.long 0x210 31. "PADCONFIG132_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x210 21. "PADCONFIG132_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x210 19.--20. "PADCONFIG132_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x210 18. "PADCONFIG132_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x210 17. "PADCONFIG132_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x210 16. "PADCONFIG132_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x210 14. "PADCONFIG132_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x210 11.--13. "PADCONFIG132_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x210 0.--3. 1. "PADCONFIG132_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x214 "CFG0_PADCONFIG133,"
bitfld.long 0x214 31. "PADCONFIG133_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x214 21. "PADCONFIG133_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x214 19.--20. "PADCONFIG133_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x214 18. "PADCONFIG133_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x214 17. "PADCONFIG133_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x214 16. "PADCONFIG133_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x214 14. "PADCONFIG133_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x214 11.--13. "PADCONFIG133_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x214 0.--3. 1. "PADCONFIG133_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x218 "CFG0_PADCONFIG134,"
bitfld.long 0x218 31. "PADCONFIG134_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x218 21. "PADCONFIG134_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x218 19.--20. "PADCONFIG134_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x218 18. "PADCONFIG134_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x218 17. "PADCONFIG134_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x218 16. "PADCONFIG134_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x218 14. "PADCONFIG134_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x218 11.--13. "PADCONFIG134_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x218 0.--3. 1. "PADCONFIG134_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x21C "CFG0_PADCONFIG135,"
bitfld.long 0x21C 31. "PADCONFIG135_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x21C 21. "PADCONFIG135_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x21C 19.--20. "PADCONFIG135_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x21C 18. "PADCONFIG135_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x21C 17. "PADCONFIG135_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x21C 16. "PADCONFIG135_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x21C 14. "PADCONFIG135_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x21C 11.--13. "PADCONFIG135_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x21C 0.--3. 1. "PADCONFIG135_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x220 "CFG0_PADCONFIG136,"
bitfld.long 0x220 31. "PADCONFIG136_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x220 21. "PADCONFIG136_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x220 19.--20. "PADCONFIG136_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x220 18. "PADCONFIG136_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x220 17. "PADCONFIG136_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x220 16. "PADCONFIG136_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x220 14. "PADCONFIG136_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x220 11.--13. "PADCONFIG136_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x220 0.--3. 1. "PADCONFIG136_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x224 "CFG0_PADCONFIG137,"
bitfld.long 0x224 31. "PADCONFIG137_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x224 21. "PADCONFIG137_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x224 19.--20. "PADCONFIG137_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x224 18. "PADCONFIG137_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x224 17. "PADCONFIG137_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x224 16. "PADCONFIG137_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x224 14. "PADCONFIG137_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x224 11.--13. "PADCONFIG137_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x224 0.--3. 1. "PADCONFIG137_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x228 "CFG0_PADCONFIG138,"
bitfld.long 0x228 31. "PADCONFIG138_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x228 21. "PADCONFIG138_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x228 19.--20. "PADCONFIG138_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x228 18. "PADCONFIG138_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x228 17. "PADCONFIG138_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x228 16. "PADCONFIG138_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x228 14. "PADCONFIG138_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x228 11.--13. "PADCONFIG138_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x228 0.--3. 1. "PADCONFIG138_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x22C "CFG0_PADCONFIG139,"
bitfld.long 0x22C 31. "PADCONFIG139_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x22C 21. "PADCONFIG139_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x22C 19.--20. "PADCONFIG139_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x22C 18. "PADCONFIG139_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x22C 17. "PADCONFIG139_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x22C 16. "PADCONFIG139_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x22C 14. "PADCONFIG139_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x22C 11.--13. "PADCONFIG139_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x22C 0.--3. 1. "PADCONFIG139_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x230 "CFG0_PADCONFIG140,"
bitfld.long 0x230 31. "PADCONFIG140_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x230 21. "PADCONFIG140_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x230 19.--20. "PADCONFIG140_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x230 18. "PADCONFIG140_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x230 17. "PADCONFIG140_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x230 16. "PADCONFIG140_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x230 14. "PADCONFIG140_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x230 11.--13. "PADCONFIG140_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x230 0.--3. 1. "PADCONFIG140_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x234 "CFG0_PADCONFIG141,"
bitfld.long 0x234 31. "PADCONFIG141_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x234 21. "PADCONFIG141_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x234 19.--20. "PADCONFIG141_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x234 18. "PADCONFIG141_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x234 17. "PADCONFIG141_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x234 16. "PADCONFIG141_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x234 14. "PADCONFIG141_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x234 11.--13. "PADCONFIG141_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x234 0.--3. 1. "PADCONFIG141_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x238 "CFG0_PADCONFIG142,"
bitfld.long 0x238 31. "PADCONFIG142_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x238 21. "PADCONFIG142_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x238 19.--20. "PADCONFIG142_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x238 18. "PADCONFIG142_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x238 17. "PADCONFIG142_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x238 16. "PADCONFIG142_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x238 14. "PADCONFIG142_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x238 11.--13. "PADCONFIG142_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x238 0.--3. 1. "PADCONFIG142_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x23C "CFG0_PADCONFIG143,"
bitfld.long 0x23C 31. "PADCONFIG143_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x23C 21. "PADCONFIG143_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x23C 19.--20. "PADCONFIG143_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x23C 18. "PADCONFIG143_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x23C 17. "PADCONFIG143_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x23C 16. "PADCONFIG143_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x23C 14. "PADCONFIG143_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x23C 11.--13. "PADCONFIG143_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x23C 0.--3. 1. "PADCONFIG143_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x240 "CFG0_PADCONFIG144,"
bitfld.long 0x240 31. "PADCONFIG144_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x240 21. "PADCONFIG144_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x240 19.--20. "PADCONFIG144_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x240 18. "PADCONFIG144_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x240 17. "PADCONFIG144_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x240 16. "PADCONFIG144_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x240 14. "PADCONFIG144_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x240 11.--13. "PADCONFIG144_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x240 0.--3. 1. "PADCONFIG144_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x244 "CFG0_PADCONFIG145,"
bitfld.long 0x244 31. "PADCONFIG145_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x244 21. "PADCONFIG145_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x244 19.--20. "PADCONFIG145_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x244 18. "PADCONFIG145_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x244 17. "PADCONFIG145_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x244 16. "PADCONFIG145_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x244 14. "PADCONFIG145_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x244 11.--13. "PADCONFIG145_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x244 0.--3. 1. "PADCONFIG145_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x248 "CFG0_PADCONFIG146,"
bitfld.long 0x248 31. "PADCONFIG146_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x248 21. "PADCONFIG146_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x248 19.--20. "PADCONFIG146_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x248 18. "PADCONFIG146_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x248 17. "PADCONFIG146_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x248 16. "PADCONFIG146_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x248 14. "PADCONFIG146_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x248 11.--13. "PADCONFIG146_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x248 0.--3. 1. "PADCONFIG146_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x24C "CFG0_PADCONFIG147,"
bitfld.long 0x24C 31. "PADCONFIG147_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x24C 21. "PADCONFIG147_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x24C 19.--20. "PADCONFIG147_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x24C 18. "PADCONFIG147_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x24C 17. "PADCONFIG147_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x24C 16. "PADCONFIG147_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x24C 14. "PADCONFIG147_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x24C 11.--13. "PADCONFIG147_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24C 0.--3. 1. "PADCONFIG147_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x250 "CFG0_PADCONFIG148,"
bitfld.long 0x250 31. "PADCONFIG148_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x250 21. "PADCONFIG148_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x250 19.--20. "PADCONFIG148_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x250 18. "PADCONFIG148_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x250 17. "PADCONFIG148_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x250 16. "PADCONFIG148_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x250 14. "PADCONFIG148_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x250 11.--13. "PADCONFIG148_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x250 0.--3. 1. "PADCONFIG148_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x254 "CFG0_PADCONFIG149,"
bitfld.long 0x254 31. "PADCONFIG149_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x254 21. "PADCONFIG149_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x254 19.--20. "PADCONFIG149_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x254 18. "PADCONFIG149_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x254 17. "PADCONFIG149_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x254 16. "PADCONFIG149_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x254 14. "PADCONFIG149_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x254 11.--13. "PADCONFIG149_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x254 0.--3. 1. "PADCONFIG149_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x258 "CFG0_PADCONFIG150,"
bitfld.long 0x258 31. "PADCONFIG150_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x258 21. "PADCONFIG150_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x258 19.--20. "PADCONFIG150_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x258 18. "PADCONFIG150_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x258 17. "PADCONFIG150_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x258 16. "PADCONFIG150_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x258 14. "PADCONFIG150_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x258 11.--13. "PADCONFIG150_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x258 0.--3. 1. "PADCONFIG150_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x25C "CFG0_PADCONFIG151,"
bitfld.long 0x25C 31. "PADCONFIG151_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x25C 21. "PADCONFIG151_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x25C 19.--20. "PADCONFIG151_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x25C 18. "PADCONFIG151_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x25C 17. "PADCONFIG151_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x25C 16. "PADCONFIG151_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x25C 14. "PADCONFIG151_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x25C 11.--13. "PADCONFIG151_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x25C 0.--3. 1. "PADCONFIG151_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x260 "CFG0_PADCONFIG152,"
bitfld.long 0x260 31. "PADCONFIG152_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x260 21. "PADCONFIG152_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x260 19.--20. "PADCONFIG152_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x260 18. "PADCONFIG152_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x260 17. "PADCONFIG152_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x260 16. "PADCONFIG152_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x260 14. "PADCONFIG152_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x260 11.--13. "PADCONFIG152_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x260 0.--3. 1. "PADCONFIG152_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x264 "CFG0_PADCONFIG153,"
bitfld.long 0x264 31. "PADCONFIG153_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x264 21. "PADCONFIG153_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x264 19.--20. "PADCONFIG153_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x264 18. "PADCONFIG153_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x264 17. "PADCONFIG153_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x264 16. "PADCONFIG153_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x264 14. "PADCONFIG153_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x264 11.--13. "PADCONFIG153_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x264 0.--3. 1. "PADCONFIG153_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x268 "CFG0_PADCONFIG154,"
bitfld.long 0x268 31. "PADCONFIG154_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x268 21. "PADCONFIG154_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x268 19.--20. "PADCONFIG154_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x268 18. "PADCONFIG154_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x268 17. "PADCONFIG154_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x268 16. "PADCONFIG154_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x268 14. "PADCONFIG154_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x268 11.--13. "PADCONFIG154_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x268 0.--3. 1. "PADCONFIG154_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x26C "CFG0_PADCONFIG155,"
bitfld.long 0x26C 31. "PADCONFIG155_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x26C 21. "PADCONFIG155_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x26C 19.--20. "PADCONFIG155_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x26C 18. "PADCONFIG155_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x26C 17. "PADCONFIG155_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x26C 16. "PADCONFIG155_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x26C 14. "PADCONFIG155_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x26C 11.--13. "PADCONFIG155_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x26C 0.--3. 1. "PADCONFIG155_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x270 "CFG0_PADCONFIG156,"
bitfld.long 0x270 31. "PADCONFIG156_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x270 21. "PADCONFIG156_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x270 19.--20. "PADCONFIG156_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x270 18. "PADCONFIG156_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x270 17. "PADCONFIG156_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x270 16. "PADCONFIG156_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x270 14. "PADCONFIG156_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x270 11.--13. "PADCONFIG156_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x270 0.--3. 1. "PADCONFIG156_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x274 "CFG0_PADCONFIG157,"
bitfld.long 0x274 31. "PADCONFIG157_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x274 21. "PADCONFIG157_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x274 19.--20. "PADCONFIG157_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x274 18. "PADCONFIG157_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x274 17. "PADCONFIG157_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x274 16. "PADCONFIG157_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x274 14. "PADCONFIG157_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x274 11.--13. "PADCONFIG157_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x274 0.--3. 1. "PADCONFIG157_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x278 "CFG0_PADCONFIG158,"
bitfld.long 0x278 31. "PADCONFIG158_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x278 21. "PADCONFIG158_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x278 19.--20. "PADCONFIG158_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x278 18. "PADCONFIG158_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x278 17. "PADCONFIG158_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x278 16. "PADCONFIG158_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x278 14. "PADCONFIG158_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x278 11.--13. "PADCONFIG158_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x278 0.--3. 1. "PADCONFIG158_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x27C "CFG0_PADCONFIG159,"
bitfld.long 0x27C 31. "PADCONFIG159_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x27C 21. "PADCONFIG159_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x27C 19.--20. "PADCONFIG159_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x27C 18. "PADCONFIG159_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x27C 17. "PADCONFIG159_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x27C 16. "PADCONFIG159_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x27C 14. "PADCONFIG159_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x27C 11.--13. "PADCONFIG159_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x27C 0.--3. 1. "PADCONFIG159_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x280 "CFG0_PADCONFIG160,"
bitfld.long 0x280 31. "PADCONFIG160_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x280 21. "PADCONFIG160_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x280 19.--20. "PADCONFIG160_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x280 18. "PADCONFIG160_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x280 17. "PADCONFIG160_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x280 16. "PADCONFIG160_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x280 14. "PADCONFIG160_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x280 11.--13. "PADCONFIG160_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x280 0.--3. 1. "PADCONFIG160_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x284 "CFG0_PADCONFIG161,"
bitfld.long 0x284 31. "PADCONFIG161_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x284 21. "PADCONFIG161_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x284 19.--20. "PADCONFIG161_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x284 18. "PADCONFIG161_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x284 17. "PADCONFIG161_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x284 16. "PADCONFIG161_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x284 14. "PADCONFIG161_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x284 11.--13. "PADCONFIG161_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x284 0.--3. 1. "PADCONFIG161_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x288 "CFG0_PADCONFIG162,"
bitfld.long 0x288 31. "PADCONFIG162_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x288 21. "PADCONFIG162_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x288 19.--20. "PADCONFIG162_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x288 18. "PADCONFIG162_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x288 17. "PADCONFIG162_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x288 16. "PADCONFIG162_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x288 14. "PADCONFIG162_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x288 11.--13. "PADCONFIG162_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x288 0.--3. 1. "PADCONFIG162_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x28C "CFG0_PADCONFIG163,"
bitfld.long 0x28C 31. "PADCONFIG163_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x28C 21. "PADCONFIG163_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x28C 19.--20. "PADCONFIG163_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x28C 18. "PADCONFIG163_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x28C 17. "PADCONFIG163_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x28C 16. "PADCONFIG163_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x28C 14. "PADCONFIG163_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x28C 11.--13. "PADCONFIG163_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x28C 0.--3. 1. "PADCONFIG163_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x290 "CFG0_PADCONFIG164,"
bitfld.long 0x290 31. "PADCONFIG164_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x290 21. "PADCONFIG164_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x290 19.--20. "PADCONFIG164_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x290 18. "PADCONFIG164_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x290 17. "PADCONFIG164_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x290 16. "PADCONFIG164_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x290 14. "PADCONFIG164_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x290 11.--13. "PADCONFIG164_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x290 0.--3. 1. "PADCONFIG164_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x294 "CFG0_PADCONFIG165,"
bitfld.long 0x294 31. "PADCONFIG165_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x294 21. "PADCONFIG165_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x294 19.--20. "PADCONFIG165_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x294 18. "PADCONFIG165_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x294 17. "PADCONFIG165_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x294 16. "PADCONFIG165_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x294 14. "PADCONFIG165_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x294 11.--13. "PADCONFIG165_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x294 0.--3. 1. "PADCONFIG165_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x298 "CFG0_PADCONFIG166,"
bitfld.long 0x298 31. "PADCONFIG166_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x298 21. "PADCONFIG166_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x298 19.--20. "PADCONFIG166_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x298 18. "PADCONFIG166_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x298 17. "PADCONFIG166_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x298 16. "PADCONFIG166_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x298 14. "PADCONFIG166_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x298 11.--13. "PADCONFIG166_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x298 0.--3. 1. "PADCONFIG166_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x29C "CFG0_PADCONFIG167,"
bitfld.long 0x29C 31. "PADCONFIG167_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x29C 21. "PADCONFIG167_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x29C 19.--20. "PADCONFIG167_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x29C 18. "PADCONFIG167_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x29C 17. "PADCONFIG167_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x29C 16. "PADCONFIG167_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x29C 14. "PADCONFIG167_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x29C 11.--13. "PADCONFIG167_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x29C 0.--3. 1. "PADCONFIG167_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2A0 "CFG0_PADCONFIG168,"
bitfld.long 0x2A0 31. "PADCONFIG168_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2A0 21. "PADCONFIG168_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2A0 19.--20. "PADCONFIG168_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2A0 18. "PADCONFIG168_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2A0 17. "PADCONFIG168_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2A0 16. "PADCONFIG168_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2A0 14. "PADCONFIG168_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2A0 11.--13. "PADCONFIG168_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2A0 0.--3. 1. "PADCONFIG168_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2A4 "CFG0_PADCONFIG169,"
bitfld.long 0x2A4 31. "PADCONFIG169_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2A4 21. "PADCONFIG169_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2A4 19.--20. "PADCONFIG169_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2A4 18. "PADCONFIG169_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2A4 17. "PADCONFIG169_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2A4 16. "PADCONFIG169_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2A4 14. "PADCONFIG169_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2A4 11.--13. "PADCONFIG169_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2A4 0.--3. 1. "PADCONFIG169_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2A8 "CFG0_PADCONFIG170,"
bitfld.long 0x2A8 31. "PADCONFIG170_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2A8 21. "PADCONFIG170_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2A8 19.--20. "PADCONFIG170_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2A8 18. "PADCONFIG170_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2A8 17. "PADCONFIG170_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2A8 16. "PADCONFIG170_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2A8 14. "PADCONFIG170_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2A8 11.--13. "PADCONFIG170_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2A8 0.--3. 1. "PADCONFIG170_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2AC "CFG0_PADCONFIG171,"
bitfld.long 0x2AC 31. "PADCONFIG171_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2AC 21. "PADCONFIG171_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2AC 19.--20. "PADCONFIG171_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2AC 18. "PADCONFIG171_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2AC 17. "PADCONFIG171_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2AC 16. "PADCONFIG171_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2AC 14. "PADCONFIG171_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2AC 11.--13. "PADCONFIG171_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2AC 0.--3. 1. "PADCONFIG171_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2B0 "CFG0_PADCONFIG172,"
bitfld.long 0x2B0 31. "PADCONFIG172_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2B0 21. "PADCONFIG172_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2B0 19.--20. "PADCONFIG172_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2B0 18. "PADCONFIG172_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2B0 17. "PADCONFIG172_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2B0 16. "PADCONFIG172_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2B0 14. "PADCONFIG172_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2B0 11.--13. "PADCONFIG172_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2B0 0.--3. 1. "PADCONFIG172_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2B4 "CFG0_PADCONFIG173,"
bitfld.long 0x2B4 31. "PADCONFIG173_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2B4 21. "PADCONFIG173_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2B4 19.--20. "PADCONFIG173_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2B4 18. "PADCONFIG173_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2B4 17. "PADCONFIG173_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2B4 16. "PADCONFIG173_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2B4 14. "PADCONFIG173_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2B4 11.--13. "PADCONFIG173_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2B4 0.--3. 1. "PADCONFIG173_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2B8 "CFG0_PADCONFIG174,"
bitfld.long 0x2B8 31. "PADCONFIG174_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2B8 21. "PADCONFIG174_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2B8 19.--20. "PADCONFIG174_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2B8 18. "PADCONFIG174_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2B8 17. "PADCONFIG174_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2B8 16. "PADCONFIG174_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2B8 14. "PADCONFIG174_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2B8 11.--13. "PADCONFIG174_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2B8 0.--3. 1. "PADCONFIG174_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2BC "CFG0_PADCONFIG175,"
bitfld.long 0x2BC 31. "PADCONFIG175_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2BC 21. "PADCONFIG175_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2BC 19.--20. "PADCONFIG175_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2BC 18. "PADCONFIG175_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2BC 17. "PADCONFIG175_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2BC 16. "PADCONFIG175_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2BC 14. "PADCONFIG175_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2BC 11.--13. "PADCONFIG175_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2BC 0.--3. 1. "PADCONFIG175_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2C0 "CFG0_PADCONFIG176,"
bitfld.long 0x2C0 31. "PADCONFIG176_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2C0 21. "PADCONFIG176_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2C0 19.--20. "PADCONFIG176_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2C0 18. "PADCONFIG176_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2C0 17. "PADCONFIG176_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2C0 16. "PADCONFIG176_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2C0 14. "PADCONFIG176_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2C0 11.--13. "PADCONFIG176_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C0 0.--3. 1. "PADCONFIG176_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2C4 "CFG0_PADCONFIG177,"
bitfld.long 0x2C4 31. "PADCONFIG177_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2C4 21. "PADCONFIG177_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2C4 19.--20. "PADCONFIG177_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2C4 18. "PADCONFIG177_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2C4 17. "PADCONFIG177_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2C4 16. "PADCONFIG177_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2C4 14. "PADCONFIG177_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2C4 11.--13. "PADCONFIG177_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C4 0.--3. 1. "PADCONFIG177_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2C8 "CFG0_PADCONFIG178,"
bitfld.long 0x2C8 31. "PADCONFIG178_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2C8 21. "PADCONFIG178_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2C8 19.--20. "PADCONFIG178_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2C8 18. "PADCONFIG178_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2C8 17. "PADCONFIG178_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2C8 16. "PADCONFIG178_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2C8 14. "PADCONFIG178_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2C8 11.--13. "PADCONFIG178_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C8 0.--3. 1. "PADCONFIG178_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
line.long 0x2CC "CFG0_PADCONFIG179,"
bitfld.long 0x2CC 31. "PADCONFIG179_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2CC 21. "PADCONFIG179_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2CC 19.--20. "PADCONFIG179_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2CC 18. "PADCONFIG179_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2CC 17. "PADCONFIG179_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2CC 16. "PADCONFIG179_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2CC 14. "PADCONFIG179_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2CC 11.--13. "PADCONFIG179_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2CC 0.--3. 1. "PADCONFIG179_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.."
group.long 0x5008++0x7
line.long 0x0 "CFG0_LOCK1_KICK0,"
hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component"
line.long 0x4 "CFG0_LOCK1_KICK1,"
hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component"
group.long 0x6000++0x2CF
line.long 0x0 "CFG0_PADCONFIG0_PROXY,"
bitfld.long 0x0 31. "PADCONFIG0_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x0 21. "PADCONFIG0_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x0 19.--20. "PADCONFIG0_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x0 17. "PADCONFIG0_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x0 16. "PADCONFIG0_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x0 14. "PADCONFIG0_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x4 "CFG0_PADCONFIG1_PROXY,"
bitfld.long 0x4 31. "PADCONFIG1_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x4 21. "PADCONFIG1_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x4 14. "PADCONFIG1_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x8 "CFG0_PADCONFIG2_PROXY,"
bitfld.long 0x8 31. "PADCONFIG2_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x8 21. "PADCONFIG2_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x8 14. "PADCONFIG2_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xC "CFG0_PADCONFIG3_PROXY,"
bitfld.long 0xC 31. "PADCONFIG3_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xC 21. "PADCONFIG3_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0xC 14. "PADCONFIG3_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x10 "CFG0_PADCONFIG4_PROXY,"
bitfld.long 0x10 31. "PADCONFIG4_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x10 21. "PADCONFIG4_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x10 14. "PADCONFIG4_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x14 "CFG0_PADCONFIG5_PROXY,"
bitfld.long 0x14 31. "PADCONFIG5_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x14 21. "PADCONFIG5_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x14 14. "PADCONFIG5_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x18 "CFG0_PADCONFIG6_PROXY,"
bitfld.long 0x18 31. "PADCONFIG6_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x18 21. "PADCONFIG6_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x18 14. "PADCONFIG6_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x1C "CFG0_PADCONFIG7_PROXY,"
bitfld.long 0x1C 31. "PADCONFIG7_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1C 14. "PADCONFIG7_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x20 "CFG0_PADCONFIG8_PROXY,"
bitfld.long 0x20 31. "PADCONFIG8_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x20 21. "PADCONFIG8_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x20 14. "PADCONFIG8_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x24 "CFG0_PADCONFIG9_PROXY,"
bitfld.long 0x24 31. "PADCONFIG9_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x24 21. "PADCONFIG9_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x24 14. "PADCONFIG9_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x28 "CFG0_PADCONFIG10_PROXY,"
bitfld.long 0x28 31. "PADCONFIG10_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x28 21. "PADCONFIG10_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x28 14. "PADCONFIG10_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x2C "CFG0_PADCONFIG11_PROXY,"
bitfld.long 0x2C 31. "PADCONFIG11_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2C 14. "PADCONFIG11_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x30 "CFG0_PADCONFIG12_PROXY,"
bitfld.long 0x30 31. "PADCONFIG12_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x30 21. "PADCONFIG12_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x30 14. "PADCONFIG12_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x34 "CFG0_PADCONFIG13_PROXY,"
bitfld.long 0x34 31. "PADCONFIG13_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x34 21. "PADCONFIG13_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x34 14. "PADCONFIG13_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG13_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x38 "CFG0_PADCONFIG14_PROXY,"
bitfld.long 0x38 31. "PADCONFIG14_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x38 21. "PADCONFIG14_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x38 14. "PADCONFIG14_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG14_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x3C "CFG0_PADCONFIG15_PROXY,"
bitfld.long 0x3C 31. "PADCONFIG15_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x3C 14. "PADCONFIG15_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG15_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x40 "CFG0_PADCONFIG16_PROXY,"
bitfld.long 0x40 31. "PADCONFIG16_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x40 21. "PADCONFIG16_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x40 14. "PADCONFIG16_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG16_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x44 "CFG0_PADCONFIG17_PROXY,"
bitfld.long 0x44 31. "PADCONFIG17_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x44 21. "PADCONFIG17_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x44 14. "PADCONFIG17_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG17_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x48 "CFG0_PADCONFIG18_PROXY,"
bitfld.long 0x48 31. "PADCONFIG18_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x48 21. "PADCONFIG18_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x48 14. "PADCONFIG18_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG18_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x4C "CFG0_PADCONFIG19_PROXY,"
bitfld.long 0x4C 31. "PADCONFIG19_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x4C 14. "PADCONFIG19_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG19_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x50 "CFG0_PADCONFIG20_PROXY,"
bitfld.long 0x50 31. "PADCONFIG20_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x50 21. "PADCONFIG20_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x50 14. "PADCONFIG20_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG20_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x54 "CFG0_PADCONFIG21_PROXY,"
bitfld.long 0x54 31. "PADCONFIG21_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x54 21. "PADCONFIG21_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x54 14. "PADCONFIG21_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG21_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x58 "CFG0_PADCONFIG22_PROXY,"
bitfld.long 0x58 31. "PADCONFIG22_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x58 21. "PADCONFIG22_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x58 14. "PADCONFIG22_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG22_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x5C "CFG0_PADCONFIG23_PROXY,"
bitfld.long 0x5C 31. "PADCONFIG23_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x5C 14. "PADCONFIG23_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG23_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x60 "CFG0_PADCONFIG24_PROXY,"
bitfld.long 0x60 31. "PADCONFIG24_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x60 21. "PADCONFIG24_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x60 14. "PADCONFIG24_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG24_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x64 "CFG0_PADCONFIG25_PROXY,"
bitfld.long 0x64 31. "PADCONFIG25_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x64 21. "PADCONFIG25_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x64 14. "PADCONFIG25_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG25_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x68 "CFG0_PADCONFIG26_PROXY,"
bitfld.long 0x68 31. "PADCONFIG26_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x68 21. "PADCONFIG26_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x68 14. "PADCONFIG26_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG26_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x6C "CFG0_PADCONFIG27_PROXY,"
bitfld.long 0x6C 31. "PADCONFIG27_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x6C 14. "PADCONFIG27_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG27_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x70 "CFG0_PADCONFIG28_PROXY,"
bitfld.long 0x70 31. "PADCONFIG28_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x70 21. "PADCONFIG28_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x70 14. "PADCONFIG28_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG28_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x74 "CFG0_PADCONFIG29_PROXY,"
bitfld.long 0x74 31. "PADCONFIG29_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x74 21. "PADCONFIG29_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x74 14. "PADCONFIG29_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG29_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x78 "CFG0_PADCONFIG30_PROXY,"
bitfld.long 0x78 31. "PADCONFIG30_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x78 21. "PADCONFIG30_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x78 14. "PADCONFIG30_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG30_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x7C "CFG0_PADCONFIG31_PROXY,"
bitfld.long 0x7C 31. "PADCONFIG31_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x7C 14. "PADCONFIG31_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG31_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x80 "CFG0_PADCONFIG32_PROXY,"
bitfld.long 0x80 31. "PADCONFIG32_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x80 21. "PADCONFIG32_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x80 14. "PADCONFIG32_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG32_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x84 "CFG0_PADCONFIG33_PROXY,"
bitfld.long 0x84 31. "PADCONFIG33_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x84 21. "PADCONFIG33_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x84 14. "PADCONFIG33_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x84 0.--3. 1. "PADCONFIG33_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x88 "CFG0_PADCONFIG34_PROXY,"
bitfld.long 0x88 31. "PADCONFIG34_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x88 21. "PADCONFIG34_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x88 19.--20. "PADCONFIG34_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x88 18. "PADCONFIG34_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x88 17. "PADCONFIG34_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x88 16. "PADCONFIG34_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x88 14. "PADCONFIG34_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x88 11.--13. "PADCONFIG34_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x88 0.--3. 1. "PADCONFIG34_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x8C "CFG0_PADCONFIG35_PROXY,"
bitfld.long 0x8C 31. "PADCONFIG35_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x8C 21. "PADCONFIG35_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x8C 19.--20. "PADCONFIG35_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x8C 18. "PADCONFIG35_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x8C 17. "PADCONFIG35_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x8C 16. "PADCONFIG35_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x8C 14. "PADCONFIG35_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x8C 11.--13. "PADCONFIG35_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8C 0.--3. 1. "PADCONFIG35_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x90 "CFG0_PADCONFIG36_PROXY,"
bitfld.long 0x90 31. "PADCONFIG36_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x90 21. "PADCONFIG36_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x90 19.--20. "PADCONFIG36_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x90 18. "PADCONFIG36_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x90 17. "PADCONFIG36_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x90 16. "PADCONFIG36_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x90 14. "PADCONFIG36_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x90 11.--13. "PADCONFIG36_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x90 0.--3. 1. "PADCONFIG36_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x94 "CFG0_PADCONFIG37_PROXY,"
bitfld.long 0x94 31. "PADCONFIG37_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x94 21. "PADCONFIG37_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x94 19.--20. "PADCONFIG37_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x94 18. "PADCONFIG37_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x94 17. "PADCONFIG37_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x94 16. "PADCONFIG37_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x94 14. "PADCONFIG37_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x94 11.--13. "PADCONFIG37_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x94 0.--3. 1. "PADCONFIG37_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x98 "CFG0_PADCONFIG38_PROXY,"
bitfld.long 0x98 31. "PADCONFIG38_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x98 21. "PADCONFIG38_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x98 19.--20. "PADCONFIG38_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x98 18. "PADCONFIG38_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x98 17. "PADCONFIG38_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x98 16. "PADCONFIG38_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x98 14. "PADCONFIG38_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x98 11.--13. "PADCONFIG38_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x98 0.--3. 1. "PADCONFIG38_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x9C "CFG0_PADCONFIG39_PROXY,"
bitfld.long 0x9C 31. "PADCONFIG39_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x9C 21. "PADCONFIG39_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x9C 19.--20. "PADCONFIG39_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x9C 18. "PADCONFIG39_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x9C 17. "PADCONFIG39_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x9C 16. "PADCONFIG39_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x9C 14. "PADCONFIG39_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x9C 11.--13. "PADCONFIG39_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x9C 0.--3. 1. "PADCONFIG39_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xA0 "CFG0_PADCONFIG40_PROXY,"
bitfld.long 0xA0 31. "PADCONFIG40_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xA0 21. "PADCONFIG40_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xA0 19.--20. "PADCONFIG40_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xA0 18. "PADCONFIG40_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xA0 17. "PADCONFIG40_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xA0 16. "PADCONFIG40_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xA0 14. "PADCONFIG40_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xA0 11.--13. "PADCONFIG40_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xA0 0.--3. 1. "PADCONFIG40_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xA4 "CFG0_PADCONFIG41_PROXY,"
bitfld.long 0xA4 31. "PADCONFIG41_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xA4 21. "PADCONFIG41_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xA4 19.--20. "PADCONFIG41_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xA4 18. "PADCONFIG41_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xA4 17. "PADCONFIG41_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xA4 16. "PADCONFIG41_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xA4 14. "PADCONFIG41_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xA4 11.--13. "PADCONFIG41_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xA4 0.--3. 1. "PADCONFIG41_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xA8 "CFG0_PADCONFIG42_PROXY,"
bitfld.long 0xA8 31. "PADCONFIG42_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xA8 21. "PADCONFIG42_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xA8 19.--20. "PADCONFIG42_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xA8 18. "PADCONFIG42_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xA8 17. "PADCONFIG42_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xA8 16. "PADCONFIG42_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xA8 14. "PADCONFIG42_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xA8 11.--13. "PADCONFIG42_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xA8 0.--3. 1. "PADCONFIG42_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xAC "CFG0_PADCONFIG43_PROXY,"
bitfld.long 0xAC 31. "PADCONFIG43_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xAC 21. "PADCONFIG43_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xAC 19.--20. "PADCONFIG43_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xAC 18. "PADCONFIG43_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xAC 17. "PADCONFIG43_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xAC 16. "PADCONFIG43_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0xAC 14. "PADCONFIG43_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xAC 11.--13. "PADCONFIG43_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xAC 0.--3. 1. "PADCONFIG43_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xB0 "CFG0_PADCONFIG44_PROXY,"
bitfld.long 0xB0 31. "PADCONFIG44_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xB0 21. "PADCONFIG44_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xB0 19.--20. "PADCONFIG44_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xB0 18. "PADCONFIG44_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xB0 17. "PADCONFIG44_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xB0 16. "PADCONFIG44_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0xB0 14. "PADCONFIG44_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xB0 11.--13. "PADCONFIG44_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xB0 0.--3. 1. "PADCONFIG44_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xB4 "CFG0_PADCONFIG45_PROXY,"
bitfld.long 0xB4 31. "PADCONFIG45_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xB4 21. "PADCONFIG45_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xB4 19.--20. "PADCONFIG45_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xB4 18. "PADCONFIG45_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xB4 17. "PADCONFIG45_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xB4 16. "PADCONFIG45_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xB4 14. "PADCONFIG45_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xB4 11.--13. "PADCONFIG45_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xB4 0.--3. 1. "PADCONFIG45_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xB8 "CFG0_PADCONFIG46_PROXY,"
bitfld.long 0xB8 31. "PADCONFIG46_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xB8 21. "PADCONFIG46_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xB8 19.--20. "PADCONFIG46_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xB8 18. "PADCONFIG46_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xB8 17. "PADCONFIG46_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xB8 16. "PADCONFIG46_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xB8 14. "PADCONFIG46_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xB8 11.--13. "PADCONFIG46_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xB8 0.--3. 1. "PADCONFIG46_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xBC "CFG0_PADCONFIG47_PROXY,"
bitfld.long 0xBC 31. "PADCONFIG47_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xBC 21. "PADCONFIG47_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xBC 19.--20. "PADCONFIG47_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xBC 18. "PADCONFIG47_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xBC 17. "PADCONFIG47_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xBC 16. "PADCONFIG47_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xBC 14. "PADCONFIG47_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xBC 11.--13. "PADCONFIG47_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xBC 0.--3. 1. "PADCONFIG47_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xC0 "CFG0_PADCONFIG48_PROXY,"
bitfld.long 0xC0 31. "PADCONFIG48_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xC0 21. "PADCONFIG48_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xC0 19.--20. "PADCONFIG48_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xC0 18. "PADCONFIG48_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xC0 17. "PADCONFIG48_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xC0 16. "PADCONFIG48_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xC0 14. "PADCONFIG48_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xC0 11.--13. "PADCONFIG48_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC0 0.--3. 1. "PADCONFIG48_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xC4 "CFG0_PADCONFIG49_PROXY,"
bitfld.long 0xC4 31. "PADCONFIG49_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xC4 21. "PADCONFIG49_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xC4 19.--20. "PADCONFIG49_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xC4 18. "PADCONFIG49_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xC4 17. "PADCONFIG49_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xC4 16. "PADCONFIG49_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xC4 14. "PADCONFIG49_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xC4 11.--13. "PADCONFIG49_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC4 0.--3. 1. "PADCONFIG49_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xC8 "CFG0_PADCONFIG50_PROXY,"
bitfld.long 0xC8 31. "PADCONFIG50_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xC8 21. "PADCONFIG50_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xC8 19.--20. "PADCONFIG50_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xC8 18. "PADCONFIG50_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xC8 17. "PADCONFIG50_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xC8 16. "PADCONFIG50_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xC8 14. "PADCONFIG50_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xC8 11.--13. "PADCONFIG50_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC8 0.--3. 1. "PADCONFIG50_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xCC "CFG0_PADCONFIG51_PROXY,"
bitfld.long 0xCC 31. "PADCONFIG51_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xCC 21. "PADCONFIG51_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xCC 19.--20. "PADCONFIG51_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xCC 18. "PADCONFIG51_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xCC 17. "PADCONFIG51_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xCC 16. "PADCONFIG51_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xCC 14. "PADCONFIG51_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xCC 11.--13. "PADCONFIG51_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xCC 0.--3. 1. "PADCONFIG51_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xD0 "CFG0_PADCONFIG52_PROXY,"
bitfld.long 0xD0 31. "PADCONFIG52_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xD0 21. "PADCONFIG52_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xD0 19.--20. "PADCONFIG52_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xD0 18. "PADCONFIG52_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xD0 17. "PADCONFIG52_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xD0 16. "PADCONFIG52_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xD0 14. "PADCONFIG52_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xD0 11.--13. "PADCONFIG52_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xD0 0.--3. 1. "PADCONFIG52_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xD4 "CFG0_PADCONFIG53_PROXY,"
bitfld.long 0xD4 31. "PADCONFIG53_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xD4 21. "PADCONFIG53_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xD4 19.--20. "PADCONFIG53_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xD4 18. "PADCONFIG53_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xD4 17. "PADCONFIG53_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xD4 16. "PADCONFIG53_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xD4 14. "PADCONFIG53_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xD4 11.--13. "PADCONFIG53_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xD4 0.--3. 1. "PADCONFIG53_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xD8 "CFG0_PADCONFIG54_PROXY,"
bitfld.long 0xD8 31. "PADCONFIG54_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xD8 21. "PADCONFIG54_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xD8 19.--20. "PADCONFIG54_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xD8 18. "PADCONFIG54_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xD8 17. "PADCONFIG54_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xD8 16. "PADCONFIG54_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xD8 14. "PADCONFIG54_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xD8 11.--13. "PADCONFIG54_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xD8 0.--3. 1. "PADCONFIG54_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xDC "CFG0_PADCONFIG55_PROXY,"
bitfld.long 0xDC 31. "PADCONFIG55_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xDC 21. "PADCONFIG55_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xDC 19.--20. "PADCONFIG55_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xDC 18. "PADCONFIG55_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xDC 17. "PADCONFIG55_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xDC 16. "PADCONFIG55_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xDC 14. "PADCONFIG55_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xDC 11.--13. "PADCONFIG55_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xDC 0.--3. 1. "PADCONFIG55_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xE0 "CFG0_PADCONFIG56_PROXY,"
bitfld.long 0xE0 31. "PADCONFIG56_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xE0 21. "PADCONFIG56_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xE0 19.--20. "PADCONFIG56_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xE0 18. "PADCONFIG56_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xE0 17. "PADCONFIG56_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xE0 16. "PADCONFIG56_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xE0 14. "PADCONFIG56_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xE0 11.--13. "PADCONFIG56_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xE0 0.--3. 1. "PADCONFIG56_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xE4 "CFG0_PADCONFIG57_PROXY,"
bitfld.long 0xE4 31. "PADCONFIG57_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xE4 21. "PADCONFIG57_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xE4 19.--20. "PADCONFIG57_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xE4 18. "PADCONFIG57_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xE4 17. "PADCONFIG57_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xE4 16. "PADCONFIG57_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xE4 14. "PADCONFIG57_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xE4 11.--13. "PADCONFIG57_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xE4 0.--3. 1. "PADCONFIG57_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xE8 "CFG0_PADCONFIG58_PROXY,"
bitfld.long 0xE8 31. "PADCONFIG58_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xE8 21. "PADCONFIG58_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xE8 19.--20. "PADCONFIG58_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xE8 18. "PADCONFIG58_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xE8 17. "PADCONFIG58_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xE8 16. "PADCONFIG58_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xE8 14. "PADCONFIG58_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xE8 11.--13. "PADCONFIG58_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xE8 0.--3. 1. "PADCONFIG58_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xEC "CFG0_PADCONFIG59_PROXY,"
bitfld.long 0xEC 31. "PADCONFIG59_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xEC 21. "PADCONFIG59_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xEC 19.--20. "PADCONFIG59_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xEC 18. "PADCONFIG59_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xEC 17. "PADCONFIG59_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xEC 16. "PADCONFIG59_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xEC 14. "PADCONFIG59_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xEC 11.--13. "PADCONFIG59_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xEC 0.--3. 1. "PADCONFIG59_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xF0 "CFG0_PADCONFIG60_PROXY,"
bitfld.long 0xF0 31. "PADCONFIG60_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xF0 21. "PADCONFIG60_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xF0 19.--20. "PADCONFIG60_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xF0 18. "PADCONFIG60_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xF0 17. "PADCONFIG60_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xF0 16. "PADCONFIG60_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xF0 14. "PADCONFIG60_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xF0 11.--13. "PADCONFIG60_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xF0 0.--3. 1. "PADCONFIG60_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xF4 "CFG0_PADCONFIG61_PROXY,"
bitfld.long 0xF4 31. "PADCONFIG61_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xF4 21. "PADCONFIG61_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xF4 19.--20. "PADCONFIG61_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xF4 18. "PADCONFIG61_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xF4 17. "PADCONFIG61_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xF4 16. "PADCONFIG61_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xF4 14. "PADCONFIG61_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xF4 11.--13. "PADCONFIG61_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xF4 0.--3. 1. "PADCONFIG61_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xF8 "CFG0_PADCONFIG62_PROXY,"
bitfld.long 0xF8 31. "PADCONFIG62_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xF8 21. "PADCONFIG62_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xF8 19.--20. "PADCONFIG62_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xF8 18. "PADCONFIG62_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xF8 17. "PADCONFIG62_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xF8 16. "PADCONFIG62_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xF8 14. "PADCONFIG62_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xF8 11.--13. "PADCONFIG62_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xF8 0.--3. 1. "PADCONFIG62_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0xFC "CFG0_PADCONFIG63_PROXY,"
bitfld.long 0xFC 31. "PADCONFIG63_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0xFC 21. "PADCONFIG63_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0xFC 19.--20. "PADCONFIG63_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0xFC 18. "PADCONFIG63_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0xFC 17. "PADCONFIG63_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0xFC 16. "PADCONFIG63_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0xFC 14. "PADCONFIG63_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0xFC 11.--13. "PADCONFIG63_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xFC 0.--3. 1. "PADCONFIG63_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x100 "CFG0_PADCONFIG64_PROXY,"
bitfld.long 0x100 31. "PADCONFIG64_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x100 21. "PADCONFIG64_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x100 19.--20. "PADCONFIG64_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x100 18. "PADCONFIG64_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x100 17. "PADCONFIG64_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x100 16. "PADCONFIG64_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x100 14. "PADCONFIG64_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x100 11.--13. "PADCONFIG64_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x100 0.--3. 1. "PADCONFIG64_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x104 "CFG0_PADCONFIG65_PROXY,"
bitfld.long 0x104 31. "PADCONFIG65_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x104 21. "PADCONFIG65_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x104 19.--20. "PADCONFIG65_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x104 18. "PADCONFIG65_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x104 17. "PADCONFIG65_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x104 16. "PADCONFIG65_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x104 14. "PADCONFIG65_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x104 11.--13. "PADCONFIG65_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x104 0.--3. 1. "PADCONFIG65_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x108 "CFG0_PADCONFIG66_PROXY,"
bitfld.long 0x108 31. "PADCONFIG66_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x108 21. "PADCONFIG66_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x108 19.--20. "PADCONFIG66_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x108 18. "PADCONFIG66_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x108 17. "PADCONFIG66_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x108 16. "PADCONFIG66_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x108 14. "PADCONFIG66_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x108 11.--13. "PADCONFIG66_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x108 0.--3. 1. "PADCONFIG66_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x10C "CFG0_PADCONFIG67_PROXY,"
bitfld.long 0x10C 31. "PADCONFIG67_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x10C 21. "PADCONFIG67_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x10C 19.--20. "PADCONFIG67_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x10C 18. "PADCONFIG67_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x10C 17. "PADCONFIG67_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x10C 16. "PADCONFIG67_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x10C 14. "PADCONFIG67_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x10C 11.--13. "PADCONFIG67_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10C 0.--3. 1. "PADCONFIG67_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x110 "CFG0_PADCONFIG68_PROXY,"
bitfld.long 0x110 31. "PADCONFIG68_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x110 21. "PADCONFIG68_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x110 19.--20. "PADCONFIG68_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x110 18. "PADCONFIG68_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x110 17. "PADCONFIG68_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x110 16. "PADCONFIG68_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x110 14. "PADCONFIG68_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x110 11.--13. "PADCONFIG68_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x110 0.--3. 1. "PADCONFIG68_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x114 "CFG0_PADCONFIG69_PROXY,"
bitfld.long 0x114 31. "PADCONFIG69_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x114 21. "PADCONFIG69_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x114 19.--20. "PADCONFIG69_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x114 18. "PADCONFIG69_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x114 17. "PADCONFIG69_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x114 16. "PADCONFIG69_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x114 14. "PADCONFIG69_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x114 11.--13. "PADCONFIG69_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x114 0.--3. 1. "PADCONFIG69_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x118 "CFG0_PADCONFIG70_PROXY,"
bitfld.long 0x118 31. "PADCONFIG70_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x118 21. "PADCONFIG70_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x118 19.--20. "PADCONFIG70_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x118 18. "PADCONFIG70_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x118 17. "PADCONFIG70_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x118 16. "PADCONFIG70_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x118 14. "PADCONFIG70_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x118 11.--13. "PADCONFIG70_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x118 0.--3. 1. "PADCONFIG70_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x11C "CFG0_PADCONFIG71_PROXY,"
bitfld.long 0x11C 31. "PADCONFIG71_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x11C 21. "PADCONFIG71_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x11C 19.--20. "PADCONFIG71_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x11C 18. "PADCONFIG71_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x11C 17. "PADCONFIG71_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x11C 16. "PADCONFIG71_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x11C 14. "PADCONFIG71_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x11C 11.--13. "PADCONFIG71_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x11C 0.--3. 1. "PADCONFIG71_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x120 "CFG0_PADCONFIG72_PROXY,"
bitfld.long 0x120 31. "PADCONFIG72_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x120 21. "PADCONFIG72_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x120 19.--20. "PADCONFIG72_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x120 18. "PADCONFIG72_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x120 17. "PADCONFIG72_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x120 16. "PADCONFIG72_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x120 14. "PADCONFIG72_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x120 11.--13. "PADCONFIG72_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x120 0.--3. 1. "PADCONFIG72_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x124 "CFG0_PADCONFIG73_PROXY,"
bitfld.long 0x124 31. "PADCONFIG73_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x124 21. "PADCONFIG73_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x124 19.--20. "PADCONFIG73_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x124 18. "PADCONFIG73_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x124 17. "PADCONFIG73_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x124 16. "PADCONFIG73_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x124 14. "PADCONFIG73_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x124 11.--13. "PADCONFIG73_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x124 0.--3. 1. "PADCONFIG73_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x128 "CFG0_PADCONFIG74_PROXY,"
bitfld.long 0x128 31. "PADCONFIG74_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x128 21. "PADCONFIG74_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x128 19.--20. "PADCONFIG74_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x128 18. "PADCONFIG74_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x128 17. "PADCONFIG74_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x128 16. "PADCONFIG74_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x128 14. "PADCONFIG74_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x128 11.--13. "PADCONFIG74_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x128 0.--3. 1. "PADCONFIG74_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x12C "CFG0_PADCONFIG75_PROXY,"
bitfld.long 0x12C 31. "PADCONFIG75_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x12C 21. "PADCONFIG75_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x12C 19.--20. "PADCONFIG75_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x12C 18. "PADCONFIG75_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x12C 17. "PADCONFIG75_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x12C 16. "PADCONFIG75_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x12C 14. "PADCONFIG75_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x12C 11.--13. "PADCONFIG75_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x12C 0.--3. 1. "PADCONFIG75_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x130 "CFG0_PADCONFIG76_PROXY,"
bitfld.long 0x130 31. "PADCONFIG76_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x130 21. "PADCONFIG76_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x130 19.--20. "PADCONFIG76_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x130 18. "PADCONFIG76_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x130 17. "PADCONFIG76_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x130 16. "PADCONFIG76_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x130 14. "PADCONFIG76_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x130 11.--13. "PADCONFIG76_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x130 0.--3. 1. "PADCONFIG76_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x134 "CFG0_PADCONFIG77_PROXY,"
bitfld.long 0x134 31. "PADCONFIG77_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x134 21. "PADCONFIG77_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x134 19.--20. "PADCONFIG77_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x134 18. "PADCONFIG77_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x134 17. "PADCONFIG77_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x134 16. "PADCONFIG77_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x134 14. "PADCONFIG77_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x134 11.--13. "PADCONFIG77_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x134 0.--3. 1. "PADCONFIG77_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x138 "CFG0_PADCONFIG78_PROXY,"
bitfld.long 0x138 31. "PADCONFIG78_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x138 21. "PADCONFIG78_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x138 19.--20. "PADCONFIG78_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x138 18. "PADCONFIG78_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x138 17. "PADCONFIG78_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x138 16. "PADCONFIG78_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x138 14. "PADCONFIG78_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x138 11.--13. "PADCONFIG78_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x138 0.--3. 1. "PADCONFIG78_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x13C "CFG0_PADCONFIG79_PROXY,"
bitfld.long 0x13C 31. "PADCONFIG79_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x13C 21. "PADCONFIG79_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x13C 19.--20. "PADCONFIG79_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x13C 18. "PADCONFIG79_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x13C 17. "PADCONFIG79_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x13C 16. "PADCONFIG79_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x13C 14. "PADCONFIG79_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x13C 11.--13. "PADCONFIG79_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x13C 0.--3. 1. "PADCONFIG79_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x140 "CFG0_PADCONFIG80_PROXY,"
bitfld.long 0x140 31. "PADCONFIG80_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x140 21. "PADCONFIG80_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x140 19.--20. "PADCONFIG80_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x140 18. "PADCONFIG80_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x140 17. "PADCONFIG80_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x140 16. "PADCONFIG80_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x140 14. "PADCONFIG80_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x140 11.--13. "PADCONFIG80_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x140 0.--3. 1. "PADCONFIG80_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x144 "CFG0_PADCONFIG81_PROXY,"
bitfld.long 0x144 31. "PADCONFIG81_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x144 21. "PADCONFIG81_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x144 19.--20. "PADCONFIG81_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x144 18. "PADCONFIG81_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x144 17. "PADCONFIG81_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x144 16. "PADCONFIG81_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x144 14. "PADCONFIG81_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x144 11.--13. "PADCONFIG81_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x144 0.--3. 1. "PADCONFIG81_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x148 "CFG0_PADCONFIG82_PROXY,"
bitfld.long 0x148 31. "PADCONFIG82_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x148 21. "PADCONFIG82_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x148 19.--20. "PADCONFIG82_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x148 18. "PADCONFIG82_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x148 17. "PADCONFIG82_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x148 16. "PADCONFIG82_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x148 14. "PADCONFIG82_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x148 11.--13. "PADCONFIG82_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x148 0.--3. 1. "PADCONFIG82_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x14C "CFG0_PADCONFIG83_PROXY,"
bitfld.long 0x14C 31. "PADCONFIG83_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x14C 21. "PADCONFIG83_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x14C 19.--20. "PADCONFIG83_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x14C 18. "PADCONFIG83_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x14C 17. "PADCONFIG83_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x14C 16. "PADCONFIG83_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x14C 14. "PADCONFIG83_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x14C 11.--13. "PADCONFIG83_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14C 0.--3. 1. "PADCONFIG83_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x150 "CFG0_PADCONFIG84_PROXY,"
bitfld.long 0x150 31. "PADCONFIG84_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x150 21. "PADCONFIG84_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x150 19.--20. "PADCONFIG84_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x150 18. "PADCONFIG84_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x150 17. "PADCONFIG84_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x150 16. "PADCONFIG84_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x150 14. "PADCONFIG84_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x150 11.--13. "PADCONFIG84_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x150 0.--3. 1. "PADCONFIG84_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x154 "CFG0_PADCONFIG85_PROXY,"
bitfld.long 0x154 31. "PADCONFIG85_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x154 21. "PADCONFIG85_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x154 19.--20. "PADCONFIG85_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x154 18. "PADCONFIG85_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x154 17. "PADCONFIG85_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x154 16. "PADCONFIG85_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x154 14. "PADCONFIG85_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x154 11.--13. "PADCONFIG85_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x154 0.--3. 1. "PADCONFIG85_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x158 "CFG0_PADCONFIG86_PROXY,"
bitfld.long 0x158 31. "PADCONFIG86_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x158 21. "PADCONFIG86_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x158 19.--20. "PADCONFIG86_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x158 18. "PADCONFIG86_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x158 17. "PADCONFIG86_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x158 16. "PADCONFIG86_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x158 14. "PADCONFIG86_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x158 11.--13. "PADCONFIG86_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x158 0.--3. 1. "PADCONFIG86_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x15C "CFG0_PADCONFIG87_PROXY,"
bitfld.long 0x15C 31. "PADCONFIG87_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x15C 21. "PADCONFIG87_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x15C 19.--20. "PADCONFIG87_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x15C 18. "PADCONFIG87_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x15C 17. "PADCONFIG87_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x15C 16. "PADCONFIG87_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x15C 14. "PADCONFIG87_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x15C 11.--13. "PADCONFIG87_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x15C 0.--3. 1. "PADCONFIG87_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x160 "CFG0_PADCONFIG88_PROXY,"
bitfld.long 0x160 31. "PADCONFIG88_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x160 21. "PADCONFIG88_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x160 19.--20. "PADCONFIG88_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x160 18. "PADCONFIG88_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x160 17. "PADCONFIG88_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x160 16. "PADCONFIG88_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x160 14. "PADCONFIG88_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x160 11.--13. "PADCONFIG88_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x160 0.--3. 1. "PADCONFIG88_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x164 "CFG0_PADCONFIG89_PROXY,"
bitfld.long 0x164 31. "PADCONFIG89_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x164 21. "PADCONFIG89_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x164 19.--20. "PADCONFIG89_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x164 18. "PADCONFIG89_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x164 17. "PADCONFIG89_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x164 16. "PADCONFIG89_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x164 14. "PADCONFIG89_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x164 11.--13. "PADCONFIG89_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x164 0.--3. 1. "PADCONFIG89_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x168 "CFG0_PADCONFIG90_PROXY,"
bitfld.long 0x168 31. "PADCONFIG90_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x168 21. "PADCONFIG90_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x168 19.--20. "PADCONFIG90_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x168 18. "PADCONFIG90_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x168 17. "PADCONFIG90_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x168 16. "PADCONFIG90_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x168 14. "PADCONFIG90_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x168 11.--13. "PADCONFIG90_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x168 0.--3. 1. "PADCONFIG90_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x16C "CFG0_PADCONFIG91_PROXY,"
bitfld.long 0x16C 31. "PADCONFIG91_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x16C 21. "PADCONFIG91_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x16C 19.--20. "PADCONFIG91_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x16C 18. "PADCONFIG91_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x16C 17. "PADCONFIG91_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x16C 16. "PADCONFIG91_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x16C 14. "PADCONFIG91_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x16C 11.--13. "PADCONFIG91_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x16C 0.--3. 1. "PADCONFIG91_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x170 "CFG0_PADCONFIG92_PROXY,"
bitfld.long 0x170 31. "PADCONFIG92_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x170 21. "PADCONFIG92_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x170 19.--20. "PADCONFIG92_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x170 18. "PADCONFIG92_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x170 17. "PADCONFIG92_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x170 16. "PADCONFIG92_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x170 14. "PADCONFIG92_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x170 11.--13. "PADCONFIG92_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x170 0.--3. 1. "PADCONFIG92_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x174 "CFG0_PADCONFIG93_PROXY,"
bitfld.long 0x174 31. "PADCONFIG93_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x174 21. "PADCONFIG93_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x174 19.--20. "PADCONFIG93_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x174 18. "PADCONFIG93_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x174 17. "PADCONFIG93_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x174 16. "PADCONFIG93_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x174 14. "PADCONFIG93_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x174 11.--13. "PADCONFIG93_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x174 0.--3. 1. "PADCONFIG93_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x178 "CFG0_PADCONFIG94_PROXY,"
bitfld.long 0x178 31. "PADCONFIG94_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x178 21. "PADCONFIG94_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x178 19.--20. "PADCONFIG94_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x178 18. "PADCONFIG94_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x178 17. "PADCONFIG94_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x178 16. "PADCONFIG94_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x178 14. "PADCONFIG94_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x178 11.--13. "PADCONFIG94_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x178 0.--3. 1. "PADCONFIG94_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x17C "CFG0_PADCONFIG95_PROXY,"
bitfld.long 0x17C 31. "PADCONFIG95_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x17C 21. "PADCONFIG95_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x17C 19.--20. "PADCONFIG95_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x17C 18. "PADCONFIG95_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x17C 17. "PADCONFIG95_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x17C 16. "PADCONFIG95_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x17C 14. "PADCONFIG95_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x17C 11.--13. "PADCONFIG95_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x17C 0.--3. 1. "PADCONFIG95_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x180 "CFG0_PADCONFIG96_PROXY,"
bitfld.long 0x180 31. "PADCONFIG96_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x180 21. "PADCONFIG96_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x180 19.--20. "PADCONFIG96_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x180 18. "PADCONFIG96_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x180 17. "PADCONFIG96_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x180 16. "PADCONFIG96_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x180 14. "PADCONFIG96_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x180 11.--13. "PADCONFIG96_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x180 0.--3. 1. "PADCONFIG96_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x184 "CFG0_PADCONFIG97_PROXY,"
bitfld.long 0x184 31. "PADCONFIG97_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x184 21. "PADCONFIG97_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x184 19.--20. "PADCONFIG97_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x184 18. "PADCONFIG97_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x184 17. "PADCONFIG97_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x184 16. "PADCONFIG97_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x184 14. "PADCONFIG97_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x184 11.--13. "PADCONFIG97_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x184 0.--3. 1. "PADCONFIG97_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x188 "CFG0_PADCONFIG98_PROXY,"
bitfld.long 0x188 31. "PADCONFIG98_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x188 21. "PADCONFIG98_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x188 19.--20. "PADCONFIG98_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x188 18. "PADCONFIG98_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x188 17. "PADCONFIG98_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x188 16. "PADCONFIG98_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x188 14. "PADCONFIG98_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x188 11.--13. "PADCONFIG98_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x188 0.--3. 1. "PADCONFIG98_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x18C "CFG0_PADCONFIG99_PROXY,"
bitfld.long 0x18C 31. "PADCONFIG99_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x18C 21. "PADCONFIG99_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x18C 19.--20. "PADCONFIG99_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x18C 18. "PADCONFIG99_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x18C 17. "PADCONFIG99_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x18C 16. "PADCONFIG99_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x18C 14. "PADCONFIG99_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x18C 11.--13. "PADCONFIG99_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x18C 0.--3. 1. "PADCONFIG99_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.."
line.long 0x190 "CFG0_PADCONFIG100_PROXY,"
bitfld.long 0x190 31. "PADCONFIG100_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x190 21. "PADCONFIG100_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x190 19.--20. "PADCONFIG100_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x190 18. "PADCONFIG100_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x190 17. "PADCONFIG100_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x190 16. "PADCONFIG100_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x190 14. "PADCONFIG100_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x190 11.--13. "PADCONFIG100_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x190 0.--3. 1. "PADCONFIG100_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x194 "CFG0_PADCONFIG101_PROXY,"
bitfld.long 0x194 31. "PADCONFIG101_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x194 21. "PADCONFIG101_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x194 19.--20. "PADCONFIG101_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x194 18. "PADCONFIG101_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x194 17. "PADCONFIG101_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x194 16. "PADCONFIG101_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x194 14. "PADCONFIG101_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x194 11.--13. "PADCONFIG101_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x194 0.--3. 1. "PADCONFIG101_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x198 "CFG0_PADCONFIG102_PROXY,"
bitfld.long 0x198 31. "PADCONFIG102_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x198 21. "PADCONFIG102_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x198 19.--20. "PADCONFIG102_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x198 18. "PADCONFIG102_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x198 17. "PADCONFIG102_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x198 16. "PADCONFIG102_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x198 14. "PADCONFIG102_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x198 11.--13. "PADCONFIG102_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x198 0.--3. 1. "PADCONFIG102_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x19C "CFG0_PADCONFIG103_PROXY,"
bitfld.long 0x19C 31. "PADCONFIG103_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x19C 21. "PADCONFIG103_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x19C 19.--20. "PADCONFIG103_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x19C 18. "PADCONFIG103_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x19C 17. "PADCONFIG103_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x19C 16. "PADCONFIG103_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x19C 14. "PADCONFIG103_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x19C 11.--13. "PADCONFIG103_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x19C 0.--3. 1. "PADCONFIG103_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1A0 "CFG0_PADCONFIG104_PROXY,"
bitfld.long 0x1A0 31. "PADCONFIG104_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1A0 21. "PADCONFIG104_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1A0 19.--20. "PADCONFIG104_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1A0 18. "PADCONFIG104_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1A0 17. "PADCONFIG104_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1A0 16. "PADCONFIG104_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1A0 14. "PADCONFIG104_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1A0 11.--13. "PADCONFIG104_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1A0 0.--3. 1. "PADCONFIG104_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1A4 "CFG0_PADCONFIG105_PROXY,"
bitfld.long 0x1A4 31. "PADCONFIG105_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1A4 21. "PADCONFIG105_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1A4 19.--20. "PADCONFIG105_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1A4 18. "PADCONFIG105_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1A4 17. "PADCONFIG105_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1A4 16. "PADCONFIG105_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1A4 14. "PADCONFIG105_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1A4 11.--13. "PADCONFIG105_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1A4 0.--3. 1. "PADCONFIG105_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1A8 "CFG0_PADCONFIG106_PROXY,"
bitfld.long 0x1A8 31. "PADCONFIG106_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1A8 21. "PADCONFIG106_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1A8 19.--20. "PADCONFIG106_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1A8 18. "PADCONFIG106_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1A8 17. "PADCONFIG106_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1A8 16. "PADCONFIG106_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1A8 14. "PADCONFIG106_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1A8 11.--13. "PADCONFIG106_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1A8 0.--3. 1. "PADCONFIG106_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1AC "CFG0_PADCONFIG107_PROXY,"
bitfld.long 0x1AC 31. "PADCONFIG107_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1AC 21. "PADCONFIG107_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1AC 19.--20. "PADCONFIG107_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1AC 18. "PADCONFIG107_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1AC 17. "PADCONFIG107_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1AC 16. "PADCONFIG107_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1AC 14. "PADCONFIG107_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1AC 11.--13. "PADCONFIG107_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1AC 0.--3. 1. "PADCONFIG107_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1B0 "CFG0_PADCONFIG108_PROXY,"
bitfld.long 0x1B0 31. "PADCONFIG108_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1B0 21. "PADCONFIG108_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1B0 19.--20. "PADCONFIG108_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1B0 18. "PADCONFIG108_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1B0 17. "PADCONFIG108_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1B0 16. "PADCONFIG108_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1B0 14. "PADCONFIG108_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1B0 11.--13. "PADCONFIG108_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1B0 0.--3. 1. "PADCONFIG108_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1B4 "CFG0_PADCONFIG109_PROXY,"
bitfld.long 0x1B4 31. "PADCONFIG109_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1B4 21. "PADCONFIG109_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1B4 19.--20. "PADCONFIG109_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1B4 18. "PADCONFIG109_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1B4 17. "PADCONFIG109_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1B4 16. "PADCONFIG109_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1B4 14. "PADCONFIG109_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1B4 11.--13. "PADCONFIG109_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1B4 0.--3. 1. "PADCONFIG109_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1B8 "CFG0_PADCONFIG110_PROXY,"
bitfld.long 0x1B8 31. "PADCONFIG110_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1B8 21. "PADCONFIG110_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1B8 19.--20. "PADCONFIG110_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1B8 18. "PADCONFIG110_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1B8 17. "PADCONFIG110_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1B8 16. "PADCONFIG110_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1B8 14. "PADCONFIG110_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1B8 11.--13. "PADCONFIG110_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1B8 0.--3. 1. "PADCONFIG110_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1BC "CFG0_PADCONFIG111_PROXY,"
bitfld.long 0x1BC 31. "PADCONFIG111_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1BC 21. "PADCONFIG111_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1BC 19.--20. "PADCONFIG111_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1BC 18. "PADCONFIG111_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1BC 17. "PADCONFIG111_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1BC 16. "PADCONFIG111_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1BC 14. "PADCONFIG111_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1BC 11.--13. "PADCONFIG111_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1BC 0.--3. 1. "PADCONFIG111_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1C0 "CFG0_PADCONFIG112_PROXY,"
bitfld.long 0x1C0 31. "PADCONFIG112_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1C0 21. "PADCONFIG112_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1C0 19.--20. "PADCONFIG112_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1C0 18. "PADCONFIG112_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1C0 17. "PADCONFIG112_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1C0 16. "PADCONFIG112_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1C0 14. "PADCONFIG112_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1C0 11.--13. "PADCONFIG112_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C0 0.--3. 1. "PADCONFIG112_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1C4 "CFG0_PADCONFIG113_PROXY,"
bitfld.long 0x1C4 31. "PADCONFIG113_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1C4 21. "PADCONFIG113_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1C4 19.--20. "PADCONFIG113_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1C4 18. "PADCONFIG113_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1C4 17. "PADCONFIG113_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1C4 16. "PADCONFIG113_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1C4 14. "PADCONFIG113_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1C4 11.--13. "PADCONFIG113_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C4 0.--3. 1. "PADCONFIG113_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1C8 "CFG0_PADCONFIG114_PROXY,"
bitfld.long 0x1C8 31. "PADCONFIG114_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1C8 21. "PADCONFIG114_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1C8 19.--20. "PADCONFIG114_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1C8 18. "PADCONFIG114_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1C8 17. "PADCONFIG114_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1C8 16. "PADCONFIG114_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1C8 14. "PADCONFIG114_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1C8 11.--13. "PADCONFIG114_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C8 0.--3. 1. "PADCONFIG114_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1CC "CFG0_PADCONFIG115_PROXY,"
bitfld.long 0x1CC 31. "PADCONFIG115_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1CC 21. "PADCONFIG115_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1CC 19.--20. "PADCONFIG115_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1CC 18. "PADCONFIG115_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1CC 17. "PADCONFIG115_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1CC 16. "PADCONFIG115_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1CC 14. "PADCONFIG115_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1CC 11.--13. "PADCONFIG115_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1CC 0.--3. 1. "PADCONFIG115_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1D0 "CFG0_PADCONFIG116_PROXY,"
bitfld.long 0x1D0 31. "PADCONFIG116_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1D0 21. "PADCONFIG116_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1D0 19.--20. "PADCONFIG116_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1D0 18. "PADCONFIG116_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1D0 17. "PADCONFIG116_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1D0 16. "PADCONFIG116_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1D0 14. "PADCONFIG116_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1D0 11.--13. "PADCONFIG116_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1D0 0.--3. 1. "PADCONFIG116_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1D4 "CFG0_PADCONFIG117_PROXY,"
bitfld.long 0x1D4 31. "PADCONFIG117_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1D4 21. "PADCONFIG117_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1D4 19.--20. "PADCONFIG117_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1D4 18. "PADCONFIG117_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1D4 17. "PADCONFIG117_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1D4 16. "PADCONFIG117_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1D4 14. "PADCONFIG117_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1D4 11.--13. "PADCONFIG117_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1D4 0.--3. 1. "PADCONFIG117_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1D8 "CFG0_PADCONFIG118_PROXY,"
bitfld.long 0x1D8 31. "PADCONFIG118_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1D8 21. "PADCONFIG118_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1D8 19.--20. "PADCONFIG118_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1D8 18. "PADCONFIG118_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1D8 17. "PADCONFIG118_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1D8 16. "PADCONFIG118_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1D8 14. "PADCONFIG118_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1D8 11.--13. "PADCONFIG118_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1D8 0.--3. 1. "PADCONFIG118_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1DC "CFG0_PADCONFIG119_PROXY,"
bitfld.long 0x1DC 31. "PADCONFIG119_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1DC 21. "PADCONFIG119_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1DC 19.--20. "PADCONFIG119_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1DC 18. "PADCONFIG119_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1DC 17. "PADCONFIG119_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1DC 16. "PADCONFIG119_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1DC 14. "PADCONFIG119_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1DC 11.--13. "PADCONFIG119_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1DC 0.--3. 1. "PADCONFIG119_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1E0 "CFG0_PADCONFIG120_PROXY,"
bitfld.long 0x1E0 31. "PADCONFIG120_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1E0 21. "PADCONFIG120_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1E0 19.--20. "PADCONFIG120_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1E0 18. "PADCONFIG120_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1E0 17. "PADCONFIG120_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1E0 16. "PADCONFIG120_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1E0 14. "PADCONFIG120_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1E0 11.--13. "PADCONFIG120_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1E0 0.--3. 1. "PADCONFIG120_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1E4 "CFG0_PADCONFIG121_PROXY,"
bitfld.long 0x1E4 31. "PADCONFIG121_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1E4 21. "PADCONFIG121_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1E4 19.--20. "PADCONFIG121_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1E4 18. "PADCONFIG121_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1E4 17. "PADCONFIG121_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1E4 16. "PADCONFIG121_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1E4 14. "PADCONFIG121_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1E4 11.--13. "PADCONFIG121_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1E4 0.--3. 1. "PADCONFIG121_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1E8 "CFG0_PADCONFIG122_PROXY,"
bitfld.long 0x1E8 31. "PADCONFIG122_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1E8 21. "PADCONFIG122_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1E8 19.--20. "PADCONFIG122_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1E8 18. "PADCONFIG122_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1E8 17. "PADCONFIG122_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1E8 16. "PADCONFIG122_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1E8 14. "PADCONFIG122_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1E8 11.--13. "PADCONFIG122_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1E8 0.--3. 1. "PADCONFIG122_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1EC "CFG0_PADCONFIG123_PROXY,"
bitfld.long 0x1EC 31. "PADCONFIG123_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1EC 21. "PADCONFIG123_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1EC 19.--20. "PADCONFIG123_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1EC 18. "PADCONFIG123_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1EC 17. "PADCONFIG123_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1EC 16. "PADCONFIG123_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1EC 14. "PADCONFIG123_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1EC 11.--13. "PADCONFIG123_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1EC 0.--3. 1. "PADCONFIG123_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1F0 "CFG0_PADCONFIG124_PROXY,"
bitfld.long 0x1F0 31. "PADCONFIG124_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1F0 21. "PADCONFIG124_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1F0 19.--20. "PADCONFIG124_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1F0 18. "PADCONFIG124_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1F0 17. "PADCONFIG124_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1F0 16. "PADCONFIG124_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1F0 14. "PADCONFIG124_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1F0 11.--13. "PADCONFIG124_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1F0 0.--3. 1. "PADCONFIG124_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1F4 "CFG0_PADCONFIG125_PROXY,"
bitfld.long 0x1F4 31. "PADCONFIG125_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1F4 21. "PADCONFIG125_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1F4 19.--20. "PADCONFIG125_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1F4 18. "PADCONFIG125_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1F4 17. "PADCONFIG125_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1F4 16. "PADCONFIG125_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1F4 14. "PADCONFIG125_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1F4 11.--13. "PADCONFIG125_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1F4 0.--3. 1. "PADCONFIG125_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1F8 "CFG0_PADCONFIG126_PROXY,"
bitfld.long 0x1F8 31. "PADCONFIG126_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1F8 21. "PADCONFIG126_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1F8 19.--20. "PADCONFIG126_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1F8 18. "PADCONFIG126_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1F8 17. "PADCONFIG126_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1F8 16. "PADCONFIG126_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x1F8 14. "PADCONFIG126_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1F8 11.--13. "PADCONFIG126_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1F8 0.--3. 1. "PADCONFIG126_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x1FC "CFG0_PADCONFIG127_PROXY,"
bitfld.long 0x1FC 31. "PADCONFIG127_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x1FC 21. "PADCONFIG127_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x1FC 19.--20. "PADCONFIG127_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x1FC 18. "PADCONFIG127_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x1FC 17. "PADCONFIG127_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x1FC 16. "PADCONFIG127_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x1FC 14. "PADCONFIG127_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x1FC 11.--13. "PADCONFIG127_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1FC 0.--3. 1. "PADCONFIG127_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x200 "CFG0_PADCONFIG128_PROXY,"
bitfld.long 0x200 31. "PADCONFIG128_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x200 21. "PADCONFIG128_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x200 19.--20. "PADCONFIG128_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x200 18. "PADCONFIG128_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x200 17. "PADCONFIG128_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x200 16. "PADCONFIG128_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x200 14. "PADCONFIG128_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x200 11.--13. "PADCONFIG128_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x200 0.--3. 1. "PADCONFIG128_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x204 "CFG0_PADCONFIG129_PROXY,"
bitfld.long 0x204 31. "PADCONFIG129_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x204 21. "PADCONFIG129_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x204 19.--20. "PADCONFIG129_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x204 18. "PADCONFIG129_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x204 17. "PADCONFIG129_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x204 16. "PADCONFIG129_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x204 14. "PADCONFIG129_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x204 11.--13. "PADCONFIG129_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x204 0.--3. 1. "PADCONFIG129_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x208 "CFG0_PADCONFIG130_PROXY,"
bitfld.long 0x208 31. "PADCONFIG130_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x208 21. "PADCONFIG130_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x208 19.--20. "PADCONFIG130_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x208 18. "PADCONFIG130_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x208 17. "PADCONFIG130_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x208 16. "PADCONFIG130_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x208 14. "PADCONFIG130_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x208 11.--13. "PADCONFIG130_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x208 0.--3. 1. "PADCONFIG130_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x20C "CFG0_PADCONFIG131_PROXY,"
bitfld.long 0x20C 31. "PADCONFIG131_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x20C 21. "PADCONFIG131_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x20C 19.--20. "PADCONFIG131_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x20C 18. "PADCONFIG131_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x20C 17. "PADCONFIG131_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x20C 16. "PADCONFIG131_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x20C 14. "PADCONFIG131_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x20C 11.--13. "PADCONFIG131_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20C 0.--3. 1. "PADCONFIG131_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x210 "CFG0_PADCONFIG132_PROXY,"
bitfld.long 0x210 31. "PADCONFIG132_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x210 21. "PADCONFIG132_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x210 19.--20. "PADCONFIG132_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x210 18. "PADCONFIG132_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x210 17. "PADCONFIG132_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x210 16. "PADCONFIG132_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x210 14. "PADCONFIG132_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x210 11.--13. "PADCONFIG132_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x210 0.--3. 1. "PADCONFIG132_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x214 "CFG0_PADCONFIG133_PROXY,"
bitfld.long 0x214 31. "PADCONFIG133_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x214 21. "PADCONFIG133_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x214 19.--20. "PADCONFIG133_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x214 18. "PADCONFIG133_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x214 17. "PADCONFIG133_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x214 16. "PADCONFIG133_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x214 14. "PADCONFIG133_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x214 11.--13. "PADCONFIG133_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x214 0.--3. 1. "PADCONFIG133_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x218 "CFG0_PADCONFIG134_PROXY,"
bitfld.long 0x218 31. "PADCONFIG134_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x218 21. "PADCONFIG134_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x218 19.--20. "PADCONFIG134_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x218 18. "PADCONFIG134_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x218 17. "PADCONFIG134_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x218 16. "PADCONFIG134_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x218 14. "PADCONFIG134_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x218 11.--13. "PADCONFIG134_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x218 0.--3. 1. "PADCONFIG134_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x21C "CFG0_PADCONFIG135_PROXY,"
bitfld.long 0x21C 31. "PADCONFIG135_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x21C 21. "PADCONFIG135_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x21C 19.--20. "PADCONFIG135_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x21C 18. "PADCONFIG135_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x21C 17. "PADCONFIG135_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x21C 16. "PADCONFIG135_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x21C 14. "PADCONFIG135_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x21C 11.--13. "PADCONFIG135_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x21C 0.--3. 1. "PADCONFIG135_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x220 "CFG0_PADCONFIG136_PROXY,"
bitfld.long 0x220 31. "PADCONFIG136_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x220 21. "PADCONFIG136_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x220 19.--20. "PADCONFIG136_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x220 18. "PADCONFIG136_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x220 17. "PADCONFIG136_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x220 16. "PADCONFIG136_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x220 14. "PADCONFIG136_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x220 11.--13. "PADCONFIG136_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x220 0.--3. 1. "PADCONFIG136_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x224 "CFG0_PADCONFIG137_PROXY,"
bitfld.long 0x224 31. "PADCONFIG137_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x224 21. "PADCONFIG137_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x224 19.--20. "PADCONFIG137_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x224 18. "PADCONFIG137_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x224 17. "PADCONFIG137_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x224 16. "PADCONFIG137_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x224 14. "PADCONFIG137_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x224 11.--13. "PADCONFIG137_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x224 0.--3. 1. "PADCONFIG137_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x228 "CFG0_PADCONFIG138_PROXY,"
bitfld.long 0x228 31. "PADCONFIG138_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x228 21. "PADCONFIG138_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x228 19.--20. "PADCONFIG138_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x228 18. "PADCONFIG138_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x228 17. "PADCONFIG138_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x228 16. "PADCONFIG138_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x228 14. "PADCONFIG138_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x228 11.--13. "PADCONFIG138_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x228 0.--3. 1. "PADCONFIG138_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x22C "CFG0_PADCONFIG139_PROXY,"
bitfld.long 0x22C 31. "PADCONFIG139_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x22C 21. "PADCONFIG139_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x22C 19.--20. "PADCONFIG139_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x22C 18. "PADCONFIG139_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x22C 17. "PADCONFIG139_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x22C 16. "PADCONFIG139_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x22C 14. "PADCONFIG139_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x22C 11.--13. "PADCONFIG139_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x22C 0.--3. 1. "PADCONFIG139_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x230 "CFG0_PADCONFIG140_PROXY,"
bitfld.long 0x230 31. "PADCONFIG140_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x230 21. "PADCONFIG140_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x230 19.--20. "PADCONFIG140_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x230 18. "PADCONFIG140_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x230 17. "PADCONFIG140_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x230 16. "PADCONFIG140_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x230 14. "PADCONFIG140_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x230 11.--13. "PADCONFIG140_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x230 0.--3. 1. "PADCONFIG140_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x234 "CFG0_PADCONFIG141_PROXY,"
bitfld.long 0x234 31. "PADCONFIG141_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x234 21. "PADCONFIG141_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x234 19.--20. "PADCONFIG141_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x234 18. "PADCONFIG141_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x234 17. "PADCONFIG141_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x234 16. "PADCONFIG141_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x234 14. "PADCONFIG141_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x234 11.--13. "PADCONFIG141_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x234 0.--3. 1. "PADCONFIG141_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x238 "CFG0_PADCONFIG142_PROXY,"
bitfld.long 0x238 31. "PADCONFIG142_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x238 21. "PADCONFIG142_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x238 19.--20. "PADCONFIG142_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x238 18. "PADCONFIG142_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x238 17. "PADCONFIG142_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x238 16. "PADCONFIG142_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x238 14. "PADCONFIG142_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x238 11.--13. "PADCONFIG142_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x238 0.--3. 1. "PADCONFIG142_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x23C "CFG0_PADCONFIG143_PROXY,"
bitfld.long 0x23C 31. "PADCONFIG143_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x23C 21. "PADCONFIG143_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x23C 19.--20. "PADCONFIG143_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x23C 18. "PADCONFIG143_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x23C 17. "PADCONFIG143_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x23C 16. "PADCONFIG143_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x23C 14. "PADCONFIG143_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x23C 11.--13. "PADCONFIG143_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x23C 0.--3. 1. "PADCONFIG143_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x240 "CFG0_PADCONFIG144_PROXY,"
bitfld.long 0x240 31. "PADCONFIG144_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x240 21. "PADCONFIG144_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x240 19.--20. "PADCONFIG144_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x240 18. "PADCONFIG144_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x240 17. "PADCONFIG144_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x240 16. "PADCONFIG144_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x240 14. "PADCONFIG144_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x240 11.--13. "PADCONFIG144_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x240 0.--3. 1. "PADCONFIG144_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x244 "CFG0_PADCONFIG145_PROXY,"
bitfld.long 0x244 31. "PADCONFIG145_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x244 21. "PADCONFIG145_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x244 19.--20. "PADCONFIG145_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x244 18. "PADCONFIG145_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x244 17. "PADCONFIG145_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x244 16. "PADCONFIG145_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x244 14. "PADCONFIG145_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x244 11.--13. "PADCONFIG145_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x244 0.--3. 1. "PADCONFIG145_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x248 "CFG0_PADCONFIG146_PROXY,"
bitfld.long 0x248 31. "PADCONFIG146_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x248 21. "PADCONFIG146_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x248 19.--20. "PADCONFIG146_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x248 18. "PADCONFIG146_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x248 17. "PADCONFIG146_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x248 16. "PADCONFIG146_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x248 14. "PADCONFIG146_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x248 11.--13. "PADCONFIG146_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x248 0.--3. 1. "PADCONFIG146_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x24C "CFG0_PADCONFIG147_PROXY,"
bitfld.long 0x24C 31. "PADCONFIG147_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x24C 21. "PADCONFIG147_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x24C 19.--20. "PADCONFIG147_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x24C 18. "PADCONFIG147_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x24C 17. "PADCONFIG147_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x24C 16. "PADCONFIG147_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x24C 14. "PADCONFIG147_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x24C 11.--13. "PADCONFIG147_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24C 0.--3. 1. "PADCONFIG147_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x250 "CFG0_PADCONFIG148_PROXY,"
bitfld.long 0x250 31. "PADCONFIG148_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x250 21. "PADCONFIG148_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x250 19.--20. "PADCONFIG148_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x250 18. "PADCONFIG148_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x250 17. "PADCONFIG148_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x250 16. "PADCONFIG148_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x250 14. "PADCONFIG148_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x250 11.--13. "PADCONFIG148_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x250 0.--3. 1. "PADCONFIG148_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x254 "CFG0_PADCONFIG149_PROXY,"
bitfld.long 0x254 31. "PADCONFIG149_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x254 21. "PADCONFIG149_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x254 19.--20. "PADCONFIG149_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x254 18. "PADCONFIG149_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x254 17. "PADCONFIG149_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x254 16. "PADCONFIG149_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x254 14. "PADCONFIG149_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x254 11.--13. "PADCONFIG149_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x254 0.--3. 1. "PADCONFIG149_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x258 "CFG0_PADCONFIG150_PROXY,"
bitfld.long 0x258 31. "PADCONFIG150_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x258 21. "PADCONFIG150_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x258 19.--20. "PADCONFIG150_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x258 18. "PADCONFIG150_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x258 17. "PADCONFIG150_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x258 16. "PADCONFIG150_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x258 14. "PADCONFIG150_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x258 11.--13. "PADCONFIG150_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x258 0.--3. 1. "PADCONFIG150_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x25C "CFG0_PADCONFIG151_PROXY,"
bitfld.long 0x25C 31. "PADCONFIG151_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x25C 21. "PADCONFIG151_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x25C 19.--20. "PADCONFIG151_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x25C 18. "PADCONFIG151_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x25C 17. "PADCONFIG151_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x25C 16. "PADCONFIG151_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x25C 14. "PADCONFIG151_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x25C 11.--13. "PADCONFIG151_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x25C 0.--3. 1. "PADCONFIG151_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x260 "CFG0_PADCONFIG152_PROXY,"
bitfld.long 0x260 31. "PADCONFIG152_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x260 21. "PADCONFIG152_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x260 19.--20. "PADCONFIG152_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x260 18. "PADCONFIG152_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x260 17. "PADCONFIG152_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x260 16. "PADCONFIG152_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x260 14. "PADCONFIG152_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x260 11.--13. "PADCONFIG152_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x260 0.--3. 1. "PADCONFIG152_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x264 "CFG0_PADCONFIG153_PROXY,"
bitfld.long 0x264 31. "PADCONFIG153_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x264 21. "PADCONFIG153_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x264 19.--20. "PADCONFIG153_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x264 18. "PADCONFIG153_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x264 17. "PADCONFIG153_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x264 16. "PADCONFIG153_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x264 14. "PADCONFIG153_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x264 11.--13. "PADCONFIG153_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x264 0.--3. 1. "PADCONFIG153_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x268 "CFG0_PADCONFIG154_PROXY,"
bitfld.long 0x268 31. "PADCONFIG154_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x268 21. "PADCONFIG154_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x268 19.--20. "PADCONFIG154_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x268 18. "PADCONFIG154_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x268 17. "PADCONFIG154_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x268 16. "PADCONFIG154_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x268 14. "PADCONFIG154_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x268 11.--13. "PADCONFIG154_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x268 0.--3. 1. "PADCONFIG154_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x26C "CFG0_PADCONFIG155_PROXY,"
bitfld.long 0x26C 31. "PADCONFIG155_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x26C 21. "PADCONFIG155_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x26C 19.--20. "PADCONFIG155_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x26C 18. "PADCONFIG155_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x26C 17. "PADCONFIG155_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x26C 16. "PADCONFIG155_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x26C 14. "PADCONFIG155_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x26C 11.--13. "PADCONFIG155_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x26C 0.--3. 1. "PADCONFIG155_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x270 "CFG0_PADCONFIG156_PROXY,"
bitfld.long 0x270 31. "PADCONFIG156_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x270 21. "PADCONFIG156_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x270 19.--20. "PADCONFIG156_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x270 18. "PADCONFIG156_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x270 17. "PADCONFIG156_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x270 16. "PADCONFIG156_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x270 14. "PADCONFIG156_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x270 11.--13. "PADCONFIG156_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x270 0.--3. 1. "PADCONFIG156_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x274 "CFG0_PADCONFIG157_PROXY,"
bitfld.long 0x274 31. "PADCONFIG157_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x274 21. "PADCONFIG157_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x274 19.--20. "PADCONFIG157_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x274 18. "PADCONFIG157_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x274 17. "PADCONFIG157_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x274 16. "PADCONFIG157_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x274 14. "PADCONFIG157_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x274 11.--13. "PADCONFIG157_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x274 0.--3. 1. "PADCONFIG157_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x278 "CFG0_PADCONFIG158_PROXY,"
bitfld.long 0x278 31. "PADCONFIG158_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x278 21. "PADCONFIG158_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x278 19.--20. "PADCONFIG158_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x278 18. "PADCONFIG158_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x278 17. "PADCONFIG158_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x278 16. "PADCONFIG158_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x278 14. "PADCONFIG158_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x278 11.--13. "PADCONFIG158_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x278 0.--3. 1. "PADCONFIG158_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x27C "CFG0_PADCONFIG159_PROXY,"
bitfld.long 0x27C 31. "PADCONFIG159_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x27C 21. "PADCONFIG159_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x27C 19.--20. "PADCONFIG159_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x27C 18. "PADCONFIG159_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x27C 17. "PADCONFIG159_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x27C 16. "PADCONFIG159_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x27C 14. "PADCONFIG159_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x27C 11.--13. "PADCONFIG159_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x27C 0.--3. 1. "PADCONFIG159_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x280 "CFG0_PADCONFIG160_PROXY,"
bitfld.long 0x280 31. "PADCONFIG160_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x280 21. "PADCONFIG160_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x280 19.--20. "PADCONFIG160_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x280 18. "PADCONFIG160_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x280 17. "PADCONFIG160_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x280 16. "PADCONFIG160_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x280 14. "PADCONFIG160_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x280 11.--13. "PADCONFIG160_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x280 0.--3. 1. "PADCONFIG160_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x284 "CFG0_PADCONFIG161_PROXY,"
bitfld.long 0x284 31. "PADCONFIG161_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x284 21. "PADCONFIG161_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x284 19.--20. "PADCONFIG161_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x284 18. "PADCONFIG161_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x284 17. "PADCONFIG161_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x284 16. "PADCONFIG161_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x284 14. "PADCONFIG161_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x284 11.--13. "PADCONFIG161_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x284 0.--3. 1. "PADCONFIG161_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x288 "CFG0_PADCONFIG162_PROXY,"
bitfld.long 0x288 31. "PADCONFIG162_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x288 21. "PADCONFIG162_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x288 19.--20. "PADCONFIG162_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x288 18. "PADCONFIG162_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x288 17. "PADCONFIG162_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x288 16. "PADCONFIG162_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x288 14. "PADCONFIG162_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x288 11.--13. "PADCONFIG162_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x288 0.--3. 1. "PADCONFIG162_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x28C "CFG0_PADCONFIG163_PROXY,"
bitfld.long 0x28C 31. "PADCONFIG163_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x28C 21. "PADCONFIG163_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x28C 19.--20. "PADCONFIG163_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x28C 18. "PADCONFIG163_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x28C 17. "PADCONFIG163_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x28C 16. "PADCONFIG163_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x28C 14. "PADCONFIG163_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x28C 11.--13. "PADCONFIG163_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x28C 0.--3. 1. "PADCONFIG163_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x290 "CFG0_PADCONFIG164_PROXY,"
bitfld.long 0x290 31. "PADCONFIG164_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x290 21. "PADCONFIG164_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x290 19.--20. "PADCONFIG164_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x290 18. "PADCONFIG164_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x290 17. "PADCONFIG164_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x290 16. "PADCONFIG164_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x290 14. "PADCONFIG164_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x290 11.--13. "PADCONFIG164_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x290 0.--3. 1. "PADCONFIG164_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x294 "CFG0_PADCONFIG165_PROXY,"
bitfld.long 0x294 31. "PADCONFIG165_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x294 21. "PADCONFIG165_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x294 19.--20. "PADCONFIG165_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x294 18. "PADCONFIG165_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x294 17. "PADCONFIG165_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x294 16. "PADCONFIG165_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x294 14. "PADCONFIG165_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x294 11.--13. "PADCONFIG165_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x294 0.--3. 1. "PADCONFIG165_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x298 "CFG0_PADCONFIG166_PROXY,"
bitfld.long 0x298 31. "PADCONFIG166_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x298 21. "PADCONFIG166_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x298 19.--20. "PADCONFIG166_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x298 18. "PADCONFIG166_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x298 17. "PADCONFIG166_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x298 16. "PADCONFIG166_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x298 14. "PADCONFIG166_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x298 11.--13. "PADCONFIG166_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x298 0.--3. 1. "PADCONFIG166_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x29C "CFG0_PADCONFIG167_PROXY,"
bitfld.long 0x29C 31. "PADCONFIG167_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x29C 21. "PADCONFIG167_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x29C 19.--20. "PADCONFIG167_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x29C 18. "PADCONFIG167_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x29C 17. "PADCONFIG167_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x29C 16. "PADCONFIG167_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x29C 14. "PADCONFIG167_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x29C 11.--13. "PADCONFIG167_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x29C 0.--3. 1. "PADCONFIG167_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2A0 "CFG0_PADCONFIG168_PROXY,"
bitfld.long 0x2A0 31. "PADCONFIG168_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2A0 21. "PADCONFIG168_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2A0 19.--20. "PADCONFIG168_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2A0 18. "PADCONFIG168_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2A0 17. "PADCONFIG168_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2A0 16. "PADCONFIG168_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2A0 14. "PADCONFIG168_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2A0 11.--13. "PADCONFIG168_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2A0 0.--3. 1. "PADCONFIG168_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2A4 "CFG0_PADCONFIG169_PROXY,"
bitfld.long 0x2A4 31. "PADCONFIG169_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2A4 21. "PADCONFIG169_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2A4 19.--20. "PADCONFIG169_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2A4 18. "PADCONFIG169_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2A4 17. "PADCONFIG169_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2A4 16. "PADCONFIG169_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2A4 14. "PADCONFIG169_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2A4 11.--13. "PADCONFIG169_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2A4 0.--3. 1. "PADCONFIG169_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2A8 "CFG0_PADCONFIG170_PROXY,"
bitfld.long 0x2A8 31. "PADCONFIG170_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2A8 21. "PADCONFIG170_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2A8 19.--20. "PADCONFIG170_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2A8 18. "PADCONFIG170_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2A8 17. "PADCONFIG170_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2A8 16. "PADCONFIG170_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2A8 14. "PADCONFIG170_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2A8 11.--13. "PADCONFIG170_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2A8 0.--3. 1. "PADCONFIG170_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2AC "CFG0_PADCONFIG171_PROXY,"
bitfld.long 0x2AC 31. "PADCONFIG171_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2AC 21. "PADCONFIG171_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2AC 19.--20. "PADCONFIG171_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
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bitfld.long 0x2AC 18. "PADCONFIG171_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2AC 17. "PADCONFIG171_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2AC 16. "PADCONFIG171_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2AC 14. "PADCONFIG171_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2AC 11.--13. "PADCONFIG171_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2AC 0.--3. 1. "PADCONFIG171_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2B0 "CFG0_PADCONFIG172_PROXY,"
bitfld.long 0x2B0 31. "PADCONFIG172_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2B0 21. "PADCONFIG172_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2B0 19.--20. "PADCONFIG172_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2B0 18. "PADCONFIG172_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2B0 17. "PADCONFIG172_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2B0 16. "PADCONFIG172_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2B0 14. "PADCONFIG172_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2B0 11.--13. "PADCONFIG172_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2B0 0.--3. 1. "PADCONFIG172_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2B4 "CFG0_PADCONFIG173_PROXY,"
bitfld.long 0x2B4 31. "PADCONFIG173_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2B4 21. "PADCONFIG173_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2B4 19.--20. "PADCONFIG173_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2B4 18. "PADCONFIG173_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2B4 17. "PADCONFIG173_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2B4 16. "PADCONFIG173_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
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bitfld.long 0x2B4 14. "PADCONFIG173_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2B4 11.--13. "PADCONFIG173_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2B4 0.--3. 1. "PADCONFIG173_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2B8 "CFG0_PADCONFIG174_PROXY,"
bitfld.long 0x2B8 31. "PADCONFIG174_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2B8 21. "PADCONFIG174_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2B8 19.--20. "PADCONFIG174_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2B8 18. "PADCONFIG174_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2B8 17. "PADCONFIG174_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2B8 16. "PADCONFIG174_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2B8 14. "PADCONFIG174_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2B8 11.--13. "PADCONFIG174_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2B8 0.--3. 1. "PADCONFIG174_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2BC "CFG0_PADCONFIG175_PROXY,"
bitfld.long 0x2BC 31. "PADCONFIG175_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2BC 21. "PADCONFIG175_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2BC 19.--20. "PADCONFIG175_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2BC 18. "PADCONFIG175_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2BC 17. "PADCONFIG175_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2BC 16. "PADCONFIG175_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2BC 14. "PADCONFIG175_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2BC 11.--13. "PADCONFIG175_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2BC 0.--3. 1. "PADCONFIG175_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2C0 "CFG0_PADCONFIG176_PROXY,"
bitfld.long 0x2C0 31. "PADCONFIG176_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2C0 21. "PADCONFIG176_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2C0 19.--20. "PADCONFIG176_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2C0 18. "PADCONFIG176_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2C0 17. "PADCONFIG176_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2C0 16. "PADCONFIG176_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2C0 14. "PADCONFIG176_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2C0 11.--13. "PADCONFIG176_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C0 0.--3. 1. "PADCONFIG176_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2C4 "CFG0_PADCONFIG177_PROXY,"
bitfld.long 0x2C4 31. "PADCONFIG177_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2C4 21. "PADCONFIG177_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2C4 19.--20. "PADCONFIG177_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2C4 18. "PADCONFIG177_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2C4 17. "PADCONFIG177_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2C4 16. "PADCONFIG177_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2C4 14. "PADCONFIG177_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2C4 11.--13. "PADCONFIG177_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C4 0.--3. 1. "PADCONFIG177_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2C8 "CFG0_PADCONFIG178_PROXY,"
bitfld.long 0x2C8 31. "PADCONFIG178_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2C8 21. "PADCONFIG178_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2C8 19.--20. "PADCONFIG178_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2C8 18. "PADCONFIG178_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2C8 17. "PADCONFIG178_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2C8 16. "PADCONFIG178_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2C8 14. "PADCONFIG178_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2C8 11.--13. "PADCONFIG178_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2C8 0.--3. 1. "PADCONFIG178_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
line.long 0x2CC "CFG0_PADCONFIG179_PROXY,"
bitfld.long 0x2CC 31. "PADCONFIG179_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1"
bitfld.long 0x2CC 21. "PADCONFIG179_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1"
bitfld.long 0x2CC 19.--20. "PADCONFIG179_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3"
newline
bitfld.long 0x2CC 18. "PADCONFIG179_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1"
bitfld.long 0x2CC 17. "PADCONFIG179_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1"
bitfld.long 0x2CC 16. "PADCONFIG179_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1"
newline
bitfld.long 0x2CC 14. "PADCONFIG179_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1"
bitfld.long 0x2CC 11.--13. "PADCONFIG179_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x2CC 0.--3. 1. "PADCONFIG179_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.."
group.long 0x7008++0x7
line.long 0x0 "CFG0_LOCK1_KICK0_PROXY,"
hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component"
line.long 0x4 "CFG0_LOCK1_KICK1_PROXY,"
hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component"
tree.end
tree "PDMA"
base ad:0x0
tree "PDMA0_REGS (PDMA0_REGS)"
base ad:0xC00000
rgroup.long 0x0++0x3
line.long 0x0 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PDMA1_REGS (PDMA1_REGS)"
base ad:0xC01000
rgroup.long 0x0++0x3
line.long 0x0 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "PLL0_CFG (PLL0_CFG)"
base ad:0x680000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_pll0_PID,"
bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier"
hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number"
bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number"
rgroup.long 0x8++0x3
line.long 0x0 "CFG_pll0_CFG,"
hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3"
bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1"
bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3"
group.long 0x10++0x7
line.long 0x0 "CFG_pll0_LOCKKEY0,"
hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set  indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
line.long 0x4 "CFG_pll0_LOCKKEY1,"
hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers"
group.long 0x20++0x3
line.long 0x0 "CFG_pll0_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1"
bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1"
bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1"
bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1"
bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2  FOUT3  FOUT4 clocks are enabled." "0,1"
newline
bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV  4-phase and synchronous clocks are enabled." "0,1"
bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1"
bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "CFG_pll0_STAT,"
bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1"
group.long 0x30++0xB
line.long 0x0 "CFG_pll0_FREQ_CTRL0,"
hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.."
line.long 0x4 "CFG_pll0_FREQ_CTRL1,"
hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.."
line.long 0x8 "CFG_pll0_DIV_CTRL,"
bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation  post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63"
group.long 0x40++0x7
line.long 0x0 "CFG_pll0_SS_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1"
hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0"
bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1"
bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1"
line.long 0x4 "CFG_pll0_SS_SPREAD,"
hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63"
hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%"
group.long 0x60++0x3
line.long 0x0 "CFG_pll0_CAL_CTRL,"
bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1"
bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1"
bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0  this represents the initial condition for calibration. When cal_byp is 1'b1  this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.."
rgroup.long 0x64++0x3
line.long 0x0 "CFG_pll0_CAL_STAT,"
bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use"
hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration"
group.long 0x80++0x27
line.long 0x0 "CFG_pll0_HSDIV_CTRL0,"
bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x4 "CFG_pll0_HSDIV_CTRL1,"
bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x8 "CFG_pll0_HSDIV_CTRL2,"
bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0xC "CFG_pll0_HSDIV_CTRL3,"
bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x10 "CFG_pll0_HSDIV_CTRL4,"
bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x14 "CFG_pll0_HSDIV_CTRL5,"
bitfld.long 0x14 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x18 "CFG_pll0_HSDIV_CTRL6,"
bitfld.long 0x18 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x1C "CFG_pll0_HSDIV_CTRL7,"
bitfld.long 0x1C 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x20 "CFG_pll0_HSDIV_CTRL8,"
bitfld.long 0x20 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x20 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x20 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x20 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x24 "CFG_pll0_HSDIV_CTRL9,"
bitfld.long 0x24 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x24 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x24 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x24 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
rgroup.long 0x1000++0x3
line.long 0x0 "CFG_pll1_PID,"
bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier"
hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number"
bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number"
rgroup.long 0x1008++0x3
line.long 0x0 "CFG_pll1_CFG,"
hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3"
bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1"
bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3"
group.long 0x1010++0x7
line.long 0x0 "CFG_pll1_LOCKKEY0,"
hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set  indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
line.long 0x4 "CFG_pll1_LOCKKEY1,"
hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers"
group.long 0x1020++0x3
line.long 0x0 "CFG_pll1_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1"
bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1"
bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1"
bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1"
bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2  FOUT3  FOUT4 clocks are enabled." "0,1"
newline
bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV  4-phase and synchronous clocks are enabled." "0,1"
bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1"
bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1"
rgroup.long 0x1024++0x3
line.long 0x0 "CFG_pll1_STAT,"
bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1"
group.long 0x1030++0xB
line.long 0x0 "CFG_pll1_FREQ_CTRL0,"
hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.."
line.long 0x4 "CFG_pll1_FREQ_CTRL1,"
hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.."
line.long 0x8 "CFG_pll1_DIV_CTRL,"
bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation  post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63"
group.long 0x1040++0x7
line.long 0x0 "CFG_pll1_SS_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1"
hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0"
bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1"
bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1"
line.long 0x4 "CFG_pll1_SS_SPREAD,"
hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63"
hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%"
group.long 0x1060++0x3
line.long 0x0 "CFG_pll1_CAL_CTRL,"
bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1"
bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1"
bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0  this represents the initial condition for calibration. When cal_byp is 1'b1  this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.."
rgroup.long 0x1064++0x3
line.long 0x0 "CFG_pll1_CAL_STAT,"
bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use"
hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration"
group.long 0x1080++0x1B
line.long 0x0 "CFG_pll1_HSDIV_CTRL0,"
bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x4 "CFG_pll1_HSDIV_CTRL1,"
bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x8 "CFG_pll1_HSDIV_CTRL2,"
bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0xC "CFG_pll1_HSDIV_CTRL3,"
bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x10 "CFG_pll1_HSDIV_CTRL4,"
bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x14 "CFG_pll1_HSDIV_CTRL5,"
bitfld.long 0x14 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x18 "CFG_pll1_HSDIV_CTRL6,"
bitfld.long 0x18 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
rgroup.long 0x2000++0x3
line.long 0x0 "CFG_pll2_PID,"
bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier"
hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number"
bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number"
rgroup.long 0x2008++0x3
line.long 0x0 "CFG_pll2_CFG,"
hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3"
bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1"
bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3"
group.long 0x2010++0x7
line.long 0x0 "CFG_pll2_LOCKKEY0,"
hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set  indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
line.long 0x4 "CFG_pll2_LOCKKEY1,"
hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers"
group.long 0x2020++0x3
line.long 0x0 "CFG_pll2_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1"
bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1"
bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1"
bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1"
bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2  FOUT3  FOUT4 clocks are enabled." "0,1"
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bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV  4-phase and synchronous clocks are enabled." "0,1"
bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1"
bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1"
rgroup.long 0x2024++0x3
line.long 0x0 "CFG_pll2_STAT,"
bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1"
group.long 0x2030++0xB
line.long 0x0 "CFG_pll2_FREQ_CTRL0,"
hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.."
line.long 0x4 "CFG_pll2_FREQ_CTRL1,"
hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.."
line.long 0x8 "CFG_pll2_DIV_CTRL,"
bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation  post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63"
group.long 0x2040++0x7
line.long 0x0 "CFG_pll2_SS_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1"
hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0"
bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1"
bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1"
line.long 0x4 "CFG_pll2_SS_SPREAD,"
hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63"
hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%"
group.long 0x2060++0x3
line.long 0x0 "CFG_pll2_CAL_CTRL,"
bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1"
bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1"
bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0  this represents the initial condition for calibration. When cal_byp is 1'b1  this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.."
rgroup.long 0x2064++0x3
line.long 0x0 "CFG_pll2_CAL_STAT,"
bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use"
hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration"
group.long 0x2080++0x27
line.long 0x0 "CFG_pll2_HSDIV_CTRL0,"
bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x4 "CFG_pll2_HSDIV_CTRL1,"
bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x8 "CFG_pll2_HSDIV_CTRL2,"
bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0xC "CFG_pll2_HSDIV_CTRL3,"
bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x10 "CFG_pll2_HSDIV_CTRL4,"
bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x14 "CFG_pll2_HSDIV_CTRL5,"
bitfld.long 0x14 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x18 "CFG_pll2_HSDIV_CTRL6,"
bitfld.long 0x18 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x1C "CFG_pll2_HSDIV_CTRL7,"
bitfld.long 0x1C 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x20 "CFG_pll2_HSDIV_CTRL8,"
bitfld.long 0x20 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x20 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x20 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x20 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x24 "CFG_pll2_HSDIV_CTRL9,"
bitfld.long 0x24 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x24 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x24 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x24 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
rgroup.long 0x8000++0x3
line.long 0x0 "CFG_pll8_PID,"
bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier"
hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number"
bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number"
rgroup.long 0x8008++0x3
line.long 0x0 "CFG_pll8_CFG,"
hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3"
bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1"
bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3"
group.long 0x8010++0x7
line.long 0x0 "CFG_pll8_LOCKKEY0,"
hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition8 registers"
rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set  indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
line.long 0x4 "CFG_pll8_LOCKKEY1,"
hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition8 registers"
group.long 0x8020++0x3
line.long 0x0 "CFG_pll8_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1"
bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1"
bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1"
bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1"
bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2  FOUT3  FOUT4 clocks are enabled." "0,1"
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bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV  4-phase and synchronous clocks are enabled." "0,1"
bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1"
bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1"
rgroup.long 0x8024++0x3
line.long 0x0 "CFG_pll8_STAT,"
bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1"
group.long 0x8030++0xB
line.long 0x0 "CFG_pll8_FREQ_CTRL0,"
hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.."
line.long 0x4 "CFG_pll8_FREQ_CTRL1,"
hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.."
line.long 0x8 "CFG_pll8_DIV_CTRL,"
bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation  post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63"
group.long 0x8040++0x7
line.long 0x0 "CFG_pll8_SS_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1"
hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0"
bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1"
bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1"
line.long 0x4 "CFG_pll8_SS_SPREAD,"
hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63"
hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%"
group.long 0x8060++0x3
line.long 0x0 "CFG_pll8_CAL_CTRL,"
bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1"
bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1"
bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0  this represents the initial condition for calibration. When cal_byp is 1'b1  this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.."
rgroup.long 0x8064++0x3
line.long 0x0 "CFG_pll8_CAL_STAT,"
bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use"
hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration"
group.long 0x8080++0x3
line.long 0x0 "CFG_pll8_HSDIV_CTRL0,"
bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
rgroup.long 0xC000++0x3
line.long 0x0 "CFG_pll12_PID,"
bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier"
hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number"
bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number"
rgroup.long 0xC008++0x3
line.long 0x0 "CFG_pll12_CFG,"
hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3"
bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1"
bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3"
group.long 0xC010++0x7
line.long 0x0 "CFG_pll12_LOCKKEY0,"
hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition12 registers"
rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set  indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
line.long 0x4 "CFG_pll12_LOCKKEY1,"
hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition12 registers"
group.long 0xC020++0x3
line.long 0x0 "CFG_pll12_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1"
bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1"
bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1"
bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1"
bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2  FOUT3  FOUT4 clocks are enabled." "0,1"
newline
bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV  4-phase and synchronous clocks are enabled." "0,1"
bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1"
bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1"
rgroup.long 0xC024++0x3
line.long 0x0 "CFG_pll12_STAT,"
bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1"
group.long 0xC030++0xB
line.long 0x0 "CFG_pll12_FREQ_CTRL0,"
hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.."
line.long 0x4 "CFG_pll12_FREQ_CTRL1,"
hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.."
line.long 0x8 "CFG_pll12_DIV_CTRL,"
bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation  post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63"
group.long 0xC040++0x7
line.long 0x0 "CFG_pll12_SS_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1"
hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0"
bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1"
bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1"
line.long 0x4 "CFG_pll12_SS_SPREAD,"
hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63"
hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%"
group.long 0xC060++0x3
line.long 0x0 "CFG_pll12_CAL_CTRL,"
bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1"
bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1"
bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0  this represents the initial condition for calibration. When cal_byp is 1'b1  this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.."
rgroup.long 0xC064++0x3
line.long 0x0 "CFG_pll12_CAL_STAT,"
bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use"
hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration"
group.long 0xC080++0x3
line.long 0x0 "CFG_pll12_HSDIV_CTRL0,"
bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
rgroup.long 0xE000++0x3
line.long 0x0 "CFG_pll14_PID,"
bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier"
hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number"
bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number"
rgroup.long 0xE008++0x3
line.long 0x0 "CFG_pll14_CFG,"
hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3"
bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1"
bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3"
group.long 0xE010++0x7
line.long 0x0 "CFG_pll14_LOCKKEY0,"
hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition14 registers"
rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set  indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
line.long 0x4 "CFG_pll14_LOCKKEY1,"
hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition14 registers"
group.long 0xE020++0x3
line.long 0x0 "CFG_pll14_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1"
bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1"
bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1"
bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1"
bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2  FOUT3  FOUT4 clocks are enabled." "0,1"
newline
bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV  4-phase and synchronous clocks are enabled." "0,1"
bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1"
bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1"
rgroup.long 0xE024++0x3
line.long 0x0 "CFG_pll14_STAT,"
bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1"
group.long 0xE030++0xB
line.long 0x0 "CFG_pll14_FREQ_CTRL0,"
hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.."
line.long 0x4 "CFG_pll14_FREQ_CTRL1,"
hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.."
line.long 0x8 "CFG_pll14_DIV_CTRL,"
bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation  post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63"
group.long 0xE040++0x7
line.long 0x0 "CFG_pll14_SS_CTRL,"
bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1"
hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0"
bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1"
bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1"
line.long 0x4 "CFG_pll14_SS_SPREAD,"
hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63"
hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%"
group.long 0xE060++0x3
line.long 0x0 "CFG_pll14_CAL_CTRL,"
bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1"
bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1"
bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0  this represents the initial condition for calibration. When cal_byp is 1'b1  this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.."
rgroup.long 0xE064++0x3
line.long 0x0 "CFG_pll14_CAL_STAT,"
bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use"
hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration"
group.long 0xE080++0x7
line.long 0x0 "CFG_pll14_HSDIV_CTRL0,"
bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
line.long 0x4 "CFG_pll14_HSDIV_CTRL1,"
bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1"
bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1"
bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1"
hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
tree.end
endif
tree "PRU"
base ad:0x0
tree "PRU_ICSSG0"
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_DRAM0_SLV_RAM (PRU_ICSSG0_DRAM0_SLV_RAM)"
base ad:0x30000000
group.long 0x0++0x3
line.long 0x0 "DRAM0__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_DRAM1_SLV_RAM (PRU_ICSSG0_DRAM1_SLV_RAM)"
base ad:0x30002000
group.long 0x0++0x3
line.long 0x0 "DRAM1__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_RAM_SLV_RAM (PRU_ICSSG0_RAM_SLV_RAM)"
base ad:0x30010000
group.long 0x0++0x3
line.long 0x0 "RAM__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_IEP0 (PRU_ICSSG0_IEP0)"
base ad:0x3002E000
group.long 0x0++0x1B
line.long 0x0 "PR1_IEP0__SLV__REGS_global_cfg_reg,"
hexmask.long.word 0x0 8.--19. 1. "CMP_INC,"
hexmask.long.byte 0x0 4.--7. 1. "DEFAULT_INC,"
bitfld.long 0x0 0. "CNT_ENABLE," "0,1"
line.long 0x4 "PR1_IEP0__SLV__REGS_global_status_reg,"
bitfld.long 0x4 0. "CNT_OVF," "0,1"
line.long 0x8 "PR1_IEP0__SLV__REGS_compen_reg,"
hexmask.long.tbyte 0x8 0.--22. 1. "COMPEN_CNT,"
line.long 0xC "PR1_IEP0__SLV__REGS_slow_compen_reg,"
hexmask.long 0xC 0.--31. 1. "SLOW_COMPEN_CNT,"
line.long 0x10 "PR1_IEP0__SLV__REGS_count_reg0,"
hexmask.long 0x10 0.--31. 1. "COUNT_LO,"
line.long 0x14 "PR1_IEP0__SLV__REGS_count_reg1,"
hexmask.long 0x14 0.--31. 1. "COUNT_HI,"
line.long 0x18 "PR1_IEP0__SLV__REGS_cap_cfg_reg,"
hexmask.long.byte 0x18 18.--23. 1. "EXT_CAP_EN,"
hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN,"
hexmask.long.word 0x18 0.--9. 1. "CAP_EN,"
rgroup.long 0x1C++0x53
line.long 0x0 "PR1_IEP0__SLV__REGS_cap_status_reg,"
hexmask.long.byte 0x0 16.--23. 1. "CAP_RAW,"
hexmask.long.word 0x0 0.--10. 1. "CAP_VALID,"
line.long 0x4 "PR1_IEP0__SLV__REGS_capr0_reg0,"
hexmask.long 0x4 0.--31. 1. "CAPR0_0,"
line.long 0x8 "PR1_IEP0__SLV__REGS_capr0_reg1,"
hexmask.long 0x8 0.--31. 1. "CAPR0_1,"
line.long 0xC "PR1_IEP0__SLV__REGS_capr1_reg0,"
hexmask.long 0xC 0.--31. 1. "CAPR1_0,"
line.long 0x10 "PR1_IEP0__SLV__REGS_capr1_reg1,"
hexmask.long 0x10 0.--31. 1. "CAPR1_1,"
line.long 0x14 "PR1_IEP0__SLV__REGS_capr2_reg0,"
hexmask.long 0x14 0.--31. 1. "CAPR2_0,"
line.long 0x18 "PR1_IEP0__SLV__REGS_capr2_reg1,"
hexmask.long 0x18 0.--31. 1. "CAPR2_1,"
line.long 0x1C "PR1_IEP0__SLV__REGS_capr3_reg0,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_0,"
line.long 0x20 "PR1_IEP0__SLV__REGS_capr3_reg1,"
hexmask.long 0x20 0.--31. 1. "CAPR3_1,"
line.long 0x24 "PR1_IEP0__SLV__REGS_capr4_reg0,"
hexmask.long 0x24 0.--31. 1. "CAPR4_0,"
line.long 0x28 "PR1_IEP0__SLV__REGS_capr4_reg1,"
hexmask.long 0x28 0.--31. 1. "CAPR4_1,"
line.long 0x2C "PR1_IEP0__SLV__REGS_capr5_reg0,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_0,"
line.long 0x30 "PR1_IEP0__SLV__REGS_capr5_reg1,"
hexmask.long 0x30 0.--31. 1. "CAPR5_1,"
line.long 0x34 "PR1_IEP0__SLV__REGS_capr6_reg0,"
hexmask.long 0x34 0.--31. 1. "CAPR6_0,"
line.long 0x38 "PR1_IEP0__SLV__REGS_capr6_reg1,"
hexmask.long 0x38 0.--31. 1. "CAPR6_1,"
line.long 0x3C "PR1_IEP0__SLV__REGS_capf6_reg0,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_0,"
line.long 0x40 "PR1_IEP0__SLV__REGS_capf6_reg1,"
hexmask.long 0x40 0.--31. 1. "CAPF6_1,"
line.long 0x44 "PR1_IEP0__SLV__REGS_capr7_reg0,"
hexmask.long 0x44 0.--31. 1. "CAPR7_0,"
line.long 0x48 "PR1_IEP0__SLV__REGS_capr7_reg1,"
hexmask.long 0x48 0.--31. 1. "CAPR7_1,"
line.long 0x4C "PR1_IEP0__SLV__REGS_capf7_reg0,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_0,"
line.long 0x50 "PR1_IEP0__SLV__REGS_capf7_reg1,"
hexmask.long 0x50 0.--31. 1. "CAPF7_1,"
group.long 0x70++0x9B
line.long 0x0 "PR1_IEP0__SLV__REGS_cmp_cfg_reg,"
bitfld.long 0x0 17. "SHADOW_EN," "0,1"
hexmask.long.word 0x0 1.--16. 1. "CMP_EN,"
bitfld.long 0x0 0. "CMP0_RST_CNT_EN," "0,1"
line.long 0x4 "PR1_IEP0__SLV__REGS_cmp_status_reg,"
hexmask.long.word 0x4 0.--15. 1. "CMP_STATUS,"
line.long 0x8 "PR1_IEP0__SLV__REGS_cmp0_reg0,"
hexmask.long 0x8 0.--31. 1. "CMP0_0,"
line.long 0xC "PR1_IEP0__SLV__REGS_cmp0_reg1,"
hexmask.long 0xC 0.--31. 1. "CMP0_1,"
line.long 0x10 "PR1_IEP0__SLV__REGS_cmp1_reg0,"
hexmask.long 0x10 0.--31. 1. "CMP1_0,"
line.long 0x14 "PR1_IEP0__SLV__REGS_cmp1_reg1,"
hexmask.long 0x14 0.--31. 1. "CMP1_1,"
line.long 0x18 "PR1_IEP0__SLV__REGS_cmp2_reg0,"
hexmask.long 0x18 0.--31. 1. "CMP2_0,"
line.long 0x1C "PR1_IEP0__SLV__REGS_cmp2_reg1,"
hexmask.long 0x1C 0.--31. 1. "CMP2_1,"
line.long 0x20 "PR1_IEP0__SLV__REGS_cmp3_reg0,"
hexmask.long 0x20 0.--31. 1. "CMP3_0,"
line.long 0x24 "PR1_IEP0__SLV__REGS_cmp3_reg1,"
hexmask.long 0x24 0.--31. 1. "CMP3_1,"
line.long 0x28 "PR1_IEP0__SLV__REGS_cmp4_reg0,"
hexmask.long 0x28 0.--31. 1. "CMP4_0,"
line.long 0x2C "PR1_IEP0__SLV__REGS_cmp4_reg1,"
hexmask.long 0x2C 0.--31. 1. "CMP4_1,"
line.long 0x30 "PR1_IEP0__SLV__REGS_cmp5_reg0,"
hexmask.long 0x30 0.--31. 1. "CMP5_0,"
line.long 0x34 "PR1_IEP0__SLV__REGS_cmp5_reg1,"
hexmask.long 0x34 0.--31. 1. "CMP5_1,"
line.long 0x38 "PR1_IEP0__SLV__REGS_cmp6_reg0,"
hexmask.long 0x38 0.--31. 1. "CMP6_0,"
line.long 0x3C "PR1_IEP0__SLV__REGS_cmp6_reg1,"
hexmask.long 0x3C 0.--31. 1. "CMP6_1,"
line.long 0x40 "PR1_IEP0__SLV__REGS_cmp7_reg0,"
hexmask.long 0x40 0.--31. 1. "CMP7_0,"
line.long 0x44 "PR1_IEP0__SLV__REGS_cmp7_reg1,"
hexmask.long 0x44 0.--31. 1. "CMP7_1,"
line.long 0x48 "PR1_IEP0__SLV__REGS_rxipg0_reg,"
hexmask.long.word 0x48 16.--31. 1. "RX_MIN_IPG0,"
hexmask.long.word 0x48 0.--15. 1. "RX_IPG0,"
line.long 0x4C "PR1_IEP0__SLV__REGS_rxipg1_reg,"
hexmask.long.word 0x4C 16.--31. 1. "RX_MIN_IPG1,"
hexmask.long.word 0x4C 0.--15. 1. "RX_IPG1,"
line.long 0x50 "PR1_IEP0__SLV__REGS_cmp8_reg0,"
hexmask.long 0x50 0.--31. 1. "CMP8_0,"
line.long 0x54 "PR1_IEP0__SLV__REGS_cmp8_reg1,"
hexmask.long 0x54 0.--31. 1. "CMP8_1,"
line.long 0x58 "PR1_IEP0__SLV__REGS_cmp9_reg0,"
hexmask.long 0x58 0.--31. 1. "CMP9_0,"
line.long 0x5C "PR1_IEP0__SLV__REGS_cmp9_reg1,"
hexmask.long 0x5C 0.--31. 1. "CMP9_1,"
line.long 0x60 "PR1_IEP0__SLV__REGS_cmp10_reg0,"
hexmask.long 0x60 0.--31. 1. "CMP10_0,"
line.long 0x64 "PR1_IEP0__SLV__REGS_cmp10_reg1,"
hexmask.long 0x64 0.--31. 1. "CMP10_1,"
line.long 0x68 "PR1_IEP0__SLV__REGS_cmp11_reg0,"
hexmask.long 0x68 0.--31. 1. "CMP11_0,"
line.long 0x6C "PR1_IEP0__SLV__REGS_cmp11_reg1,"
hexmask.long 0x6C 0.--31. 1. "CMP11_1,"
line.long 0x70 "PR1_IEP0__SLV__REGS_cmp12_reg0,"
hexmask.long 0x70 0.--31. 1. "CMP12_0,"
line.long 0x74 "PR1_IEP0__SLV__REGS_cmp12_reg1,"
hexmask.long 0x74 0.--31. 1. "CMP12_1,"
line.long 0x78 "PR1_IEP0__SLV__REGS_cmp13_reg0,"
hexmask.long 0x78 0.--31. 1. "CMP13_0,"
line.long 0x7C "PR1_IEP0__SLV__REGS_cmp13_reg1,"
hexmask.long 0x7C 0.--31. 1. "CMP13_1,"
line.long 0x80 "PR1_IEP0__SLV__REGS_cmp14_reg0,"
hexmask.long 0x80 0.--31. 1. "CMP14_0,"
line.long 0x84 "PR1_IEP0__SLV__REGS_cmp14_reg1,"
hexmask.long 0x84 0.--31. 1. "CMP14_1,"
line.long 0x88 "PR1_IEP0__SLV__REGS_cmp15_reg0,"
hexmask.long 0x88 0.--31. 1. "CMP15_0,"
line.long 0x8C "PR1_IEP0__SLV__REGS_cmp15_reg1,"
hexmask.long 0x8C 0.--31. 1. "CMP15_1,"
line.long 0x90 "PR1_IEP0__SLV__REGS_count_reset_val_reg0,"
hexmask.long 0x90 0.--31. 1. "RESET_VAL_0,"
line.long 0x94 "PR1_IEP0__SLV__REGS_count_reset_val_reg1,"
hexmask.long 0x94 0.--31. 1. "RESET_VAL_1,"
line.long 0x98 "PR1_IEP0__SLV__REGS_pwm_reg,"
bitfld.long 0x98 3. "PWM3_HIT," "0,1"
bitfld.long 0x98 2. "PWM3_RST_CNT_EN," "0,1"
bitfld.long 0x98 1. "PWM0_HIT," "0,1"
bitfld.long 0x98 0. "PWM0_RST_CNT_EN," "0,1"
rgroup.long 0x10C++0x4F
line.long 0x0 "PR1_IEP0__SLV__REGS_capr0_bi_reg0,"
hexmask.long 0x0 0.--31. 1. "CAPR0_0,"
line.long 0x4 "PR1_IEP0__SLV__REGS_capr0_bi_reg1,"
hexmask.long 0x4 0.--31. 1. "CAPR0_1,"
line.long 0x8 "PR1_IEP0__SLV__REGS_capr1_bi_reg0,"
hexmask.long 0x8 0.--31. 1. "CAPR1_0,"
line.long 0xC "PR1_IEP0__SLV__REGS_capr1_bi_reg1,"
hexmask.long 0xC 0.--31. 1. "CAPR1_1,"
line.long 0x10 "PR1_IEP0__SLV__REGS_capr2_bi_reg0,"
hexmask.long 0x10 0.--31. 1. "CAPR2_0,"
line.long 0x14 "PR1_IEP0__SLV__REGS_capr2_bi_reg1,"
hexmask.long 0x14 0.--31. 1. "CAPR2_1,"
line.long 0x18 "PR1_IEP0__SLV__REGS_capr3_bi_reg0,"
hexmask.long 0x18 0.--31. 1. "CAPR3_0,"
line.long 0x1C "PR1_IEP0__SLV__REGS_capr3_bi_reg1,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_1,"
line.long 0x20 "PR1_IEP0__SLV__REGS_capr4_bi_reg0,"
hexmask.long 0x20 0.--31. 1. "CAPR4_0,"
line.long 0x24 "PR1_IEP0__SLV__REGS_capr4_bi_reg1,"
hexmask.long 0x24 0.--31. 1. "CAPR4_1,"
line.long 0x28 "PR1_IEP0__SLV__REGS_capr5_bi_reg0,"
hexmask.long 0x28 0.--31. 1. "CAPR5_0,"
line.long 0x2C "PR1_IEP0__SLV__REGS_capr5_bi_reg1,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_1,"
line.long 0x30 "PR1_IEP0__SLV__REGS_capr6_bi_reg0,"
hexmask.long 0x30 0.--31. 1. "CAPR6_0,"
line.long 0x34 "PR1_IEP0__SLV__REGS_capr6_bi_reg1,"
hexmask.long 0x34 0.--31. 1. "CAPR6_1,"
line.long 0x38 "PR1_IEP0__SLV__REGS_capf6_bi_reg0,"
hexmask.long 0x38 0.--31. 1. "CAPF6_0,"
line.long 0x3C "PR1_IEP0__SLV__REGS_capf6_bi_reg1,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_1,"
line.long 0x40 "PR1_IEP0__SLV__REGS_capr7_bi_reg0,"
hexmask.long 0x40 0.--31. 1. "CAPR7_0,"
line.long 0x44 "PR1_IEP0__SLV__REGS_capr7_bi_reg1,"
hexmask.long 0x44 0.--31. 1. "CAPR7_1,"
line.long 0x48 "PR1_IEP0__SLV__REGS_capf7_bi_reg0,"
hexmask.long 0x48 0.--31. 1. "CAPF7_0,"
line.long 0x4C "PR1_IEP0__SLV__REGS_capf7_bi_reg1,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_1,"
group.long 0x180++0x3
line.long 0x0 "PR1_IEP0__SLV__REGS_sync_ctrl_reg,"
bitfld.long 0x0 10. "SYNC1_OUT_NV_EN," "0,1"
bitfld.long 0x0 9. "SYNC0_OUT_NV_EN," "0,1"
bitfld.long 0x0 8. "SYNC1_IND_EN," "0,1"
bitfld.long 0x0 7. "SYNC1_CYCLIC_EN," "0,1"
newline
bitfld.long 0x0 6. "SYNC1_ACK_EN," "0,1"
bitfld.long 0x0 5. "SYNC0_CYCLIC_EN," "0,1"
bitfld.long 0x0 4. "SYNC0_ACK_EN," "0,1"
bitfld.long 0x0 2. "SYNC1_EN," "0,1"
newline
bitfld.long 0x0 1. "SYNC0_EN," "0,1"
bitfld.long 0x0 0. "SYNC_EN," "0,1"
rgroup.long 0x184++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_sync_first_stat_reg,"
bitfld.long 0x0 1. "FIRST_SYNC1," "0,1"
bitfld.long 0x0 0. "FIRST_SYNC0," "0,1"
line.long 0x4 "PR1_IEP0__SLV__REGS_sync0_stat_reg,"
bitfld.long 0x4 0. "SYNC0_PEND," "0,1"
line.long 0x8 "PR1_IEP0__SLV__REGS_sync1_stat_reg,"
bitfld.long 0x8 0. "SYNC1_PEND," "0,1"
group.long 0x190++0xF
line.long 0x0 "PR1_IEP0__SLV__REGS_sync_pwidth_reg,"
hexmask.long 0x0 0.--31. 1. "SYNC_HPW,"
line.long 0x4 "PR1_IEP0__SLV__REGS_sync0_period_reg,"
hexmask.long 0x4 0.--31. 1. "SYNC0_PERIOD,"
line.long 0x8 "PR1_IEP0__SLV__REGS_sync1_delay_reg,"
hexmask.long 0x8 0.--31. 1. "SYNC1_DELAY,"
line.long 0xC "PR1_IEP0__SLV__REGS_sync_start_reg,"
hexmask.long 0xC 0.--31. 1. "SYNC_START,"
group.long 0x200++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_wd_prediv_reg,"
hexmask.long.word 0x0 0.--15. 1. "PRE_DIV,"
line.long 0x4 "PR1_IEP0__SLV__REGS_pdi_wd_tim_reg,"
hexmask.long.word 0x4 0.--15. 1. "PDI_WD_TIME,"
line.long 0x8 "PR1_IEP0__SLV__REGS_pd_wd_tim_reg,"
hexmask.long.word 0x8 0.--15. 1. "PD_WD_TIME,"
rgroup.long 0x20C++0x3
line.long 0x0 "PR1_IEP0__SLV__REGS_wd_status_reg,"
bitfld.long 0x0 16. "PDI_WD_STAT," "0,1"
bitfld.long 0x0 0. "PD_WD_STAT," "0,1"
group.long 0x210++0x7
line.long 0x0 "PR1_IEP0__SLV__REGS_wd_exp_cnt_reg,"
hexmask.long.byte 0x0 8.--15. 1. "PD_EXP_CNT,"
hexmask.long.byte 0x0 0.--7. 1. "PDI_EXP_CNT,"
line.long 0x4 "PR1_IEP0__SLV__REGS_wd_ctrl_reg,"
bitfld.long 0x4 16. "PDI_WD_EN," "0,1"
bitfld.long 0x4 0. "PD_WD_EN," "0,1"
group.long 0x300++0x3
line.long 0x0 "PR1_IEP0__SLV__REGS_digio_ctrl_reg,"
bitfld.long 0x0 6.--7. "OUT_MODE," "0,1,2,3"
bitfld.long 0x0 4.--5. "IN_MODE," "0,1,2,3"
bitfld.long 0x0 3. "WD_MODE," "0,1"
rbitfld.long 0x0 2. "BIDI_MODE," "0,1"
newline
bitfld.long 0x0 1. "OUTVALID_MODE," "0,1"
rbitfld.long 0x0 0. "OUTVALID_POL," "0,1"
rgroup.long 0x304++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_digio_status_reg,"
hexmask.long 0x0 0.--31. 1. "DIGIO_STAT,"
line.long 0x4 "PR1_IEP0__SLV__REGS_digio_data_in_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_IN,"
line.long 0x8 "PR1_IEP0__SLV__REGS_digio_data_in_raw_reg,"
hexmask.long 0x8 0.--31. 1. "DATA_IN_RAW,"
group.long 0x310++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_digio_data_out_reg,"
hexmask.long 0x0 0.--31. 1. "DATA_OUT,"
line.long 0x4 "PR1_IEP0__SLV__REGS_digio_data_out_en_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_OUT_EN,"
line.long 0x8 "PR1_IEP0__SLV__REGS_digio_exp_reg,"
bitfld.long 0x8 13. "EOF_SEL," "0,1"
bitfld.long 0x8 12. "SOF_SEL," "0,1"
hexmask.long.byte 0x8 8.--11. 1. "SOF_DLY,"
hexmask.long.byte 0x8 4.--7. 1. "OUTVALID_DLY,"
newline
bitfld.long 0x8 2. "SW_OUTVALID," "0,1"
bitfld.long 0x8 1. "OUTVALID_OVR_EN," "0,1"
bitfld.long 0x8 0. "SW_DATA_OUT_UP," "0,1"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_IEP1 (PRU_ICSSG0_IEP1)"
base ad:0x3002F000
group.long 0x0++0x1B
line.long 0x0 "PR1_IEP1__SLV__REGS_global_cfg_reg,"
hexmask.long.word 0x0 8.--19. 1. "CMP_INC,"
hexmask.long.byte 0x0 4.--7. 1. "DEFAULT_INC,"
bitfld.long 0x0 0. "CNT_ENABLE," "0,1"
line.long 0x4 "PR1_IEP1__SLV__REGS_global_status_reg,"
bitfld.long 0x4 0. "CNT_OVF," "0,1"
line.long 0x8 "PR1_IEP1__SLV__REGS_compen_reg,"
hexmask.long.tbyte 0x8 0.--22. 1. "COMPEN_CNT,"
line.long 0xC "PR1_IEP1__SLV__REGS_slow_compen_reg,"
hexmask.long 0xC 0.--31. 1. "SLOW_COMPEN_CNT,"
line.long 0x10 "PR1_IEP1__SLV__REGS_count_reg0,"
hexmask.long 0x10 0.--31. 1. "COUNT_LO,"
line.long 0x14 "PR1_IEP1__SLV__REGS_count_reg1,"
hexmask.long 0x14 0.--31. 1. "COUNT_HI,"
line.long 0x18 "PR1_IEP1__SLV__REGS_cap_cfg_reg,"
hexmask.long.byte 0x18 18.--23. 1. "EXT_CAP_EN,"
hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN,"
hexmask.long.word 0x18 0.--9. 1. "CAP_EN,"
rgroup.long 0x1C++0x53
line.long 0x0 "PR1_IEP1__SLV__REGS_cap_status_reg,"
hexmask.long.byte 0x0 16.--23. 1. "CAP_RAW,"
hexmask.long.word 0x0 0.--10. 1. "CAP_VALID,"
line.long 0x4 "PR1_IEP1__SLV__REGS_capr0_reg0,"
hexmask.long 0x4 0.--31. 1. "CAPR0_0,"
line.long 0x8 "PR1_IEP1__SLV__REGS_capr0_reg1,"
hexmask.long 0x8 0.--31. 1. "CAPR0_1,"
line.long 0xC "PR1_IEP1__SLV__REGS_capr1_reg0,"
hexmask.long 0xC 0.--31. 1. "CAPR1_0,"
line.long 0x10 "PR1_IEP1__SLV__REGS_capr1_reg1,"
hexmask.long 0x10 0.--31. 1. "CAPR1_1,"
line.long 0x14 "PR1_IEP1__SLV__REGS_capr2_reg0,"
hexmask.long 0x14 0.--31. 1. "CAPR2_0,"
line.long 0x18 "PR1_IEP1__SLV__REGS_capr2_reg1,"
hexmask.long 0x18 0.--31. 1. "CAPR2_1,"
line.long 0x1C "PR1_IEP1__SLV__REGS_capr3_reg0,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_0,"
line.long 0x20 "PR1_IEP1__SLV__REGS_capr3_reg1,"
hexmask.long 0x20 0.--31. 1. "CAPR3_1,"
line.long 0x24 "PR1_IEP1__SLV__REGS_capr4_reg0,"
hexmask.long 0x24 0.--31. 1. "CAPR4_0,"
line.long 0x28 "PR1_IEP1__SLV__REGS_capr4_reg1,"
hexmask.long 0x28 0.--31. 1. "CAPR4_1,"
line.long 0x2C "PR1_IEP1__SLV__REGS_capr5_reg0,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_0,"
line.long 0x30 "PR1_IEP1__SLV__REGS_capr5_reg1,"
hexmask.long 0x30 0.--31. 1. "CAPR5_1,"
line.long 0x34 "PR1_IEP1__SLV__REGS_capr6_reg0,"
hexmask.long 0x34 0.--31. 1. "CAPR6_0,"
line.long 0x38 "PR1_IEP1__SLV__REGS_capr6_reg1,"
hexmask.long 0x38 0.--31. 1. "CAPR6_1,"
line.long 0x3C "PR1_IEP1__SLV__REGS_capf6_reg0,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_0,"
line.long 0x40 "PR1_IEP1__SLV__REGS_capf6_reg1,"
hexmask.long 0x40 0.--31. 1. "CAPF6_1,"
line.long 0x44 "PR1_IEP1__SLV__REGS_capr7_reg0,"
hexmask.long 0x44 0.--31. 1. "CAPR7_0,"
line.long 0x48 "PR1_IEP1__SLV__REGS_capr7_reg1,"
hexmask.long 0x48 0.--31. 1. "CAPR7_1,"
line.long 0x4C "PR1_IEP1__SLV__REGS_capf7_reg0,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_0,"
line.long 0x50 "PR1_IEP1__SLV__REGS_capf7_reg1,"
hexmask.long 0x50 0.--31. 1. "CAPF7_1,"
group.long 0x70++0x9B
line.long 0x0 "PR1_IEP1__SLV__REGS_cmp_cfg_reg,"
bitfld.long 0x0 17. "SHADOW_EN," "0,1"
hexmask.long.word 0x0 1.--16. 1. "CMP_EN,"
bitfld.long 0x0 0. "CMP0_RST_CNT_EN," "0,1"
line.long 0x4 "PR1_IEP1__SLV__REGS_cmp_status_reg,"
hexmask.long.word 0x4 0.--15. 1. "CMP_STATUS,"
line.long 0x8 "PR1_IEP1__SLV__REGS_cmp0_reg0,"
hexmask.long 0x8 0.--31. 1. "CMP0_0,"
line.long 0xC "PR1_IEP1__SLV__REGS_cmp0_reg1,"
hexmask.long 0xC 0.--31. 1. "CMP0_1,"
line.long 0x10 "PR1_IEP1__SLV__REGS_cmp1_reg0,"
hexmask.long 0x10 0.--31. 1. "CMP1_0,"
line.long 0x14 "PR1_IEP1__SLV__REGS_cmp1_reg1,"
hexmask.long 0x14 0.--31. 1. "CMP1_1,"
line.long 0x18 "PR1_IEP1__SLV__REGS_cmp2_reg0,"
hexmask.long 0x18 0.--31. 1. "CMP2_0,"
line.long 0x1C "PR1_IEP1__SLV__REGS_cmp2_reg1,"
hexmask.long 0x1C 0.--31. 1. "CMP2_1,"
line.long 0x20 "PR1_IEP1__SLV__REGS_cmp3_reg0,"
hexmask.long 0x20 0.--31. 1. "CMP3_0,"
line.long 0x24 "PR1_IEP1__SLV__REGS_cmp3_reg1,"
hexmask.long 0x24 0.--31. 1. "CMP3_1,"
line.long 0x28 "PR1_IEP1__SLV__REGS_cmp4_reg0,"
hexmask.long 0x28 0.--31. 1. "CMP4_0,"
line.long 0x2C "PR1_IEP1__SLV__REGS_cmp4_reg1,"
hexmask.long 0x2C 0.--31. 1. "CMP4_1,"
line.long 0x30 "PR1_IEP1__SLV__REGS_cmp5_reg0,"
hexmask.long 0x30 0.--31. 1. "CMP5_0,"
line.long 0x34 "PR1_IEP1__SLV__REGS_cmp5_reg1,"
hexmask.long 0x34 0.--31. 1. "CMP5_1,"
line.long 0x38 "PR1_IEP1__SLV__REGS_cmp6_reg0,"
hexmask.long 0x38 0.--31. 1. "CMP6_0,"
line.long 0x3C "PR1_IEP1__SLV__REGS_cmp6_reg1,"
hexmask.long 0x3C 0.--31. 1. "CMP6_1,"
line.long 0x40 "PR1_IEP1__SLV__REGS_cmp7_reg0,"
hexmask.long 0x40 0.--31. 1. "CMP7_0,"
line.long 0x44 "PR1_IEP1__SLV__REGS_cmp7_reg1,"
hexmask.long 0x44 0.--31. 1. "CMP7_1,"
line.long 0x48 "PR1_IEP1__SLV__REGS_rxipg0_reg,"
hexmask.long.word 0x48 16.--31. 1. "RX_MIN_IPG0,"
hexmask.long.word 0x48 0.--15. 1. "RX_IPG0,"
line.long 0x4C "PR1_IEP1__SLV__REGS_rxipg1_reg,"
hexmask.long.word 0x4C 16.--31. 1. "RX_MIN_IPG1,"
hexmask.long.word 0x4C 0.--15. 1. "RX_IPG1,"
line.long 0x50 "PR1_IEP1__SLV__REGS_cmp8_reg0,"
hexmask.long 0x50 0.--31. 1. "CMP8_0,"
line.long 0x54 "PR1_IEP1__SLV__REGS_cmp8_reg1,"
hexmask.long 0x54 0.--31. 1. "CMP8_1,"
line.long 0x58 "PR1_IEP1__SLV__REGS_cmp9_reg0,"
hexmask.long 0x58 0.--31. 1. "CMP9_0,"
line.long 0x5C "PR1_IEP1__SLV__REGS_cmp9_reg1,"
hexmask.long 0x5C 0.--31. 1. "CMP9_1,"
line.long 0x60 "PR1_IEP1__SLV__REGS_cmp10_reg0,"
hexmask.long 0x60 0.--31. 1. "CMP10_0,"
line.long 0x64 "PR1_IEP1__SLV__REGS_cmp10_reg1,"
hexmask.long 0x64 0.--31. 1. "CMP10_1,"
line.long 0x68 "PR1_IEP1__SLV__REGS_cmp11_reg0,"
hexmask.long 0x68 0.--31. 1. "CMP11_0,"
line.long 0x6C "PR1_IEP1__SLV__REGS_cmp11_reg1,"
hexmask.long 0x6C 0.--31. 1. "CMP11_1,"
line.long 0x70 "PR1_IEP1__SLV__REGS_cmp12_reg0,"
hexmask.long 0x70 0.--31. 1. "CMP12_0,"
line.long 0x74 "PR1_IEP1__SLV__REGS_cmp12_reg1,"
hexmask.long 0x74 0.--31. 1. "CMP12_1,"
line.long 0x78 "PR1_IEP1__SLV__REGS_cmp13_reg0,"
hexmask.long 0x78 0.--31. 1. "CMP13_0,"
line.long 0x7C "PR1_IEP1__SLV__REGS_cmp13_reg1,"
hexmask.long 0x7C 0.--31. 1. "CMP13_1,"
line.long 0x80 "PR1_IEP1__SLV__REGS_cmp14_reg0,"
hexmask.long 0x80 0.--31. 1. "CMP14_0,"
line.long 0x84 "PR1_IEP1__SLV__REGS_cmp14_reg1,"
hexmask.long 0x84 0.--31. 1. "CMP14_1,"
line.long 0x88 "PR1_IEP1__SLV__REGS_cmp15_reg0,"
hexmask.long 0x88 0.--31. 1. "CMP15_0,"
line.long 0x8C "PR1_IEP1__SLV__REGS_cmp15_reg1,"
hexmask.long 0x8C 0.--31. 1. "CMP15_1,"
line.long 0x90 "PR1_IEP1__SLV__REGS_count_reset_val_reg0,"
hexmask.long 0x90 0.--31. 1. "RESET_VAL_0,"
line.long 0x94 "PR1_IEP1__SLV__REGS_count_reset_val_reg1,"
hexmask.long 0x94 0.--31. 1. "RESET_VAL_1,"
line.long 0x98 "PR1_IEP1__SLV__REGS_pwm_reg,"
bitfld.long 0x98 3. "PWM3_HIT," "0,1"
bitfld.long 0x98 2. "PWM3_RST_CNT_EN," "0,1"
bitfld.long 0x98 1. "PWM0_HIT," "0,1"
bitfld.long 0x98 0. "PWM0_RST_CNT_EN," "0,1"
rgroup.long 0x10C++0x4F
line.long 0x0 "PR1_IEP1__SLV__REGS_capr0_bi_reg0,"
hexmask.long 0x0 0.--31. 1. "CAPR0_0,"
line.long 0x4 "PR1_IEP1__SLV__REGS_capr0_bi_reg1,"
hexmask.long 0x4 0.--31. 1. "CAPR0_1,"
line.long 0x8 "PR1_IEP1__SLV__REGS_capr1_bi_reg0,"
hexmask.long 0x8 0.--31. 1. "CAPR1_0,"
line.long 0xC "PR1_IEP1__SLV__REGS_capr1_bi_reg1,"
hexmask.long 0xC 0.--31. 1. "CAPR1_1,"
line.long 0x10 "PR1_IEP1__SLV__REGS_capr2_bi_reg0,"
hexmask.long 0x10 0.--31. 1. "CAPR2_0,"
line.long 0x14 "PR1_IEP1__SLV__REGS_capr2_bi_reg1,"
hexmask.long 0x14 0.--31. 1. "CAPR2_1,"
line.long 0x18 "PR1_IEP1__SLV__REGS_capr3_bi_reg0,"
hexmask.long 0x18 0.--31. 1. "CAPR3_0,"
line.long 0x1C "PR1_IEP1__SLV__REGS_capr3_bi_reg1,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_1,"
line.long 0x20 "PR1_IEP1__SLV__REGS_capr4_bi_reg0,"
hexmask.long 0x20 0.--31. 1. "CAPR4_0,"
line.long 0x24 "PR1_IEP1__SLV__REGS_capr4_bi_reg1,"
hexmask.long 0x24 0.--31. 1. "CAPR4_1,"
line.long 0x28 "PR1_IEP1__SLV__REGS_capr5_bi_reg0,"
hexmask.long 0x28 0.--31. 1. "CAPR5_0,"
line.long 0x2C "PR1_IEP1__SLV__REGS_capr5_bi_reg1,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_1,"
line.long 0x30 "PR1_IEP1__SLV__REGS_capr6_bi_reg0,"
hexmask.long 0x30 0.--31. 1. "CAPR6_0,"
line.long 0x34 "PR1_IEP1__SLV__REGS_capr6_bi_reg1,"
hexmask.long 0x34 0.--31. 1. "CAPR6_1,"
line.long 0x38 "PR1_IEP1__SLV__REGS_capf6_bi_reg0,"
hexmask.long 0x38 0.--31. 1. "CAPF6_0,"
line.long 0x3C "PR1_IEP1__SLV__REGS_capf6_bi_reg1,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_1,"
line.long 0x40 "PR1_IEP1__SLV__REGS_capr7_bi_reg0,"
hexmask.long 0x40 0.--31. 1. "CAPR7_0,"
line.long 0x44 "PR1_IEP1__SLV__REGS_capr7_bi_reg1,"
hexmask.long 0x44 0.--31. 1. "CAPR7_1,"
line.long 0x48 "PR1_IEP1__SLV__REGS_capf7_bi_reg0,"
hexmask.long 0x48 0.--31. 1. "CAPF7_0,"
line.long 0x4C "PR1_IEP1__SLV__REGS_capf7_bi_reg1,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_1,"
group.long 0x180++0x3
line.long 0x0 "PR1_IEP1__SLV__REGS_sync_ctrl_reg,"
bitfld.long 0x0 10. "SYNC1_OUT_NV_EN," "0,1"
bitfld.long 0x0 9. "SYNC0_OUT_NV_EN," "0,1"
bitfld.long 0x0 8. "SYNC1_IND_EN," "0,1"
bitfld.long 0x0 7. "SYNC1_CYCLIC_EN," "0,1"
newline
bitfld.long 0x0 6. "SYNC1_ACK_EN," "0,1"
bitfld.long 0x0 5. "SYNC0_CYCLIC_EN," "0,1"
bitfld.long 0x0 4. "SYNC0_ACK_EN," "0,1"
bitfld.long 0x0 2. "SYNC1_EN," "0,1"
newline
bitfld.long 0x0 1. "SYNC0_EN," "0,1"
bitfld.long 0x0 0. "SYNC_EN," "0,1"
rgroup.long 0x184++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_sync_first_stat_reg,"
bitfld.long 0x0 1. "FIRST_SYNC1," "0,1"
bitfld.long 0x0 0. "FIRST_SYNC0," "0,1"
line.long 0x4 "PR1_IEP1__SLV__REGS_sync0_stat_reg,"
bitfld.long 0x4 0. "SYNC0_PEND," "0,1"
line.long 0x8 "PR1_IEP1__SLV__REGS_sync1_stat_reg,"
bitfld.long 0x8 0. "SYNC1_PEND," "0,1"
group.long 0x190++0xF
line.long 0x0 "PR1_IEP1__SLV__REGS_sync_pwidth_reg,"
hexmask.long 0x0 0.--31. 1. "SYNC_HPW,"
line.long 0x4 "PR1_IEP1__SLV__REGS_sync0_period_reg,"
hexmask.long 0x4 0.--31. 1. "SYNC0_PERIOD,"
line.long 0x8 "PR1_IEP1__SLV__REGS_sync1_delay_reg,"
hexmask.long 0x8 0.--31. 1. "SYNC1_DELAY,"
line.long 0xC "PR1_IEP1__SLV__REGS_sync_start_reg,"
hexmask.long 0xC 0.--31. 1. "SYNC_START,"
group.long 0x200++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_wd_prediv_reg,"
hexmask.long.word 0x0 0.--15. 1. "PRE_DIV,"
line.long 0x4 "PR1_IEP1__SLV__REGS_pdi_wd_tim_reg,"
hexmask.long.word 0x4 0.--15. 1. "PDI_WD_TIME,"
line.long 0x8 "PR1_IEP1__SLV__REGS_pd_wd_tim_reg,"
hexmask.long.word 0x8 0.--15. 1. "PD_WD_TIME,"
rgroup.long 0x20C++0x3
line.long 0x0 "PR1_IEP1__SLV__REGS_wd_status_reg,"
bitfld.long 0x0 16. "PDI_WD_STAT," "0,1"
bitfld.long 0x0 0. "PD_WD_STAT," "0,1"
group.long 0x210++0x7
line.long 0x0 "PR1_IEP1__SLV__REGS_wd_exp_cnt_reg,"
hexmask.long.byte 0x0 8.--15. 1. "PD_EXP_CNT,"
hexmask.long.byte 0x0 0.--7. 1. "PDI_EXP_CNT,"
line.long 0x4 "PR1_IEP1__SLV__REGS_wd_ctrl_reg,"
bitfld.long 0x4 16. "PDI_WD_EN," "0,1"
bitfld.long 0x4 0. "PD_WD_EN," "0,1"
group.long 0x300++0x3
line.long 0x0 "PR1_IEP1__SLV__REGS_digio_ctrl_reg,"
bitfld.long 0x0 6.--7. "OUT_MODE," "0,1,2,3"
bitfld.long 0x0 4.--5. "IN_MODE," "0,1,2,3"
bitfld.long 0x0 3. "WD_MODE," "0,1"
rbitfld.long 0x0 2. "BIDI_MODE," "0,1"
newline
bitfld.long 0x0 1. "OUTVALID_MODE," "0,1"
rbitfld.long 0x0 0. "OUTVALID_POL," "0,1"
rgroup.long 0x304++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_digio_status_reg,"
hexmask.long 0x0 0.--31. 1. "DIGIO_STAT,"
line.long 0x4 "PR1_IEP1__SLV__REGS_digio_data_in_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_IN,"
line.long 0x8 "PR1_IEP1__SLV__REGS_digio_data_in_raw_reg,"
hexmask.long 0x8 0.--31. 1. "DATA_IN_RAW,"
group.long 0x310++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_digio_data_out_reg,"
hexmask.long 0x0 0.--31. 1. "DATA_OUT,"
line.long 0x4 "PR1_IEP1__SLV__REGS_digio_data_out_en_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_OUT_EN,"
line.long 0x8 "PR1_IEP1__SLV__REGS_digio_exp_reg,"
bitfld.long 0x8 13. "EOF_SEL," "0,1"
bitfld.long 0x8 12. "SOF_SEL," "0,1"
hexmask.long.byte 0x8 8.--11. 1. "SOF_DLY,"
hexmask.long.byte 0x8 4.--7. 1. "OUTVALID_DLY,"
newline
bitfld.long 0x8 2. "SW_OUTVALID," "0,1"
bitfld.long 0x8 1. "OUTVALID_OVR_EN," "0,1"
bitfld.long 0x8 0. "SW_DATA_OUT_UP," "0,1"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_ECC_AGGR (PRU_ICSSG0_ECC_AGGR)"
base ad:0x3F00A000
rgroup.long 0x0++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x7
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "BORG_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 8. "PR1_PDSP_TX1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x4 7. "PR1_PDSP_TX0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x4 6. "PR1_RTU1_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x4 5. "PR1_RTU0_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x4 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x4 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x4 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x4 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1"
bitfld.long 0x4 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 8. "PR1_PDSP_TX1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x0 7. "PR1_PDSP_TX0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x0 6. "PR1_RTU1_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x0 5. "PR1_RTU0_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x0 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 8. "PR1_PDSP_TX1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x0 7. "PR1_PDSP_TX0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x0 6. "PR1_RTU1_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x0 5. "PR1_RTU0_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x0 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1"
bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1"
bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "BORG_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 8. "PR1_PDSP_TX1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x4 7. "PR1_PDSP_TX0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x4 6. "PR1_RTU1_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x4 5. "PR1_RTU0_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x4 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x4 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x4 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x4 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1"
bitfld.long 0x4 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 8. "PR1_PDSP_TX1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x0 7. "PR1_PDSP_TX0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x0 6. "PR1_RTU1_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x0 5. "PR1_RTU0_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x0 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 8. "PR1_PDSP_TX1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x0 7. "PR1_PDSP_TX0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x0 6. "PR1_RTU1_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x0 5. "PR1_RTU0_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x0 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1"
bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1"
bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "BORG_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "BORG_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "BORG_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_DRAM0_SLV_RAM"
base ad:0x0
group.long 0x0++0x3
line.long 0x0 "DRAM0__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_DRAM1_SLV_RAM"
base ad:0x2000
group.long 0x0++0x3
line.long 0x0 "DRAM1__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_RAM_SLV_RAM"
base ad:0x10000
group.long 0x0++0x3
line.long 0x0 "RAM__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_IEP0"
base ad:0x2E000
group.long 0x0++0x1B
line.long 0x0 "PR1_IEP0__SLV__REGS_global_cfg_reg,"
hexmask.long.word 0x0 8.--19. 1. "CMP_INC,"
hexmask.long.byte 0x0 4.--7. 1. "DEFAULT_INC,"
bitfld.long 0x0 0. "CNT_ENABLE," "0,1"
line.long 0x4 "PR1_IEP0__SLV__REGS_global_status_reg,"
bitfld.long 0x4 0. "CNT_OVF," "0,1"
line.long 0x8 "PR1_IEP0__SLV__REGS_compen_reg,"
hexmask.long.tbyte 0x8 0.--22. 1. "COMPEN_CNT,"
line.long 0xC "PR1_IEP0__SLV__REGS_slow_compen_reg,"
hexmask.long 0xC 0.--31. 1. "SLOW_COMPEN_CNT,"
line.long 0x10 "PR1_IEP0__SLV__REGS_count_reg0,"
hexmask.long 0x10 0.--31. 1. "COUNT_LO,"
line.long 0x14 "PR1_IEP0__SLV__REGS_count_reg1,"
hexmask.long 0x14 0.--31. 1. "COUNT_HI,"
line.long 0x18 "PR1_IEP0__SLV__REGS_cap_cfg_reg,"
hexmask.long.byte 0x18 18.--23. 1. "EXT_CAP_EN,"
hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN,"
hexmask.long.word 0x18 0.--9. 1. "CAP_EN,"
rgroup.long 0x1C++0x53
line.long 0x0 "PR1_IEP0__SLV__REGS_cap_status_reg,"
hexmask.long.byte 0x0 16.--23. 1. "CAP_RAW,"
hexmask.long.word 0x0 0.--10. 1. "CAP_VALID,"
line.long 0x4 "PR1_IEP0__SLV__REGS_capr0_reg0,"
hexmask.long 0x4 0.--31. 1. "CAPR0_0,"
line.long 0x8 "PR1_IEP0__SLV__REGS_capr0_reg1,"
hexmask.long 0x8 0.--31. 1. "CAPR0_1,"
line.long 0xC "PR1_IEP0__SLV__REGS_capr1_reg0,"
hexmask.long 0xC 0.--31. 1. "CAPR1_0,"
line.long 0x10 "PR1_IEP0__SLV__REGS_capr1_reg1,"
hexmask.long 0x10 0.--31. 1. "CAPR1_1,"
line.long 0x14 "PR1_IEP0__SLV__REGS_capr2_reg0,"
hexmask.long 0x14 0.--31. 1. "CAPR2_0,"
line.long 0x18 "PR1_IEP0__SLV__REGS_capr2_reg1,"
hexmask.long 0x18 0.--31. 1. "CAPR2_1,"
line.long 0x1C "PR1_IEP0__SLV__REGS_capr3_reg0,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_0,"
line.long 0x20 "PR1_IEP0__SLV__REGS_capr3_reg1,"
hexmask.long 0x20 0.--31. 1. "CAPR3_1,"
line.long 0x24 "PR1_IEP0__SLV__REGS_capr4_reg0,"
hexmask.long 0x24 0.--31. 1. "CAPR4_0,"
line.long 0x28 "PR1_IEP0__SLV__REGS_capr4_reg1,"
hexmask.long 0x28 0.--31. 1. "CAPR4_1,"
line.long 0x2C "PR1_IEP0__SLV__REGS_capr5_reg0,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_0,"
line.long 0x30 "PR1_IEP0__SLV__REGS_capr5_reg1,"
hexmask.long 0x30 0.--31. 1. "CAPR5_1,"
line.long 0x34 "PR1_IEP0__SLV__REGS_capr6_reg0,"
hexmask.long 0x34 0.--31. 1. "CAPR6_0,"
line.long 0x38 "PR1_IEP0__SLV__REGS_capr6_reg1,"
hexmask.long 0x38 0.--31. 1. "CAPR6_1,"
line.long 0x3C "PR1_IEP0__SLV__REGS_capf6_reg0,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_0,"
line.long 0x40 "PR1_IEP0__SLV__REGS_capf6_reg1,"
hexmask.long 0x40 0.--31. 1. "CAPF6_1,"
line.long 0x44 "PR1_IEP0__SLV__REGS_capr7_reg0,"
hexmask.long 0x44 0.--31. 1. "CAPR7_0,"
line.long 0x48 "PR1_IEP0__SLV__REGS_capr7_reg1,"
hexmask.long 0x48 0.--31. 1. "CAPR7_1,"
line.long 0x4C "PR1_IEP0__SLV__REGS_capf7_reg0,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_0,"
line.long 0x50 "PR1_IEP0__SLV__REGS_capf7_reg1,"
hexmask.long 0x50 0.--31. 1. "CAPF7_1,"
group.long 0x70++0x9B
line.long 0x0 "PR1_IEP0__SLV__REGS_cmp_cfg_reg,"
bitfld.long 0x0 17. "SHADOW_EN," "0,1"
hexmask.long.word 0x0 1.--16. 1. "CMP_EN,"
bitfld.long 0x0 0. "CMP0_RST_CNT_EN," "0,1"
line.long 0x4 "PR1_IEP0__SLV__REGS_cmp_status_reg,"
hexmask.long.word 0x4 0.--15. 1. "CMP_STATUS,"
line.long 0x8 "PR1_IEP0__SLV__REGS_cmp0_reg0,"
hexmask.long 0x8 0.--31. 1. "CMP0_0,"
line.long 0xC "PR1_IEP0__SLV__REGS_cmp0_reg1,"
hexmask.long 0xC 0.--31. 1. "CMP0_1,"
line.long 0x10 "PR1_IEP0__SLV__REGS_cmp1_reg0,"
hexmask.long 0x10 0.--31. 1. "CMP1_0,"
line.long 0x14 "PR1_IEP0__SLV__REGS_cmp1_reg1,"
hexmask.long 0x14 0.--31. 1. "CMP1_1,"
line.long 0x18 "PR1_IEP0__SLV__REGS_cmp2_reg0,"
hexmask.long 0x18 0.--31. 1. "CMP2_0,"
line.long 0x1C "PR1_IEP0__SLV__REGS_cmp2_reg1,"
hexmask.long 0x1C 0.--31. 1. "CMP2_1,"
line.long 0x20 "PR1_IEP0__SLV__REGS_cmp3_reg0,"
hexmask.long 0x20 0.--31. 1. "CMP3_0,"
line.long 0x24 "PR1_IEP0__SLV__REGS_cmp3_reg1,"
hexmask.long 0x24 0.--31. 1. "CMP3_1,"
line.long 0x28 "PR1_IEP0__SLV__REGS_cmp4_reg0,"
hexmask.long 0x28 0.--31. 1. "CMP4_0,"
line.long 0x2C "PR1_IEP0__SLV__REGS_cmp4_reg1,"
hexmask.long 0x2C 0.--31. 1. "CMP4_1,"
line.long 0x30 "PR1_IEP0__SLV__REGS_cmp5_reg0,"
hexmask.long 0x30 0.--31. 1. "CMP5_0,"
line.long 0x34 "PR1_IEP0__SLV__REGS_cmp5_reg1,"
hexmask.long 0x34 0.--31. 1. "CMP5_1,"
line.long 0x38 "PR1_IEP0__SLV__REGS_cmp6_reg0,"
hexmask.long 0x38 0.--31. 1. "CMP6_0,"
line.long 0x3C "PR1_IEP0__SLV__REGS_cmp6_reg1,"
hexmask.long 0x3C 0.--31. 1. "CMP6_1,"
line.long 0x40 "PR1_IEP0__SLV__REGS_cmp7_reg0,"
hexmask.long 0x40 0.--31. 1. "CMP7_0,"
line.long 0x44 "PR1_IEP0__SLV__REGS_cmp7_reg1,"
hexmask.long 0x44 0.--31. 1. "CMP7_1,"
line.long 0x48 "PR1_IEP0__SLV__REGS_rxipg0_reg,"
hexmask.long.word 0x48 16.--31. 1. "RX_MIN_IPG0,"
hexmask.long.word 0x48 0.--15. 1. "RX_IPG0,"
line.long 0x4C "PR1_IEP0__SLV__REGS_rxipg1_reg,"
hexmask.long.word 0x4C 16.--31. 1. "RX_MIN_IPG1,"
hexmask.long.word 0x4C 0.--15. 1. "RX_IPG1,"
line.long 0x50 "PR1_IEP0__SLV__REGS_cmp8_reg0,"
hexmask.long 0x50 0.--31. 1. "CMP8_0,"
line.long 0x54 "PR1_IEP0__SLV__REGS_cmp8_reg1,"
hexmask.long 0x54 0.--31. 1. "CMP8_1,"
line.long 0x58 "PR1_IEP0__SLV__REGS_cmp9_reg0,"
hexmask.long 0x58 0.--31. 1. "CMP9_0,"
line.long 0x5C "PR1_IEP0__SLV__REGS_cmp9_reg1,"
hexmask.long 0x5C 0.--31. 1. "CMP9_1,"
line.long 0x60 "PR1_IEP0__SLV__REGS_cmp10_reg0,"
hexmask.long 0x60 0.--31. 1. "CMP10_0,"
line.long 0x64 "PR1_IEP0__SLV__REGS_cmp10_reg1,"
hexmask.long 0x64 0.--31. 1. "CMP10_1,"
line.long 0x68 "PR1_IEP0__SLV__REGS_cmp11_reg0,"
hexmask.long 0x68 0.--31. 1. "CMP11_0,"
line.long 0x6C "PR1_IEP0__SLV__REGS_cmp11_reg1,"
hexmask.long 0x6C 0.--31. 1. "CMP11_1,"
line.long 0x70 "PR1_IEP0__SLV__REGS_cmp12_reg0,"
hexmask.long 0x70 0.--31. 1. "CMP12_0,"
line.long 0x74 "PR1_IEP0__SLV__REGS_cmp12_reg1,"
hexmask.long 0x74 0.--31. 1. "CMP12_1,"
line.long 0x78 "PR1_IEP0__SLV__REGS_cmp13_reg0,"
hexmask.long 0x78 0.--31. 1. "CMP13_0,"
line.long 0x7C "PR1_IEP0__SLV__REGS_cmp13_reg1,"
hexmask.long 0x7C 0.--31. 1. "CMP13_1,"
line.long 0x80 "PR1_IEP0__SLV__REGS_cmp14_reg0,"
hexmask.long 0x80 0.--31. 1. "CMP14_0,"
line.long 0x84 "PR1_IEP0__SLV__REGS_cmp14_reg1,"
hexmask.long 0x84 0.--31. 1. "CMP14_1,"
line.long 0x88 "PR1_IEP0__SLV__REGS_cmp15_reg0,"
hexmask.long 0x88 0.--31. 1. "CMP15_0,"
line.long 0x8C "PR1_IEP0__SLV__REGS_cmp15_reg1,"
hexmask.long 0x8C 0.--31. 1. "CMP15_1,"
line.long 0x90 "PR1_IEP0__SLV__REGS_count_reset_val_reg0,"
hexmask.long 0x90 0.--31. 1. "RESET_VAL_0,"
line.long 0x94 "PR1_IEP0__SLV__REGS_count_reset_val_reg1,"
hexmask.long 0x94 0.--31. 1. "RESET_VAL_1,"
line.long 0x98 "PR1_IEP0__SLV__REGS_pwm_reg,"
bitfld.long 0x98 3. "PWM3_HIT," "0,1"
bitfld.long 0x98 2. "PWM3_RST_CNT_EN," "0,1"
bitfld.long 0x98 1. "PWM0_HIT," "0,1"
bitfld.long 0x98 0. "PWM0_RST_CNT_EN," "0,1"
rgroup.long 0x10C++0x4F
line.long 0x0 "PR1_IEP0__SLV__REGS_capr0_bi_reg0,"
hexmask.long 0x0 0.--31. 1. "CAPR0_0,"
line.long 0x4 "PR1_IEP0__SLV__REGS_capr0_bi_reg1,"
hexmask.long 0x4 0.--31. 1. "CAPR0_1,"
line.long 0x8 "PR1_IEP0__SLV__REGS_capr1_bi_reg0,"
hexmask.long 0x8 0.--31. 1. "CAPR1_0,"
line.long 0xC "PR1_IEP0__SLV__REGS_capr1_bi_reg1,"
hexmask.long 0xC 0.--31. 1. "CAPR1_1,"
line.long 0x10 "PR1_IEP0__SLV__REGS_capr2_bi_reg0,"
hexmask.long 0x10 0.--31. 1. "CAPR2_0,"
line.long 0x14 "PR1_IEP0__SLV__REGS_capr2_bi_reg1,"
hexmask.long 0x14 0.--31. 1. "CAPR2_1,"
line.long 0x18 "PR1_IEP0__SLV__REGS_capr3_bi_reg0,"
hexmask.long 0x18 0.--31. 1. "CAPR3_0,"
line.long 0x1C "PR1_IEP0__SLV__REGS_capr3_bi_reg1,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_1,"
line.long 0x20 "PR1_IEP0__SLV__REGS_capr4_bi_reg0,"
hexmask.long 0x20 0.--31. 1. "CAPR4_0,"
line.long 0x24 "PR1_IEP0__SLV__REGS_capr4_bi_reg1,"
hexmask.long 0x24 0.--31. 1. "CAPR4_1,"
line.long 0x28 "PR1_IEP0__SLV__REGS_capr5_bi_reg0,"
hexmask.long 0x28 0.--31. 1. "CAPR5_0,"
line.long 0x2C "PR1_IEP0__SLV__REGS_capr5_bi_reg1,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_1,"
line.long 0x30 "PR1_IEP0__SLV__REGS_capr6_bi_reg0,"
hexmask.long 0x30 0.--31. 1. "CAPR6_0,"
line.long 0x34 "PR1_IEP0__SLV__REGS_capr6_bi_reg1,"
hexmask.long 0x34 0.--31. 1. "CAPR6_1,"
line.long 0x38 "PR1_IEP0__SLV__REGS_capf6_bi_reg0,"
hexmask.long 0x38 0.--31. 1. "CAPF6_0,"
line.long 0x3C "PR1_IEP0__SLV__REGS_capf6_bi_reg1,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_1,"
line.long 0x40 "PR1_IEP0__SLV__REGS_capr7_bi_reg0,"
hexmask.long 0x40 0.--31. 1. "CAPR7_0,"
line.long 0x44 "PR1_IEP0__SLV__REGS_capr7_bi_reg1,"
hexmask.long 0x44 0.--31. 1. "CAPR7_1,"
line.long 0x48 "PR1_IEP0__SLV__REGS_capf7_bi_reg0,"
hexmask.long 0x48 0.--31. 1. "CAPF7_0,"
line.long 0x4C "PR1_IEP0__SLV__REGS_capf7_bi_reg1,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_1,"
group.long 0x180++0x3
line.long 0x0 "PR1_IEP0__SLV__REGS_sync_ctrl_reg,"
bitfld.long 0x0 10. "SYNC1_OUT_NV_EN," "0,1"
bitfld.long 0x0 9. "SYNC0_OUT_NV_EN," "0,1"
bitfld.long 0x0 8. "SYNC1_IND_EN," "0,1"
bitfld.long 0x0 7. "SYNC1_CYCLIC_EN," "0,1"
newline
bitfld.long 0x0 6. "SYNC1_ACK_EN," "0,1"
bitfld.long 0x0 5. "SYNC0_CYCLIC_EN," "0,1"
bitfld.long 0x0 4. "SYNC0_ACK_EN," "0,1"
bitfld.long 0x0 2. "SYNC1_EN," "0,1"
newline
bitfld.long 0x0 1. "SYNC0_EN," "0,1"
bitfld.long 0x0 0. "SYNC_EN," "0,1"
rgroup.long 0x184++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_sync_first_stat_reg,"
bitfld.long 0x0 1. "FIRST_SYNC1," "0,1"
bitfld.long 0x0 0. "FIRST_SYNC0," "0,1"
line.long 0x4 "PR1_IEP0__SLV__REGS_sync0_stat_reg,"
bitfld.long 0x4 0. "SYNC0_PEND," "0,1"
line.long 0x8 "PR1_IEP0__SLV__REGS_sync1_stat_reg,"
bitfld.long 0x8 0. "SYNC1_PEND," "0,1"
group.long 0x190++0xF
line.long 0x0 "PR1_IEP0__SLV__REGS_sync_pwidth_reg,"
hexmask.long 0x0 0.--31. 1. "SYNC_HPW,"
line.long 0x4 "PR1_IEP0__SLV__REGS_sync0_period_reg,"
hexmask.long 0x4 0.--31. 1. "SYNC0_PERIOD,"
line.long 0x8 "PR1_IEP0__SLV__REGS_sync1_delay_reg,"
hexmask.long 0x8 0.--31. 1. "SYNC1_DELAY,"
line.long 0xC "PR1_IEP0__SLV__REGS_sync_start_reg,"
hexmask.long 0xC 0.--31. 1. "SYNC_START,"
group.long 0x200++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_wd_prediv_reg,"
hexmask.long.word 0x0 0.--15. 1. "PRE_DIV,"
line.long 0x4 "PR1_IEP0__SLV__REGS_pdi_wd_tim_reg,"
hexmask.long.word 0x4 0.--15. 1. "PDI_WD_TIME,"
line.long 0x8 "PR1_IEP0__SLV__REGS_pd_wd_tim_reg,"
hexmask.long.word 0x8 0.--15. 1. "PD_WD_TIME,"
rgroup.long 0x20C++0x3
line.long 0x0 "PR1_IEP0__SLV__REGS_wd_status_reg,"
bitfld.long 0x0 16. "PDI_WD_STAT," "0,1"
bitfld.long 0x0 0. "PD_WD_STAT," "0,1"
group.long 0x210++0x7
line.long 0x0 "PR1_IEP0__SLV__REGS_wd_exp_cnt_reg,"
hexmask.long.byte 0x0 8.--15. 1. "PD_EXP_CNT,"
hexmask.long.byte 0x0 0.--7. 1. "PDI_EXP_CNT,"
line.long 0x4 "PR1_IEP0__SLV__REGS_wd_ctrl_reg,"
bitfld.long 0x4 16. "PDI_WD_EN," "0,1"
bitfld.long 0x4 0. "PD_WD_EN," "0,1"
group.long 0x300++0x3
line.long 0x0 "PR1_IEP0__SLV__REGS_digio_ctrl_reg,"
bitfld.long 0x0 6.--7. "OUT_MODE," "0,1,2,3"
bitfld.long 0x0 4.--5. "IN_MODE," "0,1,2,3"
bitfld.long 0x0 3. "WD_MODE," "0,1"
rbitfld.long 0x0 2. "BIDI_MODE," "0,1"
newline
bitfld.long 0x0 1. "OUTVALID_MODE," "0,1"
rbitfld.long 0x0 0. "OUTVALID_POL," "0,1"
rgroup.long 0x304++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_digio_status_reg,"
hexmask.long 0x0 0.--31. 1. "DIGIO_STAT,"
line.long 0x4 "PR1_IEP0__SLV__REGS_digio_data_in_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_IN,"
line.long 0x8 "PR1_IEP0__SLV__REGS_digio_data_in_raw_reg,"
hexmask.long 0x8 0.--31. 1. "DATA_IN_RAW,"
group.long 0x310++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_digio_data_out_reg,"
hexmask.long 0x0 0.--31. 1. "DATA_OUT,"
line.long 0x4 "PR1_IEP0__SLV__REGS_digio_data_out_en_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_OUT_EN,"
line.long 0x8 "PR1_IEP0__SLV__REGS_digio_exp_reg,"
bitfld.long 0x8 13. "EOF_SEL," "0,1"
bitfld.long 0x8 12. "SOF_SEL," "0,1"
hexmask.long.byte 0x8 8.--11. 1. "SOF_DLY,"
hexmask.long.byte 0x8 4.--7. 1. "OUTVALID_DLY,"
newline
bitfld.long 0x8 2. "SW_OUTVALID," "0,1"
bitfld.long 0x8 1. "OUTVALID_OVR_EN," "0,1"
bitfld.long 0x8 0. "SW_DATA_OUT_UP," "0,1"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_IEP1"
base ad:0x2F000
group.long 0x0++0x1B
line.long 0x0 "PR1_IEP1__SLV__REGS_global_cfg_reg,"
hexmask.long.word 0x0 8.--19. 1. "CMP_INC,"
hexmask.long.byte 0x0 4.--7. 1. "DEFAULT_INC,"
bitfld.long 0x0 0. "CNT_ENABLE," "0,1"
line.long 0x4 "PR1_IEP1__SLV__REGS_global_status_reg,"
bitfld.long 0x4 0. "CNT_OVF," "0,1"
line.long 0x8 "PR1_IEP1__SLV__REGS_compen_reg,"
hexmask.long.tbyte 0x8 0.--22. 1. "COMPEN_CNT,"
line.long 0xC "PR1_IEP1__SLV__REGS_slow_compen_reg,"
hexmask.long 0xC 0.--31. 1. "SLOW_COMPEN_CNT,"
line.long 0x10 "PR1_IEP1__SLV__REGS_count_reg0,"
hexmask.long 0x10 0.--31. 1. "COUNT_LO,"
line.long 0x14 "PR1_IEP1__SLV__REGS_count_reg1,"
hexmask.long 0x14 0.--31. 1. "COUNT_HI,"
line.long 0x18 "PR1_IEP1__SLV__REGS_cap_cfg_reg,"
hexmask.long.byte 0x18 18.--23. 1. "EXT_CAP_EN,"
hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN,"
hexmask.long.word 0x18 0.--9. 1. "CAP_EN,"
rgroup.long 0x1C++0x53
line.long 0x0 "PR1_IEP1__SLV__REGS_cap_status_reg,"
hexmask.long.byte 0x0 16.--23. 1. "CAP_RAW,"
hexmask.long.word 0x0 0.--10. 1. "CAP_VALID,"
line.long 0x4 "PR1_IEP1__SLV__REGS_capr0_reg0,"
hexmask.long 0x4 0.--31. 1. "CAPR0_0,"
line.long 0x8 "PR1_IEP1__SLV__REGS_capr0_reg1,"
hexmask.long 0x8 0.--31. 1. "CAPR0_1,"
line.long 0xC "PR1_IEP1__SLV__REGS_capr1_reg0,"
hexmask.long 0xC 0.--31. 1. "CAPR1_0,"
line.long 0x10 "PR1_IEP1__SLV__REGS_capr1_reg1,"
hexmask.long 0x10 0.--31. 1. "CAPR1_1,"
line.long 0x14 "PR1_IEP1__SLV__REGS_capr2_reg0,"
hexmask.long 0x14 0.--31. 1. "CAPR2_0,"
line.long 0x18 "PR1_IEP1__SLV__REGS_capr2_reg1,"
hexmask.long 0x18 0.--31. 1. "CAPR2_1,"
line.long 0x1C "PR1_IEP1__SLV__REGS_capr3_reg0,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_0,"
line.long 0x20 "PR1_IEP1__SLV__REGS_capr3_reg1,"
hexmask.long 0x20 0.--31. 1. "CAPR3_1,"
line.long 0x24 "PR1_IEP1__SLV__REGS_capr4_reg0,"
hexmask.long 0x24 0.--31. 1. "CAPR4_0,"
line.long 0x28 "PR1_IEP1__SLV__REGS_capr4_reg1,"
hexmask.long 0x28 0.--31. 1. "CAPR4_1,"
line.long 0x2C "PR1_IEP1__SLV__REGS_capr5_reg0,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_0,"
line.long 0x30 "PR1_IEP1__SLV__REGS_capr5_reg1,"
hexmask.long 0x30 0.--31. 1. "CAPR5_1,"
line.long 0x34 "PR1_IEP1__SLV__REGS_capr6_reg0,"
hexmask.long 0x34 0.--31. 1. "CAPR6_0,"
line.long 0x38 "PR1_IEP1__SLV__REGS_capr6_reg1,"
hexmask.long 0x38 0.--31. 1. "CAPR6_1,"
line.long 0x3C "PR1_IEP1__SLV__REGS_capf6_reg0,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_0,"
line.long 0x40 "PR1_IEP1__SLV__REGS_capf6_reg1,"
hexmask.long 0x40 0.--31. 1. "CAPF6_1,"
line.long 0x44 "PR1_IEP1__SLV__REGS_capr7_reg0,"
hexmask.long 0x44 0.--31. 1. "CAPR7_0,"
line.long 0x48 "PR1_IEP1__SLV__REGS_capr7_reg1,"
hexmask.long 0x48 0.--31. 1. "CAPR7_1,"
line.long 0x4C "PR1_IEP1__SLV__REGS_capf7_reg0,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_0,"
line.long 0x50 "PR1_IEP1__SLV__REGS_capf7_reg1,"
hexmask.long 0x50 0.--31. 1. "CAPF7_1,"
group.long 0x70++0x9B
line.long 0x0 "PR1_IEP1__SLV__REGS_cmp_cfg_reg,"
bitfld.long 0x0 17. "SHADOW_EN," "0,1"
hexmask.long.word 0x0 1.--16. 1. "CMP_EN,"
bitfld.long 0x0 0. "CMP0_RST_CNT_EN," "0,1"
line.long 0x4 "PR1_IEP1__SLV__REGS_cmp_status_reg,"
hexmask.long.word 0x4 0.--15. 1. "CMP_STATUS,"
line.long 0x8 "PR1_IEP1__SLV__REGS_cmp0_reg0,"
hexmask.long 0x8 0.--31. 1. "CMP0_0,"
line.long 0xC "PR1_IEP1__SLV__REGS_cmp0_reg1,"
hexmask.long 0xC 0.--31. 1. "CMP0_1,"
line.long 0x10 "PR1_IEP1__SLV__REGS_cmp1_reg0,"
hexmask.long 0x10 0.--31. 1. "CMP1_0,"
line.long 0x14 "PR1_IEP1__SLV__REGS_cmp1_reg1,"
hexmask.long 0x14 0.--31. 1. "CMP1_1,"
line.long 0x18 "PR1_IEP1__SLV__REGS_cmp2_reg0,"
hexmask.long 0x18 0.--31. 1. "CMP2_0,"
line.long 0x1C "PR1_IEP1__SLV__REGS_cmp2_reg1,"
hexmask.long 0x1C 0.--31. 1. "CMP2_1,"
line.long 0x20 "PR1_IEP1__SLV__REGS_cmp3_reg0,"
hexmask.long 0x20 0.--31. 1. "CMP3_0,"
line.long 0x24 "PR1_IEP1__SLV__REGS_cmp3_reg1,"
hexmask.long 0x24 0.--31. 1. "CMP3_1,"
line.long 0x28 "PR1_IEP1__SLV__REGS_cmp4_reg0,"
hexmask.long 0x28 0.--31. 1. "CMP4_0,"
line.long 0x2C "PR1_IEP1__SLV__REGS_cmp4_reg1,"
hexmask.long 0x2C 0.--31. 1. "CMP4_1,"
line.long 0x30 "PR1_IEP1__SLV__REGS_cmp5_reg0,"
hexmask.long 0x30 0.--31. 1. "CMP5_0,"
line.long 0x34 "PR1_IEP1__SLV__REGS_cmp5_reg1,"
hexmask.long 0x34 0.--31. 1. "CMP5_1,"
line.long 0x38 "PR1_IEP1__SLV__REGS_cmp6_reg0,"
hexmask.long 0x38 0.--31. 1. "CMP6_0,"
line.long 0x3C "PR1_IEP1__SLV__REGS_cmp6_reg1,"
hexmask.long 0x3C 0.--31. 1. "CMP6_1,"
line.long 0x40 "PR1_IEP1__SLV__REGS_cmp7_reg0,"
hexmask.long 0x40 0.--31. 1. "CMP7_0,"
line.long 0x44 "PR1_IEP1__SLV__REGS_cmp7_reg1,"
hexmask.long 0x44 0.--31. 1. "CMP7_1,"
line.long 0x48 "PR1_IEP1__SLV__REGS_rxipg0_reg,"
hexmask.long.word 0x48 16.--31. 1. "RX_MIN_IPG0,"
hexmask.long.word 0x48 0.--15. 1. "RX_IPG0,"
line.long 0x4C "PR1_IEP1__SLV__REGS_rxipg1_reg,"
hexmask.long.word 0x4C 16.--31. 1. "RX_MIN_IPG1,"
hexmask.long.word 0x4C 0.--15. 1. "RX_IPG1,"
line.long 0x50 "PR1_IEP1__SLV__REGS_cmp8_reg0,"
hexmask.long 0x50 0.--31. 1. "CMP8_0,"
line.long 0x54 "PR1_IEP1__SLV__REGS_cmp8_reg1,"
hexmask.long 0x54 0.--31. 1. "CMP8_1,"
line.long 0x58 "PR1_IEP1__SLV__REGS_cmp9_reg0,"
hexmask.long 0x58 0.--31. 1. "CMP9_0,"
line.long 0x5C "PR1_IEP1__SLV__REGS_cmp9_reg1,"
hexmask.long 0x5C 0.--31. 1. "CMP9_1,"
line.long 0x60 "PR1_IEP1__SLV__REGS_cmp10_reg0,"
hexmask.long 0x60 0.--31. 1. "CMP10_0,"
line.long 0x64 "PR1_IEP1__SLV__REGS_cmp10_reg1,"
hexmask.long 0x64 0.--31. 1. "CMP10_1,"
line.long 0x68 "PR1_IEP1__SLV__REGS_cmp11_reg0,"
hexmask.long 0x68 0.--31. 1. "CMP11_0,"
line.long 0x6C "PR1_IEP1__SLV__REGS_cmp11_reg1,"
hexmask.long 0x6C 0.--31. 1. "CMP11_1,"
line.long 0x70 "PR1_IEP1__SLV__REGS_cmp12_reg0,"
hexmask.long 0x70 0.--31. 1. "CMP12_0,"
line.long 0x74 "PR1_IEP1__SLV__REGS_cmp12_reg1,"
hexmask.long 0x74 0.--31. 1. "CMP12_1,"
line.long 0x78 "PR1_IEP1__SLV__REGS_cmp13_reg0,"
hexmask.long 0x78 0.--31. 1. "CMP13_0,"
line.long 0x7C "PR1_IEP1__SLV__REGS_cmp13_reg1,"
hexmask.long 0x7C 0.--31. 1. "CMP13_1,"
line.long 0x80 "PR1_IEP1__SLV__REGS_cmp14_reg0,"
hexmask.long 0x80 0.--31. 1. "CMP14_0,"
line.long 0x84 "PR1_IEP1__SLV__REGS_cmp14_reg1,"
hexmask.long 0x84 0.--31. 1. "CMP14_1,"
line.long 0x88 "PR1_IEP1__SLV__REGS_cmp15_reg0,"
hexmask.long 0x88 0.--31. 1. "CMP15_0,"
line.long 0x8C "PR1_IEP1__SLV__REGS_cmp15_reg1,"
hexmask.long 0x8C 0.--31. 1. "CMP15_1,"
line.long 0x90 "PR1_IEP1__SLV__REGS_count_reset_val_reg0,"
hexmask.long 0x90 0.--31. 1. "RESET_VAL_0,"
line.long 0x94 "PR1_IEP1__SLV__REGS_count_reset_val_reg1,"
hexmask.long 0x94 0.--31. 1. "RESET_VAL_1,"
line.long 0x98 "PR1_IEP1__SLV__REGS_pwm_reg,"
bitfld.long 0x98 3. "PWM3_HIT," "0,1"
bitfld.long 0x98 2. "PWM3_RST_CNT_EN," "0,1"
bitfld.long 0x98 1. "PWM0_HIT," "0,1"
bitfld.long 0x98 0. "PWM0_RST_CNT_EN," "0,1"
rgroup.long 0x10C++0x4F
line.long 0x0 "PR1_IEP1__SLV__REGS_capr0_bi_reg0,"
hexmask.long 0x0 0.--31. 1. "CAPR0_0,"
line.long 0x4 "PR1_IEP1__SLV__REGS_capr0_bi_reg1,"
hexmask.long 0x4 0.--31. 1. "CAPR0_1,"
line.long 0x8 "PR1_IEP1__SLV__REGS_capr1_bi_reg0,"
hexmask.long 0x8 0.--31. 1. "CAPR1_0,"
line.long 0xC "PR1_IEP1__SLV__REGS_capr1_bi_reg1,"
hexmask.long 0xC 0.--31. 1. "CAPR1_1,"
line.long 0x10 "PR1_IEP1__SLV__REGS_capr2_bi_reg0,"
hexmask.long 0x10 0.--31. 1. "CAPR2_0,"
line.long 0x14 "PR1_IEP1__SLV__REGS_capr2_bi_reg1,"
hexmask.long 0x14 0.--31. 1. "CAPR2_1,"
line.long 0x18 "PR1_IEP1__SLV__REGS_capr3_bi_reg0,"
hexmask.long 0x18 0.--31. 1. "CAPR3_0,"
line.long 0x1C "PR1_IEP1__SLV__REGS_capr3_bi_reg1,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_1,"
line.long 0x20 "PR1_IEP1__SLV__REGS_capr4_bi_reg0,"
hexmask.long 0x20 0.--31. 1. "CAPR4_0,"
line.long 0x24 "PR1_IEP1__SLV__REGS_capr4_bi_reg1,"
hexmask.long 0x24 0.--31. 1. "CAPR4_1,"
line.long 0x28 "PR1_IEP1__SLV__REGS_capr5_bi_reg0,"
hexmask.long 0x28 0.--31. 1. "CAPR5_0,"
line.long 0x2C "PR1_IEP1__SLV__REGS_capr5_bi_reg1,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_1,"
line.long 0x30 "PR1_IEP1__SLV__REGS_capr6_bi_reg0,"
hexmask.long 0x30 0.--31. 1. "CAPR6_0,"
line.long 0x34 "PR1_IEP1__SLV__REGS_capr6_bi_reg1,"
hexmask.long 0x34 0.--31. 1. "CAPR6_1,"
line.long 0x38 "PR1_IEP1__SLV__REGS_capf6_bi_reg0,"
hexmask.long 0x38 0.--31. 1. "CAPF6_0,"
line.long 0x3C "PR1_IEP1__SLV__REGS_capf6_bi_reg1,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_1,"
line.long 0x40 "PR1_IEP1__SLV__REGS_capr7_bi_reg0,"
hexmask.long 0x40 0.--31. 1. "CAPR7_0,"
line.long 0x44 "PR1_IEP1__SLV__REGS_capr7_bi_reg1,"
hexmask.long 0x44 0.--31. 1. "CAPR7_1,"
line.long 0x48 "PR1_IEP1__SLV__REGS_capf7_bi_reg0,"
hexmask.long 0x48 0.--31. 1. "CAPF7_0,"
line.long 0x4C "PR1_IEP1__SLV__REGS_capf7_bi_reg1,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_1,"
group.long 0x180++0x3
line.long 0x0 "PR1_IEP1__SLV__REGS_sync_ctrl_reg,"
bitfld.long 0x0 10. "SYNC1_OUT_NV_EN," "0,1"
bitfld.long 0x0 9. "SYNC0_OUT_NV_EN," "0,1"
bitfld.long 0x0 8. "SYNC1_IND_EN," "0,1"
bitfld.long 0x0 7. "SYNC1_CYCLIC_EN," "0,1"
newline
bitfld.long 0x0 6. "SYNC1_ACK_EN," "0,1"
bitfld.long 0x0 5. "SYNC0_CYCLIC_EN," "0,1"
bitfld.long 0x0 4. "SYNC0_ACK_EN," "0,1"
bitfld.long 0x0 2. "SYNC1_EN," "0,1"
newline
bitfld.long 0x0 1. "SYNC0_EN," "0,1"
bitfld.long 0x0 0. "SYNC_EN," "0,1"
rgroup.long 0x184++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_sync_first_stat_reg,"
bitfld.long 0x0 1. "FIRST_SYNC1," "0,1"
bitfld.long 0x0 0. "FIRST_SYNC0," "0,1"
line.long 0x4 "PR1_IEP1__SLV__REGS_sync0_stat_reg,"
bitfld.long 0x4 0. "SYNC0_PEND," "0,1"
line.long 0x8 "PR1_IEP1__SLV__REGS_sync1_stat_reg,"
bitfld.long 0x8 0. "SYNC1_PEND," "0,1"
group.long 0x190++0xF
line.long 0x0 "PR1_IEP1__SLV__REGS_sync_pwidth_reg,"
hexmask.long 0x0 0.--31. 1. "SYNC_HPW,"
line.long 0x4 "PR1_IEP1__SLV__REGS_sync0_period_reg,"
hexmask.long 0x4 0.--31. 1. "SYNC0_PERIOD,"
line.long 0x8 "PR1_IEP1__SLV__REGS_sync1_delay_reg,"
hexmask.long 0x8 0.--31. 1. "SYNC1_DELAY,"
line.long 0xC "PR1_IEP1__SLV__REGS_sync_start_reg,"
hexmask.long 0xC 0.--31. 1. "SYNC_START,"
group.long 0x200++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_wd_prediv_reg,"
hexmask.long.word 0x0 0.--15. 1. "PRE_DIV,"
line.long 0x4 "PR1_IEP1__SLV__REGS_pdi_wd_tim_reg,"
hexmask.long.word 0x4 0.--15. 1. "PDI_WD_TIME,"
line.long 0x8 "PR1_IEP1__SLV__REGS_pd_wd_tim_reg,"
hexmask.long.word 0x8 0.--15. 1. "PD_WD_TIME,"
rgroup.long 0x20C++0x3
line.long 0x0 "PR1_IEP1__SLV__REGS_wd_status_reg,"
bitfld.long 0x0 16. "PDI_WD_STAT," "0,1"
bitfld.long 0x0 0. "PD_WD_STAT," "0,1"
group.long 0x210++0x7
line.long 0x0 "PR1_IEP1__SLV__REGS_wd_exp_cnt_reg,"
hexmask.long.byte 0x0 8.--15. 1. "PD_EXP_CNT,"
hexmask.long.byte 0x0 0.--7. 1. "PDI_EXP_CNT,"
line.long 0x4 "PR1_IEP1__SLV__REGS_wd_ctrl_reg,"
bitfld.long 0x4 16. "PDI_WD_EN," "0,1"
bitfld.long 0x4 0. "PD_WD_EN," "0,1"
group.long 0x300++0x3
line.long 0x0 "PR1_IEP1__SLV__REGS_digio_ctrl_reg,"
bitfld.long 0x0 6.--7. "OUT_MODE," "0,1,2,3"
bitfld.long 0x0 4.--5. "IN_MODE," "0,1,2,3"
bitfld.long 0x0 3. "WD_MODE," "0,1"
rbitfld.long 0x0 2. "BIDI_MODE," "0,1"
newline
bitfld.long 0x0 1. "OUTVALID_MODE," "0,1"
rbitfld.long 0x0 0. "OUTVALID_POL," "0,1"
rgroup.long 0x304++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_digio_status_reg,"
hexmask.long 0x0 0.--31. 1. "DIGIO_STAT,"
line.long 0x4 "PR1_IEP1__SLV__REGS_digio_data_in_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_IN,"
line.long 0x8 "PR1_IEP1__SLV__REGS_digio_data_in_raw_reg,"
hexmask.long 0x8 0.--31. 1. "DATA_IN_RAW,"
group.long 0x310++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_digio_data_out_reg,"
hexmask.long 0x0 0.--31. 1. "DATA_OUT,"
line.long 0x4 "PR1_IEP1__SLV__REGS_digio_data_out_en_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_OUT_EN,"
line.long 0x8 "PR1_IEP1__SLV__REGS_digio_exp_reg,"
bitfld.long 0x8 13. "EOF_SEL," "0,1"
bitfld.long 0x8 12. "SOF_SEL," "0,1"
hexmask.long.byte 0x8 8.--11. 1. "SOF_DLY,"
hexmask.long.byte 0x8 4.--7. 1. "OUTVALID_DLY,"
newline
bitfld.long 0x8 2. "SW_OUTVALID," "0,1"
bitfld.long 0x8 1. "OUTVALID_OVR_EN," "0,1"
bitfld.long 0x8 0. "SW_DATA_OUT_UP," "0,1"
tree.end
endif
tree "PRU_ICSSG0_PA_STAT"
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_QSTAT (PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_QSTAT)"
base ad:0x30027000
group.long 0x0++0x3
line.long 0x0 "PA_STAT_WRAP__PA_SLV__QSTAT_QRAM,query mode RAM"
hexmask.long 0x0 0.--31. 1. "VALUE,query statistic"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_CSTAT (PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_CSTAT)"
base ad:0x3002C000
group.long 0x0++0x3
line.long 0x0 "PA_STAT_WRAP__PA_SLV__CSTAT_CRAM,query mode RAM"
hexmask.long 0x0 0.--31. 1. "VALUE,collect statistic"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_QSTAT"
base ad:0x27000
group.long 0x0++0x3
line.long 0x0 "PA_STAT_WRAP__PA_SLV__QSTAT_QRAM,query mode RAM"
hexmask.long 0x0 0.--31. 1. "VALUE,query statistic"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_CSTAT"
base ad:0x2C000
group.long 0x0++0x3
line.long 0x0 "PA_STAT_WRAP__PA_SLV__CSTAT_CRAM,query mode RAM"
hexmask.long 0x0 0.--31. 1. "VALUE,collect statistic"
tree.end
endif
tree.end
tree "PRU_ICSSG0_PR1"
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_PROT_SLV (PRU_ICSSG0_PR1_PROT_SLV)"
base ad:0x30024C00
group.long 0x0++0x7
line.long 0x0 "PR1_PROTECT__SLV__REGS_unlock_key,"
hexmask.long 0x0 0.--31. 1. "UNLOCK_KEY,UnLock Key Pattern 0x83E7_0B13 to UnLock 0x0000_0000 to Lock Must unlock to update MMRs"
line.long 0x4 "PR1_PROTECT__SLV__REGS_cfg,Config"
bitfld.long 0x4 6. "PRU1_DMEM1_LOCK_EN,Write Protect DMEM1 0: disable 1: enable When enabled only PRU1 can write to DMEM1" "0: disable,1: enable When enabled only PRU1 can write to DMEM1"
newline
bitfld.long 0x4 5. "PRU0_DMEM0_LOCK_EN,Write Protect DMEM0 0: disable 1: enable When enabled only PRU0 can write to DMEM0" "0: disable,1: enable When enabled only PRU0 can write to DMEM0"
newline
bitfld.long 0x4 4. "ICSS_CFG_WP_EN,Write Protect ICSS_CFG 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 3. "RTU1_PRU_WP_EN,Write Protect RTU1_PRU access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 2. "RTU0_PRU_WP_EN,Write Protect RTU0_PRU access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 1. "PRU1_WP_EN,Write Protect PRU1 access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 0. "PRU0_WP_EN,Write Protect PRU0 access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_CFG_SLV (PRU_ICSSG0_PR1_CFG_SLV)"
base ad:0x30026000
rgroup.long 0x0++0x7
line.long 0x0 "PR1_CFG__SLV__REGS_pid_reg,"
hexmask.long 0x0 0.--31. 1. "ICSS_IDVER,Module ID field"
line.long 0x4 "PR1_CFG__SLV__REGS_hwdis_reg,"
hexmask.long.byte 0x4 0.--7. 1. "HWDIS,HW Disable Observation"
group.long 0x8++0x17
line.long 0x0 "PR1_CFG__SLV__REGS_gpcfg0_reg,"
hexmask.long.byte 0x0 26.--29. 1. "PR1_PRU0_GP_MUX_SEL,"
rbitfld.long 0x0 25. "PRU0_GPO_SH1_SEL," "0,1"
newline
hexmask.long.byte 0x0 20.--24. 1. "PRU0_GPO_DIV1,"
hexmask.long.byte 0x0 15.--19. 1. "PRU0_GPO_DIV0,"
newline
bitfld.long 0x0 14. "PRU0_GPO_MODE," "0,1"
bitfld.long 0x0 13. "PRU0_GPI_SB," "0,1"
newline
hexmask.long.byte 0x0 8.--12. 1. "PRU0_GPI_DIV1,"
hexmask.long.byte 0x0 3.--7. 1. "PRU0_GPI_DIV0,"
newline
bitfld.long 0x0 2. "PRU0_GPI_CLK_MODE," "0,1"
bitfld.long 0x0 0.--1. "PRU0_GPI_MODE," "0,1,2,3"
line.long 0x4 "PR1_CFG__SLV__REGS_gpcfg1_reg,"
hexmask.long.byte 0x4 26.--29. 1. "PR1_PRU1_GP_MUX_SEL,"
rbitfld.long 0x4 25. "PRU1_GPO_SH1_SEL," "0,1"
newline
hexmask.long.byte 0x4 20.--24. 1. "PRU1_GPO_DIV1,"
hexmask.long.byte 0x4 15.--19. 1. "PRU1_GPO_DIV0,"
newline
bitfld.long 0x4 14. "PRU1_GPO_MODE," "0,1"
bitfld.long 0x4 13. "PRU1_GPI_SB," "0,1"
newline
hexmask.long.byte 0x4 8.--12. 1. "PRU1_GPI_DIV1,"
hexmask.long.byte 0x4 3.--7. 1. "PRU1_GPI_DIV0,"
newline
bitfld.long 0x4 2. "PRU1_GPI_CLK_MODE," "0,1"
bitfld.long 0x4 0.--1. "PRU1_GPI_MODE," "0,1,2,3"
line.long 0x8 "PR1_CFG__SLV__REGS_cgr_reg,"
bitfld.long 0x8 31. "ICSS_STOP_ACK," "0,1"
rbitfld.long 0x8 30. "ICSS_STOP_REQ," "0,1"
newline
bitfld.long 0x8 29. "ICSS_PWR_IDLE," "0,1"
bitfld.long 0x8 21. "BOTTOM_HALF_CLK_GATE_EN," "0,1"
newline
bitfld.long 0x8 20. "TOP_HALF_CLK_GATE_EN," "0,1"
bitfld.long 0x8 19. "AUTO_SLICE1_CLK_GATE_EN," "0,1"
newline
bitfld.long 0x8 18. "AUTO_SLICE0_CLK_GATE_EN," "0,1"
bitfld.long 0x8 17. "IEP_CLK_EN," "0,1"
newline
rbitfld.long 0x8 16. "IEP_CLK_STOP_ACK," "0,1"
bitfld.long 0x8 15. "IEP_CLK_STOP_REQ," "0,1"
newline
bitfld.long 0x8 14. "ECAP_CLK_EN," "0,1"
rbitfld.long 0x8 13. "ECAP_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x8 12. "ECAP_CLK_STOP_REQ," "0,1"
bitfld.long 0x8 11. "UART_CLK_EN," "0,1"
newline
rbitfld.long 0x8 10. "UART_CLK_STOP_ACK," "0,1"
bitfld.long 0x8 9. "UART_CLK_STOP_REQ," "0,1"
newline
bitfld.long 0x8 8. "INTC_CLK_EN," "0,1"
rbitfld.long 0x8 7. "INTC_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x8 6. "INTC_CLK_STOP_REQ," "0,1"
line.long 0xC "PR1_CFG__SLV__REGS_gpecfg0_reg,"
bitfld.long 0xC 17. "PRU0_GPO_SHIFT_CLK_DONE," "0,1"
bitfld.long 0xC 16. "PRU0_GPO_SHIFT_CLK_HIGH," "0,1"
newline
hexmask.long.byte 0xC 8.--15. 1. "PRU0_GPO_SHIFT_CNT,"
bitfld.long 0xC 6. "PRU0_GPO_SHIFT_GP_EN," "0,1"
newline
bitfld.long 0xC 5. "PRU0_GPO_SHIFT_CLK_FREE," "0,1"
bitfld.long 0xC 4. "PRU0_GPO_SHIFT_SWAP," "0,1"
newline
bitfld.long 0xC 1. "PRU0_GPI_SHIFT_EN," "0,1"
bitfld.long 0xC 0. "PRU0_GPI_SB_P," "0,1"
line.long 0x10 "PR1_CFG__SLV__REGS_gpecfg1_reg,"
bitfld.long 0x10 17. "PRU1_GPO_SHIFT_CLK_DONE," "0,1"
bitfld.long 0x10 16. "PRU1_GPO_SHIFT_CLK_HIGH," "0,1"
newline
hexmask.long.byte 0x10 8.--15. 1. "PRU1_GPO_SHIFT_CNT,"
bitfld.long 0x10 6. "PRU1_GPO_SHIFT_GP_EN," "0,1"
newline
bitfld.long 0x10 5. "PRU1_GPO_SHIFT_CLK_FREE," "0,1"
bitfld.long 0x10 4. "PRU1_GPO_SHIFT_SWAP," "0,1"
newline
bitfld.long 0x10 1. "PRU1_GPI_SHIFT_EN," "0,1"
bitfld.long 0x10 0. "PRU1_GPI_SB_P," "0,1"
line.long 0x14 "PR1_CFG__SLV__REGS_reset_iso_reg,"
bitfld.long 0x14 2. "RESET_ISO_EDGE," "0,1"
bitfld.long 0x14 1. "RESET_ISO_ACK," "0,1"
newline
bitfld.long 0x14 0. "RESET_ISO_REQ," "0,1"
group.long 0x2C++0xB
line.long 0x0 "PR1_CFG__SLV__REGS_mii_rt_reg,"
bitfld.long 0x0 0. "MII_RT_EVENT_EN," "0,1"
line.long 0x4 "PR1_CFG__SLV__REGS_iepclk_reg,"
bitfld.long 0x4 1. "IEP1_SLV_EN," "0,1"
bitfld.long 0x4 0. "IEP_OCP_CLK_EN," "0,1"
line.long 0x8 "PR1_CFG__SLV__REGS_spp_reg,"
bitfld.long 0x8 3. "RTU_XFR_SHIFT_EN," "0,1"
bitfld.long 0x8 2. "XFR_BYTE_SHIFT_EN," "0,1"
newline
bitfld.long 0x8 1. "XFR_SHIFT_EN," "0,1"
bitfld.long 0x8 0. "PRU1_PAD_HP_EN," "0,1"
group.long 0x3C++0x9F
line.long 0x0 "PR1_CFG__SLV__REGS_core_sync_reg,"
bitfld.long 0x0 0. "CORE_VBUSP_SYNC_EN," "0,1"
line.long 0x4 "PR1_CFG__SLV__REGS_sa_mx_reg,"
bitfld.long 0x4 16. "PWM_EFC_EN," "0,1"
bitfld.long 0x4 10.--11. "PWM3_REMAP_EN," "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "PWM0_REMAP_EN," "0,1,2,3"
hexmask.long.byte 0x4 0.--7. 1. "SA_MUX_SEL,"
line.long 0x8 "PR1_CFG__SLV__REGS_pru0_sd_clk_div_reg,"
hexmask.long.byte 0x8 24.--31. 1. "PRU0_SD_MAN_REC_CLK_PERIOD,"
rbitfld.long 0x8 16. "PRU0_SD_MAN_CLK_CAL_DONE," "0,1"
newline
rbitfld.long 0x8 15. "PRU0_SD_MAN_STATUS," "0,1"
hexmask.long.byte 0x8 11.--14. 1. "PRU0_SD_CH_SEL,"
newline
bitfld.long 0x8 10. "PRU0_SD_MAN_NV_DATA_EN," "0,1"
bitfld.long 0x8 9. "PRU0_SD_MAN_EN," "0,1"
newline
bitfld.long 0x8 8. "PRU0_SD_SHARE_EN," "0,1"
line.long 0xC "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg0,"
bitfld.long 0xC 22. "PRU0_FD_ZERO_MAX_0," "0,1"
hexmask.long.byte 0xC 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_0,"
newline
bitfld.long 0xC 16. "PRU0_FD_ZERO_MIN_0," "0,1"
hexmask.long.byte 0xC 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_0,"
newline
bitfld.long 0xC 4.--5. "PRU0_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0xC 2. "PRU0_SD_CLK_INV0," "0,1"
newline
bitfld.long 0xC 0.--1. "PRU0_SD_CLK_SEL0," "0,1,2,3"
line.long 0x10 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg0,"
bitfld.long 0x10 23. "PRU0_FD_EN_0," "0,1"
bitfld.long 0x10 22. "PRU0_FD_ONE_MAX_0," "0,1"
newline
hexmask.long.byte 0x10 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_0,"
bitfld.long 0x10 16. "PRU0_FD_ONE_MIN_0," "0,1"
newline
hexmask.long.byte 0x10 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_0,"
bitfld.long 0x10 8.--10. "PRU0_FD_WINDOW_SIZE_0," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 0.--7. 1. "PRU0_SD_SAMPLE_SIZE0,"
line.long 0x14 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg1,"
bitfld.long 0x14 22. "PRU0_FD_ZERO_MAX_1," "0,1"
hexmask.long.byte 0x14 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_1,"
newline
bitfld.long 0x14 16. "PRU0_FD_ZERO_MIN_1," "0,1"
hexmask.long.byte 0x14 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_1,"
newline
bitfld.long 0x14 4.--5. "PRU0_SD_ACC_SEL1," "0,1,2,3"
bitfld.long 0x14 2. "PRU0_SD_CLK_INV1," "0,1"
newline
bitfld.long 0x14 0.--1. "PRU0_SD_CLK_SEL1," "0,1,2,3"
line.long 0x18 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg1,"
bitfld.long 0x18 23. "PRU0_FD_EN_1," "0,1"
bitfld.long 0x18 22. "PRU0_FD_ONE_MAX_1," "0,1"
newline
hexmask.long.byte 0x18 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_1,"
bitfld.long 0x18 16. "PRU0_FD_ONE_MIN_1," "0,1"
newline
hexmask.long.byte 0x18 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_1,"
bitfld.long 0x18 8.--10. "PRU0_FD_WINDOW_SIZE_1," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x18 0.--7. 1. "PRU0_SD_SAMPLE_SIZE1,"
line.long 0x1C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg2,"
bitfld.long 0x1C 22. "PRU0_FD_ZERO_MAX_2," "0,1"
hexmask.long.byte 0x1C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_2,"
newline
bitfld.long 0x1C 16. "PRU0_FD_ZERO_MIN_2," "0,1"
hexmask.long.byte 0x1C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_2,"
newline
bitfld.long 0x1C 4.--5. "PRU0_SD_ACC_SEL2," "0,1,2,3"
bitfld.long 0x1C 2. "PRU0_SD_CLK_INV2," "0,1"
newline
bitfld.long 0x1C 0.--1. "PRU0_SD_CLK_SEL2," "0,1,2,3"
line.long 0x20 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg2,"
bitfld.long 0x20 23. "PRU0_FD_EN_2," "0,1"
bitfld.long 0x20 22. "PRU0_FD_ONE_MAX_2," "0,1"
newline
hexmask.long.byte 0x20 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_2,"
bitfld.long 0x20 16. "PRU0_FD_ONE_MIN_2," "0,1"
newline
hexmask.long.byte 0x20 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_2,"
bitfld.long 0x20 8.--10. "PRU0_FD_WINDOW_SIZE_2," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x20 0.--7. 1. "PRU0_SD_SAMPLE_SIZE2,"
line.long 0x24 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg3,"
bitfld.long 0x24 22. "PRU0_FD_ZERO_MAX_3," "0,1"
hexmask.long.byte 0x24 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_3,"
newline
bitfld.long 0x24 16. "PRU0_FD_ZERO_MIN_3," "0,1"
hexmask.long.byte 0x24 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_3,"
newline
bitfld.long 0x24 4.--5. "PRU0_SD_ACC_SEL3," "0,1,2,3"
bitfld.long 0x24 2. "PRU0_SD_CLK_INV3," "0,1"
newline
bitfld.long 0x24 0.--1. "PRU0_SD_CLK_SEL3," "0,1,2,3"
line.long 0x28 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg3,"
bitfld.long 0x28 23. "PRU0_FD_EN_3," "0,1"
bitfld.long 0x28 22. "PRU0_FD_ONE_MAX_3," "0,1"
newline
hexmask.long.byte 0x28 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_3,"
bitfld.long 0x28 16. "PRU0_FD_ONE_MIN_3," "0,1"
newline
hexmask.long.byte 0x28 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_3,"
bitfld.long 0x28 8.--10. "PRU0_FD_WINDOW_SIZE_3," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 0.--7. 1. "PRU0_SD_SAMPLE_SIZE3,"
line.long 0x2C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg4,"
bitfld.long 0x2C 22. "PRU0_FD_ZERO_MAX_4," "0,1"
hexmask.long.byte 0x2C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_4,"
newline
bitfld.long 0x2C 16. "PRU0_FD_ZERO_MIN_4," "0,1"
hexmask.long.byte 0x2C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_4,"
newline
bitfld.long 0x2C 4.--5. "PRU0_SD_ACC_SEL4," "0,1,2,3"
bitfld.long 0x2C 2. "PRU0_SD_CLK_INV4," "0,1"
newline
bitfld.long 0x2C 0.--1. "PRU0_SD_CLK_SEL4," "0,1,2,3"
line.long 0x30 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg4,"
bitfld.long 0x30 23. "PRU0_FD_EN_4," "0,1"
bitfld.long 0x30 22. "PRU0_FD_ONE_MAX_4," "0,1"
newline
hexmask.long.byte 0x30 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_4,"
bitfld.long 0x30 16. "PRU0_FD_ONE_MIN_4," "0,1"
newline
hexmask.long.byte 0x30 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_4,"
bitfld.long 0x30 8.--10. "PRU0_FD_WINDOW_SIZE_4," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x30 0.--7. 1. "PRU0_SD_SAMPLE_SIZE4,"
line.long 0x34 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg5,"
bitfld.long 0x34 22. "PRU0_FD_ZERO_MAX_5," "0,1"
hexmask.long.byte 0x34 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_5,"
newline
bitfld.long 0x34 16. "PRU0_FD_ZERO_MIN_5," "0,1"
hexmask.long.byte 0x34 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_5,"
newline
bitfld.long 0x34 4.--5. "PRU0_SD_ACC_SEL5," "0,1,2,3"
bitfld.long 0x34 2. "PRU0_SD_CLK_INV5," "0,1"
newline
bitfld.long 0x34 0.--1. "PRU0_SD_CLK_SEL5," "0,1,2,3"
line.long 0x38 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg5,"
bitfld.long 0x38 23. "PRU0_FD_EN_5," "0,1"
bitfld.long 0x38 22. "PRU0_FD_ONE_MAX_5," "0,1"
newline
hexmask.long.byte 0x38 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_5,"
bitfld.long 0x38 16. "PRU0_FD_ONE_MIN_5," "0,1"
newline
hexmask.long.byte 0x38 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_5,"
bitfld.long 0x38 8.--10. "PRU0_FD_WINDOW_SIZE_5," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x38 0.--7. 1. "PRU0_SD_SAMPLE_SIZE5,"
line.long 0x3C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg6,"
bitfld.long 0x3C 22. "PRU0_FD_ZERO_MAX_6," "0,1"
hexmask.long.byte 0x3C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_6,"
newline
bitfld.long 0x3C 16. "PRU0_FD_ZERO_MIN_6," "0,1"
hexmask.long.byte 0x3C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_6,"
newline
bitfld.long 0x3C 4.--5. "PRU0_SD_ACC_SEL6," "0,1,2,3"
bitfld.long 0x3C 2. "PRU0_SD_CLK_INV6," "0,1"
newline
bitfld.long 0x3C 0.--1. "PRU0_SD_CLK_SEL6," "0,1,2,3"
line.long 0x40 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg6,"
bitfld.long 0x40 23. "PRU0_FD_EN_6," "0,1"
bitfld.long 0x40 22. "PRU0_FD_ONE_MAX_6," "0,1"
newline
hexmask.long.byte 0x40 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_6,"
bitfld.long 0x40 16. "PRU0_FD_ONE_MIN_6," "0,1"
newline
hexmask.long.byte 0x40 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_6,"
bitfld.long 0x40 8.--10. "PRU0_FD_WINDOW_SIZE_6," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x40 0.--7. 1. "PRU0_SD_SAMPLE_SIZE6,"
line.long 0x44 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg7,"
bitfld.long 0x44 22. "PRU0_FD_ZERO_MAX_7," "0,1"
hexmask.long.byte 0x44 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_7,"
newline
bitfld.long 0x44 16. "PRU0_FD_ZERO_MIN_7," "0,1"
hexmask.long.byte 0x44 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_7,"
newline
bitfld.long 0x44 4.--5. "PRU0_SD_ACC_SEL7," "0,1,2,3"
bitfld.long 0x44 2. "PRU0_SD_CLK_INV7," "0,1"
newline
bitfld.long 0x44 0.--1. "PRU0_SD_CLK_SEL7," "0,1,2,3"
line.long 0x48 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg7,"
bitfld.long 0x48 23. "PRU0_FD_EN_7," "0,1"
bitfld.long 0x48 22. "PRU0_FD_ONE_MAX_7," "0,1"
newline
hexmask.long.byte 0x48 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_7,"
bitfld.long 0x48 16. "PRU0_FD_ONE_MIN_7," "0,1"
newline
hexmask.long.byte 0x48 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_7,"
bitfld.long 0x48 8.--10. "PRU0_FD_WINDOW_SIZE_7," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x48 0.--7. 1. "PRU0_SD_SAMPLE_SIZE7,"
line.long 0x4C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg8,"
bitfld.long 0x4C 22. "PRU0_FD_ZERO_MAX_8," "0,1"
hexmask.long.byte 0x4C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_8,"
newline
bitfld.long 0x4C 16. "PRU0_FD_ZERO_MIN_8," "0,1"
hexmask.long.byte 0x4C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_8,"
newline
bitfld.long 0x4C 4.--5. "PRU0_SD_ACC_SEL8," "0,1,2,3"
bitfld.long 0x4C 2. "PRU0_SD_CLK_INV8," "0,1"
newline
bitfld.long 0x4C 0.--1. "PRU0_SD_CLK_SEL8," "0,1,2,3"
line.long 0x50 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg8,"
bitfld.long 0x50 23. "PRU0_FD_EN_8," "0,1"
bitfld.long 0x50 22. "PRU0_FD_ONE_MAX_8," "0,1"
newline
hexmask.long.byte 0x50 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_8,"
bitfld.long 0x50 16. "PRU0_FD_ONE_MIN_8," "0,1"
newline
hexmask.long.byte 0x50 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_8,"
bitfld.long 0x50 8.--10. "PRU0_FD_WINDOW_SIZE_8," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x50 0.--7. 1. "PRU0_SD_SAMPLE_SIZE8,"
line.long 0x54 "PR1_CFG__SLV__REGS_pru1_sd_clk_div_reg,"
hexmask.long.byte 0x54 24.--31. 1. "PRU1_SD_MAN_REC_CLK_PERIOD,"
rbitfld.long 0x54 16. "PRU1_SD_MAN_CLK_CAL_DONE," "0,1"
newline
rbitfld.long 0x54 15. "PRU1_SD_MAN_STATUS," "0,1"
hexmask.long.byte 0x54 11.--14. 1. "PRU1_SD_CH_SEL,"
newline
bitfld.long 0x54 10. "PRU1_SD_MAN_NV_DATA_EN," "0,1"
bitfld.long 0x54 9. "PRU1_SD_MAN_EN," "0,1"
newline
bitfld.long 0x54 8. "PRU1_SD_SHARE_EN," "0,1"
line.long 0x58 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg0,"
bitfld.long 0x58 22. "PRU1_FD_ZERO_MAX_0," "0,1"
hexmask.long.byte 0x58 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_0,"
newline
bitfld.long 0x58 16. "PRU1_FD_ZERO_MIN_0," "0,1"
hexmask.long.byte 0x58 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_0,"
newline
bitfld.long 0x58 4.--5. "PRU1_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x58 2. "PRU1_SD_CLK_INV0," "0,1"
newline
bitfld.long 0x58 0.--1. "PRU1_SD_CLK_SEL0," "0,1,2,3"
line.long 0x5C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg0,"
bitfld.long 0x5C 23. "PRU1_FD_EN_0," "0,1"
bitfld.long 0x5C 22. "PRU1_FD_ONE_MAX_0," "0,1"
newline
hexmask.long.byte 0x5C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_0,"
bitfld.long 0x5C 16. "PRU1_FD_ONE_MIN_0," "0,1"
newline
hexmask.long.byte 0x5C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_0,"
bitfld.long 0x5C 8.--10. "PRU1_FD_WINDOW_SIZE_0," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x5C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE0,"
line.long 0x60 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg1,"
bitfld.long 0x60 22. "PRU1_FD_ZERO_MAX_1," "0,1"
hexmask.long.byte 0x60 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_1,"
newline
bitfld.long 0x60 16. "PRU1_FD_ZERO_MIN_1," "0,1"
hexmask.long.byte 0x60 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_1,"
newline
bitfld.long 0x60 4.--5. "PRU1_SD_ACC_SEL1," "0,1,2,3"
bitfld.long 0x60 2. "PRU1_SD_CLK_INV1," "0,1"
newline
bitfld.long 0x60 0.--1. "PRU1_SD_CLK_SEL1," "0,1,2,3"
line.long 0x64 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg1,"
bitfld.long 0x64 23. "PRU1_FD_EN_1," "0,1"
bitfld.long 0x64 22. "PRU1_FD_ONE_MAX_1," "0,1"
newline
hexmask.long.byte 0x64 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_1,"
bitfld.long 0x64 16. "PRU1_FD_ONE_MIN_1," "0,1"
newline
hexmask.long.byte 0x64 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_1,"
bitfld.long 0x64 8.--10. "PRU1_FD_WINDOW_SIZE_1," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x64 0.--7. 1. "PRU1_SD_SAMPLE_SIZE1,"
line.long 0x68 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg2,"
bitfld.long 0x68 22. "PRU1_FD_ZERO_MAX_2," "0,1"
hexmask.long.byte 0x68 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_2,"
newline
bitfld.long 0x68 16. "PRU1_FD_ZERO_MIN_2," "0,1"
hexmask.long.byte 0x68 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_2,"
newline
bitfld.long 0x68 4.--5. "PRU1_SD_ACC_SEL2," "0,1,2,3"
bitfld.long 0x68 2. "PRU1_SD_CLK_INV2," "0,1"
newline
bitfld.long 0x68 0.--1. "PRU1_SD_CLK_SEL2," "0,1,2,3"
line.long 0x6C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg2,"
bitfld.long 0x6C 23. "PRU1_FD_EN_2," "0,1"
bitfld.long 0x6C 22. "PRU1_FD_ONE_MAX_2," "0,1"
newline
hexmask.long.byte 0x6C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_2,"
bitfld.long 0x6C 16. "PRU1_FD_ONE_MIN_2," "0,1"
newline
hexmask.long.byte 0x6C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_2,"
bitfld.long 0x6C 8.--10. "PRU1_FD_WINDOW_SIZE_2," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x6C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE2,"
line.long 0x70 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg3,"
bitfld.long 0x70 22. "PRU1_FD_ZERO_MAX_3," "0,1"
hexmask.long.byte 0x70 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_3,"
newline
bitfld.long 0x70 16. "PRU1_FD_ZERO_MIN_3," "0,1"
hexmask.long.byte 0x70 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_3,"
newline
bitfld.long 0x70 4.--5. "PRU1_SD_ACC_SEL3," "0,1,2,3"
bitfld.long 0x70 2. "PRU1_SD_CLK_INV3," "0,1"
newline
bitfld.long 0x70 0.--1. "PRU1_SD_CLK_SEL3," "0,1,2,3"
line.long 0x74 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg3,"
bitfld.long 0x74 23. "PRU1_FD_EN_3," "0,1"
bitfld.long 0x74 22. "PRU1_FD_ONE_MAX_3," "0,1"
newline
hexmask.long.byte 0x74 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_3,"
bitfld.long 0x74 16. "PRU1_FD_ONE_MIN_3," "0,1"
newline
hexmask.long.byte 0x74 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_3,"
bitfld.long 0x74 8.--10. "PRU1_FD_WINDOW_SIZE_3," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x74 0.--7. 1. "PRU1_SD_SAMPLE_SIZE3,"
line.long 0x78 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg4,"
bitfld.long 0x78 22. "PRU1_FD_ZERO_MAX_4," "0,1"
hexmask.long.byte 0x78 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_4,"
newline
bitfld.long 0x78 16. "PRU1_FD_ZERO_MIN_4," "0,1"
hexmask.long.byte 0x78 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_4,"
newline
bitfld.long 0x78 4.--5. "PRU1_SD_ACC_SEL4," "0,1,2,3"
bitfld.long 0x78 2. "PRU1_SD_CLK_INV4," "0,1"
newline
bitfld.long 0x78 0.--1. "PRU1_SD_CLK_SEL4," "0,1,2,3"
line.long 0x7C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg4,"
bitfld.long 0x7C 23. "PRU1_FD_EN_4," "0,1"
bitfld.long 0x7C 22. "PRU1_FD_ONE_MAX_4," "0,1"
newline
hexmask.long.byte 0x7C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_4,"
bitfld.long 0x7C 16. "PRU1_FD_ONE_MIN_4," "0,1"
newline
hexmask.long.byte 0x7C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_4,"
bitfld.long 0x7C 8.--10. "PRU1_FD_WINDOW_SIZE_4," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x7C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE4,"
line.long 0x80 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg5,"
bitfld.long 0x80 22. "PRU1_FD_ZERO_MAX_5," "0,1"
hexmask.long.byte 0x80 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_5,"
newline
bitfld.long 0x80 16. "PRU1_FD_ZERO_MIN_5," "0,1"
hexmask.long.byte 0x80 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_5,"
newline
bitfld.long 0x80 4.--5. "PRU1_SD_ACC_SEL5," "0,1,2,3"
bitfld.long 0x80 2. "PRU1_SD_CLK_INV5," "0,1"
newline
bitfld.long 0x80 0.--1. "PRU1_SD_CLK_SEL5," "0,1,2,3"
line.long 0x84 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg5,"
bitfld.long 0x84 23. "PRU1_FD_EN_5," "0,1"
bitfld.long 0x84 22. "PRU1_FD_ONE_MAX_5," "0,1"
newline
hexmask.long.byte 0x84 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_5,"
bitfld.long 0x84 16. "PRU1_FD_ONE_MIN_5," "0,1"
newline
hexmask.long.byte 0x84 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_5,"
bitfld.long 0x84 8.--10. "PRU1_FD_WINDOW_SIZE_5," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x84 0.--7. 1. "PRU1_SD_SAMPLE_SIZE5,"
line.long 0x88 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg6,"
bitfld.long 0x88 22. "PRU1_FD_ZERO_MAX_6," "0,1"
hexmask.long.byte 0x88 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_6,"
newline
bitfld.long 0x88 16. "PRU1_FD_ZERO_MIN_6," "0,1"
hexmask.long.byte 0x88 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_6,"
newline
bitfld.long 0x88 4.--5. "PRU1_SD_ACC_SEL6," "0,1,2,3"
bitfld.long 0x88 2. "PRU1_SD_CLK_INV6," "0,1"
newline
bitfld.long 0x88 0.--1. "PRU1_SD_CLK_SEL6," "0,1,2,3"
line.long 0x8C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg6,"
bitfld.long 0x8C 23. "PRU1_FD_EN_6," "0,1"
bitfld.long 0x8C 22. "PRU1_FD_ONE_MAX_6," "0,1"
newline
hexmask.long.byte 0x8C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_6,"
bitfld.long 0x8C 16. "PRU1_FD_ONE_MIN_6," "0,1"
newline
hexmask.long.byte 0x8C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_6,"
bitfld.long 0x8C 8.--10. "PRU1_FD_WINDOW_SIZE_6," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE6,"
line.long 0x90 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg7,"
bitfld.long 0x90 22. "PRU1_FD_ZERO_MAX_7," "0,1"
hexmask.long.byte 0x90 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_7,"
newline
bitfld.long 0x90 16. "PRU1_FD_ZERO_MIN_7," "0,1"
hexmask.long.byte 0x90 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_7,"
newline
bitfld.long 0x90 4.--5. "PRU1_SD_ACC_SEL7," "0,1,2,3"
bitfld.long 0x90 2. "PRU1_SD_CLK_INV7," "0,1"
newline
bitfld.long 0x90 0.--1. "PRU1_SD_CLK_SEL7," "0,1,2,3"
line.long 0x94 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg7,"
bitfld.long 0x94 23. "PRU1_FD_EN_7," "0,1"
bitfld.long 0x94 22. "PRU1_FD_ONE_MAX_7," "0,1"
newline
hexmask.long.byte 0x94 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_7,"
bitfld.long 0x94 16. "PRU1_FD_ONE_MIN_7," "0,1"
newline
hexmask.long.byte 0x94 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_7,"
bitfld.long 0x94 8.--10. "PRU1_FD_WINDOW_SIZE_7," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x94 0.--7. 1. "PRU1_SD_SAMPLE_SIZE7,"
line.long 0x98 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg8,"
bitfld.long 0x98 22. "PRU1_FD_ZERO_MAX_8," "0,1"
hexmask.long.byte 0x98 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_8,"
newline
bitfld.long 0x98 16. "PRU1_FD_ZERO_MIN_8," "0,1"
hexmask.long.byte 0x98 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_8,"
newline
bitfld.long 0x98 4.--5. "PRU1_SD_ACC_SEL8," "0,1,2,3"
bitfld.long 0x98 2. "PRU1_SD_CLK_INV8," "0,1"
newline
bitfld.long 0x98 0.--1. "PRU1_SD_CLK_SEL8," "0,1,2,3"
line.long 0x9C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg8,"
bitfld.long 0x9C 23. "PRU1_FD_EN_8," "0,1"
bitfld.long 0x9C 22. "PRU1_FD_ONE_MAX_8," "0,1"
newline
hexmask.long.byte 0x9C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_8,"
bitfld.long 0x9C 16. "PRU1_FD_ONE_MIN_8," "0,1"
newline
hexmask.long.byte 0x9C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_8,"
bitfld.long 0x9C 8.--10. "PRU1_FD_WINDOW_SIZE_8," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x9C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE8,"
group.long 0xE0++0x3F
line.long 0x0 "PR1_CFG__SLV__REGS_pru0_ed_rx_cfg_reg,"
hexmask.long.word 0x0 16.--31. 1. "PRU0_ED_RX_DIV_FACTOR,"
bitfld.long 0x0 15. "PRU0_ED_RX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x0 4. "PRU0_ED_RX_CLK_SEL," "0,1"
bitfld.long 0x0 3. "PRU0_ED_RX_SB_POL," "0,1"
newline
bitfld.long 0x0 0.--2. "PRU0_ED_RX_SAMPLE_SIZE," "0,1,2,3,4,5,6,7"
line.long 0x4 "PR1_CFG__SLV__REGS_pru0_ed_tx_cfg_reg,"
hexmask.long.word 0x4 16.--31. 1. "PRU0_ED_TX_DIV_FACTOR,"
bitfld.long 0x4 15. "PRU0_ED_TX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x4 11. "PRU0_ENDAT_SHARE_EN," "0,1"
rbitfld.long 0x4 10. "PRU0_ENDAT2_CLK_SYNC," "0,1"
newline
rbitfld.long 0x4 9. "PRU0_ENDAT1_CLK_SYNC," "0,1"
rbitfld.long 0x4 8. "PRU0_ENDAT0_CLK_SYNC," "0,1"
newline
rbitfld.long 0x4 7. "PRU0_ED_BUSY_2," "0,1"
rbitfld.long 0x4 6. "PRU0_ED_BUSY_1," "0,1"
newline
rbitfld.long 0x4 5. "PRU0_ED_BUSY_0," "0,1"
bitfld.long 0x4 4. "PRU0_ED_TX_CLK_SEL," "0,1"
line.long 0x8 "PR1_CFG__SLV__REGS_pru0_ed_ch0_cfg0_reg,"
bitfld.long 0x8 31. "PRU0_ED_TX_FIFO_SWAP_BITS0," "0,1"
bitfld.long 0x8 30. "PRU0_ED_SW_CLK_OUT0," "0,1"
newline
bitfld.long 0x8 29. "PRU0_ED_CLK_OUT_OVR_EN0," "0,1"
rbitfld.long 0x8 28. "PRU0_ED_RX_SNOOP0," "0,1"
newline
hexmask.long.word 0x8 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE0,"
hexmask.long.byte 0x8 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE0,"
newline
hexmask.long.word 0x8 0.--10. 1. "PRU0_ED_TX_WDLY0,"
line.long 0xC "PR1_CFG__SLV__REGS_pru0_ed_ch0_cfg1_reg,"
hexmask.long.word 0xC 16.--31. 1. "PRU0_ED_RX_EN_COUNTER0,"
hexmask.long.word 0xC 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER0,"
line.long 0x10 "PR1_CFG__SLV__REGS_pru0_ed_ch1_cfg0_reg,"
bitfld.long 0x10 31. "PRU0_ED_TX_FIFO_SWAP_BITS1," "0,1"
bitfld.long 0x10 30. "PRU0_ED_SW_CLK_OUT1," "0,1"
newline
bitfld.long 0x10 29. "PRU0_ED_CLK_OUT_OVR_EN1," "0,1"
rbitfld.long 0x10 28. "PRU0_ED_RX_SNOOP1," "0,1"
newline
hexmask.long.word 0x10 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE1,"
hexmask.long.byte 0x10 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE1,"
newline
hexmask.long.word 0x10 0.--10. 1. "PRU0_ED_TX_WDLY1,"
line.long 0x14 "PR1_CFG__SLV__REGS_pru0_ed_ch1_cfg1_reg,"
hexmask.long.word 0x14 16.--31. 1. "PRU0_ED_RX_EN_COUNTER1,"
hexmask.long.word 0x14 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER1,"
line.long 0x18 "PR1_CFG__SLV__REGS_pru0_ed_ch2_cfg0_reg,"
bitfld.long 0x18 31. "PRU0_ED_TX_FIFO_SWAP_BITS2," "0,1"
bitfld.long 0x18 30. "PRU0_ED_SW_CLK_OUT2," "0,1"
newline
bitfld.long 0x18 29. "PRU0_ED_CLK_OUT_OVR_EN2," "0,1"
rbitfld.long 0x18 28. "PRU0_ED_RX_SNOOP2," "0,1"
newline
hexmask.long.word 0x18 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE2,"
hexmask.long.byte 0x18 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE2,"
newline
hexmask.long.word 0x18 0.--10. 1. "PRU0_ED_TX_WDLY2,"
line.long 0x1C "PR1_CFG__SLV__REGS_pru0_ed_ch2_cfg1_reg,"
hexmask.long.word 0x1C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER2,"
hexmask.long.word 0x1C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER2,"
line.long 0x20 "PR1_CFG__SLV__REGS_pru1_ed_rx_cfg_reg,"
hexmask.long.word 0x20 16.--31. 1. "PRU1_ED_RX_DIV_FACTOR,"
bitfld.long 0x20 15. "PRU1_ED_RX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x20 4. "PRU1_ED_RX_CLK_SEL," "0,1"
bitfld.long 0x20 3. "PRU1_ED_RX_SB_POL," "0,1"
newline
bitfld.long 0x20 0.--2. "PRU1_ED_RX_SAMPLE_SIZE," "0,1,2,3,4,5,6,7"
line.long 0x24 "PR1_CFG__SLV__REGS_pru1_ed_tx_cfg_reg,"
hexmask.long.word 0x24 16.--31. 1. "PRU1_ED_TX_DIV_FACTOR,"
bitfld.long 0x24 15. "PRU1_ED_TX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x24 11. "PRU1_ENDAT_SHARE_EN," "0,1"
rbitfld.long 0x24 10. "PRU1_ENDAT2_CLK_SYNC," "0,1"
newline
rbitfld.long 0x24 9. "PRU1_ENDAT1_CLK_SYNC," "0,1"
rbitfld.long 0x24 8. "PRU1_ENDAT0_CLK_SYNC," "0,1"
newline
rbitfld.long 0x24 7. "PRU1_ED_BUSY_2," "0,1"
rbitfld.long 0x24 6. "PRU1_ED_BUSY_1," "0,1"
newline
rbitfld.long 0x24 5. "PRU1_ED_BUSY_0," "0,1"
bitfld.long 0x24 4. "PRU1_ED_TX_CLK_SEL," "0,1"
line.long 0x28 "PR1_CFG__SLV__REGS_pru1_ed_ch0_cfg0_reg,"
bitfld.long 0x28 31. "PRU1_ED_TX_FIFO_SWAP_BITS0," "0,1"
bitfld.long 0x28 30. "PRU1_ED_SW_CLK_OUT0," "0,1"
newline
bitfld.long 0x28 29. "PRU1_ED_CLK_OUT_OVR_EN0," "0,1"
rbitfld.long 0x28 28. "PRU1_ED_RX_SNOOP0," "0,1"
newline
hexmask.long.word 0x28 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE0,"
hexmask.long.byte 0x28 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE0,"
newline
hexmask.long.word 0x28 0.--10. 1. "PRU1_ED_TX_WDLY0,"
line.long 0x2C "PR1_CFG__SLV__REGS_pru1_ed_ch0_cfg1_reg,"
hexmask.long.word 0x2C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER0,"
hexmask.long.word 0x2C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER0,"
line.long 0x30 "PR1_CFG__SLV__REGS_pru1_ed_ch1_cfg0_reg,"
bitfld.long 0x30 31. "PRU1_ED_TX_FIFO_SWAP_BITS1," "0,1"
bitfld.long 0x30 30. "PRU1_ED_SW_CLK_OUT1," "0,1"
newline
bitfld.long 0x30 29. "PRU1_ED_CLK_OUT_OVR_EN1," "0,1"
rbitfld.long 0x30 28. "PRU1_ED_RX_SNOOP1," "0,1"
newline
hexmask.long.word 0x30 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE1,"
hexmask.long.byte 0x30 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE1,"
newline
hexmask.long.word 0x30 0.--10. 1. "PRU1_ED_TX_WDLY1,"
line.long 0x34 "PR1_CFG__SLV__REGS_pru1_ed_ch1_cfg1_reg,"
hexmask.long.word 0x34 16.--31. 1. "PRU1_ED_RX_EN_COUNTER1,"
hexmask.long.word 0x34 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER1,"
line.long 0x38 "PR1_CFG__SLV__REGS_pru1_ed_ch2_cfg0_reg,"
bitfld.long 0x38 31. "PRU1_ED_TX_FIFO_SWAP_BITS2," "0,1"
bitfld.long 0x38 30. "PRU1_ED_SW_CLK_OUT2," "0,1"
newline
bitfld.long 0x38 29. "PRU1_ED_CLK_OUT_OVR_EN2," "0,1"
rbitfld.long 0x38 28. "PRU1_ED_RX_SNOOP2," "0,1"
newline
hexmask.long.word 0x38 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE2,"
hexmask.long.byte 0x38 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE2,"
newline
hexmask.long.word 0x38 0.--10. 1. "PRU1_ED_TX_WDLY2,"
line.long 0x3C "PR1_CFG__SLV__REGS_pru1_ed_ch2_cfg1_reg,"
hexmask.long.word 0x3C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER2,"
hexmask.long.word 0x3C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER2,"
group.long 0x124++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_rtu0_poke_en0_reg,"
hexmask.long.byte 0x0 28.--31. 1. "RTU0_POKE_R27_EN,"
hexmask.long.byte 0x0 24.--27. 1. "RTU0_POKE_R26_EN,"
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hexmask.long.byte 0x0 20.--23. 1. "RTU0_POKE_R25_EN,"
hexmask.long.byte 0x0 16.--19. 1. "RTU0_POKE_R24_EN,"
newline
hexmask.long.byte 0x0 12.--15. 1. "RTU0_POKE_R23_EN,"
hexmask.long.byte 0x0 8.--11. 1. "RTU0_POKE_R22_EN,"
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hexmask.long.byte 0x0 4.--7. 1. "RTU0_POKE_R21_EN,"
hexmask.long.byte 0x0 0.--3. 1. "RTU0_POKE_R20_EN,"
group.long 0x12C++0x4F
line.long 0x0 "PR1_CFG__SLV__REGS_rtu1_poke_en0_reg,"
hexmask.long.byte 0x0 28.--31. 1. "RTU1_POKE_R27_EN,"
hexmask.long.byte 0x0 24.--27. 1. "RTU1_POKE_R26_EN,"
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hexmask.long.byte 0x0 20.--23. 1. "RTU1_POKE_R25_EN,"
hexmask.long.byte 0x0 16.--19. 1. "RTU1_POKE_R24_EN,"
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hexmask.long.byte 0x0 12.--15. 1. "RTU1_POKE_R23_EN,"
hexmask.long.byte 0x0 8.--11. 1. "RTU1_POKE_R22_EN,"
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hexmask.long.byte 0x0 4.--7. 1. "RTU1_POKE_R21_EN,"
hexmask.long.byte 0x0 0.--3. 1. "RTU1_POKE_R20_EN,"
line.long 0x4 "PR1_CFG__SLV__REGS_pwm0,"
bitfld.long 0x4 30. "PWM0_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0x4 21.--29. 1. "PWM0_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0x4 20. "PWM0_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0x4 19. "PWM0_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0x4 18. "PWM0_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0x4 17. "PWM0_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0x4 8.--16. 1. "PWM0_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0x4 0.--7. 1. "PWM0_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0x8 "PR1_CFG__SLV__REGS_pwm1,"
bitfld.long 0x8 30. "PWM1_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0x8 21.--29. 1. "PWM1_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0x8 20. "PWM1_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0x8 19. "PWM1_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0x8 18. "PWM1_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0x8 17. "PWM1_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0x8 8.--16. 1. "PWM1_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0x8 0.--7. 1. "PWM1_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0xC "PR1_CFG__SLV__REGS_pwm2,"
bitfld.long 0xC 30. "PWM2_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0xC 21.--29. 1. "PWM2_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0xC 20. "PWM2_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0xC 19. "PWM2_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0xC 18. "PWM2_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0xC 17. "PWM2_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0xC 8.--16. 1. "PWM2_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0xC 0.--7. 1. "PWM2_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0x10 "PR1_CFG__SLV__REGS_pwm3,"
bitfld.long 0x10 30. "PWM3_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0x10 21.--29. 1. "PWM3_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0x10 20. "PWM3_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0x10 19. "PWM3_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0x10 18. "PWM3_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0x10 17. "PWM3_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0x10 8.--16. 1. "PWM3_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0x10 0.--7. 1. "PWM3_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0x14 "PR1_CFG__SLV__REGS_pwm0_0,"
bitfld.long 0x14 10.--11. "PWM0_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x14 8.--9. "PWM0_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x14 6.--7. "PWM0_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x14 4.--5. "PWM0_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "PWM0_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x14 0.--1. "PWM0_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x18 "PR1_CFG__SLV__REGS_pwm0_1,"
bitfld.long 0x18 10.--11. "PWM0_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x18 8.--9. "PWM0_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x18 6.--7. "PWM0_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x18 4.--5. "PWM0_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "PWM0_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x18 0.--1. "PWM0_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x1C "PR1_CFG__SLV__REGS_pwm0_2,"
bitfld.long 0x1C 10.--11. "PWM0_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x1C 8.--9. "PWM0_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "PWM0_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x1C 4.--5. "PWM0_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x1C 2.--3. "PWM0_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x1C 0.--1. "PWM0_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x20 "PR1_CFG__SLV__REGS_pwm1_0,"
bitfld.long 0x20 10.--11. "PWM1_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x20 8.--9. "PWM1_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x20 6.--7. "PWM1_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x20 4.--5. "PWM1_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x20 2.--3. "PWM1_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x20 0.--1. "PWM1_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x24 "PR1_CFG__SLV__REGS_pwm1_1,"
bitfld.long 0x24 10.--11. "PWM1_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x24 8.--9. "PWM1_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "PWM1_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x24 4.--5. "PWM1_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x24 2.--3. "PWM1_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x24 0.--1. "PWM1_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x28 "PR1_CFG__SLV__REGS_pwm1_2,"
bitfld.long 0x28 10.--11. "PWM1_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x28 8.--9. "PWM1_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x28 6.--7. "PWM1_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x28 4.--5. "PWM1_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x28 2.--3. "PWM1_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x28 0.--1. "PWM1_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x2C "PR1_CFG__SLV__REGS_pwm2_0,"
bitfld.long 0x2C 10.--11. "PWM2_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x2C 8.--9. "PWM2_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x2C 6.--7. "PWM2_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x2C 4.--5. "PWM2_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x2C 2.--3. "PWM2_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x2C 0.--1. "PWM2_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x30 "PR1_CFG__SLV__REGS_pwm2_1,"
bitfld.long 0x30 10.--11. "PWM2_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x30 8.--9. "PWM2_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x30 6.--7. "PWM2_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x30 4.--5. "PWM2_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x30 2.--3. "PWM2_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x30 0.--1. "PWM2_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x34 "PR1_CFG__SLV__REGS_pwm2_2,"
bitfld.long 0x34 10.--11. "PWM2_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x34 8.--9. "PWM2_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "PWM2_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x34 4.--5. "PWM2_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x34 2.--3. "PWM2_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x34 0.--1. "PWM2_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x38 "PR1_CFG__SLV__REGS_pwm3_0,"
bitfld.long 0x38 10.--11. "PWM3_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x38 8.--9. "PWM3_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x38 6.--7. "PWM3_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x38 4.--5. "PWM3_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x38 2.--3. "PWM3_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x38 0.--1. "PWM3_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x3C "PR1_CFG__SLV__REGS_pwm3_1,"
bitfld.long 0x3C 10.--11. "PWM3_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x3C 8.--9. "PWM3_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x3C 6.--7. "PWM3_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x3C 4.--5. "PWM3_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x3C 2.--3. "PWM3_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x3C 0.--1. "PWM3_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x40 "PR1_CFG__SLV__REGS_pwm3_2,"
bitfld.long 0x40 10.--11. "PWM3_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x40 8.--9. "PWM3_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x40 6.--7. "PWM3_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x40 4.--5. "PWM3_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x40 2.--3. "PWM3_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x40 0.--1. "PWM3_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x44 "PR1_CFG__SLV__REGS_spin_lock0,"
hexmask.long.byte 0x44 8.--13. 1. "MMR_OWN_REQ_VECTOR_0,Spin Lock flag Vector"
eventfld.long 0x44 1. "MMR_OWN_REQ_CLR_0,Spin Lock Status Clear" "0,1"
newline
rbitfld.long 0x44 0. "MMR_OWN_REQ_STATUS_0,Spin Lock Status" "0,1"
line.long 0x48 "PR1_CFG__SLV__REGS_spin_lock1,"
hexmask.long.byte 0x48 8.--13. 1. "MMR_OWN_REQ_VECTOR_1,Spin Lock flag Vector"
eventfld.long 0x48 1. "MMR_OWN_REQ_CLR_1,Spin Lock Status Clear" "0,1"
newline
rbitfld.long 0x48 0. "MMR_OWN_REQ_STATUS_1,Spin Lock Status" "0,1"
line.long 0x4C "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg0,"
bitfld.long 0x4C 31. "PA_PDSP0_INC_TYPE,pa_pdsp0_inc_type" "0,1"
hexmask.long.tbyte 0x4C 14.--30. 1. "PA_PDSP0_INC_VAL,pa_pdsp0_inc_val"
newline
hexmask.long.word 0x4C 0.--13. 1. "PA_PDSP0_INDEX,pa_pdsp0_index"
rgroup.long 0x17C++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat0,"
bitfld.long 0x0 1.--3. "PA_PDSP0_STATUS,pa_pdsp0_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP0_READY,pa_pdsp0_ready" "0,1"
group.long 0x180++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg1,"
bitfld.long 0x0 31. "PA_PDSP1_INC_TYPE,pa_pdsp1_inc_type" "0,1"
hexmask.long.tbyte 0x0 14.--30. 1. "PA_PDSP1_INC_VAL,pa_pdsp1_inc_val"
newline
hexmask.long.word 0x0 0.--13. 1. "PA_PDSP1_INDEX,pa_pdsp1_index"
rgroup.long 0x184++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat1,"
bitfld.long 0x0 1.--3. "PA_PDSP1_STATUS,pa_pdsp1_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP1_READY,pa_pdsp1_ready" "0,1"
group.long 0x188++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg2,"
bitfld.long 0x0 31. "PA_PDSP2_INC_TYPE,pa_pdsp2_inc_type" "0,1"
hexmask.long.tbyte 0x0 14.--30. 1. "PA_PDSP2_INC_VAL,pa_pdsp2_inc_val"
newline
hexmask.long.word 0x0 0.--13. 1. "PA_PDSP2_INDEX,pa_pdsp2_index"
rgroup.long 0x18C++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat2,"
bitfld.long 0x0 1.--3. "PA_PDSP2_STATUS,pa_pdsp2_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP2_READY,pa_pdsp2_ready" "0,1"
group.long 0x190++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg3,"
bitfld.long 0x0 31. "PA_PDSP3_INC_TYPE,pa_pdsp3_inc_type" "0,1"
hexmask.long.tbyte 0x0 14.--30. 1. "PA_PDSP3_INC_VAL,pa_pdsp3_inc_val"
newline
hexmask.long.word 0x0 0.--13. 1. "PA_PDSP3_INDEX,pa_pdsp3_index"
rgroup.long 0x194++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat3,"
bitfld.long 0x0 1.--3. "PA_PDSP3_STATUS,pa_pdsp3_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP3_READY,pa_pdsp3_ready" "0,1"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_MDIO_V1P7_MDIO (PRU_ICSSG0_PR1_MDIO_V1P7_MDIO)"
base ad:0x30032400
rgroup.long 0x0++0x3
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_MDIO_VERSION_REG,version_reg"
hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID"
hexmask.long.byte 0x0 8.--15. 1. "REVMAJ,Major revision value"
hexmask.long.byte 0x0 0.--7. 1. "REVMINOR,Minor revision value"
group.long 0x4++0x7
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_CONTROL_REG,control_reg"
rbitfld.long 0x0 31. "IDLE,MDIO state machine idle" "0,1"
bitfld.long 0x0 30. "ENABLE,Enable control" "0,1"
hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel"
newline
bitfld.long 0x0 20. "PREAMBLE,Preamble disable" "0,1"
bitfld.long 0x0 19. "FAULT,Fault indicator" "0,1"
bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
newline
bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock divider"
line.long 0x4 "PR1_MDIO_V1P7__MDIO__REGS_ALIVE_REG,alive_reg"
hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO alive"
rgroup.long 0xC++0x3
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_LINK_REG,link_reg"
hexmask.long 0x0 0.--31. 1. "LINK,MDIO link state"
group.long 0x10++0x37
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_RAW_REG,link_int_raw_reg"
bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x4 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASKED_REG,link_int_masked_reg"
bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x8 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASK_SET_REG,link_int_mask_set_reg"
bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0xC "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASK_CLEAR_REG,link_int_mask_clear_reg"
bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x10 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_RAW_REG,user_int_raw_reg"
bitfld.long 0x10 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
line.long 0x14 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASKED_REG,user_int_masked_reg"
bitfld.long 0x14 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
line.long 0x18 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASK_SET_REG,user_int_mask_set_reg"
bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
line.long 0x1C "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASK_CLEAR_REG,user_int_mask_clear_reg"
bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
line.long 0x20 "PR1_MDIO_V1P7__MDIO__REGS_MANUAL_IF_REG,manual_if_reg"
bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable" "0,1"
bitfld.long 0x20 0. "MDIO_PIN,MDIO Pin" "0,1"
line.long 0x24 "PR1_MDIO_V1P7__MDIO__REGS_POLL_REG,poll_reg"
bitfld.long 0x24 31. "MANUALMODE,MDIO Manual Mode" "0,1"
bitfld.long 0x24 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
hexmask.long.byte 0x24 0.--7. 1. "IPG,MDIO IPG"
line.long 0x28 "PR1_MDIO_V1P7__MDIO__REGS_POLL_EN_REG,poll_en_reg"
hexmask.long 0x28 0.--31. 1. "POLL_EN,MDIO Poll Enable"
line.long 0x2C "PR1_MDIO_V1P7__MDIO__REGS_CLAUS45_REG,"
hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO Clause 45"
line.long 0x30 "PR1_MDIO_V1P7__MDIO__REGS_USER_ADDR0_REG,MDIO USER Address 0"
hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
line.long 0x34 "PR1_MDIO_V1P7__MDIO__REGS_USER_ADDR1_REG,MDIO USER Address 1"
hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
group.long 0x80++0x7
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_USER_ACCESS_REG,user_access_reg"
bitfld.long 0x0 31. "GO,Go" "0,1"
bitfld.long 0x0 30. "WRITE,Write" "0,1"
bitfld.long 0x0 29. "ACK,Acknowledge" "0,1"
newline
hexmask.long.byte 0x0 21.--25. 1. "REGADR,Register address"
hexmask.long.byte 0x0 16.--20. 1. "PHYADR,PHY address"
hexmask.long.word 0x0 0.--15. 1. "DATA,User data"
line.long 0x4 "PR1_MDIO_V1P7__MDIO__REGS_USER_PHY_SEL_REG,user_phy_sel_reg"
bitfld.long 0x4 7. "LINKSEL,Link status determination select" "0,1"
bitfld.long 0x4 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
hexmask.long.byte 0x4 0.--4. 1. "PHYADR_MON,PHY address whose link status is monitored"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_PROT_SLV"
base ad:0x24C00
group.long 0x0++0x7
line.long 0x0 "PR1_PROTECT__SLV__REGS_unlock_key,"
hexmask.long 0x0 0.--31. 1. "UNLOCK_KEY,UnLock Key Pattern 0x83E7_0B13 to UnLock 0x0000_0000 to Lock Must unlock to update MMRs"
line.long 0x4 "PR1_PROTECT__SLV__REGS_cfg,Config"
bitfld.long 0x4 6. "PRU1_DMEM1_LOCK_EN,Write Protect DMEM1 0: disable 1: enable When enabled only PRU1 can write to DMEM1" "0: disable,1: enable When enabled only PRU1 can write to DMEM1"
newline
bitfld.long 0x4 5. "PRU0_DMEM0_LOCK_EN,Write Protect DMEM0 0: disable 1: enable When enabled only PRU0 can write to DMEM0" "0: disable,1: enable When enabled only PRU0 can write to DMEM0"
newline
bitfld.long 0x4 4. "ICSS_CFG_WP_EN,Write Protect ICSS_CFG 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 3. "RTU1_PRU_WP_EN,Write Protect RTU1_PRU access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 2. "RTU0_PRU_WP_EN,Write Protect RTU0_PRU access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 1. "PRU1_WP_EN,Write Protect PRU1 access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 0. "PRU0_WP_EN,Write Protect PRU0 access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_CFG_SLV"
base ad:0x26000
rgroup.long 0x0++0x7
line.long 0x0 "PR1_CFG__SLV__REGS_pid_reg,"
hexmask.long 0x0 0.--31. 1. "ICSS_IDVER,Module ID field"
line.long 0x4 "PR1_CFG__SLV__REGS_hwdis_reg,"
hexmask.long.byte 0x4 0.--7. 1. "HWDIS,HW Disable Observation"
group.long 0x8++0x17
line.long 0x0 "PR1_CFG__SLV__REGS_gpcfg0_reg,"
hexmask.long.byte 0x0 26.--29. 1. "PR1_PRU0_GP_MUX_SEL,"
rbitfld.long 0x0 25. "PRU0_GPO_SH1_SEL," "0,1"
newline
hexmask.long.byte 0x0 20.--24. 1. "PRU0_GPO_DIV1,"
hexmask.long.byte 0x0 15.--19. 1. "PRU0_GPO_DIV0,"
newline
bitfld.long 0x0 14. "PRU0_GPO_MODE," "0,1"
bitfld.long 0x0 13. "PRU0_GPI_SB," "0,1"
newline
hexmask.long.byte 0x0 8.--12. 1. "PRU0_GPI_DIV1,"
hexmask.long.byte 0x0 3.--7. 1. "PRU0_GPI_DIV0,"
newline
bitfld.long 0x0 2. "PRU0_GPI_CLK_MODE," "0,1"
bitfld.long 0x0 0.--1. "PRU0_GPI_MODE," "0,1,2,3"
line.long 0x4 "PR1_CFG__SLV__REGS_gpcfg1_reg,"
hexmask.long.byte 0x4 26.--29. 1. "PR1_PRU1_GP_MUX_SEL,"
rbitfld.long 0x4 25. "PRU1_GPO_SH1_SEL," "0,1"
newline
hexmask.long.byte 0x4 20.--24. 1. "PRU1_GPO_DIV1,"
hexmask.long.byte 0x4 15.--19. 1. "PRU1_GPO_DIV0,"
newline
bitfld.long 0x4 14. "PRU1_GPO_MODE," "0,1"
bitfld.long 0x4 13. "PRU1_GPI_SB," "0,1"
newline
hexmask.long.byte 0x4 8.--12. 1. "PRU1_GPI_DIV1,"
hexmask.long.byte 0x4 3.--7. 1. "PRU1_GPI_DIV0,"
newline
bitfld.long 0x4 2. "PRU1_GPI_CLK_MODE," "0,1"
bitfld.long 0x4 0.--1. "PRU1_GPI_MODE," "0,1,2,3"
line.long 0x8 "PR1_CFG__SLV__REGS_cgr_reg,"
bitfld.long 0x8 31. "ICSS_STOP_ACK," "0,1"
rbitfld.long 0x8 30. "ICSS_STOP_REQ," "0,1"
newline
bitfld.long 0x8 29. "ICSS_PWR_IDLE," "0,1"
bitfld.long 0x8 21. "BOTTOM_HALF_CLK_GATE_EN," "0,1"
newline
bitfld.long 0x8 20. "TOP_HALF_CLK_GATE_EN," "0,1"
bitfld.long 0x8 19. "AUTO_SLICE1_CLK_GATE_EN," "0,1"
newline
bitfld.long 0x8 18. "AUTO_SLICE0_CLK_GATE_EN," "0,1"
bitfld.long 0x8 17. "IEP_CLK_EN," "0,1"
newline
rbitfld.long 0x8 16. "IEP_CLK_STOP_ACK," "0,1"
bitfld.long 0x8 15. "IEP_CLK_STOP_REQ," "0,1"
newline
bitfld.long 0x8 14. "ECAP_CLK_EN," "0,1"
rbitfld.long 0x8 13. "ECAP_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x8 12. "ECAP_CLK_STOP_REQ," "0,1"
bitfld.long 0x8 11. "UART_CLK_EN," "0,1"
newline
rbitfld.long 0x8 10. "UART_CLK_STOP_ACK," "0,1"
bitfld.long 0x8 9. "UART_CLK_STOP_REQ," "0,1"
newline
bitfld.long 0x8 8. "INTC_CLK_EN," "0,1"
rbitfld.long 0x8 7. "INTC_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x8 6. "INTC_CLK_STOP_REQ," "0,1"
line.long 0xC "PR1_CFG__SLV__REGS_gpecfg0_reg,"
bitfld.long 0xC 17. "PRU0_GPO_SHIFT_CLK_DONE," "0,1"
bitfld.long 0xC 16. "PRU0_GPO_SHIFT_CLK_HIGH," "0,1"
newline
hexmask.long.byte 0xC 8.--15. 1. "PRU0_GPO_SHIFT_CNT,"
bitfld.long 0xC 6. "PRU0_GPO_SHIFT_GP_EN," "0,1"
newline
bitfld.long 0xC 5. "PRU0_GPO_SHIFT_CLK_FREE," "0,1"
bitfld.long 0xC 4. "PRU0_GPO_SHIFT_SWAP," "0,1"
newline
bitfld.long 0xC 1. "PRU0_GPI_SHIFT_EN," "0,1"
bitfld.long 0xC 0. "PRU0_GPI_SB_P," "0,1"
line.long 0x10 "PR1_CFG__SLV__REGS_gpecfg1_reg,"
bitfld.long 0x10 17. "PRU1_GPO_SHIFT_CLK_DONE," "0,1"
bitfld.long 0x10 16. "PRU1_GPO_SHIFT_CLK_HIGH," "0,1"
newline
hexmask.long.byte 0x10 8.--15. 1. "PRU1_GPO_SHIFT_CNT,"
bitfld.long 0x10 6. "PRU1_GPO_SHIFT_GP_EN," "0,1"
newline
bitfld.long 0x10 5. "PRU1_GPO_SHIFT_CLK_FREE," "0,1"
bitfld.long 0x10 4. "PRU1_GPO_SHIFT_SWAP," "0,1"
newline
bitfld.long 0x10 1. "PRU1_GPI_SHIFT_EN," "0,1"
bitfld.long 0x10 0. "PRU1_GPI_SB_P," "0,1"
line.long 0x14 "PR1_CFG__SLV__REGS_reset_iso_reg,"
bitfld.long 0x14 2. "RESET_ISO_EDGE," "0,1"
bitfld.long 0x14 1. "RESET_ISO_ACK," "0,1"
newline
bitfld.long 0x14 0. "RESET_ISO_REQ," "0,1"
group.long 0x2C++0xB
line.long 0x0 "PR1_CFG__SLV__REGS_mii_rt_reg,"
bitfld.long 0x0 0. "MII_RT_EVENT_EN," "0,1"
line.long 0x4 "PR1_CFG__SLV__REGS_iepclk_reg,"
bitfld.long 0x4 1. "IEP1_SLV_EN," "0,1"
bitfld.long 0x4 0. "IEP_OCP_CLK_EN," "0,1"
line.long 0x8 "PR1_CFG__SLV__REGS_spp_reg,"
bitfld.long 0x8 3. "RTU_XFR_SHIFT_EN," "0,1"
bitfld.long 0x8 2. "XFR_BYTE_SHIFT_EN," "0,1"
newline
bitfld.long 0x8 1. "XFR_SHIFT_EN," "0,1"
bitfld.long 0x8 0. "PRU1_PAD_HP_EN," "0,1"
group.long 0x3C++0x9F
line.long 0x0 "PR1_CFG__SLV__REGS_core_sync_reg,"
bitfld.long 0x0 0. "CORE_VBUSP_SYNC_EN," "0,1"
line.long 0x4 "PR1_CFG__SLV__REGS_sa_mx_reg,"
bitfld.long 0x4 16. "PWM_EFC_EN," "0,1"
bitfld.long 0x4 10.--11. "PWM3_REMAP_EN," "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "PWM0_REMAP_EN," "0,1,2,3"
hexmask.long.byte 0x4 0.--7. 1. "SA_MUX_SEL,"
line.long 0x8 "PR1_CFG__SLV__REGS_pru0_sd_clk_div_reg,"
hexmask.long.byte 0x8 24.--31. 1. "PRU0_SD_MAN_REC_CLK_PERIOD,"
rbitfld.long 0x8 16. "PRU0_SD_MAN_CLK_CAL_DONE," "0,1"
newline
rbitfld.long 0x8 15. "PRU0_SD_MAN_STATUS," "0,1"
hexmask.long.byte 0x8 11.--14. 1. "PRU0_SD_CH_SEL,"
newline
bitfld.long 0x8 10. "PRU0_SD_MAN_NV_DATA_EN," "0,1"
bitfld.long 0x8 9. "PRU0_SD_MAN_EN," "0,1"
newline
bitfld.long 0x8 8. "PRU0_SD_SHARE_EN," "0,1"
line.long 0xC "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg0,"
bitfld.long 0xC 22. "PRU0_FD_ZERO_MAX_0," "0,1"
hexmask.long.byte 0xC 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_0,"
newline
bitfld.long 0xC 16. "PRU0_FD_ZERO_MIN_0," "0,1"
hexmask.long.byte 0xC 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_0,"
newline
bitfld.long 0xC 4.--5. "PRU0_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0xC 2. "PRU0_SD_CLK_INV0," "0,1"
newline
bitfld.long 0xC 0.--1. "PRU0_SD_CLK_SEL0," "0,1,2,3"
line.long 0x10 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg0,"
bitfld.long 0x10 23. "PRU0_FD_EN_0," "0,1"
bitfld.long 0x10 22. "PRU0_FD_ONE_MAX_0," "0,1"
newline
hexmask.long.byte 0x10 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_0,"
bitfld.long 0x10 16. "PRU0_FD_ONE_MIN_0," "0,1"
newline
hexmask.long.byte 0x10 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_0,"
bitfld.long 0x10 8.--10. "PRU0_FD_WINDOW_SIZE_0," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 0.--7. 1. "PRU0_SD_SAMPLE_SIZE0,"
line.long 0x14 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg1,"
bitfld.long 0x14 22. "PRU0_FD_ZERO_MAX_1," "0,1"
hexmask.long.byte 0x14 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_1,"
newline
bitfld.long 0x14 16. "PRU0_FD_ZERO_MIN_1," "0,1"
hexmask.long.byte 0x14 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_1,"
newline
bitfld.long 0x14 4.--5. "PRU0_SD_ACC_SEL1," "0,1,2,3"
bitfld.long 0x14 2. "PRU0_SD_CLK_INV1," "0,1"
newline
bitfld.long 0x14 0.--1. "PRU0_SD_CLK_SEL1," "0,1,2,3"
line.long 0x18 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg1,"
bitfld.long 0x18 23. "PRU0_FD_EN_1," "0,1"
bitfld.long 0x18 22. "PRU0_FD_ONE_MAX_1," "0,1"
newline
hexmask.long.byte 0x18 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_1,"
bitfld.long 0x18 16. "PRU0_FD_ONE_MIN_1," "0,1"
newline
hexmask.long.byte 0x18 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_1,"
bitfld.long 0x18 8.--10. "PRU0_FD_WINDOW_SIZE_1," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x18 0.--7. 1. "PRU0_SD_SAMPLE_SIZE1,"
line.long 0x1C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg2,"
bitfld.long 0x1C 22. "PRU0_FD_ZERO_MAX_2," "0,1"
hexmask.long.byte 0x1C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_2,"
newline
bitfld.long 0x1C 16. "PRU0_FD_ZERO_MIN_2," "0,1"
hexmask.long.byte 0x1C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_2,"
newline
bitfld.long 0x1C 4.--5. "PRU0_SD_ACC_SEL2," "0,1,2,3"
bitfld.long 0x1C 2. "PRU0_SD_CLK_INV2," "0,1"
newline
bitfld.long 0x1C 0.--1. "PRU0_SD_CLK_SEL2," "0,1,2,3"
line.long 0x20 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg2,"
bitfld.long 0x20 23. "PRU0_FD_EN_2," "0,1"
bitfld.long 0x20 22. "PRU0_FD_ONE_MAX_2," "0,1"
newline
hexmask.long.byte 0x20 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_2,"
bitfld.long 0x20 16. "PRU0_FD_ONE_MIN_2," "0,1"
newline
hexmask.long.byte 0x20 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_2,"
bitfld.long 0x20 8.--10. "PRU0_FD_WINDOW_SIZE_2," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x20 0.--7. 1. "PRU0_SD_SAMPLE_SIZE2,"
line.long 0x24 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg3,"
bitfld.long 0x24 22. "PRU0_FD_ZERO_MAX_3," "0,1"
hexmask.long.byte 0x24 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_3,"
newline
bitfld.long 0x24 16. "PRU0_FD_ZERO_MIN_3," "0,1"
hexmask.long.byte 0x24 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_3,"
newline
bitfld.long 0x24 4.--5. "PRU0_SD_ACC_SEL3," "0,1,2,3"
bitfld.long 0x24 2. "PRU0_SD_CLK_INV3," "0,1"
newline
bitfld.long 0x24 0.--1. "PRU0_SD_CLK_SEL3," "0,1,2,3"
line.long 0x28 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg3,"
bitfld.long 0x28 23. "PRU0_FD_EN_3," "0,1"
bitfld.long 0x28 22. "PRU0_FD_ONE_MAX_3," "0,1"
newline
hexmask.long.byte 0x28 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_3,"
bitfld.long 0x28 16. "PRU0_FD_ONE_MIN_3," "0,1"
newline
hexmask.long.byte 0x28 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_3,"
bitfld.long 0x28 8.--10. "PRU0_FD_WINDOW_SIZE_3," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 0.--7. 1. "PRU0_SD_SAMPLE_SIZE3,"
line.long 0x2C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg4,"
bitfld.long 0x2C 22. "PRU0_FD_ZERO_MAX_4," "0,1"
hexmask.long.byte 0x2C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_4,"
newline
bitfld.long 0x2C 16. "PRU0_FD_ZERO_MIN_4," "0,1"
hexmask.long.byte 0x2C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_4,"
newline
bitfld.long 0x2C 4.--5. "PRU0_SD_ACC_SEL4," "0,1,2,3"
bitfld.long 0x2C 2. "PRU0_SD_CLK_INV4," "0,1"
newline
bitfld.long 0x2C 0.--1. "PRU0_SD_CLK_SEL4," "0,1,2,3"
line.long 0x30 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg4,"
bitfld.long 0x30 23. "PRU0_FD_EN_4," "0,1"
bitfld.long 0x30 22. "PRU0_FD_ONE_MAX_4," "0,1"
newline
hexmask.long.byte 0x30 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_4,"
bitfld.long 0x30 16. "PRU0_FD_ONE_MIN_4," "0,1"
newline
hexmask.long.byte 0x30 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_4,"
bitfld.long 0x30 8.--10. "PRU0_FD_WINDOW_SIZE_4," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x30 0.--7. 1. "PRU0_SD_SAMPLE_SIZE4,"
line.long 0x34 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg5,"
bitfld.long 0x34 22. "PRU0_FD_ZERO_MAX_5," "0,1"
hexmask.long.byte 0x34 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_5,"
newline
bitfld.long 0x34 16. "PRU0_FD_ZERO_MIN_5," "0,1"
hexmask.long.byte 0x34 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_5,"
newline
bitfld.long 0x34 4.--5. "PRU0_SD_ACC_SEL5," "0,1,2,3"
bitfld.long 0x34 2. "PRU0_SD_CLK_INV5," "0,1"
newline
bitfld.long 0x34 0.--1. "PRU0_SD_CLK_SEL5," "0,1,2,3"
line.long 0x38 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg5,"
bitfld.long 0x38 23. "PRU0_FD_EN_5," "0,1"
bitfld.long 0x38 22. "PRU0_FD_ONE_MAX_5," "0,1"
newline
hexmask.long.byte 0x38 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_5,"
bitfld.long 0x38 16. "PRU0_FD_ONE_MIN_5," "0,1"
newline
hexmask.long.byte 0x38 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_5,"
bitfld.long 0x38 8.--10. "PRU0_FD_WINDOW_SIZE_5," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x38 0.--7. 1. "PRU0_SD_SAMPLE_SIZE5,"
line.long 0x3C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg6,"
bitfld.long 0x3C 22. "PRU0_FD_ZERO_MAX_6," "0,1"
hexmask.long.byte 0x3C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_6,"
newline
bitfld.long 0x3C 16. "PRU0_FD_ZERO_MIN_6," "0,1"
hexmask.long.byte 0x3C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_6,"
newline
bitfld.long 0x3C 4.--5. "PRU0_SD_ACC_SEL6," "0,1,2,3"
bitfld.long 0x3C 2. "PRU0_SD_CLK_INV6," "0,1"
newline
bitfld.long 0x3C 0.--1. "PRU0_SD_CLK_SEL6," "0,1,2,3"
line.long 0x40 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg6,"
bitfld.long 0x40 23. "PRU0_FD_EN_6," "0,1"
bitfld.long 0x40 22. "PRU0_FD_ONE_MAX_6," "0,1"
newline
hexmask.long.byte 0x40 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_6,"
bitfld.long 0x40 16. "PRU0_FD_ONE_MIN_6," "0,1"
newline
hexmask.long.byte 0x40 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_6,"
bitfld.long 0x40 8.--10. "PRU0_FD_WINDOW_SIZE_6," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x40 0.--7. 1. "PRU0_SD_SAMPLE_SIZE6,"
line.long 0x44 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg7,"
bitfld.long 0x44 22. "PRU0_FD_ZERO_MAX_7," "0,1"
hexmask.long.byte 0x44 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_7,"
newline
bitfld.long 0x44 16. "PRU0_FD_ZERO_MIN_7," "0,1"
hexmask.long.byte 0x44 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_7,"
newline
bitfld.long 0x44 4.--5. "PRU0_SD_ACC_SEL7," "0,1,2,3"
bitfld.long 0x44 2. "PRU0_SD_CLK_INV7," "0,1"
newline
bitfld.long 0x44 0.--1. "PRU0_SD_CLK_SEL7," "0,1,2,3"
line.long 0x48 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg7,"
bitfld.long 0x48 23. "PRU0_FD_EN_7," "0,1"
bitfld.long 0x48 22. "PRU0_FD_ONE_MAX_7," "0,1"
newline
hexmask.long.byte 0x48 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_7,"
bitfld.long 0x48 16. "PRU0_FD_ONE_MIN_7," "0,1"
newline
hexmask.long.byte 0x48 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_7,"
bitfld.long 0x48 8.--10. "PRU0_FD_WINDOW_SIZE_7," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x48 0.--7. 1. "PRU0_SD_SAMPLE_SIZE7,"
line.long 0x4C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg8,"
bitfld.long 0x4C 22. "PRU0_FD_ZERO_MAX_8," "0,1"
hexmask.long.byte 0x4C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_8,"
newline
bitfld.long 0x4C 16. "PRU0_FD_ZERO_MIN_8," "0,1"
hexmask.long.byte 0x4C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_8,"
newline
bitfld.long 0x4C 4.--5. "PRU0_SD_ACC_SEL8," "0,1,2,3"
bitfld.long 0x4C 2. "PRU0_SD_CLK_INV8," "0,1"
newline
bitfld.long 0x4C 0.--1. "PRU0_SD_CLK_SEL8," "0,1,2,3"
line.long 0x50 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg8,"
bitfld.long 0x50 23. "PRU0_FD_EN_8," "0,1"
bitfld.long 0x50 22. "PRU0_FD_ONE_MAX_8," "0,1"
newline
hexmask.long.byte 0x50 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_8,"
bitfld.long 0x50 16. "PRU0_FD_ONE_MIN_8," "0,1"
newline
hexmask.long.byte 0x50 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_8,"
bitfld.long 0x50 8.--10. "PRU0_FD_WINDOW_SIZE_8," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x50 0.--7. 1. "PRU0_SD_SAMPLE_SIZE8,"
line.long 0x54 "PR1_CFG__SLV__REGS_pru1_sd_clk_div_reg,"
hexmask.long.byte 0x54 24.--31. 1. "PRU1_SD_MAN_REC_CLK_PERIOD,"
rbitfld.long 0x54 16. "PRU1_SD_MAN_CLK_CAL_DONE," "0,1"
newline
rbitfld.long 0x54 15. "PRU1_SD_MAN_STATUS," "0,1"
hexmask.long.byte 0x54 11.--14. 1. "PRU1_SD_CH_SEL,"
newline
bitfld.long 0x54 10. "PRU1_SD_MAN_NV_DATA_EN," "0,1"
bitfld.long 0x54 9. "PRU1_SD_MAN_EN," "0,1"
newline
bitfld.long 0x54 8. "PRU1_SD_SHARE_EN," "0,1"
line.long 0x58 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg0,"
bitfld.long 0x58 22. "PRU1_FD_ZERO_MAX_0," "0,1"
hexmask.long.byte 0x58 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_0,"
newline
bitfld.long 0x58 16. "PRU1_FD_ZERO_MIN_0," "0,1"
hexmask.long.byte 0x58 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_0,"
newline
bitfld.long 0x58 4.--5. "PRU1_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x58 2. "PRU1_SD_CLK_INV0," "0,1"
newline
bitfld.long 0x58 0.--1. "PRU1_SD_CLK_SEL0," "0,1,2,3"
line.long 0x5C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg0,"
bitfld.long 0x5C 23. "PRU1_FD_EN_0," "0,1"
bitfld.long 0x5C 22. "PRU1_FD_ONE_MAX_0," "0,1"
newline
hexmask.long.byte 0x5C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_0,"
bitfld.long 0x5C 16. "PRU1_FD_ONE_MIN_0," "0,1"
newline
hexmask.long.byte 0x5C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_0,"
bitfld.long 0x5C 8.--10. "PRU1_FD_WINDOW_SIZE_0," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x5C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE0,"
line.long 0x60 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg1,"
bitfld.long 0x60 22. "PRU1_FD_ZERO_MAX_1," "0,1"
hexmask.long.byte 0x60 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_1,"
newline
bitfld.long 0x60 16. "PRU1_FD_ZERO_MIN_1," "0,1"
hexmask.long.byte 0x60 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_1,"
newline
bitfld.long 0x60 4.--5. "PRU1_SD_ACC_SEL1," "0,1,2,3"
bitfld.long 0x60 2. "PRU1_SD_CLK_INV1," "0,1"
newline
bitfld.long 0x60 0.--1. "PRU1_SD_CLK_SEL1," "0,1,2,3"
line.long 0x64 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg1,"
bitfld.long 0x64 23. "PRU1_FD_EN_1," "0,1"
bitfld.long 0x64 22. "PRU1_FD_ONE_MAX_1," "0,1"
newline
hexmask.long.byte 0x64 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_1,"
bitfld.long 0x64 16. "PRU1_FD_ONE_MIN_1," "0,1"
newline
hexmask.long.byte 0x64 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_1,"
bitfld.long 0x64 8.--10. "PRU1_FD_WINDOW_SIZE_1," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x64 0.--7. 1. "PRU1_SD_SAMPLE_SIZE1,"
line.long 0x68 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg2,"
bitfld.long 0x68 22. "PRU1_FD_ZERO_MAX_2," "0,1"
hexmask.long.byte 0x68 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_2,"
newline
bitfld.long 0x68 16. "PRU1_FD_ZERO_MIN_2," "0,1"
hexmask.long.byte 0x68 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_2,"
newline
bitfld.long 0x68 4.--5. "PRU1_SD_ACC_SEL2," "0,1,2,3"
bitfld.long 0x68 2. "PRU1_SD_CLK_INV2," "0,1"
newline
bitfld.long 0x68 0.--1. "PRU1_SD_CLK_SEL2," "0,1,2,3"
line.long 0x6C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg2,"
bitfld.long 0x6C 23. "PRU1_FD_EN_2," "0,1"
bitfld.long 0x6C 22. "PRU1_FD_ONE_MAX_2," "0,1"
newline
hexmask.long.byte 0x6C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_2,"
bitfld.long 0x6C 16. "PRU1_FD_ONE_MIN_2," "0,1"
newline
hexmask.long.byte 0x6C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_2,"
bitfld.long 0x6C 8.--10. "PRU1_FD_WINDOW_SIZE_2," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x6C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE2,"
line.long 0x70 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg3,"
bitfld.long 0x70 22. "PRU1_FD_ZERO_MAX_3," "0,1"
hexmask.long.byte 0x70 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_3,"
newline
bitfld.long 0x70 16. "PRU1_FD_ZERO_MIN_3," "0,1"
hexmask.long.byte 0x70 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_3,"
newline
bitfld.long 0x70 4.--5. "PRU1_SD_ACC_SEL3," "0,1,2,3"
bitfld.long 0x70 2. "PRU1_SD_CLK_INV3," "0,1"
newline
bitfld.long 0x70 0.--1. "PRU1_SD_CLK_SEL3," "0,1,2,3"
line.long 0x74 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg3,"
bitfld.long 0x74 23. "PRU1_FD_EN_3," "0,1"
bitfld.long 0x74 22. "PRU1_FD_ONE_MAX_3," "0,1"
newline
hexmask.long.byte 0x74 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_3,"
bitfld.long 0x74 16. "PRU1_FD_ONE_MIN_3," "0,1"
newline
hexmask.long.byte 0x74 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_3,"
bitfld.long 0x74 8.--10. "PRU1_FD_WINDOW_SIZE_3," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x74 0.--7. 1. "PRU1_SD_SAMPLE_SIZE3,"
line.long 0x78 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg4,"
bitfld.long 0x78 22. "PRU1_FD_ZERO_MAX_4," "0,1"
hexmask.long.byte 0x78 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_4,"
newline
bitfld.long 0x78 16. "PRU1_FD_ZERO_MIN_4," "0,1"
hexmask.long.byte 0x78 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_4,"
newline
bitfld.long 0x78 4.--5. "PRU1_SD_ACC_SEL4," "0,1,2,3"
bitfld.long 0x78 2. "PRU1_SD_CLK_INV4," "0,1"
newline
bitfld.long 0x78 0.--1. "PRU1_SD_CLK_SEL4," "0,1,2,3"
line.long 0x7C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg4,"
bitfld.long 0x7C 23. "PRU1_FD_EN_4," "0,1"
bitfld.long 0x7C 22. "PRU1_FD_ONE_MAX_4," "0,1"
newline
hexmask.long.byte 0x7C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_4,"
bitfld.long 0x7C 16. "PRU1_FD_ONE_MIN_4," "0,1"
newline
hexmask.long.byte 0x7C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_4,"
bitfld.long 0x7C 8.--10. "PRU1_FD_WINDOW_SIZE_4," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x7C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE4,"
line.long 0x80 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg5,"
bitfld.long 0x80 22. "PRU1_FD_ZERO_MAX_5," "0,1"
hexmask.long.byte 0x80 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_5,"
newline
bitfld.long 0x80 16. "PRU1_FD_ZERO_MIN_5," "0,1"
hexmask.long.byte 0x80 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_5,"
newline
bitfld.long 0x80 4.--5. "PRU1_SD_ACC_SEL5," "0,1,2,3"
bitfld.long 0x80 2. "PRU1_SD_CLK_INV5," "0,1"
newline
bitfld.long 0x80 0.--1. "PRU1_SD_CLK_SEL5," "0,1,2,3"
line.long 0x84 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg5,"
bitfld.long 0x84 23. "PRU1_FD_EN_5," "0,1"
bitfld.long 0x84 22. "PRU1_FD_ONE_MAX_5," "0,1"
newline
hexmask.long.byte 0x84 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_5,"
bitfld.long 0x84 16. "PRU1_FD_ONE_MIN_5," "0,1"
newline
hexmask.long.byte 0x84 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_5,"
bitfld.long 0x84 8.--10. "PRU1_FD_WINDOW_SIZE_5," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x84 0.--7. 1. "PRU1_SD_SAMPLE_SIZE5,"
line.long 0x88 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg6,"
bitfld.long 0x88 22. "PRU1_FD_ZERO_MAX_6," "0,1"
hexmask.long.byte 0x88 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_6,"
newline
bitfld.long 0x88 16. "PRU1_FD_ZERO_MIN_6," "0,1"
hexmask.long.byte 0x88 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_6,"
newline
bitfld.long 0x88 4.--5. "PRU1_SD_ACC_SEL6," "0,1,2,3"
bitfld.long 0x88 2. "PRU1_SD_CLK_INV6," "0,1"
newline
bitfld.long 0x88 0.--1. "PRU1_SD_CLK_SEL6," "0,1,2,3"
line.long 0x8C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg6,"
bitfld.long 0x8C 23. "PRU1_FD_EN_6," "0,1"
bitfld.long 0x8C 22. "PRU1_FD_ONE_MAX_6," "0,1"
newline
hexmask.long.byte 0x8C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_6,"
bitfld.long 0x8C 16. "PRU1_FD_ONE_MIN_6," "0,1"
newline
hexmask.long.byte 0x8C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_6,"
bitfld.long 0x8C 8.--10. "PRU1_FD_WINDOW_SIZE_6," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE6,"
line.long 0x90 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg7,"
bitfld.long 0x90 22. "PRU1_FD_ZERO_MAX_7," "0,1"
hexmask.long.byte 0x90 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_7,"
newline
bitfld.long 0x90 16. "PRU1_FD_ZERO_MIN_7," "0,1"
hexmask.long.byte 0x90 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_7,"
newline
bitfld.long 0x90 4.--5. "PRU1_SD_ACC_SEL7," "0,1,2,3"
bitfld.long 0x90 2. "PRU1_SD_CLK_INV7," "0,1"
newline
bitfld.long 0x90 0.--1. "PRU1_SD_CLK_SEL7," "0,1,2,3"
line.long 0x94 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg7,"
bitfld.long 0x94 23. "PRU1_FD_EN_7," "0,1"
bitfld.long 0x94 22. "PRU1_FD_ONE_MAX_7," "0,1"
newline
hexmask.long.byte 0x94 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_7,"
bitfld.long 0x94 16. "PRU1_FD_ONE_MIN_7," "0,1"
newline
hexmask.long.byte 0x94 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_7,"
bitfld.long 0x94 8.--10. "PRU1_FD_WINDOW_SIZE_7," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x94 0.--7. 1. "PRU1_SD_SAMPLE_SIZE7,"
line.long 0x98 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg8,"
bitfld.long 0x98 22. "PRU1_FD_ZERO_MAX_8," "0,1"
hexmask.long.byte 0x98 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_8,"
newline
bitfld.long 0x98 16. "PRU1_FD_ZERO_MIN_8," "0,1"
hexmask.long.byte 0x98 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_8,"
newline
bitfld.long 0x98 4.--5. "PRU1_SD_ACC_SEL8," "0,1,2,3"
bitfld.long 0x98 2. "PRU1_SD_CLK_INV8," "0,1"
newline
bitfld.long 0x98 0.--1. "PRU1_SD_CLK_SEL8," "0,1,2,3"
line.long 0x9C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg8,"
bitfld.long 0x9C 23. "PRU1_FD_EN_8," "0,1"
bitfld.long 0x9C 22. "PRU1_FD_ONE_MAX_8," "0,1"
newline
hexmask.long.byte 0x9C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_8,"
bitfld.long 0x9C 16. "PRU1_FD_ONE_MIN_8," "0,1"
newline
hexmask.long.byte 0x9C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_8,"
bitfld.long 0x9C 8.--10. "PRU1_FD_WINDOW_SIZE_8," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x9C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE8,"
group.long 0xE0++0x3F
line.long 0x0 "PR1_CFG__SLV__REGS_pru0_ed_rx_cfg_reg,"
hexmask.long.word 0x0 16.--31. 1. "PRU0_ED_RX_DIV_FACTOR,"
bitfld.long 0x0 15. "PRU0_ED_RX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x0 4. "PRU0_ED_RX_CLK_SEL," "0,1"
bitfld.long 0x0 3. "PRU0_ED_RX_SB_POL," "0,1"
newline
bitfld.long 0x0 0.--2. "PRU0_ED_RX_SAMPLE_SIZE," "0,1,2,3,4,5,6,7"
line.long 0x4 "PR1_CFG__SLV__REGS_pru0_ed_tx_cfg_reg,"
hexmask.long.word 0x4 16.--31. 1. "PRU0_ED_TX_DIV_FACTOR,"
bitfld.long 0x4 15. "PRU0_ED_TX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x4 11. "PRU0_ENDAT_SHARE_EN," "0,1"
rbitfld.long 0x4 10. "PRU0_ENDAT2_CLK_SYNC," "0,1"
newline
rbitfld.long 0x4 9. "PRU0_ENDAT1_CLK_SYNC," "0,1"
rbitfld.long 0x4 8. "PRU0_ENDAT0_CLK_SYNC," "0,1"
newline
rbitfld.long 0x4 7. "PRU0_ED_BUSY_2," "0,1"
rbitfld.long 0x4 6. "PRU0_ED_BUSY_1," "0,1"
newline
rbitfld.long 0x4 5. "PRU0_ED_BUSY_0," "0,1"
bitfld.long 0x4 4. "PRU0_ED_TX_CLK_SEL," "0,1"
line.long 0x8 "PR1_CFG__SLV__REGS_pru0_ed_ch0_cfg0_reg,"
bitfld.long 0x8 31. "PRU0_ED_TX_FIFO_SWAP_BITS0," "0,1"
bitfld.long 0x8 30. "PRU0_ED_SW_CLK_OUT0," "0,1"
newline
bitfld.long 0x8 29. "PRU0_ED_CLK_OUT_OVR_EN0," "0,1"
rbitfld.long 0x8 28. "PRU0_ED_RX_SNOOP0," "0,1"
newline
hexmask.long.word 0x8 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE0,"
hexmask.long.byte 0x8 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE0,"
newline
hexmask.long.word 0x8 0.--10. 1. "PRU0_ED_TX_WDLY0,"
line.long 0xC "PR1_CFG__SLV__REGS_pru0_ed_ch0_cfg1_reg,"
hexmask.long.word 0xC 16.--31. 1. "PRU0_ED_RX_EN_COUNTER0,"
hexmask.long.word 0xC 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER0,"
line.long 0x10 "PR1_CFG__SLV__REGS_pru0_ed_ch1_cfg0_reg,"
bitfld.long 0x10 31. "PRU0_ED_TX_FIFO_SWAP_BITS1," "0,1"
bitfld.long 0x10 30. "PRU0_ED_SW_CLK_OUT1," "0,1"
newline
bitfld.long 0x10 29. "PRU0_ED_CLK_OUT_OVR_EN1," "0,1"
rbitfld.long 0x10 28. "PRU0_ED_RX_SNOOP1," "0,1"
newline
hexmask.long.word 0x10 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE1,"
hexmask.long.byte 0x10 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE1,"
newline
hexmask.long.word 0x10 0.--10. 1. "PRU0_ED_TX_WDLY1,"
line.long 0x14 "PR1_CFG__SLV__REGS_pru0_ed_ch1_cfg1_reg,"
hexmask.long.word 0x14 16.--31. 1. "PRU0_ED_RX_EN_COUNTER1,"
hexmask.long.word 0x14 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER1,"
line.long 0x18 "PR1_CFG__SLV__REGS_pru0_ed_ch2_cfg0_reg,"
bitfld.long 0x18 31. "PRU0_ED_TX_FIFO_SWAP_BITS2," "0,1"
bitfld.long 0x18 30. "PRU0_ED_SW_CLK_OUT2," "0,1"
newline
bitfld.long 0x18 29. "PRU0_ED_CLK_OUT_OVR_EN2," "0,1"
rbitfld.long 0x18 28. "PRU0_ED_RX_SNOOP2," "0,1"
newline
hexmask.long.word 0x18 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE2,"
hexmask.long.byte 0x18 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE2,"
newline
hexmask.long.word 0x18 0.--10. 1. "PRU0_ED_TX_WDLY2,"
line.long 0x1C "PR1_CFG__SLV__REGS_pru0_ed_ch2_cfg1_reg,"
hexmask.long.word 0x1C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER2,"
hexmask.long.word 0x1C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER2,"
line.long 0x20 "PR1_CFG__SLV__REGS_pru1_ed_rx_cfg_reg,"
hexmask.long.word 0x20 16.--31. 1. "PRU1_ED_RX_DIV_FACTOR,"
bitfld.long 0x20 15. "PRU1_ED_RX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x20 4. "PRU1_ED_RX_CLK_SEL," "0,1"
bitfld.long 0x20 3. "PRU1_ED_RX_SB_POL," "0,1"
newline
bitfld.long 0x20 0.--2. "PRU1_ED_RX_SAMPLE_SIZE," "0,1,2,3,4,5,6,7"
line.long 0x24 "PR1_CFG__SLV__REGS_pru1_ed_tx_cfg_reg,"
hexmask.long.word 0x24 16.--31. 1. "PRU1_ED_TX_DIV_FACTOR,"
bitfld.long 0x24 15. "PRU1_ED_TX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x24 11. "PRU1_ENDAT_SHARE_EN," "0,1"
rbitfld.long 0x24 10. "PRU1_ENDAT2_CLK_SYNC," "0,1"
newline
rbitfld.long 0x24 9. "PRU1_ENDAT1_CLK_SYNC," "0,1"
rbitfld.long 0x24 8. "PRU1_ENDAT0_CLK_SYNC," "0,1"
newline
rbitfld.long 0x24 7. "PRU1_ED_BUSY_2," "0,1"
rbitfld.long 0x24 6. "PRU1_ED_BUSY_1," "0,1"
newline
rbitfld.long 0x24 5. "PRU1_ED_BUSY_0," "0,1"
bitfld.long 0x24 4. "PRU1_ED_TX_CLK_SEL," "0,1"
line.long 0x28 "PR1_CFG__SLV__REGS_pru1_ed_ch0_cfg0_reg,"
bitfld.long 0x28 31. "PRU1_ED_TX_FIFO_SWAP_BITS0," "0,1"
bitfld.long 0x28 30. "PRU1_ED_SW_CLK_OUT0," "0,1"
newline
bitfld.long 0x28 29. "PRU1_ED_CLK_OUT_OVR_EN0," "0,1"
rbitfld.long 0x28 28. "PRU1_ED_RX_SNOOP0," "0,1"
newline
hexmask.long.word 0x28 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE0,"
hexmask.long.byte 0x28 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE0,"
newline
hexmask.long.word 0x28 0.--10. 1. "PRU1_ED_TX_WDLY0,"
line.long 0x2C "PR1_CFG__SLV__REGS_pru1_ed_ch0_cfg1_reg,"
hexmask.long.word 0x2C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER0,"
hexmask.long.word 0x2C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER0,"
line.long 0x30 "PR1_CFG__SLV__REGS_pru1_ed_ch1_cfg0_reg,"
bitfld.long 0x30 31. "PRU1_ED_TX_FIFO_SWAP_BITS1," "0,1"
bitfld.long 0x30 30. "PRU1_ED_SW_CLK_OUT1," "0,1"
newline
bitfld.long 0x30 29. "PRU1_ED_CLK_OUT_OVR_EN1," "0,1"
rbitfld.long 0x30 28. "PRU1_ED_RX_SNOOP1," "0,1"
newline
hexmask.long.word 0x30 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE1,"
hexmask.long.byte 0x30 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE1,"
newline
hexmask.long.word 0x30 0.--10. 1. "PRU1_ED_TX_WDLY1,"
line.long 0x34 "PR1_CFG__SLV__REGS_pru1_ed_ch1_cfg1_reg,"
hexmask.long.word 0x34 16.--31. 1. "PRU1_ED_RX_EN_COUNTER1,"
hexmask.long.word 0x34 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER1,"
line.long 0x38 "PR1_CFG__SLV__REGS_pru1_ed_ch2_cfg0_reg,"
bitfld.long 0x38 31. "PRU1_ED_TX_FIFO_SWAP_BITS2," "0,1"
bitfld.long 0x38 30. "PRU1_ED_SW_CLK_OUT2," "0,1"
newline
bitfld.long 0x38 29. "PRU1_ED_CLK_OUT_OVR_EN2," "0,1"
rbitfld.long 0x38 28. "PRU1_ED_RX_SNOOP2," "0,1"
newline
hexmask.long.word 0x38 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE2,"
hexmask.long.byte 0x38 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE2,"
newline
hexmask.long.word 0x38 0.--10. 1. "PRU1_ED_TX_WDLY2,"
line.long 0x3C "PR1_CFG__SLV__REGS_pru1_ed_ch2_cfg1_reg,"
hexmask.long.word 0x3C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER2,"
hexmask.long.word 0x3C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER2,"
group.long 0x124++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_rtu0_poke_en0_reg,"
hexmask.long.byte 0x0 28.--31. 1. "RTU0_POKE_R27_EN,"
hexmask.long.byte 0x0 24.--27. 1. "RTU0_POKE_R26_EN,"
newline
hexmask.long.byte 0x0 20.--23. 1. "RTU0_POKE_R25_EN,"
hexmask.long.byte 0x0 16.--19. 1. "RTU0_POKE_R24_EN,"
newline
hexmask.long.byte 0x0 12.--15. 1. "RTU0_POKE_R23_EN,"
hexmask.long.byte 0x0 8.--11. 1. "RTU0_POKE_R22_EN,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RTU0_POKE_R21_EN,"
hexmask.long.byte 0x0 0.--3. 1. "RTU0_POKE_R20_EN,"
group.long 0x12C++0x4F
line.long 0x0 "PR1_CFG__SLV__REGS_rtu1_poke_en0_reg,"
hexmask.long.byte 0x0 28.--31. 1. "RTU1_POKE_R27_EN,"
hexmask.long.byte 0x0 24.--27. 1. "RTU1_POKE_R26_EN,"
newline
hexmask.long.byte 0x0 20.--23. 1. "RTU1_POKE_R25_EN,"
hexmask.long.byte 0x0 16.--19. 1. "RTU1_POKE_R24_EN,"
newline
hexmask.long.byte 0x0 12.--15. 1. "RTU1_POKE_R23_EN,"
hexmask.long.byte 0x0 8.--11. 1. "RTU1_POKE_R22_EN,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RTU1_POKE_R21_EN,"
hexmask.long.byte 0x0 0.--3. 1. "RTU1_POKE_R20_EN,"
line.long 0x4 "PR1_CFG__SLV__REGS_pwm0,"
bitfld.long 0x4 30. "PWM0_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0x4 21.--29. 1. "PWM0_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0x4 20. "PWM0_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0x4 19. "PWM0_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0x4 18. "PWM0_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0x4 17. "PWM0_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0x4 8.--16. 1. "PWM0_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0x4 0.--7. 1. "PWM0_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0x8 "PR1_CFG__SLV__REGS_pwm1,"
bitfld.long 0x8 30. "PWM1_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0x8 21.--29. 1. "PWM1_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0x8 20. "PWM1_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0x8 19. "PWM1_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0x8 18. "PWM1_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0x8 17. "PWM1_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0x8 8.--16. 1. "PWM1_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0x8 0.--7. 1. "PWM1_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0xC "PR1_CFG__SLV__REGS_pwm2,"
bitfld.long 0xC 30. "PWM2_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0xC 21.--29. 1. "PWM2_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0xC 20. "PWM2_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0xC 19. "PWM2_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0xC 18. "PWM2_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0xC 17. "PWM2_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0xC 8.--16. 1. "PWM2_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0xC 0.--7. 1. "PWM2_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0x10 "PR1_CFG__SLV__REGS_pwm3,"
bitfld.long 0x10 30. "PWM3_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0x10 21.--29. 1. "PWM3_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0x10 20. "PWM3_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0x10 19. "PWM3_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0x10 18. "PWM3_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0x10 17. "PWM3_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0x10 8.--16. 1. "PWM3_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0x10 0.--7. 1. "PWM3_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0x14 "PR1_CFG__SLV__REGS_pwm0_0,"
bitfld.long 0x14 10.--11. "PWM0_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x14 8.--9. "PWM0_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x14 6.--7. "PWM0_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x14 4.--5. "PWM0_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "PWM0_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x14 0.--1. "PWM0_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x18 "PR1_CFG__SLV__REGS_pwm0_1,"
bitfld.long 0x18 10.--11. "PWM0_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x18 8.--9. "PWM0_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x18 6.--7. "PWM0_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x18 4.--5. "PWM0_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "PWM0_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x18 0.--1. "PWM0_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x1C "PR1_CFG__SLV__REGS_pwm0_2,"
bitfld.long 0x1C 10.--11. "PWM0_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x1C 8.--9. "PWM0_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "PWM0_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x1C 4.--5. "PWM0_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x1C 2.--3. "PWM0_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x1C 0.--1. "PWM0_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x20 "PR1_CFG__SLV__REGS_pwm1_0,"
bitfld.long 0x20 10.--11. "PWM1_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x20 8.--9. "PWM1_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x20 6.--7. "PWM1_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x20 4.--5. "PWM1_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x20 2.--3. "PWM1_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x20 0.--1. "PWM1_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x24 "PR1_CFG__SLV__REGS_pwm1_1,"
bitfld.long 0x24 10.--11. "PWM1_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x24 8.--9. "PWM1_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "PWM1_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x24 4.--5. "PWM1_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x24 2.--3. "PWM1_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x24 0.--1. "PWM1_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x28 "PR1_CFG__SLV__REGS_pwm1_2,"
bitfld.long 0x28 10.--11. "PWM1_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x28 8.--9. "PWM1_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x28 6.--7. "PWM1_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x28 4.--5. "PWM1_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x28 2.--3. "PWM1_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x28 0.--1. "PWM1_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x2C "PR1_CFG__SLV__REGS_pwm2_0,"
bitfld.long 0x2C 10.--11. "PWM2_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x2C 8.--9. "PWM2_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x2C 6.--7. "PWM2_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x2C 4.--5. "PWM2_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x2C 2.--3. "PWM2_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x2C 0.--1. "PWM2_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x30 "PR1_CFG__SLV__REGS_pwm2_1,"
bitfld.long 0x30 10.--11. "PWM2_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x30 8.--9. "PWM2_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x30 6.--7. "PWM2_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x30 4.--5. "PWM2_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x30 2.--3. "PWM2_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x30 0.--1. "PWM2_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x34 "PR1_CFG__SLV__REGS_pwm2_2,"
bitfld.long 0x34 10.--11. "PWM2_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x34 8.--9. "PWM2_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "PWM2_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x34 4.--5. "PWM2_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x34 2.--3. "PWM2_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x34 0.--1. "PWM2_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x38 "PR1_CFG__SLV__REGS_pwm3_0,"
bitfld.long 0x38 10.--11. "PWM3_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x38 8.--9. "PWM3_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x38 6.--7. "PWM3_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x38 4.--5. "PWM3_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x38 2.--3. "PWM3_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x38 0.--1. "PWM3_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x3C "PR1_CFG__SLV__REGS_pwm3_1,"
bitfld.long 0x3C 10.--11. "PWM3_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x3C 8.--9. "PWM3_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x3C 6.--7. "PWM3_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x3C 4.--5. "PWM3_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x3C 2.--3. "PWM3_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x3C 0.--1. "PWM3_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x40 "PR1_CFG__SLV__REGS_pwm3_2,"
bitfld.long 0x40 10.--11. "PWM3_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x40 8.--9. "PWM3_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x40 6.--7. "PWM3_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x40 4.--5. "PWM3_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x40 2.--3. "PWM3_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x40 0.--1. "PWM3_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x44 "PR1_CFG__SLV__REGS_spin_lock0,"
hexmask.long.byte 0x44 8.--13. 1. "MMR_OWN_REQ_VECTOR_0,Spin Lock flag Vector"
eventfld.long 0x44 1. "MMR_OWN_REQ_CLR_0,Spin Lock Status Clear" "0,1"
newline
rbitfld.long 0x44 0. "MMR_OWN_REQ_STATUS_0,Spin Lock Status" "0,1"
line.long 0x48 "PR1_CFG__SLV__REGS_spin_lock1,"
hexmask.long.byte 0x48 8.--13. 1. "MMR_OWN_REQ_VECTOR_1,Spin Lock flag Vector"
eventfld.long 0x48 1. "MMR_OWN_REQ_CLR_1,Spin Lock Status Clear" "0,1"
newline
rbitfld.long 0x48 0. "MMR_OWN_REQ_STATUS_1,Spin Lock Status" "0,1"
line.long 0x4C "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg0,"
bitfld.long 0x4C 31. "PA_PDSP0_INC_TYPE,pa_pdsp0_inc_type" "0,1"
hexmask.long.tbyte 0x4C 14.--30. 1. "PA_PDSP0_INC_VAL,pa_pdsp0_inc_val"
newline
hexmask.long.word 0x4C 0.--13. 1. "PA_PDSP0_INDEX,pa_pdsp0_index"
rgroup.long 0x17C++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat0,"
bitfld.long 0x0 1.--3. "PA_PDSP0_STATUS,pa_pdsp0_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP0_READY,pa_pdsp0_ready" "0,1"
group.long 0x180++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg1,"
bitfld.long 0x0 31. "PA_PDSP1_INC_TYPE,pa_pdsp1_inc_type" "0,1"
hexmask.long.tbyte 0x0 14.--30. 1. "PA_PDSP1_INC_VAL,pa_pdsp1_inc_val"
newline
hexmask.long.word 0x0 0.--13. 1. "PA_PDSP1_INDEX,pa_pdsp1_index"
rgroup.long 0x184++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat1,"
bitfld.long 0x0 1.--3. "PA_PDSP1_STATUS,pa_pdsp1_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP1_READY,pa_pdsp1_ready" "0,1"
group.long 0x188++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg2,"
bitfld.long 0x0 31. "PA_PDSP2_INC_TYPE,pa_pdsp2_inc_type" "0,1"
hexmask.long.tbyte 0x0 14.--30. 1. "PA_PDSP2_INC_VAL,pa_pdsp2_inc_val"
newline
hexmask.long.word 0x0 0.--13. 1. "PA_PDSP2_INDEX,pa_pdsp2_index"
rgroup.long 0x18C++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat2,"
bitfld.long 0x0 1.--3. "PA_PDSP2_STATUS,pa_pdsp2_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP2_READY,pa_pdsp2_ready" "0,1"
group.long 0x190++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg3,"
bitfld.long 0x0 31. "PA_PDSP3_INC_TYPE,pa_pdsp3_inc_type" "0,1"
hexmask.long.tbyte 0x0 14.--30. 1. "PA_PDSP3_INC_VAL,pa_pdsp3_inc_val"
newline
hexmask.long.word 0x0 0.--13. 1. "PA_PDSP3_INDEX,pa_pdsp3_index"
rgroup.long 0x194++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat3,"
bitfld.long 0x0 1.--3. "PA_PDSP3_STATUS,pa_pdsp3_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP3_READY,pa_pdsp3_ready" "0,1"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_MDIO_V1P7_MDIO"
base ad:0x32400
rgroup.long 0x0++0x3
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_MDIO_VERSION_REG,version_reg"
hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID"
hexmask.long.byte 0x0 8.--15. 1. "REVMAJ,Major revision value"
hexmask.long.byte 0x0 0.--7. 1. "REVMINOR,Minor revision value"
group.long 0x4++0x7
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_CONTROL_REG,control_reg"
rbitfld.long 0x0 31. "IDLE,MDIO state machine idle" "0,1"
bitfld.long 0x0 30. "ENABLE,Enable control" "0,1"
hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel"
newline
bitfld.long 0x0 20. "PREAMBLE,Preamble disable" "0,1"
bitfld.long 0x0 19. "FAULT,Fault indicator" "0,1"
bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
newline
bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock divider"
line.long 0x4 "PR1_MDIO_V1P7__MDIO__REGS_ALIVE_REG,alive_reg"
hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO alive"
rgroup.long 0xC++0x3
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_LINK_REG,link_reg"
hexmask.long 0x0 0.--31. 1. "LINK,MDIO link state"
group.long 0x10++0x37
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_RAW_REG,link_int_raw_reg"
bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x4 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASKED_REG,link_int_masked_reg"
bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x8 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASK_SET_REG,link_int_mask_set_reg"
bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0xC "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASK_CLEAR_REG,link_int_mask_clear_reg"
bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x10 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_RAW_REG,user_int_raw_reg"
bitfld.long 0x10 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
line.long 0x14 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASKED_REG,user_int_masked_reg"
bitfld.long 0x14 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
line.long 0x18 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASK_SET_REG,user_int_mask_set_reg"
bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
line.long 0x1C "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASK_CLEAR_REG,user_int_mask_clear_reg"
bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
line.long 0x20 "PR1_MDIO_V1P7__MDIO__REGS_MANUAL_IF_REG,manual_if_reg"
bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable" "0,1"
bitfld.long 0x20 0. "MDIO_PIN,MDIO Pin" "0,1"
line.long 0x24 "PR1_MDIO_V1P7__MDIO__REGS_POLL_REG,poll_reg"
bitfld.long 0x24 31. "MANUALMODE,MDIO Manual Mode" "0,1"
bitfld.long 0x24 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
hexmask.long.byte 0x24 0.--7. 1. "IPG,MDIO IPG"
line.long 0x28 "PR1_MDIO_V1P7__MDIO__REGS_POLL_EN_REG,poll_en_reg"
hexmask.long 0x28 0.--31. 1. "POLL_EN,MDIO Poll Enable"
line.long 0x2C "PR1_MDIO_V1P7__MDIO__REGS_CLAUS45_REG,"
hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO Clause 45"
line.long 0x30 "PR1_MDIO_V1P7__MDIO__REGS_USER_ADDR0_REG,MDIO USER Address 0"
hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
line.long 0x34 "PR1_MDIO_V1P7__MDIO__REGS_USER_ADDR1_REG,MDIO USER Address 1"
hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
group.long 0x80++0x7
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_USER_ACCESS_REG,user_access_reg"
bitfld.long 0x0 31. "GO,Go" "0,1"
bitfld.long 0x0 30. "WRITE,Write" "0,1"
bitfld.long 0x0 29. "ACK,Acknowledge" "0,1"
newline
hexmask.long.byte 0x0 21.--25. 1. "REGADR,Register address"
hexmask.long.byte 0x0 16.--20. 1. "PHYADR,PHY address"
hexmask.long.word 0x0 0.--15. 1. "DATA,User data"
line.long 0x4 "PR1_MDIO_V1P7__MDIO__REGS_USER_PHY_SEL_REG,user_phy_sel_reg"
bitfld.long 0x4 7. "LINKSEL,Link status determination select" "0,1"
bitfld.long 0x4 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
hexmask.long.byte 0x4 0.--4. 1. "PHYADR_MON,PHY address whose link status is monitored"
tree.end
endif
tree "PRU_ICSSG0_PR1_ICSS"
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV (PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV)"
base ad:0x30020000
rgroup.long 0x0++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_REVISION_REG,"
bitfld.long 0x0 30.--31. "REV_SCHEME,Scheme" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "REV_MODULE,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REV_RTL,RTL revisions"
newline
bitfld.long 0x0 8.--10. "REV_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "REV_CUSTOM,Custom revision" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REV_MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_CONTROL_REG,"
bitfld.long 0x0 4. "PRIORITY_HOLD_MODE,Priority Holding Mode" "0,1"
bitfld.long 0x0 2.--3. "NEST_MODE,Nesting Mode" "0,1,2,3"
bitfld.long 0x0 1. "WAKEUP_MODE,Wakeup mode enable" "0,1"
group.long 0x10++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_GLOBAL_ENABLE_HINT_REG,"
bitfld.long 0x0 0. "ENABLE_HINT_ANY,Global Enable for all Host Ints" "0,1"
group.long 0x1C++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_GLB_NEST_LEVEL_REG,"
bitfld.long 0x0 31. "GLB_NEST_AUTO_OVR,Global Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x0 0.--8. 1. "GLB_NEST_LEVEL,Global Nesting Level"
wgroup.long 0x20++0x7
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_STATUS_SET_INDEX_REG,"
hexmask.long.word 0x0 0.--9. 1. "STATUS_SET_INDEX,Status Set Index Register (write index to set status of)"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_STATUS_CLR_INDEX_REG,"
hexmask.long.word 0x4 0.--9. 1. "STATUS_CLR_INDEX,Status Clear Index Register (write index to clear status of)"
group.long 0x28++0x7
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_SET_INDEX_REG,"
hexmask.long.word 0x0 0.--9. 1. "ENABLE_SET_INDEX,Enable Set Index Register (write index to set enable of)"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_INDEX_REG,"
hexmask.long.word 0x4 0.--9. 1. "ENABLE_CLR_INDEX,Enable Clear Index Register (write index to clear enable of)"
group.long 0x34++0x7
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_ENABLE_SET_INDEX_REG,"
hexmask.long.word 0x0 0.--9. 1. "HINT_ENABLE_SET_INDEX,Enable set for Host Interrupts"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_ENABLE_CLR_INDEX_REG,"
hexmask.long.word 0x4 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Enable clear for Host Interrupts"
rgroup.long 0x80++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_GLB_PRI_INTR_REG,"
bitfld.long 0x0 31. "GLB_NONE,No interrupt pending flag" "0,1"
hexmask.long.word 0x0 0.--9. 1. "GLB_PRI_INTR,Prioritized Interrupt"
group.long 0x200++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG0,"
bitfld.long 0x0 31. "RAW_STATUS_31,Raw Status (write 1 to set) for intr_in[31]" "0,1"
bitfld.long 0x0 30. "RAW_STATUS_30,Raw Status (write 1 to set) for intr_in[30]" "0,1"
bitfld.long 0x0 29. "RAW_STATUS_29,Raw Status (write 1 to set) for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "RAW_STATUS_28,Raw Status (write 1 to set) for intr_in[28]" "0,1"
bitfld.long 0x0 27. "RAW_STATUS_27,Raw Status (write 1 to set) for intr_in[27]" "0,1"
bitfld.long 0x0 26. "RAW_STATUS_26,Raw Status (write 1 to set) for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "RAW_STATUS_25,Raw Status (write 1 to set) for intr_in[25]" "0,1"
bitfld.long 0x0 24. "RAW_STATUS_24,Raw Status (write 1 to set) for intr_in[24]" "0,1"
bitfld.long 0x0 23. "RAW_STATUS_23,Raw Status (write 1 to set) for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "RAW_STATUS_22,Raw Status (write 1 to set) for intr_in[22]" "0,1"
bitfld.long 0x0 21. "RAW_STATUS_21,Raw Status (write 1 to set) for intr_in[21]" "0,1"
bitfld.long 0x0 20. "RAW_STATUS_20,Raw Status (write 1 to set) for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "RAW_STATUS_19,Raw Status (write 1 to set) for intr_in[19]" "0,1"
bitfld.long 0x0 18. "RAW_STATUS_18,Raw Status (write 1 to set) for intr_in[18]" "0,1"
bitfld.long 0x0 17. "RAW_STATUS_17,Raw Status (write 1 to set) for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "RAW_STATUS_16,Raw Status (write 1 to set) for intr_in[16]" "0,1"
bitfld.long 0x0 15. "RAW_STATUS_15,Raw Status (write 1 to set) for intr_in[15]" "0,1"
bitfld.long 0x0 14. "RAW_STATUS_14,Raw Status (write 1 to set) for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "RAW_STATUS_13,Raw Status (write 1 to set) for intr_in[13]" "0,1"
bitfld.long 0x0 12. "RAW_STATUS_12,Raw Status (write 1 to set) for intr_in[12]" "0,1"
bitfld.long 0x0 11. "RAW_STATUS_11,Raw Status (write 1 to set) for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "RAW_STATUS_10,Raw Status (write 1 to set) for intr_in[10]" "0,1"
bitfld.long 0x0 9. "RAW_STATUS_9,Raw Status (write 1 to set) for intr_in[9]" "0,1"
bitfld.long 0x0 8. "RAW_STATUS_8,Raw Status (write 1 to set) for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "RAW_STATUS_7,Raw Status (write 1 to set) for intr_in[7]" "0,1"
bitfld.long 0x0 6. "RAW_STATUS_6,Raw Status (write 1 to set) for intr_in[6]" "0,1"
bitfld.long 0x0 5. "RAW_STATUS_5,Raw Status (write 1 to set) for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "RAW_STATUS_4,Raw Status (write 1 to set) for intr_in[4]" "0,1"
bitfld.long 0x0 3. "RAW_STATUS_3,Raw Status (write 1 to set) for intr_in[3]" "0,1"
bitfld.long 0x0 2. "RAW_STATUS_2,Raw Status (write 1 to set) for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "RAW_STATUS_1,Raw Status (write 1 to set) for intr_in[1]" "0,1"
bitfld.long 0x0 0. "RAW_STATUS_0,Raw Status (write 1 to set) for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG1,"
bitfld.long 0x4 31. "RAW_STATUS_63,Raw Status (write 1 to set) for intr_in[63]" "0,1"
bitfld.long 0x4 30. "RAW_STATUS_62,Raw Status (write 1 to set) for intr_in[62]" "0,1"
bitfld.long 0x4 29. "RAW_STATUS_61,Raw Status (write 1 to set) for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "RAW_STATUS_60,Raw Status (write 1 to set) for intr_in[60]" "0,1"
bitfld.long 0x4 27. "RAW_STATUS_59,Raw Status (write 1 to set) for intr_in[59]" "0,1"
bitfld.long 0x4 26. "RAW_STATUS_58,Raw Status (write 1 to set) for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "RAW_STATUS_57,Raw Status (write 1 to set) for intr_in[57]" "0,1"
bitfld.long 0x4 24. "RAW_STATUS_56,Raw Status (write 1 to set) for intr_in[56]" "0,1"
bitfld.long 0x4 23. "RAW_STATUS_55,Raw Status (write 1 to set) for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "RAW_STATUS_54,Raw Status (write 1 to set) for intr_in[54]" "0,1"
bitfld.long 0x4 21. "RAW_STATUS_53,Raw Status (write 1 to set) for intr_in[53]" "0,1"
bitfld.long 0x4 20. "RAW_STATUS_52,Raw Status (write 1 to set) for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "RAW_STATUS_51,Raw Status (write 1 to set) for intr_in[51]" "0,1"
bitfld.long 0x4 18. "RAW_STATUS_50,Raw Status (write 1 to set) for intr_in[50]" "0,1"
bitfld.long 0x4 17. "RAW_STATUS_49,Raw Status (write 1 to set) for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "RAW_STATUS_48,Raw Status (write 1 to set) for intr_in[48]" "0,1"
bitfld.long 0x4 15. "RAW_STATUS_47,Raw Status (write 1 to set) for intr_in[47]" "0,1"
bitfld.long 0x4 14. "RAW_STATUS_46,Raw Status (write 1 to set) for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "RAW_STATUS_45,Raw Status (write 1 to set) for intr_in[45]" "0,1"
bitfld.long 0x4 12. "RAW_STATUS_44,Raw Status (write 1 to set) for intr_in[44]" "0,1"
bitfld.long 0x4 11. "RAW_STATUS_43,Raw Status (write 1 to set) for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "RAW_STATUS_42,Raw Status (write 1 to set) for intr_in[42]" "0,1"
bitfld.long 0x4 9. "RAW_STATUS_41,Raw Status (write 1 to set) for intr_in[41]" "0,1"
bitfld.long 0x4 8. "RAW_STATUS_40,Raw Status (write 1 to set) for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "RAW_STATUS_39,Raw Status (write 1 to set) for intr_in[39]" "0,1"
bitfld.long 0x4 6. "RAW_STATUS_38,Raw Status (write 1 to set) for intr_in[38]" "0,1"
bitfld.long 0x4 5. "RAW_STATUS_37,Raw Status (write 1 to set) for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "RAW_STATUS_36,Raw Status (write 1 to set) for intr_in[36]" "0,1"
bitfld.long 0x4 3. "RAW_STATUS_35,Raw Status (write 1 to set) for intr_in[35]" "0,1"
bitfld.long 0x4 2. "RAW_STATUS_34,Raw Status (write 1 to set) for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "RAW_STATUS_33,Raw Status (write 1 to set) for intr_in[33]" "0,1"
bitfld.long 0x4 0. "RAW_STATUS_32,Raw Status (write 1 to set) for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG2,"
bitfld.long 0x8 31. "RAW_STATUS_95,Raw Status (write 1 to set) for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "RAW_STATUS_94,Raw Status (write 1 to set) for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "RAW_STATUS_93,Raw Status (write 1 to set) for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "RAW_STATUS_92,Raw Status (write 1 to set) for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "RAW_STATUS_91,Raw Status (write 1 to set) for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "RAW_STATUS_90,Raw Status (write 1 to set) for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "RAW_STATUS_89,Raw Status (write 1 to set) for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "RAW_STATUS_88,Raw Status (write 1 to set) for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "RAW_STATUS_87,Raw Status (write 1 to set) for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "RAW_STATUS_86,Raw Status (write 1 to set) for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "RAW_STATUS_85,Raw Status (write 1 to set) for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "RAW_STATUS_84,Raw Status (write 1 to set) for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "RAW_STATUS_83,Raw Status (write 1 to set) for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "RAW_STATUS_82,Raw Status (write 1 to set) for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "RAW_STATUS_81,Raw Status (write 1 to set) for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "RAW_STATUS_80,Raw Status (write 1 to set) for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "RAW_STATUS_79,Raw Status (write 1 to set) for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "RAW_STATUS_78,Raw Status (write 1 to set) for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "RAW_STATUS_77,Raw Status (write 1 to set) for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "RAW_STATUS_76,Raw Status (write 1 to set) for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "RAW_STATUS_75,Raw Status (write 1 to set) for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "RAW_STATUS_74,Raw Status (write 1 to set) for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "RAW_STATUS_73,Raw Status (write 1 to set) for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "RAW_STATUS_72,Raw Status (write 1 to set) for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "RAW_STATUS_71,Raw Status (write 1 to set) for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "RAW_STATUS_70,Raw Status (write 1 to set) for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "RAW_STATUS_69,Raw Status (write 1 to set) for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "RAW_STATUS_68,Raw Status (write 1 to set) for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "RAW_STATUS_67,Raw Status (write 1 to set) for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "RAW_STATUS_66,Raw Status (write 1 to set) for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "RAW_STATUS_65,Raw Status (write 1 to set) for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "RAW_STATUS_64,Raw Status (write 1 to set) for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG3,"
bitfld.long 0xC 31. "RAW_STATUS_127,Raw Status (write 1 to set) for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "RAW_STATUS_126,Raw Status (write 1 to set) for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "RAW_STATUS_125,Raw Status (write 1 to set) for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "RAW_STATUS_124,Raw Status (write 1 to set) for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "RAW_STATUS_123,Raw Status (write 1 to set) for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "RAW_STATUS_122,Raw Status (write 1 to set) for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "RAW_STATUS_121,Raw Status (write 1 to set) for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "RAW_STATUS_120,Raw Status (write 1 to set) for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "RAW_STATUS_119,Raw Status (write 1 to set) for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "RAW_STATUS_118,Raw Status (write 1 to set) for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "RAW_STATUS_117,Raw Status (write 1 to set) for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "RAW_STATUS_116,Raw Status (write 1 to set) for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "RAW_STATUS_115,Raw Status (write 1 to set) for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "RAW_STATUS_114,Raw Status (write 1 to set) for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "RAW_STATUS_113,Raw Status (write 1 to set) for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "RAW_STATUS_112,Raw Status (write 1 to set) for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "RAW_STATUS_111,Raw Status (write 1 to set) for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "RAW_STATUS_110,Raw Status (write 1 to set) for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "RAW_STATUS_109,Raw Status (write 1 to set) for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "RAW_STATUS_108,Raw Status (write 1 to set) for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "RAW_STATUS_107,Raw Status (write 1 to set) for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "RAW_STATUS_106,Raw Status (write 1 to set) for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "RAW_STATUS_105,Raw Status (write 1 to set) for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "RAW_STATUS_104,Raw Status (write 1 to set) for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "RAW_STATUS_103,Raw Status (write 1 to set) for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "RAW_STATUS_102,Raw Status (write 1 to set) for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "RAW_STATUS_101,Raw Status (write 1 to set) for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "RAW_STATUS_100,Raw Status (write 1 to set) for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "RAW_STATUS_99,Raw Status (write 1 to set) for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "RAW_STATUS_98,Raw Status (write 1 to set) for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "RAW_STATUS_97,Raw Status (write 1 to set) for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "RAW_STATUS_96,Raw Status (write 1 to set) for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG4,"
bitfld.long 0x10 31. "RAW_STATUS_159,Raw Status (write 1 to set) for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "RAW_STATUS_158,Raw Status (write 1 to set) for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "RAW_STATUS_157,Raw Status (write 1 to set) for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "RAW_STATUS_156,Raw Status (write 1 to set) for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "RAW_STATUS_155,Raw Status (write 1 to set) for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "RAW_STATUS_154,Raw Status (write 1 to set) for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "RAW_STATUS_153,Raw Status (write 1 to set) for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "RAW_STATUS_152,Raw Status (write 1 to set) for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "RAW_STATUS_151,Raw Status (write 1 to set) for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "RAW_STATUS_150,Raw Status (write 1 to set) for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "RAW_STATUS_149,Raw Status (write 1 to set) for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "RAW_STATUS_148,Raw Status (write 1 to set) for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "RAW_STATUS_147,Raw Status (write 1 to set) for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "RAW_STATUS_146,Raw Status (write 1 to set) for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "RAW_STATUS_145,Raw Status (write 1 to set) for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "RAW_STATUS_144,Raw Status (write 1 to set) for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "RAW_STATUS_143,Raw Status (write 1 to set) for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "RAW_STATUS_142,Raw Status (write 1 to set) for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "RAW_STATUS_141,Raw Status (write 1 to set) for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "RAW_STATUS_140,Raw Status (write 1 to set) for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "RAW_STATUS_139,Raw Status (write 1 to set) for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "RAW_STATUS_138,Raw Status (write 1 to set) for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "RAW_STATUS_137,Raw Status (write 1 to set) for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "RAW_STATUS_136,Raw Status (write 1 to set) for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "RAW_STATUS_135,Raw Status (write 1 to set) for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "RAW_STATUS_134,Raw Status (write 1 to set) for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "RAW_STATUS_133,Raw Status (write 1 to set) for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "RAW_STATUS_132,Raw Status (write 1 to set) for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "RAW_STATUS_131,Raw Status (write 1 to set) for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "RAW_STATUS_130,Raw Status (write 1 to set) for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "RAW_STATUS_129,Raw Status (write 1 to set) for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "RAW_STATUS_128,Raw Status (write 1 to set) for slv_events_in[64]" "0,1"
group.long 0x280++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG0,"
bitfld.long 0x0 31. "ENA_STATUS_31,Enabled Status for intr_in[31]" "0,1"
bitfld.long 0x0 30. "ENA_STATUS_30,Enabled Status for intr_in[30]" "0,1"
bitfld.long 0x0 29. "ENA_STATUS_29,Enabled Status for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "ENA_STATUS_28,Enabled Status for intr_in[28]" "0,1"
bitfld.long 0x0 27. "ENA_STATUS_27,Enabled Status for intr_in[27]" "0,1"
bitfld.long 0x0 26. "ENA_STATUS_26,Enabled Status for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "ENA_STATUS_25,Enabled Status for intr_in[25]" "0,1"
bitfld.long 0x0 24. "ENA_STATUS_24,Enabled Status for intr_in[24]" "0,1"
bitfld.long 0x0 23. "ENA_STATUS_23,Enabled Status for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "ENA_STATUS_22,Enabled Status for intr_in[22]" "0,1"
bitfld.long 0x0 21. "ENA_STATUS_21,Enabled Status for intr_in[21]" "0,1"
bitfld.long 0x0 20. "ENA_STATUS_20,Enabled Status for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "ENA_STATUS_19,Enabled Status for intr_in[19]" "0,1"
bitfld.long 0x0 18. "ENA_STATUS_18,Enabled Status for intr_in[18]" "0,1"
bitfld.long 0x0 17. "ENA_STATUS_17,Enabled Status for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "ENA_STATUS_16,Enabled Status for intr_in[16]" "0,1"
bitfld.long 0x0 15. "ENA_STATUS_15,Enabled Status for intr_in[15]" "0,1"
bitfld.long 0x0 14. "ENA_STATUS_14,Enabled Status for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "ENA_STATUS_13,Enabled Status for intr_in[13]" "0,1"
bitfld.long 0x0 12. "ENA_STATUS_12,Enabled Status for intr_in[12]" "0,1"
bitfld.long 0x0 11. "ENA_STATUS_11,Enabled Status for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "ENA_STATUS_10,Enabled Status for intr_in[10]" "0,1"
bitfld.long 0x0 9. "ENA_STATUS_9,Enabled Status for intr_in[9]" "0,1"
bitfld.long 0x0 8. "ENA_STATUS_8,Enabled Status for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "ENA_STATUS_7,Enabled Status for intr_in[7]" "0,1"
bitfld.long 0x0 6. "ENA_STATUS_6,Enabled Status for intr_in[6]" "0,1"
bitfld.long 0x0 5. "ENA_STATUS_5,Enabled Status for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "ENA_STATUS_4,Enabled Status for intr_in[4]" "0,1"
bitfld.long 0x0 3. "ENA_STATUS_3,Enabled Status for intr_in[3]" "0,1"
bitfld.long 0x0 2. "ENA_STATUS_2,Enabled Status for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "ENA_STATUS_1,Enabled Status for intr_in[1]" "0,1"
bitfld.long 0x0 0. "ENA_STATUS_0,Enabled Status for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG1,"
bitfld.long 0x4 31. "ENA_STATUS_63,Enabled Status for intr_in[63]" "0,1"
bitfld.long 0x4 30. "ENA_STATUS_62,Enabled Status for intr_in[62]" "0,1"
bitfld.long 0x4 29. "ENA_STATUS_61,Enabled Status for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "ENA_STATUS_60,Enabled Status for intr_in[60]" "0,1"
bitfld.long 0x4 27. "ENA_STATUS_59,Enabled Status for intr_in[59]" "0,1"
bitfld.long 0x4 26. "ENA_STATUS_58,Enabled Status for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "ENA_STATUS_57,Enabled Status for intr_in[57]" "0,1"
bitfld.long 0x4 24. "ENA_STATUS_56,Enabled Status for intr_in[56]" "0,1"
bitfld.long 0x4 23. "ENA_STATUS_55,Enabled Status for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "ENA_STATUS_54,Enabled Status for intr_in[54]" "0,1"
bitfld.long 0x4 21. "ENA_STATUS_53,Enabled Status for intr_in[53]" "0,1"
bitfld.long 0x4 20. "ENA_STATUS_52,Enabled Status for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "ENA_STATUS_51,Enabled Status for intr_in[51]" "0,1"
bitfld.long 0x4 18. "ENA_STATUS_50,Enabled Status for intr_in[50]" "0,1"
bitfld.long 0x4 17. "ENA_STATUS_49,Enabled Status for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "ENA_STATUS_48,Enabled Status for intr_in[48]" "0,1"
bitfld.long 0x4 15. "ENA_STATUS_47,Enabled Status for intr_in[47]" "0,1"
bitfld.long 0x4 14. "ENA_STATUS_46,Enabled Status for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "ENA_STATUS_45,Enabled Status for intr_in[45]" "0,1"
bitfld.long 0x4 12. "ENA_STATUS_44,Enabled Status for intr_in[44]" "0,1"
bitfld.long 0x4 11. "ENA_STATUS_43,Enabled Status for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "ENA_STATUS_42,Enabled Status for intr_in[42]" "0,1"
bitfld.long 0x4 9. "ENA_STATUS_41,Enabled Status for intr_in[41]" "0,1"
bitfld.long 0x4 8. "ENA_STATUS_40,Enabled Status for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "ENA_STATUS_39,Enabled Status for intr_in[39]" "0,1"
bitfld.long 0x4 6. "ENA_STATUS_38,Enabled Status for intr_in[38]" "0,1"
bitfld.long 0x4 5. "ENA_STATUS_37,Enabled Status for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "ENA_STATUS_36,Enabled Status for intr_in[36]" "0,1"
bitfld.long 0x4 3. "ENA_STATUS_35,Enabled Status for intr_in[35]" "0,1"
bitfld.long 0x4 2. "ENA_STATUS_34,Enabled Status for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "ENA_STATUS_33,Enabled Status for intr_in[33]" "0,1"
bitfld.long 0x4 0. "ENA_STATUS_32,Enabled Status for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG2,"
bitfld.long 0x8 31. "ENA_STATUS_95,Enabled Status for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "ENA_STATUS_94,Enabled Status for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "ENA_STATUS_93,Enabled Status for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "ENA_STATUS_92,Enabled Status for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "ENA_STATUS_91,Enabled Status for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "ENA_STATUS_90,Enabled Status for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "ENA_STATUS_89,Enabled Status for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "ENA_STATUS_88,Enabled Status for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "ENA_STATUS_87,Enabled Status for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "ENA_STATUS_86,Enabled Status for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "ENA_STATUS_85,Enabled Status for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "ENA_STATUS_84,Enabled Status for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "ENA_STATUS_83,Enabled Status for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "ENA_STATUS_82,Enabled Status for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "ENA_STATUS_81,Enabled Status for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "ENA_STATUS_80,Enabled Status for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "ENA_STATUS_79,Enabled Status for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "ENA_STATUS_78,Enabled Status for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "ENA_STATUS_77,Enabled Status for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "ENA_STATUS_76,Enabled Status for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "ENA_STATUS_75,Enabled Status for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "ENA_STATUS_74,Enabled Status for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "ENA_STATUS_73,Enabled Status for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "ENA_STATUS_72,Enabled Status for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "ENA_STATUS_71,Enabled Status for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "ENA_STATUS_70,Enabled Status for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "ENA_STATUS_69,Enabled Status for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "ENA_STATUS_68,Enabled Status for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "ENA_STATUS_67,Enabled Status for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "ENA_STATUS_66,Enabled Status for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "ENA_STATUS_65,Enabled Status for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "ENA_STATUS_64,Enabled Status for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG3,"
bitfld.long 0xC 31. "ENA_STATUS_127,Enabled Status for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "ENA_STATUS_126,Enabled Status for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "ENA_STATUS_125,Enabled Status for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "ENA_STATUS_124,Enabled Status for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "ENA_STATUS_123,Enabled Status for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "ENA_STATUS_122,Enabled Status for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "ENA_STATUS_121,Enabled Status for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "ENA_STATUS_120,Enabled Status for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "ENA_STATUS_119,Enabled Status for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "ENA_STATUS_118,Enabled Status for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "ENA_STATUS_117,Enabled Status for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "ENA_STATUS_116,Enabled Status for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "ENA_STATUS_115,Enabled Status for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "ENA_STATUS_114,Enabled Status for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "ENA_STATUS_113,Enabled Status for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "ENA_STATUS_112,Enabled Status for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "ENA_STATUS_111,Enabled Status for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "ENA_STATUS_110,Enabled Status for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "ENA_STATUS_109,Enabled Status for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "ENA_STATUS_108,Enabled Status for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "ENA_STATUS_107,Enabled Status for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "ENA_STATUS_106,Enabled Status for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "ENA_STATUS_105,Enabled Status for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "ENA_STATUS_104,Enabled Status for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "ENA_STATUS_103,Enabled Status for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "ENA_STATUS_102,Enabled Status for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "ENA_STATUS_101,Enabled Status for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "ENA_STATUS_100,Enabled Status for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "ENA_STATUS_99,Enabled Status for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "ENA_STATUS_98,Enabled Status for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "ENA_STATUS_97,Enabled Status for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "ENA_STATUS_96,Enabled Status for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG4,"
bitfld.long 0x10 31. "ENA_STATUS_159,Enabled Status for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENA_STATUS_158,Enabled Status for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENA_STATUS_157,Enabled Status for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "ENA_STATUS_156,Enabled Status for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "ENA_STATUS_155,Enabled Status for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENA_STATUS_154,Enabled Status for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "ENA_STATUS_153,Enabled Status for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENA_STATUS_152,Enabled Status for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "ENA_STATUS_151,Enabled Status for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "ENA_STATUS_150,Enabled Status for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENA_STATUS_149,Enabled Status for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENA_STATUS_148,Enabled Status for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENA_STATUS_147,Enabled Status for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENA_STATUS_146,Enabled Status for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENA_STATUS_145,Enabled Status for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "ENA_STATUS_144,Enabled Status for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "ENA_STATUS_143,Enabled Status for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENA_STATUS_142,Enabled Status for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "ENA_STATUS_141,Enabled Status for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENA_STATUS_140,Enabled Status for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "ENA_STATUS_139,Enabled Status for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "ENA_STATUS_138,Enabled Status for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENA_STATUS_137,Enabled Status for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENA_STATUS_136,Enabled Status for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENA_STATUS_135,Enabled Status for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENA_STATUS_134,Enabled Status for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENA_STATUS_133,Enabled Status for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "ENA_STATUS_132,Enabled Status for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "ENA_STATUS_131,Enabled Status for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENA_STATUS_130,Enabled Status for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "ENA_STATUS_129,Enabled Status for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENA_STATUS_128,Enabled Status for slv_events_in[64]" "0,1"
group.long 0x300++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG0,"
bitfld.long 0x0 31. "ENABLE_31,Enable (set) for intr_in[31]" "0,1"
bitfld.long 0x0 30. "ENABLE_30,Enable (set) for intr_in[30]" "0,1"
bitfld.long 0x0 29. "ENABLE_29,Enable (set) for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "ENABLE_28,Enable (set) for intr_in[28]" "0,1"
bitfld.long 0x0 27. "ENABLE_27,Enable (set) for intr_in[27]" "0,1"
bitfld.long 0x0 26. "ENABLE_26,Enable (set) for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "ENABLE_25,Enable (set) for intr_in[25]" "0,1"
bitfld.long 0x0 24. "ENABLE_24,Enable (set) for intr_in[24]" "0,1"
bitfld.long 0x0 23. "ENABLE_23,Enable (set) for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "ENABLE_22,Enable (set) for intr_in[22]" "0,1"
bitfld.long 0x0 21. "ENABLE_21,Enable (set) for intr_in[21]" "0,1"
bitfld.long 0x0 20. "ENABLE_20,Enable (set) for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "ENABLE_19,Enable (set) for intr_in[19]" "0,1"
bitfld.long 0x0 18. "ENABLE_18,Enable (set) for intr_in[18]" "0,1"
bitfld.long 0x0 17. "ENABLE_17,Enable (set) for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "ENABLE_16,Enable (set) for intr_in[16]" "0,1"
bitfld.long 0x0 15. "ENABLE_15,Enable (set) for intr_in[15]" "0,1"
bitfld.long 0x0 14. "ENABLE_14,Enable (set) for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "ENABLE_13,Enable (set) for intr_in[13]" "0,1"
bitfld.long 0x0 12. "ENABLE_12,Enable (set) for intr_in[12]" "0,1"
bitfld.long 0x0 11. "ENABLE_11,Enable (set) for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "ENABLE_10,Enable (set) for intr_in[10]" "0,1"
bitfld.long 0x0 9. "ENABLE_9,Enable (set) for intr_in[9]" "0,1"
bitfld.long 0x0 8. "ENABLE_8,Enable (set) for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "ENABLE_7,Enable (set) for intr_in[7]" "0,1"
bitfld.long 0x0 6. "ENABLE_6,Enable (set) for intr_in[6]" "0,1"
bitfld.long 0x0 5. "ENABLE_5,Enable (set) for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "ENABLE_4,Enable (set) for intr_in[4]" "0,1"
bitfld.long 0x0 3. "ENABLE_3,Enable (set) for intr_in[3]" "0,1"
bitfld.long 0x0 2. "ENABLE_2,Enable (set) for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_1,Enable (set) for intr_in[1]" "0,1"
bitfld.long 0x0 0. "ENABLE_0,Enable (set) for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG1,"
bitfld.long 0x4 31. "ENABLE_63,Enable (set) for intr_in[63]" "0,1"
bitfld.long 0x4 30. "ENABLE_62,Enable (set) for intr_in[62]" "0,1"
bitfld.long 0x4 29. "ENABLE_61,Enable (set) for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "ENABLE_60,Enable (set) for intr_in[60]" "0,1"
bitfld.long 0x4 27. "ENABLE_59,Enable (set) for intr_in[59]" "0,1"
bitfld.long 0x4 26. "ENABLE_58,Enable (set) for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "ENABLE_57,Enable (set) for intr_in[57]" "0,1"
bitfld.long 0x4 24. "ENABLE_56,Enable (set) for intr_in[56]" "0,1"
bitfld.long 0x4 23. "ENABLE_55,Enable (set) for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "ENABLE_54,Enable (set) for intr_in[54]" "0,1"
bitfld.long 0x4 21. "ENABLE_53,Enable (set) for intr_in[53]" "0,1"
bitfld.long 0x4 20. "ENABLE_52,Enable (set) for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "ENABLE_51,Enable (set) for intr_in[51]" "0,1"
bitfld.long 0x4 18. "ENABLE_50,Enable (set) for intr_in[50]" "0,1"
bitfld.long 0x4 17. "ENABLE_49,Enable (set) for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "ENABLE_48,Enable (set) for intr_in[48]" "0,1"
bitfld.long 0x4 15. "ENABLE_47,Enable (set) for intr_in[47]" "0,1"
bitfld.long 0x4 14. "ENABLE_46,Enable (set) for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "ENABLE_45,Enable (set) for intr_in[45]" "0,1"
bitfld.long 0x4 12. "ENABLE_44,Enable (set) for intr_in[44]" "0,1"
bitfld.long 0x4 11. "ENABLE_43,Enable (set) for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "ENABLE_42,Enable (set) for intr_in[42]" "0,1"
bitfld.long 0x4 9. "ENABLE_41,Enable (set) for intr_in[41]" "0,1"
bitfld.long 0x4 8. "ENABLE_40,Enable (set) for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "ENABLE_39,Enable (set) for intr_in[39]" "0,1"
bitfld.long 0x4 6. "ENABLE_38,Enable (set) for intr_in[38]" "0,1"
bitfld.long 0x4 5. "ENABLE_37,Enable (set) for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "ENABLE_36,Enable (set) for intr_in[36]" "0,1"
bitfld.long 0x4 3. "ENABLE_35,Enable (set) for intr_in[35]" "0,1"
bitfld.long 0x4 2. "ENABLE_34,Enable (set) for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "ENABLE_33,Enable (set) for intr_in[33]" "0,1"
bitfld.long 0x4 0. "ENABLE_32,Enable (set) for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG2,"
bitfld.long 0x8 31. "ENABLE_95,Enable (set) for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "ENABLE_94,Enable (set) for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "ENABLE_93,Enable (set) for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "ENABLE_92,Enable (set) for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "ENABLE_91,Enable (set) for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "ENABLE_90,Enable (set) for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "ENABLE_89,Enable (set) for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "ENABLE_88,Enable (set) for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "ENABLE_87,Enable (set) for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "ENABLE_86,Enable (set) for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "ENABLE_85,Enable (set) for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "ENABLE_84,Enable (set) for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "ENABLE_83,Enable (set) for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "ENABLE_82,Enable (set) for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "ENABLE_81,Enable (set) for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "ENABLE_80,Enable (set) for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "ENABLE_79,Enable (set) for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "ENABLE_78,Enable (set) for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "ENABLE_77,Enable (set) for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "ENABLE_76,Enable (set) for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "ENABLE_75,Enable (set) for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "ENABLE_74,Enable (set) for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "ENABLE_73,Enable (set) for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "ENABLE_72,Enable (set) for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "ENABLE_71,Enable (set) for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "ENABLE_70,Enable (set) for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "ENABLE_69,Enable (set) for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "ENABLE_68,Enable (set) for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "ENABLE_67,Enable (set) for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "ENABLE_66,Enable (set) for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "ENABLE_65,Enable (set) for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "ENABLE_64,Enable (set) for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG3,"
bitfld.long 0xC 31. "ENABLE_127,Enable (set) for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "ENABLE_126,Enable (set) for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "ENABLE_125,Enable (set) for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "ENABLE_124,Enable (set) for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "ENABLE_123,Enable (set) for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "ENABLE_122,Enable (set) for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "ENABLE_121,Enable (set) for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "ENABLE_120,Enable (set) for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "ENABLE_119,Enable (set) for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "ENABLE_118,Enable (set) for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "ENABLE_117,Enable (set) for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "ENABLE_116,Enable (set) for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "ENABLE_115,Enable (set) for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "ENABLE_114,Enable (set) for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "ENABLE_113,Enable (set) for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "ENABLE_112,Enable (set) for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "ENABLE_111,Enable (set) for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "ENABLE_110,Enable (set) for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "ENABLE_109,Enable (set) for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "ENABLE_108,Enable (set) for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "ENABLE_107,Enable (set) for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "ENABLE_106,Enable (set) for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "ENABLE_105,Enable (set) for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "ENABLE_104,Enable (set) for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "ENABLE_103,Enable (set) for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "ENABLE_102,Enable (set) for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "ENABLE_101,Enable (set) for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "ENABLE_100,Enable (set) for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "ENABLE_99,Enable (set) for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "ENABLE_98,Enable (set) for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "ENABLE_97,Enable (set) for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "ENABLE_96,Enable (set) for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG4,"
bitfld.long 0x10 31. "ENABLE_159,Enable (set) for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENABLE_158,Enable (set) for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENABLE_157,Enable (set) for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_156,Enable (set) for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "ENABLE_155,Enable (set) for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENABLE_154,Enable (set) for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_153,Enable (set) for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENABLE_152,Enable (set) for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "ENABLE_151,Enable (set) for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_150,Enable (set) for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENABLE_149,Enable (set) for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENABLE_148,Enable (set) for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_147,Enable (set) for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENABLE_146,Enable (set) for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENABLE_145,Enable (set) for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_144,Enable (set) for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "ENABLE_143,Enable (set) for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENABLE_142,Enable (set) for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_141,Enable (set) for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENABLE_140,Enable (set) for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "ENABLE_139,Enable (set) for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_138,Enable (set) for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENABLE_137,Enable (set) for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENABLE_136,Enable (set) for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_135,Enable (set) for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENABLE_134,Enable (set) for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENABLE_133,Enable (set) for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_132,Enable (set) for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "ENABLE_131,Enable (set) for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENABLE_130,Enable (set) for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_129,Enable (set) for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENABLE_128,Enable (set) for slv_events_in[64]" "0,1"
group.long 0x380++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG0,"
bitfld.long 0x0 31. "ENABLE_31_CLR,Enable clear for intr_in[31]" "0,1"
bitfld.long 0x0 30. "ENABLE_30_CLR,Enable clear for intr_in[30]" "0,1"
bitfld.long 0x0 29. "ENABLE_29_CLR,Enable clear for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "ENABLE_28_CLR,Enable clear for intr_in[28]" "0,1"
bitfld.long 0x0 27. "ENABLE_27_CLR,Enable clear for intr_in[27]" "0,1"
bitfld.long 0x0 26. "ENABLE_26_CLR,Enable clear for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "ENABLE_25_CLR,Enable clear for intr_in[25]" "0,1"
bitfld.long 0x0 24. "ENABLE_24_CLR,Enable clear for intr_in[24]" "0,1"
bitfld.long 0x0 23. "ENABLE_23_CLR,Enable clear for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "ENABLE_22_CLR,Enable clear for intr_in[22]" "0,1"
bitfld.long 0x0 21. "ENABLE_21_CLR,Enable clear for intr_in[21]" "0,1"
bitfld.long 0x0 20. "ENABLE_20_CLR,Enable clear for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "ENABLE_19_CLR,Enable clear for intr_in[19]" "0,1"
bitfld.long 0x0 18. "ENABLE_18_CLR,Enable clear for intr_in[18]" "0,1"
bitfld.long 0x0 17. "ENABLE_17_CLR,Enable clear for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "ENABLE_16_CLR,Enable clear for intr_in[16]" "0,1"
bitfld.long 0x0 15. "ENABLE_15_CLR,Enable clear for intr_in[15]" "0,1"
bitfld.long 0x0 14. "ENABLE_14_CLR,Enable clear for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "ENABLE_13_CLR,Enable clear for intr_in[13]" "0,1"
bitfld.long 0x0 12. "ENABLE_12_CLR,Enable clear for intr_in[12]" "0,1"
bitfld.long 0x0 11. "ENABLE_11_CLR,Enable clear for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "ENABLE_10_CLR,Enable clear for intr_in[10]" "0,1"
bitfld.long 0x0 9. "ENABLE_9_CLR,Enable clear for intr_in[9]" "0,1"
bitfld.long 0x0 8. "ENABLE_8_CLR,Enable clear for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "ENABLE_7_CLR,Enable clear for intr_in[7]" "0,1"
bitfld.long 0x0 6. "ENABLE_6_CLR,Enable clear for intr_in[6]" "0,1"
bitfld.long 0x0 5. "ENABLE_5_CLR,Enable clear for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "ENABLE_4_CLR,Enable clear for intr_in[4]" "0,1"
bitfld.long 0x0 3. "ENABLE_3_CLR,Enable clear for intr_in[3]" "0,1"
bitfld.long 0x0 2. "ENABLE_2_CLR,Enable clear for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_1_CLR,Enable clear for intr_in[1]" "0,1"
bitfld.long 0x0 0. "ENABLE_0_CLR,Enable clear for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG1,"
bitfld.long 0x4 31. "ENABLE_63_CLR,Enable clear for intr_in[63]" "0,1"
bitfld.long 0x4 30. "ENABLE_62_CLR,Enable clear for intr_in[62]" "0,1"
bitfld.long 0x4 29. "ENABLE_61_CLR,Enable clear for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "ENABLE_60_CLR,Enable clear for intr_in[60]" "0,1"
bitfld.long 0x4 27. "ENABLE_59_CLR,Enable clear for intr_in[59]" "0,1"
bitfld.long 0x4 26. "ENABLE_58_CLR,Enable clear for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "ENABLE_57_CLR,Enable clear for intr_in[57]" "0,1"
bitfld.long 0x4 24. "ENABLE_56_CLR,Enable clear for intr_in[56]" "0,1"
bitfld.long 0x4 23. "ENABLE_55_CLR,Enable clear for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "ENABLE_54_CLR,Enable clear for intr_in[54]" "0,1"
bitfld.long 0x4 21. "ENABLE_53_CLR,Enable clear for intr_in[53]" "0,1"
bitfld.long 0x4 20. "ENABLE_52_CLR,Enable clear for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "ENABLE_51_CLR,Enable clear for intr_in[51]" "0,1"
bitfld.long 0x4 18. "ENABLE_50_CLR,Enable clear for intr_in[50]" "0,1"
bitfld.long 0x4 17. "ENABLE_49_CLR,Enable clear for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "ENABLE_48_CLR,Enable clear for intr_in[48]" "0,1"
bitfld.long 0x4 15. "ENABLE_47_CLR,Enable clear for intr_in[47]" "0,1"
bitfld.long 0x4 14. "ENABLE_46_CLR,Enable clear for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "ENABLE_45_CLR,Enable clear for intr_in[45]" "0,1"
bitfld.long 0x4 12. "ENABLE_44_CLR,Enable clear for intr_in[44]" "0,1"
bitfld.long 0x4 11. "ENABLE_43_CLR,Enable clear for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "ENABLE_42_CLR,Enable clear for intr_in[42]" "0,1"
bitfld.long 0x4 9. "ENABLE_41_CLR,Enable clear for intr_in[41]" "0,1"
bitfld.long 0x4 8. "ENABLE_40_CLR,Enable clear for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "ENABLE_39_CLR,Enable clear for intr_in[39]" "0,1"
bitfld.long 0x4 6. "ENABLE_38_CLR,Enable clear for intr_in[38]" "0,1"
bitfld.long 0x4 5. "ENABLE_37_CLR,Enable clear for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "ENABLE_36_CLR,Enable clear for intr_in[36]" "0,1"
bitfld.long 0x4 3. "ENABLE_35_CLR,Enable clear for intr_in[35]" "0,1"
bitfld.long 0x4 2. "ENABLE_34_CLR,Enable clear for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "ENABLE_33_CLR,Enable clear for intr_in[33]" "0,1"
bitfld.long 0x4 0. "ENABLE_32_CLR,Enable clear for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG2,"
bitfld.long 0x8 31. "ENABLE_95_CLR,Enable clear for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "ENABLE_94_CLR,Enable clear for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "ENABLE_93_CLR,Enable clear for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "ENABLE_92_CLR,Enable clear for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "ENABLE_91_CLR,Enable clear for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "ENABLE_90_CLR,Enable clear for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "ENABLE_89_CLR,Enable clear for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "ENABLE_88_CLR,Enable clear for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "ENABLE_87_CLR,Enable clear for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "ENABLE_86_CLR,Enable clear for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "ENABLE_85_CLR,Enable clear for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "ENABLE_84_CLR,Enable clear for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "ENABLE_83_CLR,Enable clear for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "ENABLE_82_CLR,Enable clear for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "ENABLE_81_CLR,Enable clear for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "ENABLE_80_CLR,Enable clear for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "ENABLE_79_CLR,Enable clear for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "ENABLE_78_CLR,Enable clear for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "ENABLE_77_CLR,Enable clear for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "ENABLE_76_CLR,Enable clear for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "ENABLE_75_CLR,Enable clear for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "ENABLE_74_CLR,Enable clear for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "ENABLE_73_CLR,Enable clear for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "ENABLE_72_CLR,Enable clear for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "ENABLE_71_CLR,Enable clear for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "ENABLE_70_CLR,Enable clear for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "ENABLE_69_CLR,Enable clear for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "ENABLE_68_CLR,Enable clear for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "ENABLE_67_CLR,Enable clear for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "ENABLE_66_CLR,Enable clear for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "ENABLE_65_CLR,Enable clear for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "ENABLE_64_CLR,Enable clear for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG3,"
bitfld.long 0xC 31. "ENABLE_127_CLR,Enable clear for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "ENABLE_126_CLR,Enable clear for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "ENABLE_125_CLR,Enable clear for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "ENABLE_124_CLR,Enable clear for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "ENABLE_123_CLR,Enable clear for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "ENABLE_122_CLR,Enable clear for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "ENABLE_121_CLR,Enable clear for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "ENABLE_120_CLR,Enable clear for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "ENABLE_119_CLR,Enable clear for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "ENABLE_118_CLR,Enable clear for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "ENABLE_117_CLR,Enable clear for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "ENABLE_116_CLR,Enable clear for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "ENABLE_115_CLR,Enable clear for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "ENABLE_114_CLR,Enable clear for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "ENABLE_113_CLR,Enable clear for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "ENABLE_112_CLR,Enable clear for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "ENABLE_111_CLR,Enable clear for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "ENABLE_110_CLR,Enable clear for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "ENABLE_109_CLR,Enable clear for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "ENABLE_108_CLR,Enable clear for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "ENABLE_107_CLR,Enable clear for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "ENABLE_106_CLR,Enable clear for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "ENABLE_105_CLR,Enable clear for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "ENABLE_104_CLR,Enable clear for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "ENABLE_103_CLR,Enable clear for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "ENABLE_102_CLR,Enable clear for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "ENABLE_101_CLR,Enable clear for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "ENABLE_100_CLR,Enable clear for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "ENABLE_99_CLR,Enable clear for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "ENABLE_98_CLR,Enable clear for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "ENABLE_97_CLR,Enable clear for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "ENABLE_96_CLR,Enable clear for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG4,"
bitfld.long 0x10 31. "ENABLE_159_CLR,Enable clear for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENABLE_158_CLR,Enable clear for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENABLE_157_CLR,Enable clear for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_156_CLR,Enable clear for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "ENABLE_155_CLR,Enable clear for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENABLE_154_CLR,Enable clear for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_153_CLR,Enable clear for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENABLE_152_CLR,Enable clear for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "ENABLE_151_CLR,Enable clear for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_150_CLR,Enable clear for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENABLE_149_CLR,Enable clear for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENABLE_148_CLR,Enable clear for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_147_CLR,Enable clear for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENABLE_146_CLR,Enable clear for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENABLE_145_CLR,Enable clear for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_144_CLR,Enable clear for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "ENABLE_143_CLR,Enable clear for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENABLE_142_CLR,Enable clear for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_141_CLR,Enable clear for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENABLE_140_CLR,Enable clear for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "ENABLE_139_CLR,Enable clear for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_138_CLR,Enable clear for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENABLE_137_CLR,Enable clear for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENABLE_136_CLR,Enable clear for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_135_CLR,Enable clear for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENABLE_134_CLR,Enable clear for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENABLE_133_CLR,Enable clear for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_132_CLR,Enable clear for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "ENABLE_131_CLR,Enable clear for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENABLE_130_CLR,Enable clear for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_129_CLR,Enable clear for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENABLE_128_CLR,Enable clear for slv_events_in[64]" "0,1"
group.long 0x400++0x9F
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG0,"
hexmask.long.byte 0x0 24.--28. 1. "CH_MAP_3,Interrupt Channel Map for intr_in[3]"
hexmask.long.byte 0x0 16.--20. 1. "CH_MAP_2,Interrupt Channel Map for intr_in[2]"
hexmask.long.byte 0x0 8.--12. 1. "CH_MAP_1,Interrupt Channel Map for intr_in[1]"
newline
hexmask.long.byte 0x0 0.--4. 1. "CH_MAP_0,Interrupt Channel Map for intr_in[0]"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG1,"
hexmask.long.byte 0x4 24.--28. 1. "CH_MAP_7,Interrupt Channel Map for intr_in[7]"
hexmask.long.byte 0x4 16.--20. 1. "CH_MAP_6,Interrupt Channel Map for intr_in[6]"
hexmask.long.byte 0x4 8.--12. 1. "CH_MAP_5,Interrupt Channel Map for intr_in[5]"
newline
hexmask.long.byte 0x4 0.--4. 1. "CH_MAP_4,Interrupt Channel Map for intr_in[4]"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG2,"
hexmask.long.byte 0x8 24.--28. 1. "CH_MAP_11,Interrupt Channel Map for intr_in[11]"
hexmask.long.byte 0x8 16.--20. 1. "CH_MAP_10,Interrupt Channel Map for intr_in[10]"
hexmask.long.byte 0x8 8.--12. 1. "CH_MAP_9,Interrupt Channel Map for intr_in[9]"
newline
hexmask.long.byte 0x8 0.--4. 1. "CH_MAP_8,Interrupt Channel Map for intr_in[8]"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG3,"
hexmask.long.byte 0xC 24.--28. 1. "CH_MAP_15,Interrupt Channel Map for intr_in[15]"
hexmask.long.byte 0xC 16.--20. 1. "CH_MAP_14,Interrupt Channel Map for intr_in[14]"
hexmask.long.byte 0xC 8.--12. 1. "CH_MAP_13,Interrupt Channel Map for intr_in[13]"
newline
hexmask.long.byte 0xC 0.--4. 1. "CH_MAP_12,Interrupt Channel Map for intr_in[12]"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG4,"
hexmask.long.byte 0x10 24.--28. 1. "CH_MAP_19,Interrupt Channel Map for intr_in[19]"
hexmask.long.byte 0x10 16.--20. 1. "CH_MAP_18,Interrupt Channel Map for intr_in[18]"
hexmask.long.byte 0x10 8.--12. 1. "CH_MAP_17,Interrupt Channel Map for intr_in[17]"
newline
hexmask.long.byte 0x10 0.--4. 1. "CH_MAP_16,Interrupt Channel Map for intr_in[16]"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG5,"
hexmask.long.byte 0x14 24.--28. 1. "CH_MAP_23,Interrupt Channel Map for intr_in[23]"
hexmask.long.byte 0x14 16.--20. 1. "CH_MAP_22,Interrupt Channel Map for intr_in[22]"
hexmask.long.byte 0x14 8.--12. 1. "CH_MAP_21,Interrupt Channel Map for intr_in[21]"
newline
hexmask.long.byte 0x14 0.--4. 1. "CH_MAP_20,Interrupt Channel Map for intr_in[20]"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG6,"
hexmask.long.byte 0x18 24.--28. 1. "CH_MAP_27,Interrupt Channel Map for intr_in[27]"
hexmask.long.byte 0x18 16.--20. 1. "CH_MAP_26,Interrupt Channel Map for intr_in[26]"
hexmask.long.byte 0x18 8.--12. 1. "CH_MAP_25,Interrupt Channel Map for intr_in[25]"
newline
hexmask.long.byte 0x18 0.--4. 1. "CH_MAP_24,Interrupt Channel Map for intr_in[24]"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG7,"
hexmask.long.byte 0x1C 24.--28. 1. "CH_MAP_31,Interrupt Channel Map for intr_in[31]"
hexmask.long.byte 0x1C 16.--20. 1. "CH_MAP_30,Interrupt Channel Map for intr_in[30]"
hexmask.long.byte 0x1C 8.--12. 1. "CH_MAP_29,Interrupt Channel Map for intr_in[29]"
newline
hexmask.long.byte 0x1C 0.--4. 1. "CH_MAP_28,Interrupt Channel Map for intr_in[28]"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG8,"
hexmask.long.byte 0x20 24.--28. 1. "CH_MAP_35,Interrupt Channel Map for intr_in[35]"
hexmask.long.byte 0x20 16.--20. 1. "CH_MAP_34,Interrupt Channel Map for intr_in[34]"
hexmask.long.byte 0x20 8.--12. 1. "CH_MAP_33,Interrupt Channel Map for intr_in[33]"
newline
hexmask.long.byte 0x20 0.--4. 1. "CH_MAP_32,Interrupt Channel Map for intr_in[32]"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG9,"
hexmask.long.byte 0x24 24.--28. 1. "CH_MAP_39,Interrupt Channel Map for intr_in[39]"
hexmask.long.byte 0x24 16.--20. 1. "CH_MAP_38,Interrupt Channel Map for intr_in[38]"
hexmask.long.byte 0x24 8.--12. 1. "CH_MAP_37,Interrupt Channel Map for intr_in[37]"
newline
hexmask.long.byte 0x24 0.--4. 1. "CH_MAP_36,Interrupt Channel Map for intr_in[36]"
line.long 0x28 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG10,"
hexmask.long.byte 0x28 24.--28. 1. "CH_MAP_43,Interrupt Channel Map for intr_in[43]"
hexmask.long.byte 0x28 16.--20. 1. "CH_MAP_42,Interrupt Channel Map for intr_in[42]"
hexmask.long.byte 0x28 8.--12. 1. "CH_MAP_41,Interrupt Channel Map for intr_in[41]"
newline
hexmask.long.byte 0x28 0.--4. 1. "CH_MAP_40,Interrupt Channel Map for intr_in[40]"
line.long 0x2C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG11,"
hexmask.long.byte 0x2C 24.--28. 1. "CH_MAP_47,Interrupt Channel Map for intr_in[47]"
hexmask.long.byte 0x2C 16.--20. 1. "CH_MAP_46,Interrupt Channel Map for intr_in[46]"
hexmask.long.byte 0x2C 8.--12. 1. "CH_MAP_45,Interrupt Channel Map for intr_in[45]"
newline
hexmask.long.byte 0x2C 0.--4. 1. "CH_MAP_44,Interrupt Channel Map for intr_in[44]"
line.long 0x30 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG12,"
hexmask.long.byte 0x30 24.--28. 1. "CH_MAP_51,Interrupt Channel Map for intr_in[51]"
hexmask.long.byte 0x30 16.--20. 1. "CH_MAP_50,Interrupt Channel Map for intr_in[50]"
hexmask.long.byte 0x30 8.--12. 1. "CH_MAP_49,Interrupt Channel Map for intr_in[49]"
newline
hexmask.long.byte 0x30 0.--4. 1. "CH_MAP_48,Interrupt Channel Map for intr_in[48]"
line.long 0x34 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG13,"
hexmask.long.byte 0x34 24.--28. 1. "CH_MAP_55,Interrupt Channel Map for intr_in[55]"
hexmask.long.byte 0x34 16.--20. 1. "CH_MAP_54,Interrupt Channel Map for intr_in[54]"
hexmask.long.byte 0x34 8.--12. 1. "CH_MAP_53,Interrupt Channel Map for intr_in[53]"
newline
hexmask.long.byte 0x34 0.--4. 1. "CH_MAP_52,Interrupt Channel Map for intr_in[52]"
line.long 0x38 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG14,"
hexmask.long.byte 0x38 24.--28. 1. "CH_MAP_59,Interrupt Channel Map for intr_in[59]"
hexmask.long.byte 0x38 16.--20. 1. "CH_MAP_58,Interrupt Channel Map for intr_in[58]"
hexmask.long.byte 0x38 8.--12. 1. "CH_MAP_57,Interrupt Channel Map for intr_in[57]"
newline
hexmask.long.byte 0x38 0.--4. 1. "CH_MAP_56,Interrupt Channel Map for intr_in[56]"
line.long 0x3C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG15,"
hexmask.long.byte 0x3C 24.--28. 1. "CH_MAP_63,Interrupt Channel Map for intr_in[63]"
hexmask.long.byte 0x3C 16.--20. 1. "CH_MAP_62,Interrupt Channel Map for intr_in[62]"
hexmask.long.byte 0x3C 8.--12. 1. "CH_MAP_61,Interrupt Channel Map for intr_in[61]"
newline
hexmask.long.byte 0x3C 0.--4. 1. "CH_MAP_60,Interrupt Channel Map for intr_in[60]"
line.long 0x40 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG16,"
hexmask.long.byte 0x40 24.--28. 1. "CH_MAP_67,Interrupt Channel Map for slv_events_in[3]"
hexmask.long.byte 0x40 16.--20. 1. "CH_MAP_66,Interrupt Channel Map for slv_events_in[2]"
hexmask.long.byte 0x40 8.--12. 1. "CH_MAP_65,Interrupt Channel Map for slv_events_in[1]"
newline
hexmask.long.byte 0x40 0.--4. 1. "CH_MAP_64,Interrupt Channel Map for slv_events_in[0]"
line.long 0x44 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG17,"
hexmask.long.byte 0x44 24.--28. 1. "CH_MAP_71,Interrupt Channel Map for slv_events_in[7]"
hexmask.long.byte 0x44 16.--20. 1. "CH_MAP_70,Interrupt Channel Map for slv_events_in[6]"
hexmask.long.byte 0x44 8.--12. 1. "CH_MAP_69,Interrupt Channel Map for slv_events_in[5]"
newline
hexmask.long.byte 0x44 0.--4. 1. "CH_MAP_68,Interrupt Channel Map for slv_events_in[4]"
line.long 0x48 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG18,"
hexmask.long.byte 0x48 24.--28. 1. "CH_MAP_75,Interrupt Channel Map for slv_events_in[11]"
hexmask.long.byte 0x48 16.--20. 1. "CH_MAP_74,Interrupt Channel Map for slv_events_in[10]"
hexmask.long.byte 0x48 8.--12. 1. "CH_MAP_73,Interrupt Channel Map for slv_events_in[9]"
newline
hexmask.long.byte 0x48 0.--4. 1. "CH_MAP_72,Interrupt Channel Map for slv_events_in[8]"
line.long 0x4C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG19,"
hexmask.long.byte 0x4C 24.--28. 1. "CH_MAP_79,Interrupt Channel Map for slv_events_in[15]"
hexmask.long.byte 0x4C 16.--20. 1. "CH_MAP_78,Interrupt Channel Map for slv_events_in[14]"
hexmask.long.byte 0x4C 8.--12. 1. "CH_MAP_77,Interrupt Channel Map for slv_events_in[13]"
newline
hexmask.long.byte 0x4C 0.--4. 1. "CH_MAP_76,Interrupt Channel Map for slv_events_in[12]"
line.long 0x50 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG20,"
hexmask.long.byte 0x50 24.--28. 1. "CH_MAP_83,Interrupt Channel Map for slv_events_in[19]"
hexmask.long.byte 0x50 16.--20. 1. "CH_MAP_82,Interrupt Channel Map for slv_events_in[18]"
hexmask.long.byte 0x50 8.--12. 1. "CH_MAP_81,Interrupt Channel Map for slv_events_in[17]"
newline
hexmask.long.byte 0x50 0.--4. 1. "CH_MAP_80,Interrupt Channel Map for slv_events_in[16]"
line.long 0x54 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG21,"
hexmask.long.byte 0x54 24.--28. 1. "CH_MAP_87,Interrupt Channel Map for slv_events_in[23]"
hexmask.long.byte 0x54 16.--20. 1. "CH_MAP_86,Interrupt Channel Map for slv_events_in[22]"
hexmask.long.byte 0x54 8.--12. 1. "CH_MAP_85,Interrupt Channel Map for slv_events_in[21]"
newline
hexmask.long.byte 0x54 0.--4. 1. "CH_MAP_84,Interrupt Channel Map for slv_events_in[20]"
line.long 0x58 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG22,"
hexmask.long.byte 0x58 24.--28. 1. "CH_MAP_91,Interrupt Channel Map for slv_events_in[27]"
hexmask.long.byte 0x58 16.--20. 1. "CH_MAP_90,Interrupt Channel Map for slv_events_in[26]"
hexmask.long.byte 0x58 8.--12. 1. "CH_MAP_89,Interrupt Channel Map for slv_events_in[25]"
newline
hexmask.long.byte 0x58 0.--4. 1. "CH_MAP_88,Interrupt Channel Map for slv_events_in[24]"
line.long 0x5C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG23,"
hexmask.long.byte 0x5C 24.--28. 1. "CH_MAP_95,Interrupt Channel Map for slv_events_in[31]"
hexmask.long.byte 0x5C 16.--20. 1. "CH_MAP_94,Interrupt Channel Map for slv_events_in[30]"
hexmask.long.byte 0x5C 8.--12. 1. "CH_MAP_93,Interrupt Channel Map for slv_events_in[29]"
newline
hexmask.long.byte 0x5C 0.--4. 1. "CH_MAP_92,Interrupt Channel Map for slv_events_in[28]"
line.long 0x60 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG24,"
hexmask.long.byte 0x60 24.--28. 1. "CH_MAP_99,Interrupt Channel Map for slv_events_in[35]"
hexmask.long.byte 0x60 16.--20. 1. "CH_MAP_98,Interrupt Channel Map for slv_events_in[34]"
hexmask.long.byte 0x60 8.--12. 1. "CH_MAP_97,Interrupt Channel Map for slv_events_in[33]"
newline
hexmask.long.byte 0x60 0.--4. 1. "CH_MAP_96,Interrupt Channel Map for slv_events_in[32]"
line.long 0x64 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG25,"
hexmask.long.byte 0x64 24.--28. 1. "CH_MAP_103,Interrupt Channel Map for slv_events_in[39]"
hexmask.long.byte 0x64 16.--20. 1. "CH_MAP_102,Interrupt Channel Map for slv_events_in[38]"
hexmask.long.byte 0x64 8.--12. 1. "CH_MAP_101,Interrupt Channel Map for slv_events_in[37]"
newline
hexmask.long.byte 0x64 0.--4. 1. "CH_MAP_100,Interrupt Channel Map for slv_events_in[36]"
line.long 0x68 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG26,"
hexmask.long.byte 0x68 24.--28. 1. "CH_MAP_107,Interrupt Channel Map for slv_events_in[43]"
hexmask.long.byte 0x68 16.--20. 1. "CH_MAP_106,Interrupt Channel Map for slv_events_in[42]"
hexmask.long.byte 0x68 8.--12. 1. "CH_MAP_105,Interrupt Channel Map for slv_events_in[41]"
newline
hexmask.long.byte 0x68 0.--4. 1. "CH_MAP_104,Interrupt Channel Map for slv_events_in[40]"
line.long 0x6C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG27,"
hexmask.long.byte 0x6C 24.--28. 1. "CH_MAP_111,Interrupt Channel Map for slv_events_in[47]"
hexmask.long.byte 0x6C 16.--20. 1. "CH_MAP_110,Interrupt Channel Map for slv_events_in[46]"
hexmask.long.byte 0x6C 8.--12. 1. "CH_MAP_109,Interrupt Channel Map for slv_events_in[45]"
newline
hexmask.long.byte 0x6C 0.--4. 1. "CH_MAP_108,Interrupt Channel Map for slv_events_in[44]"
line.long 0x70 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG28,"
hexmask.long.byte 0x70 24.--28. 1. "CH_MAP_115,Interrupt Channel Map for slv_events_in[51]"
hexmask.long.byte 0x70 16.--20. 1. "CH_MAP_114,Interrupt Channel Map for slv_events_in[50]"
hexmask.long.byte 0x70 8.--12. 1. "CH_MAP_113,Interrupt Channel Map for slv_events_in[49]"
newline
hexmask.long.byte 0x70 0.--4. 1. "CH_MAP_112,Interrupt Channel Map for slv_events_in[48]"
line.long 0x74 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG29,"
hexmask.long.byte 0x74 24.--28. 1. "CH_MAP_119,Interrupt Channel Map for slv_events_in[55]"
hexmask.long.byte 0x74 16.--20. 1. "CH_MAP_118,Interrupt Channel Map for slv_events_in[54]"
hexmask.long.byte 0x74 8.--12. 1. "CH_MAP_117,Interrupt Channel Map for slv_events_in[53]"
newline
hexmask.long.byte 0x74 0.--4. 1. "CH_MAP_116,Interrupt Channel Map for slv_events_in[52]"
line.long 0x78 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG30,"
hexmask.long.byte 0x78 24.--28. 1. "CH_MAP_123,Interrupt Channel Map for slv_events_in[59]"
hexmask.long.byte 0x78 16.--20. 1. "CH_MAP_122,Interrupt Channel Map for slv_events_in[58]"
hexmask.long.byte 0x78 8.--12. 1. "CH_MAP_121,Interrupt Channel Map for slv_events_in[57]"
newline
hexmask.long.byte 0x78 0.--4. 1. "CH_MAP_120,Interrupt Channel Map for slv_events_in[56]"
line.long 0x7C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG31,"
hexmask.long.byte 0x7C 24.--28. 1. "CH_MAP_127,Interrupt Channel Map for slv_events_in[63]"
hexmask.long.byte 0x7C 16.--20. 1. "CH_MAP_126,Interrupt Channel Map for slv_events_in[62]"
hexmask.long.byte 0x7C 8.--12. 1. "CH_MAP_125,Interrupt Channel Map for slv_events_in[61]"
newline
hexmask.long.byte 0x7C 0.--4. 1. "CH_MAP_124,Interrupt Channel Map for slv_events_in[60]"
line.long 0x80 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG32,"
hexmask.long.byte 0x80 24.--28. 1. "CH_MAP_131,Interrupt Channel Map for slv_events_in[67]"
hexmask.long.byte 0x80 16.--20. 1. "CH_MAP_130,Interrupt Channel Map for slv_events_in[66]"
hexmask.long.byte 0x80 8.--12. 1. "CH_MAP_129,Interrupt Channel Map for slv_events_in[65]"
newline
hexmask.long.byte 0x80 0.--4. 1. "CH_MAP_128,Interrupt Channel Map for slv_events_in[64]"
line.long 0x84 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG33,"
hexmask.long.byte 0x84 24.--28. 1. "CH_MAP_135,Interrupt Channel Map for slv_events_in[71]"
hexmask.long.byte 0x84 16.--20. 1. "CH_MAP_134,Interrupt Channel Map for slv_events_in[70]"
hexmask.long.byte 0x84 8.--12. 1. "CH_MAP_133,Interrupt Channel Map for slv_events_in[69]"
newline
hexmask.long.byte 0x84 0.--4. 1. "CH_MAP_132,Interrupt Channel Map for slv_events_in[68]"
line.long 0x88 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG34,"
hexmask.long.byte 0x88 24.--28. 1. "CH_MAP_139,Interrupt Channel Map for slv_events_in[75]"
hexmask.long.byte 0x88 16.--20. 1. "CH_MAP_138,Interrupt Channel Map for slv_events_in[74]"
hexmask.long.byte 0x88 8.--12. 1. "CH_MAP_137,Interrupt Channel Map for slv_events_in[73]"
newline
hexmask.long.byte 0x88 0.--4. 1. "CH_MAP_136,Interrupt Channel Map for slv_events_in[72]"
line.long 0x8C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG35,"
hexmask.long.byte 0x8C 24.--28. 1. "CH_MAP_143,Interrupt Channel Map for slv_events_in[79]"
hexmask.long.byte 0x8C 16.--20. 1. "CH_MAP_142,Interrupt Channel Map for slv_events_in[78]"
hexmask.long.byte 0x8C 8.--12. 1. "CH_MAP_141,Interrupt Channel Map for slv_events_in[77]"
newline
hexmask.long.byte 0x8C 0.--4. 1. "CH_MAP_140,Interrupt Channel Map for slv_events_in[76]"
line.long 0x90 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG36,"
hexmask.long.byte 0x90 24.--28. 1. "CH_MAP_147,Interrupt Channel Map for slv_events_in[83]"
hexmask.long.byte 0x90 16.--20. 1. "CH_MAP_146,Interrupt Channel Map for slv_events_in[82]"
hexmask.long.byte 0x90 8.--12. 1. "CH_MAP_145,Interrupt Channel Map for slv_events_in[81]"
newline
hexmask.long.byte 0x90 0.--4. 1. "CH_MAP_144,Interrupt Channel Map for slv_events_in[80]"
line.long 0x94 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG37,"
hexmask.long.byte 0x94 24.--28. 1. "CH_MAP_151,Interrupt Channel Map for slv_events_in[87]"
hexmask.long.byte 0x94 16.--20. 1. "CH_MAP_150,Interrupt Channel Map for slv_events_in[86]"
hexmask.long.byte 0x94 8.--12. 1. "CH_MAP_149,Interrupt Channel Map for slv_events_in[85]"
newline
hexmask.long.byte 0x94 0.--4. 1. "CH_MAP_148,Interrupt Channel Map for slv_events_in[84]"
line.long 0x98 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG38,"
hexmask.long.byte 0x98 24.--28. 1. "CH_MAP_155,Interrupt Channel Map for slv_events_in[91]"
hexmask.long.byte 0x98 16.--20. 1. "CH_MAP_154,Interrupt Channel Map for slv_events_in[90]"
hexmask.long.byte 0x98 8.--12. 1. "CH_MAP_153,Interrupt Channel Map for slv_events_in[89]"
newline
hexmask.long.byte 0x98 0.--4. 1. "CH_MAP_152,Interrupt Channel Map for slv_events_in[88]"
line.long 0x9C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG39,"
hexmask.long.byte 0x9C 24.--28. 1. "CH_MAP_159,Interrupt Channel Map for slv_events_in[95]"
hexmask.long.byte 0x9C 16.--20. 1. "CH_MAP_158,Interrupt Channel Map for slv_events_in[94]"
hexmask.long.byte 0x9C 8.--12. 1. "CH_MAP_157,Interrupt Channel Map for slv_events_in[93]"
newline
hexmask.long.byte 0x9C 0.--4. 1. "CH_MAP_156,Interrupt Channel Map for slv_events_in[92]"
group.long 0x800++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG0,"
hexmask.long.byte 0x0 24.--28. 1. "HINT_MAP_3,Host Interrupt Map for Channel 3"
hexmask.long.byte 0x0 16.--20. 1. "HINT_MAP_2,Host Interrupt Map for Channel 2"
hexmask.long.byte 0x0 8.--12. 1. "HINT_MAP_1,Host Interrupt Map for Channel 1"
newline
hexmask.long.byte 0x0 0.--4. 1. "HINT_MAP_0,Host Interrupt Map for Channel 0"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG1,"
hexmask.long.byte 0x4 24.--28. 1. "HINT_MAP_7,Host Interrupt Map for Channel 7"
hexmask.long.byte 0x4 16.--20. 1. "HINT_MAP_6,Host Interrupt Map for Channel 6"
hexmask.long.byte 0x4 8.--12. 1. "HINT_MAP_5,Host Interrupt Map for Channel 5"
newline
hexmask.long.byte 0x4 0.--4. 1. "HINT_MAP_4,Host Interrupt Map for Channel 4"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG2,"
hexmask.long.byte 0x8 24.--28. 1. "HINT_MAP_11,Host Interrupt Map for Channel 11"
hexmask.long.byte 0x8 16.--20. 1. "HINT_MAP_10,Host Interrupt Map for Channel 10"
hexmask.long.byte 0x8 8.--12. 1. "HINT_MAP_9,Host Interrupt Map for Channel 9"
newline
hexmask.long.byte 0x8 0.--4. 1. "HINT_MAP_8,Host Interrupt Map for Channel 8"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG3,"
hexmask.long.byte 0xC 24.--28. 1. "HINT_MAP_15,Host Interrupt Map for Channel 15"
hexmask.long.byte 0xC 16.--20. 1. "HINT_MAP_14,Host Interrupt Map for Channel 14"
hexmask.long.byte 0xC 8.--12. 1. "HINT_MAP_13,Host Interrupt Map for Channel 13"
newline
hexmask.long.byte 0xC 0.--4. 1. "HINT_MAP_12,Host Interrupt Map for Channel 12"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG4,"
hexmask.long.byte 0x10 24.--28. 1. "HINT_MAP_19,Host Interrupt Map for Channel 19"
hexmask.long.byte 0x10 16.--20. 1. "HINT_MAP_18,Host Interrupt Map for Channel 18"
hexmask.long.byte 0x10 8.--12. 1. "HINT_MAP_17,Host Interrupt Map for Channel 17"
newline
hexmask.long.byte 0x10 0.--4. 1. "HINT_MAP_16,Host Interrupt Map for Channel 16"
rgroup.long 0x900++0x4F
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG0,"
bitfld.long 0x0 31. "NONE_HINT_0,No interrupt pending flag" "0,1"
hexmask.long.word 0x0 0.--9. 1. "PRI_HINT_0,Host Int 0 Prioritized Interrupt"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG1,"
bitfld.long 0x4 31. "NONE_HINT_1,No interrupt pending flag" "0,1"
hexmask.long.word 0x4 0.--9. 1. "PRI_HINT_1,Host Int 1 Prioritized Interrupt"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG2,"
bitfld.long 0x8 31. "NONE_HINT_2,No interrupt pending flag" "0,1"
hexmask.long.word 0x8 0.--9. 1. "PRI_HINT_2,Host Int 2 Prioritized Interrupt"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG3,"
bitfld.long 0xC 31. "NONE_HINT_3,No interrupt pending flag" "0,1"
hexmask.long.word 0xC 0.--9. 1. "PRI_HINT_3,Host Int 3 Prioritized Interrupt"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG4,"
bitfld.long 0x10 31. "NONE_HINT_4,No interrupt pending flag" "0,1"
hexmask.long.word 0x10 0.--9. 1. "PRI_HINT_4,Host Int 4 Prioritized Interrupt"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG5,"
bitfld.long 0x14 31. "NONE_HINT_5,No interrupt pending flag" "0,1"
hexmask.long.word 0x14 0.--9. 1. "PRI_HINT_5,Host Int 5 Prioritized Interrupt"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG6,"
bitfld.long 0x18 31. "NONE_HINT_6,No interrupt pending flag" "0,1"
hexmask.long.word 0x18 0.--9. 1. "PRI_HINT_6,Host Int 6 Prioritized Interrupt"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG7,"
bitfld.long 0x1C 31. "NONE_HINT_7,No interrupt pending flag" "0,1"
hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT_7,Host Int 7 Prioritized Interrupt"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG8,"
bitfld.long 0x20 31. "NONE_HINT_8,No interrupt pending flag" "0,1"
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT_8,Host Int 8 Prioritized Interrupt"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG9,"
bitfld.long 0x24 31. "NONE_HINT_9,No interrupt pending flag" "0,1"
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT_9,Host Int 9 Prioritized Interrupt"
line.long 0x28 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG10,"
bitfld.long 0x28 31. "NONE_HINT_10,No interrupt pending flag" "0,1"
hexmask.long.word 0x28 0.--9. 1. "PRI_HINT_10,Host Int 10 Prioritized Interrupt"
line.long 0x2C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG11,"
bitfld.long 0x2C 31. "NONE_HINT_11,No interrupt pending flag" "0,1"
hexmask.long.word 0x2C 0.--9. 1. "PRI_HINT_11,Host Int 11 Prioritized Interrupt"
line.long 0x30 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG12,"
bitfld.long 0x30 31. "NONE_HINT_12,No interrupt pending flag" "0,1"
hexmask.long.word 0x30 0.--9. 1. "PRI_HINT_12,Host Int 12 Prioritized Interrupt"
line.long 0x34 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG13,"
bitfld.long 0x34 31. "NONE_HINT_13,No interrupt pending flag" "0,1"
hexmask.long.word 0x34 0.--9. 1. "PRI_HINT_13,Host Int 13 Prioritized Interrupt"
line.long 0x38 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG14,"
bitfld.long 0x38 31. "NONE_HINT_14,No interrupt pending flag" "0,1"
hexmask.long.word 0x38 0.--9. 1. "PRI_HINT_14,Host Int 14 Prioritized Interrupt"
line.long 0x3C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG15,"
bitfld.long 0x3C 31. "NONE_HINT_15,No interrupt pending flag" "0,1"
hexmask.long.word 0x3C 0.--9. 1. "PRI_HINT_15,Host Int 15 Prioritized Interrupt"
line.long 0x40 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG16,"
bitfld.long 0x40 31. "NONE_HINT_16,No interrupt pending flag" "0,1"
hexmask.long.word 0x40 0.--9. 1. "PRI_HINT_16,Host Int 16 Prioritized Interrupt"
line.long 0x44 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG17,"
bitfld.long 0x44 31. "NONE_HINT_17,No interrupt pending flag" "0,1"
hexmask.long.word 0x44 0.--9. 1. "PRI_HINT_17,Host Int 17 Prioritized Interrupt"
line.long 0x48 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG18,"
bitfld.long 0x48 31. "NONE_HINT_18,No interrupt pending flag" "0,1"
hexmask.long.word 0x48 0.--9. 1. "PRI_HINT_18,Host Int 18 Prioritized Interrupt"
line.long 0x4C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG19,"
bitfld.long 0x4C 31. "NONE_HINT_19,No interrupt pending flag" "0,1"
hexmask.long.word 0x4C 0.--9. 1. "PRI_HINT_19,Host Int 19 Prioritized Interrupt"
group.long 0xD00++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG0,"
bitfld.long 0x0 31. "POLARITY_31,Polarity for intr_in[31] 0=low" "0: low,?"
bitfld.long 0x0 30. "POLARITY_30,Polarity for intr_in[30] 0=low" "0: low,?"
bitfld.long 0x0 29. "POLARITY_29,Polarity for intr_in[29] 0=low" "0: low,?"
newline
bitfld.long 0x0 28. "POLARITY_28,Polarity for intr_in[28] 0=low" "0: low,?"
bitfld.long 0x0 27. "POLARITY_27,Polarity for intr_in[27] 0=low" "0: low,?"
bitfld.long 0x0 26. "POLARITY_26,Polarity for intr_in[26] 0=low" "0: low,?"
newline
bitfld.long 0x0 25. "POLARITY_25,Polarity for intr_in[25] 0=low" "0: low,?"
bitfld.long 0x0 24. "POLARITY_24,Polarity for intr_in[24] 0=low" "0: low,?"
bitfld.long 0x0 23. "POLARITY_23,Polarity for intr_in[23] 0=low" "0: low,?"
newline
bitfld.long 0x0 22. "POLARITY_22,Polarity for intr_in[22] 0=low" "0: low,?"
bitfld.long 0x0 21. "POLARITY_21,Polarity for intr_in[21] 0=low" "0: low,?"
bitfld.long 0x0 20. "POLARITY_20,Polarity for intr_in[20] 0=low" "0: low,?"
newline
bitfld.long 0x0 19. "POLARITY_19,Polarity for intr_in[19] 0=low" "0: low,?"
bitfld.long 0x0 18. "POLARITY_18,Polarity for intr_in[18] 0=low" "0: low,?"
bitfld.long 0x0 17. "POLARITY_17,Polarity for intr_in[17] 0=low" "0: low,?"
newline
bitfld.long 0x0 16. "POLARITY_16,Polarity for intr_in[16] 0=low" "0: low,?"
bitfld.long 0x0 15. "POLARITY_15,Polarity for intr_in[15] 0=low" "0: low,?"
bitfld.long 0x0 14. "POLARITY_14,Polarity for intr_in[14] 0=low" "0: low,?"
newline
bitfld.long 0x0 13. "POLARITY_13,Polarity for intr_in[13] 0=low" "0: low,?"
bitfld.long 0x0 12. "POLARITY_12,Polarity for intr_in[12] 0=low" "0: low,?"
bitfld.long 0x0 11. "POLARITY_11,Polarity for intr_in[11] 0=low" "0: low,?"
newline
bitfld.long 0x0 10. "POLARITY_10,Polarity for intr_in[10] 0=low" "0: low,?"
bitfld.long 0x0 9. "POLARITY_9,Polarity for intr_in[9] 0=low" "0: low,?"
bitfld.long 0x0 8. "POLARITY_8,Polarity for intr_in[8] 0=low" "0: low,?"
newline
bitfld.long 0x0 7. "POLARITY_7,Polarity for intr_in[7] 0=low" "0: low,?"
bitfld.long 0x0 6. "POLARITY_6,Polarity for intr_in[6] 0=low" "0: low,?"
bitfld.long 0x0 5. "POLARITY_5,Polarity for intr_in[5] 0=low" "0: low,?"
newline
bitfld.long 0x0 4. "POLARITY_4,Polarity for intr_in[4] 0=low" "0: low,?"
bitfld.long 0x0 3. "POLARITY_3,Polarity for intr_in[3] 0=low" "0: low,?"
bitfld.long 0x0 2. "POLARITY_2,Polarity for intr_in[2] 0=low" "0: low,?"
newline
bitfld.long 0x0 1. "POLARITY_1,Polarity for intr_in[1] 0=low" "0: low,?"
bitfld.long 0x0 0. "POLARITY_0,Polarity for intr_in[0] 0=low" "0: low,?"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG1,"
bitfld.long 0x4 31. "POLARITY_63,Polarity for intr_in[63] 0=low" "0: low,?"
bitfld.long 0x4 30. "POLARITY_62,Polarity for intr_in[62] 0=low" "0: low,?"
bitfld.long 0x4 29. "POLARITY_61,Polarity for intr_in[61] 0=low" "0: low,?"
newline
bitfld.long 0x4 28. "POLARITY_60,Polarity for intr_in[60] 0=low" "0: low,?"
bitfld.long 0x4 27. "POLARITY_59,Polarity for intr_in[59] 0=low" "0: low,?"
bitfld.long 0x4 26. "POLARITY_58,Polarity for intr_in[58] 0=low" "0: low,?"
newline
bitfld.long 0x4 25. "POLARITY_57,Polarity for intr_in[57] 0=low" "0: low,?"
bitfld.long 0x4 24. "POLARITY_56,Polarity for intr_in[56] 0=low" "0: low,?"
bitfld.long 0x4 23. "POLARITY_55,Polarity for intr_in[55] 0=low" "0: low,?"
newline
bitfld.long 0x4 22. "POLARITY_54,Polarity for intr_in[54] 0=low" "0: low,?"
bitfld.long 0x4 21. "POLARITY_53,Polarity for intr_in[53] 0=low" "0: low,?"
bitfld.long 0x4 20. "POLARITY_52,Polarity for intr_in[52] 0=low" "0: low,?"
newline
bitfld.long 0x4 19. "POLARITY_51,Polarity for intr_in[51] 0=low" "0: low,?"
bitfld.long 0x4 18. "POLARITY_50,Polarity for intr_in[50] 0=low" "0: low,?"
bitfld.long 0x4 17. "POLARITY_49,Polarity for intr_in[49] 0=low" "0: low,?"
newline
bitfld.long 0x4 16. "POLARITY_48,Polarity for intr_in[48] 0=low" "0: low,?"
bitfld.long 0x4 15. "POLARITY_47,Polarity for intr_in[47] 0=low" "0: low,?"
bitfld.long 0x4 14. "POLARITY_46,Polarity for intr_in[46] 0=low" "0: low,?"
newline
bitfld.long 0x4 13. "POLARITY_45,Polarity for intr_in[45] 0=low" "0: low,?"
bitfld.long 0x4 12. "POLARITY_44,Polarity for intr_in[44] 0=low" "0: low,?"
bitfld.long 0x4 11. "POLARITY_43,Polarity for intr_in[43] 0=low" "0: low,?"
newline
bitfld.long 0x4 10. "POLARITY_42,Polarity for intr_in[42] 0=low" "0: low,?"
bitfld.long 0x4 9. "POLARITY_41,Polarity for intr_in[41] 0=low" "0: low,?"
bitfld.long 0x4 8. "POLARITY_40,Polarity for intr_in[40] 0=low" "0: low,?"
newline
bitfld.long 0x4 7. "POLARITY_39,Polarity for intr_in[39] 0=low" "0: low,?"
bitfld.long 0x4 6. "POLARITY_38,Polarity for intr_in[38] 0=low" "0: low,?"
bitfld.long 0x4 5. "POLARITY_37,Polarity for intr_in[37] 0=low" "0: low,?"
newline
bitfld.long 0x4 4. "POLARITY_36,Polarity for intr_in[36] 0=low" "0: low,?"
bitfld.long 0x4 3. "POLARITY_35,Polarity for intr_in[35] 0=low" "0: low,?"
bitfld.long 0x4 2. "POLARITY_34,Polarity for intr_in[34] 0=low" "0: low,?"
newline
bitfld.long 0x4 1. "POLARITY_33,Polarity for intr_in[33] 0=low" "0: low,?"
bitfld.long 0x4 0. "POLARITY_32,Polarity for intr_in[32] 0=low" "0: low,?"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG2,"
bitfld.long 0x8 31. "POLARITY_95,Polarity for slv_events_in[31] 0=low" "0: low,?"
bitfld.long 0x8 30. "POLARITY_94,Polarity for slv_events_in[30] 0=low" "0: low,?"
bitfld.long 0x8 29. "POLARITY_93,Polarity for slv_events_in[29] 0=low" "0: low,?"
newline
bitfld.long 0x8 28. "POLARITY_92,Polarity for slv_events_in[28] 0=low" "0: low,?"
bitfld.long 0x8 27. "POLARITY_91,Polarity for slv_events_in[27] 0=low" "0: low,?"
bitfld.long 0x8 26. "POLARITY_90,Polarity for slv_events_in[26] 0=low" "0: low,?"
newline
bitfld.long 0x8 25. "POLARITY_89,Polarity for slv_events_in[25] 0=low" "0: low,?"
bitfld.long 0x8 24. "POLARITY_88,Polarity for slv_events_in[24] 0=low" "0: low,?"
bitfld.long 0x8 23. "POLARITY_87,Polarity for slv_events_in[23] 0=low" "0: low,?"
newline
bitfld.long 0x8 22. "POLARITY_86,Polarity for slv_events_in[22] 0=low" "0: low,?"
bitfld.long 0x8 21. "POLARITY_85,Polarity for slv_events_in[21] 0=low" "0: low,?"
bitfld.long 0x8 20. "POLARITY_84,Polarity for slv_events_in[20] 0=low" "0: low,?"
newline
bitfld.long 0x8 19. "POLARITY_83,Polarity for slv_events_in[19] 0=low" "0: low,?"
bitfld.long 0x8 18. "POLARITY_82,Polarity for slv_events_in[18] 0=low" "0: low,?"
bitfld.long 0x8 17. "POLARITY_81,Polarity for slv_events_in[17] 0=low" "0: low,?"
newline
bitfld.long 0x8 16. "POLARITY_80,Polarity for slv_events_in[16] 0=low" "0: low,?"
bitfld.long 0x8 15. "POLARITY_79,Polarity for slv_events_in[15] 0=low" "0: low,?"
bitfld.long 0x8 14. "POLARITY_78,Polarity for slv_events_in[14] 0=low" "0: low,?"
newline
bitfld.long 0x8 13. "POLARITY_77,Polarity for slv_events_in[13] 0=low" "0: low,?"
bitfld.long 0x8 12. "POLARITY_76,Polarity for slv_events_in[12] 0=low" "0: low,?"
bitfld.long 0x8 11. "POLARITY_75,Polarity for slv_events_in[11] 0=low" "0: low,?"
newline
bitfld.long 0x8 10. "POLARITY_74,Polarity for slv_events_in[10] 0=low" "0: low,?"
bitfld.long 0x8 9. "POLARITY_73,Polarity for slv_events_in[9] 0=low" "0: low,?"
bitfld.long 0x8 8. "POLARITY_72,Polarity for slv_events_in[8] 0=low" "0: low,?"
newline
bitfld.long 0x8 7. "POLARITY_71,Polarity for slv_events_in[7] 0=low" "0: low,?"
bitfld.long 0x8 6. "POLARITY_70,Polarity for slv_events_in[6] 0=low" "0: low,?"
bitfld.long 0x8 5. "POLARITY_69,Polarity for slv_events_in[5] 0=low" "0: low,?"
newline
bitfld.long 0x8 4. "POLARITY_68,Polarity for slv_events_in[4] 0=low" "0: low,?"
bitfld.long 0x8 3. "POLARITY_67,Polarity for slv_events_in[3] 0=low" "0: low,?"
bitfld.long 0x8 2. "POLARITY_66,Polarity for slv_events_in[2] 0=low" "0: low,?"
newline
bitfld.long 0x8 1. "POLARITY_65,Polarity for slv_events_in[1] 0=low" "0: low,?"
bitfld.long 0x8 0. "POLARITY_64,Polarity for slv_events_in[0] 0=low" "0: low,?"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG3,"
bitfld.long 0xC 31. "POLARITY_127,Polarity for slv_events_in[63] 0=low" "0: low,?"
bitfld.long 0xC 30. "POLARITY_126,Polarity for slv_events_in[62] 0=low" "0: low,?"
bitfld.long 0xC 29. "POLARITY_125,Polarity for slv_events_in[61] 0=low" "0: low,?"
newline
bitfld.long 0xC 28. "POLARITY_124,Polarity for slv_events_in[60] 0=low" "0: low,?"
bitfld.long 0xC 27. "POLARITY_123,Polarity for slv_events_in[59] 0=low" "0: low,?"
bitfld.long 0xC 26. "POLARITY_122,Polarity for slv_events_in[58] 0=low" "0: low,?"
newline
bitfld.long 0xC 25. "POLARITY_121,Polarity for slv_events_in[57] 0=low" "0: low,?"
bitfld.long 0xC 24. "POLARITY_120,Polarity for slv_events_in[56] 0=low" "0: low,?"
bitfld.long 0xC 23. "POLARITY_119,Polarity for slv_events_in[55] 0=low" "0: low,?"
newline
bitfld.long 0xC 22. "POLARITY_118,Polarity for slv_events_in[54] 0=low" "0: low,?"
bitfld.long 0xC 21. "POLARITY_117,Polarity for slv_events_in[53] 0=low" "0: low,?"
bitfld.long 0xC 20. "POLARITY_116,Polarity for slv_events_in[52] 0=low" "0: low,?"
newline
bitfld.long 0xC 19. "POLARITY_115,Polarity for slv_events_in[51] 0=low" "0: low,?"
bitfld.long 0xC 18. "POLARITY_114,Polarity for slv_events_in[50] 0=low" "0: low,?"
bitfld.long 0xC 17. "POLARITY_113,Polarity for slv_events_in[49] 0=low" "0: low,?"
newline
bitfld.long 0xC 16. "POLARITY_112,Polarity for slv_events_in[48] 0=low" "0: low,?"
bitfld.long 0xC 15. "POLARITY_111,Polarity for slv_events_in[47] 0=low" "0: low,?"
bitfld.long 0xC 14. "POLARITY_110,Polarity for slv_events_in[46] 0=low" "0: low,?"
newline
bitfld.long 0xC 13. "POLARITY_109,Polarity for slv_events_in[45] 0=low" "0: low,?"
bitfld.long 0xC 12. "POLARITY_108,Polarity for slv_events_in[44] 0=low" "0: low,?"
bitfld.long 0xC 11. "POLARITY_107,Polarity for slv_events_in[43] 0=low" "0: low,?"
newline
bitfld.long 0xC 10. "POLARITY_106,Polarity for slv_events_in[42] 0=low" "0: low,?"
bitfld.long 0xC 9. "POLARITY_105,Polarity for slv_events_in[41] 0=low" "0: low,?"
bitfld.long 0xC 8. "POLARITY_104,Polarity for slv_events_in[40] 0=low" "0: low,?"
newline
bitfld.long 0xC 7. "POLARITY_103,Polarity for slv_events_in[39] 0=low" "0: low,?"
bitfld.long 0xC 6. "POLARITY_102,Polarity for slv_events_in[38] 0=low" "0: low,?"
bitfld.long 0xC 5. "POLARITY_101,Polarity for slv_events_in[37] 0=low" "0: low,?"
newline
bitfld.long 0xC 4. "POLARITY_100,Polarity for slv_events_in[36] 0=low" "0: low,?"
bitfld.long 0xC 3. "POLARITY_99,Polarity for slv_events_in[35] 0=low" "0: low,?"
bitfld.long 0xC 2. "POLARITY_98,Polarity for slv_events_in[34] 0=low" "0: low,?"
newline
bitfld.long 0xC 1. "POLARITY_97,Polarity for slv_events_in[33] 0=low" "0: low,?"
bitfld.long 0xC 0. "POLARITY_96,Polarity for slv_events_in[32] 0=low" "0: low,?"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG4,"
bitfld.long 0x10 31. "POLARITY_159,Polarity for slv_events_in[95] 0=low" "0: low,?"
bitfld.long 0x10 30. "POLARITY_158,Polarity for slv_events_in[94] 0=low" "0: low,?"
bitfld.long 0x10 29. "POLARITY_157,Polarity for slv_events_in[93] 0=low" "0: low,?"
newline
bitfld.long 0x10 28. "POLARITY_156,Polarity for slv_events_in[92] 0=low" "0: low,?"
bitfld.long 0x10 27. "POLARITY_155,Polarity for slv_events_in[91] 0=low" "0: low,?"
bitfld.long 0x10 26. "POLARITY_154,Polarity for slv_events_in[90] 0=low" "0: low,?"
newline
bitfld.long 0x10 25. "POLARITY_153,Polarity for slv_events_in[89] 0=low" "0: low,?"
bitfld.long 0x10 24. "POLARITY_152,Polarity for slv_events_in[88] 0=low" "0: low,?"
bitfld.long 0x10 23. "POLARITY_151,Polarity for slv_events_in[87] 0=low" "0: low,?"
newline
bitfld.long 0x10 22. "POLARITY_150,Polarity for slv_events_in[86] 0=low" "0: low,?"
bitfld.long 0x10 21. "POLARITY_149,Polarity for slv_events_in[85] 0=low" "0: low,?"
bitfld.long 0x10 20. "POLARITY_148,Polarity for slv_events_in[84] 0=low" "0: low,?"
newline
bitfld.long 0x10 19. "POLARITY_147,Polarity for slv_events_in[83] 0=low" "0: low,?"
bitfld.long 0x10 18. "POLARITY_146,Polarity for slv_events_in[82] 0=low" "0: low,?"
bitfld.long 0x10 17. "POLARITY_145,Polarity for slv_events_in[81] 0=low" "0: low,?"
newline
bitfld.long 0x10 16. "POLARITY_144,Polarity for slv_events_in[80] 0=low" "0: low,?"
bitfld.long 0x10 15. "POLARITY_143,Polarity for slv_events_in[79] 0=low" "0: low,?"
bitfld.long 0x10 14. "POLARITY_142,Polarity for slv_events_in[78] 0=low" "0: low,?"
newline
bitfld.long 0x10 13. "POLARITY_141,Polarity for slv_events_in[77] 0=low" "0: low,?"
bitfld.long 0x10 12. "POLARITY_140,Polarity for slv_events_in[76] 0=low" "0: low,?"
bitfld.long 0x10 11. "POLARITY_139,Polarity for slv_events_in[75] 0=low" "0: low,?"
newline
bitfld.long 0x10 10. "POLARITY_138,Polarity for slv_events_in[74] 0=low" "0: low,?"
bitfld.long 0x10 9. "POLARITY_137,Polarity for slv_events_in[73] 0=low" "0: low,?"
bitfld.long 0x10 8. "POLARITY_136,Polarity for slv_events_in[72] 0=low" "0: low,?"
newline
bitfld.long 0x10 7. "POLARITY_135,Polarity for slv_events_in[71] 0=low" "0: low,?"
bitfld.long 0x10 6. "POLARITY_134,Polarity for slv_events_in[70] 0=low" "0: low,?"
bitfld.long 0x10 5. "POLARITY_133,Polarity for slv_events_in[69] 0=low" "0: low,?"
newline
bitfld.long 0x10 4. "POLARITY_132,Polarity for slv_events_in[68] 0=low" "0: low,?"
bitfld.long 0x10 3. "POLARITY_131,Polarity for slv_events_in[67] 0=low" "0: low,?"
bitfld.long 0x10 2. "POLARITY_130,Polarity for slv_events_in[66] 0=low" "0: low,?"
newline
bitfld.long 0x10 1. "POLARITY_129,Polarity for slv_events_in[65] 0=low" "0: low,?"
bitfld.long 0x10 0. "POLARITY_128,Polarity for slv_events_in[64] 0=low" "0: low,?"
group.long 0xD80++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG0,"
bitfld.long 0x0 31. "TYPE_31,Type for intr_in[31] 0=level" "0: level,?"
bitfld.long 0x0 30. "TYPE_30,Type for intr_in[30] 0=level" "0: level,?"
bitfld.long 0x0 29. "TYPE_29,Type for intr_in[29] 0=level" "0: level,?"
newline
bitfld.long 0x0 28. "TYPE_28,Type for intr_in[28] 0=level" "0: level,?"
bitfld.long 0x0 27. "TYPE_27,Type for intr_in[27] 0=level" "0: level,?"
bitfld.long 0x0 26. "TYPE_26,Type for intr_in[26] 0=level" "0: level,?"
newline
bitfld.long 0x0 25. "TYPE_25,Type for intr_in[25] 0=level" "0: level,?"
bitfld.long 0x0 24. "TYPE_24,Type for intr_in[24] 0=level" "0: level,?"
bitfld.long 0x0 23. "TYPE_23,Type for intr_in[23] 0=level" "0: level,?"
newline
bitfld.long 0x0 22. "TYPE_22,Type for intr_in[22] 0=level" "0: level,?"
bitfld.long 0x0 21. "TYPE_21,Type for intr_in[21] 0=level" "0: level,?"
bitfld.long 0x0 20. "TYPE_20,Type for intr_in[20] 0=level" "0: level,?"
newline
bitfld.long 0x0 19. "TYPE_19,Type for intr_in[19] 0=level" "0: level,?"
bitfld.long 0x0 18. "TYPE_18,Type for intr_in[18] 0=level" "0: level,?"
bitfld.long 0x0 17. "TYPE_17,Type for intr_in[17] 0=level" "0: level,?"
newline
bitfld.long 0x0 16. "TYPE_16,Type for intr_in[16] 0=level" "0: level,?"
bitfld.long 0x0 15. "TYPE_15,Type for intr_in[15] 0=level" "0: level,?"
bitfld.long 0x0 14. "TYPE_14,Type for intr_in[14] 0=level" "0: level,?"
newline
bitfld.long 0x0 13. "TYPE_13,Type for intr_in[13] 0=level" "0: level,?"
bitfld.long 0x0 12. "TYPE_12,Type for intr_in[12] 0=level" "0: level,?"
bitfld.long 0x0 11. "TYPE_11,Type for intr_in[11] 0=level" "0: level,?"
newline
bitfld.long 0x0 10. "TYPE_10,Type for intr_in[10] 0=level" "0: level,?"
bitfld.long 0x0 9. "TYPE_9,Type for intr_in[9] 0=level" "0: level,?"
bitfld.long 0x0 8. "TYPE_8,Type for intr_in[8] 0=level" "0: level,?"
newline
bitfld.long 0x0 7. "TYPE_7,Type for intr_in[7] 0=level" "0: level,?"
bitfld.long 0x0 6. "TYPE_6,Type for intr_in[6] 0=level" "0: level,?"
bitfld.long 0x0 5. "TYPE_5,Type for intr_in[5] 0=level" "0: level,?"
newline
bitfld.long 0x0 4. "TYPE_4,Type for intr_in[4] 0=level" "0: level,?"
bitfld.long 0x0 3. "TYPE_3,Type for intr_in[3] 0=level" "0: level,?"
bitfld.long 0x0 2. "TYPE_2,Type for intr_in[2] 0=level" "0: level,?"
newline
bitfld.long 0x0 1. "TYPE_1,Type for intr_in[1] 0=level" "0: level,?"
bitfld.long 0x0 0. "TYPE_0,Type for intr_in[0] 0=level" "0: level,?"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG1,"
bitfld.long 0x4 31. "TYPE_63,Type for intr_in[63] 0=level" "0: level,?"
bitfld.long 0x4 30. "TYPE_62,Type for intr_in[62] 0=level" "0: level,?"
bitfld.long 0x4 29. "TYPE_61,Type for intr_in[61] 0=level" "0: level,?"
newline
bitfld.long 0x4 28. "TYPE_60,Type for intr_in[60] 0=level" "0: level,?"
bitfld.long 0x4 27. "TYPE_59,Type for intr_in[59] 0=level" "0: level,?"
bitfld.long 0x4 26. "TYPE_58,Type for intr_in[58] 0=level" "0: level,?"
newline
bitfld.long 0x4 25. "TYPE_57,Type for intr_in[57] 0=level" "0: level,?"
bitfld.long 0x4 24. "TYPE_56,Type for intr_in[56] 0=level" "0: level,?"
bitfld.long 0x4 23. "TYPE_55,Type for intr_in[55] 0=level" "0: level,?"
newline
bitfld.long 0x4 22. "TYPE_54,Type for intr_in[54] 0=level" "0: level,?"
bitfld.long 0x4 21. "TYPE_53,Type for intr_in[53] 0=level" "0: level,?"
bitfld.long 0x4 20. "TYPE_52,Type for intr_in[52] 0=level" "0: level,?"
newline
bitfld.long 0x4 19. "TYPE_51,Type for intr_in[51] 0=level" "0: level,?"
bitfld.long 0x4 18. "TYPE_50,Type for intr_in[50] 0=level" "0: level,?"
bitfld.long 0x4 17. "TYPE_49,Type for intr_in[49] 0=level" "0: level,?"
newline
bitfld.long 0x4 16. "TYPE_48,Type for intr_in[48] 0=level" "0: level,?"
bitfld.long 0x4 15. "TYPE_47,Type for intr_in[47] 0=level" "0: level,?"
bitfld.long 0x4 14. "TYPE_46,Type for intr_in[46] 0=level" "0: level,?"
newline
bitfld.long 0x4 13. "TYPE_45,Type for intr_in[45] 0=level" "0: level,?"
bitfld.long 0x4 12. "TYPE_44,Type for intr_in[44] 0=level" "0: level,?"
bitfld.long 0x4 11. "TYPE_43,Type for intr_in[43] 0=level" "0: level,?"
newline
bitfld.long 0x4 10. "TYPE_42,Type for intr_in[42] 0=level" "0: level,?"
bitfld.long 0x4 9. "TYPE_41,Type for intr_in[41] 0=level" "0: level,?"
bitfld.long 0x4 8. "TYPE_40,Type for intr_in[40] 0=level" "0: level,?"
newline
bitfld.long 0x4 7. "TYPE_39,Type for intr_in[39] 0=level" "0: level,?"
bitfld.long 0x4 6. "TYPE_38,Type for intr_in[38] 0=level" "0: level,?"
bitfld.long 0x4 5. "TYPE_37,Type for intr_in[37] 0=level" "0: level,?"
newline
bitfld.long 0x4 4. "TYPE_36,Type for intr_in[36] 0=level" "0: level,?"
bitfld.long 0x4 3. "TYPE_35,Type for intr_in[35] 0=level" "0: level,?"
bitfld.long 0x4 2. "TYPE_34,Type for intr_in[34] 0=level" "0: level,?"
newline
bitfld.long 0x4 1. "TYPE_33,Type for intr_in[33] 0=level" "0: level,?"
bitfld.long 0x4 0. "TYPE_32,Type for intr_in[32] 0=level" "0: level,?"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG2,"
bitfld.long 0x8 31. "TYPE_95,Type for slv_events_in[31] 0=level" "0: level,?"
bitfld.long 0x8 30. "TYPE_94,Type for slv_events_in[30] 0=level" "0: level,?"
bitfld.long 0x8 29. "TYPE_93,Type for slv_events_in[29] 0=level" "0: level,?"
newline
bitfld.long 0x8 28. "TYPE_92,Type for slv_events_in[28] 0=level" "0: level,?"
bitfld.long 0x8 27. "TYPE_91,Type for slv_events_in[27] 0=level" "0: level,?"
bitfld.long 0x8 26. "TYPE_90,Type for slv_events_in[26] 0=level" "0: level,?"
newline
bitfld.long 0x8 25. "TYPE_89,Type for slv_events_in[25] 0=level" "0: level,?"
bitfld.long 0x8 24. "TYPE_88,Type for slv_events_in[24] 0=level" "0: level,?"
bitfld.long 0x8 23. "TYPE_87,Type for slv_events_in[23] 0=level" "0: level,?"
newline
bitfld.long 0x8 22. "TYPE_86,Type for slv_events_in[22] 0=level" "0: level,?"
bitfld.long 0x8 21. "TYPE_85,Type for slv_events_in[21] 0=level" "0: level,?"
bitfld.long 0x8 20. "TYPE_84,Type for slv_events_in[20] 0=level" "0: level,?"
newline
bitfld.long 0x8 19. "TYPE_83,Type for slv_events_in[19] 0=level" "0: level,?"
bitfld.long 0x8 18. "TYPE_82,Type for slv_events_in[18] 0=level" "0: level,?"
bitfld.long 0x8 17. "TYPE_81,Type for slv_events_in[17] 0=level" "0: level,?"
newline
bitfld.long 0x8 16. "TYPE_80,Type for slv_events_in[16] 0=level" "0: level,?"
bitfld.long 0x8 15. "TYPE_79,Type for slv_events_in[15] 0=level" "0: level,?"
bitfld.long 0x8 14. "TYPE_78,Type for slv_events_in[14] 0=level" "0: level,?"
newline
bitfld.long 0x8 13. "TYPE_77,Type for slv_events_in[13] 0=level" "0: level,?"
bitfld.long 0x8 12. "TYPE_76,Type for slv_events_in[12] 0=level" "0: level,?"
bitfld.long 0x8 11. "TYPE_75,Type for slv_events_in[11] 0=level" "0: level,?"
newline
bitfld.long 0x8 10. "TYPE_74,Type for slv_events_in[10] 0=level" "0: level,?"
bitfld.long 0x8 9. "TYPE_73,Type for slv_events_in[9] 0=level" "0: level,?"
bitfld.long 0x8 8. "TYPE_72,Type for slv_events_in[8] 0=level" "0: level,?"
newline
bitfld.long 0x8 7. "TYPE_71,Type for slv_events_in[7] 0=level" "0: level,?"
bitfld.long 0x8 6. "TYPE_70,Type for slv_events_in[6] 0=level" "0: level,?"
bitfld.long 0x8 5. "TYPE_69,Type for slv_events_in[5] 0=level" "0: level,?"
newline
bitfld.long 0x8 4. "TYPE_68,Type for slv_events_in[4] 0=level" "0: level,?"
bitfld.long 0x8 3. "TYPE_67,Type for slv_events_in[3] 0=level" "0: level,?"
bitfld.long 0x8 2. "TYPE_66,Type for slv_events_in[2] 0=level" "0: level,?"
newline
bitfld.long 0x8 1. "TYPE_65,Type for slv_events_in[1] 0=level" "0: level,?"
bitfld.long 0x8 0. "TYPE_64,Type for slv_events_in[0] 0=level" "0: level,?"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG3,"
bitfld.long 0xC 31. "TYPE_127,Type for slv_events_in[63] 0=level" "0: level,?"
bitfld.long 0xC 30. "TYPE_126,Type for slv_events_in[62] 0=level" "0: level,?"
bitfld.long 0xC 29. "TYPE_125,Type for slv_events_in[61] 0=level" "0: level,?"
newline
bitfld.long 0xC 28. "TYPE_124,Type for slv_events_in[60] 0=level" "0: level,?"
bitfld.long 0xC 27. "TYPE_123,Type for slv_events_in[59] 0=level" "0: level,?"
bitfld.long 0xC 26. "TYPE_122,Type for slv_events_in[58] 0=level" "0: level,?"
newline
bitfld.long 0xC 25. "TYPE_121,Type for slv_events_in[57] 0=level" "0: level,?"
bitfld.long 0xC 24. "TYPE_120,Type for slv_events_in[56] 0=level" "0: level,?"
bitfld.long 0xC 23. "TYPE_119,Type for slv_events_in[55] 0=level" "0: level,?"
newline
bitfld.long 0xC 22. "TYPE_118,Type for slv_events_in[54] 0=level" "0: level,?"
bitfld.long 0xC 21. "TYPE_117,Type for slv_events_in[53] 0=level" "0: level,?"
bitfld.long 0xC 20. "TYPE_116,Type for slv_events_in[52] 0=level" "0: level,?"
newline
bitfld.long 0xC 19. "TYPE_115,Type for slv_events_in[51] 0=level" "0: level,?"
bitfld.long 0xC 18. "TYPE_114,Type for slv_events_in[50] 0=level" "0: level,?"
bitfld.long 0xC 17. "TYPE_113,Type for slv_events_in[49] 0=level" "0: level,?"
newline
bitfld.long 0xC 16. "TYPE_112,Type for slv_events_in[48] 0=level" "0: level,?"
bitfld.long 0xC 15. "TYPE_111,Type for slv_events_in[47] 0=level" "0: level,?"
bitfld.long 0xC 14. "TYPE_110,Type for slv_events_in[46] 0=level" "0: level,?"
newline
bitfld.long 0xC 13. "TYPE_109,Type for slv_events_in[45] 0=level" "0: level,?"
bitfld.long 0xC 12. "TYPE_108,Type for slv_events_in[44] 0=level" "0: level,?"
bitfld.long 0xC 11. "TYPE_107,Type for slv_events_in[43] 0=level" "0: level,?"
newline
bitfld.long 0xC 10. "TYPE_106,Type for slv_events_in[42] 0=level" "0: level,?"
bitfld.long 0xC 9. "TYPE_105,Type for slv_events_in[41] 0=level" "0: level,?"
bitfld.long 0xC 8. "TYPE_104,Type for slv_events_in[40] 0=level" "0: level,?"
newline
bitfld.long 0xC 7. "TYPE_103,Type for slv_events_in[39] 0=level" "0: level,?"
bitfld.long 0xC 6. "TYPE_102,Type for slv_events_in[38] 0=level" "0: level,?"
bitfld.long 0xC 5. "TYPE_101,Type for slv_events_in[37] 0=level" "0: level,?"
newline
bitfld.long 0xC 4. "TYPE_100,Type for slv_events_in[36] 0=level" "0: level,?"
bitfld.long 0xC 3. "TYPE_99,Type for slv_events_in[35] 0=level" "0: level,?"
bitfld.long 0xC 2. "TYPE_98,Type for slv_events_in[34] 0=level" "0: level,?"
newline
bitfld.long 0xC 1. "TYPE_97,Type for slv_events_in[33] 0=level" "0: level,?"
bitfld.long 0xC 0. "TYPE_96,Type for slv_events_in[32] 0=level" "0: level,?"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG4,"
bitfld.long 0x10 31. "TYPE_159,Type for slv_events_in[95] 0=level" "0: level,?"
bitfld.long 0x10 30. "TYPE_158,Type for slv_events_in[94] 0=level" "0: level,?"
bitfld.long 0x10 29. "TYPE_157,Type for slv_events_in[93] 0=level" "0: level,?"
newline
bitfld.long 0x10 28. "TYPE_156,Type for slv_events_in[92] 0=level" "0: level,?"
bitfld.long 0x10 27. "TYPE_155,Type for slv_events_in[91] 0=level" "0: level,?"
bitfld.long 0x10 26. "TYPE_154,Type for slv_events_in[90] 0=level" "0: level,?"
newline
bitfld.long 0x10 25. "TYPE_153,Type for slv_events_in[89] 0=level" "0: level,?"
bitfld.long 0x10 24. "TYPE_152,Type for slv_events_in[88] 0=level" "0: level,?"
bitfld.long 0x10 23. "TYPE_151,Type for slv_events_in[87] 0=level" "0: level,?"
newline
bitfld.long 0x10 22. "TYPE_150,Type for slv_events_in[86] 0=level" "0: level,?"
bitfld.long 0x10 21. "TYPE_149,Type for slv_events_in[85] 0=level" "0: level,?"
bitfld.long 0x10 20. "TYPE_148,Type for slv_events_in[84] 0=level" "0: level,?"
newline
bitfld.long 0x10 19. "TYPE_147,Type for slv_events_in[83] 0=level" "0: level,?"
bitfld.long 0x10 18. "TYPE_146,Type for slv_events_in[82] 0=level" "0: level,?"
bitfld.long 0x10 17. "TYPE_145,Type for slv_events_in[81] 0=level" "0: level,?"
newline
bitfld.long 0x10 16. "TYPE_144,Type for slv_events_in[80] 0=level" "0: level,?"
bitfld.long 0x10 15. "TYPE_143,Type for slv_events_in[79] 0=level" "0: level,?"
bitfld.long 0x10 14. "TYPE_142,Type for slv_events_in[78] 0=level" "0: level,?"
newline
bitfld.long 0x10 13. "TYPE_141,Type for slv_events_in[77] 0=level" "0: level,?"
bitfld.long 0x10 12. "TYPE_140,Type for slv_events_in[76] 0=level" "0: level,?"
bitfld.long 0x10 11. "TYPE_139,Type for slv_events_in[75] 0=level" "0: level,?"
newline
bitfld.long 0x10 10. "TYPE_138,Type for slv_events_in[74] 0=level" "0: level,?"
bitfld.long 0x10 9. "TYPE_137,Type for slv_events_in[73] 0=level" "0: level,?"
bitfld.long 0x10 8. "TYPE_136,Type for slv_events_in[72] 0=level" "0: level,?"
newline
bitfld.long 0x10 7. "TYPE_135,Type for slv_events_in[71] 0=level" "0: level,?"
bitfld.long 0x10 6. "TYPE_134,Type for slv_events_in[70] 0=level" "0: level,?"
bitfld.long 0x10 5. "TYPE_133,Type for slv_events_in[69] 0=level" "0: level,?"
newline
bitfld.long 0x10 4. "TYPE_132,Type for slv_events_in[68] 0=level" "0: level,?"
bitfld.long 0x10 3. "TYPE_131,Type for slv_events_in[67] 0=level" "0: level,?"
bitfld.long 0x10 2. "TYPE_130,Type for slv_events_in[66] 0=level" "0: level,?"
newline
bitfld.long 0x10 1. "TYPE_129,Type for slv_events_in[65] 0=level" "0: level,?"
bitfld.long 0x10 0. "TYPE_128,Type for slv_events_in[64] 0=level" "0: level,?"
group.long 0x1100++0x4F
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG0,"
bitfld.long 0x0 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x0 0.--8. 1. "NEST_HINT_0,Host Int 0 Nesting Level"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG1,"
bitfld.long 0x4 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x4 0.--8. 1. "NEST_HINT_1,Host Int 1 Nesting Level"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG2,"
bitfld.long 0x8 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x8 0.--8. 1. "NEST_HINT_2,Host Int 2 Nesting Level"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG3,"
bitfld.long 0xC 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0xC 0.--8. 1. "NEST_HINT_3,Host Int 3 Nesting Level"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG4,"
bitfld.long 0x10 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT_4,Host Int 4 Nesting Level"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG5,"
bitfld.long 0x14 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT_5,Host Int 5 Nesting Level"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG6,"
bitfld.long 0x18 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT_6,Host Int 6 Nesting Level"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG7,"
bitfld.long 0x1C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT_7,Host Int 7 Nesting Level"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG8,"
bitfld.long 0x20 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT_8,Host Int 8 Nesting Level"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG9,"
bitfld.long 0x24 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT_9,Host Int 9 Nesting Level"
line.long 0x28 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG10,"
bitfld.long 0x28 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x28 0.--8. 1. "NEST_HINT_10,Host Int 10 Nesting Level"
line.long 0x2C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG11,"
bitfld.long 0x2C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x2C 0.--8. 1. "NEST_HINT_11,Host Int 11 Nesting Level"
line.long 0x30 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG12,"
bitfld.long 0x30 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x30 0.--8. 1. "NEST_HINT_12,Host Int 12 Nesting Level"
line.long 0x34 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG13,"
bitfld.long 0x34 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x34 0.--8. 1. "NEST_HINT_13,Host Int 13 Nesting Level"
line.long 0x38 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG14,"
bitfld.long 0x38 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x38 0.--8. 1. "NEST_HINT_14,Host Int 14 Nesting Level"
line.long 0x3C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG15,"
bitfld.long 0x3C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x3C 0.--8. 1. "NEST_HINT_15,Host Int 15 Nesting Level"
line.long 0x40 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG16,"
bitfld.long 0x40 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x40 0.--8. 1. "NEST_HINT_16,Host Int 16 Nesting Level"
line.long 0x44 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG17,"
bitfld.long 0x44 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x44 0.--8. 1. "NEST_HINT_17,Host Int 17 Nesting Level"
line.long 0x48 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG18,"
bitfld.long 0x48 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x48 0.--8. 1. "NEST_HINT_18,Host Int 18 Nesting Level"
line.long 0x4C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG19,"
bitfld.long 0x4C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x4C 0.--8. 1. "NEST_HINT_19,Host Int 19 Nesting Level"
group.long 0x1500++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_HINT_REG0,"
bitfld.long 0x0 19. "ENABLE_HINT_19,Enable for Host Int 19" "0,1"
bitfld.long 0x0 18. "ENABLE_HINT_18,Enable for Host Int 18" "0,1"
bitfld.long 0x0 17. "ENABLE_HINT_17,Enable for Host Int 17" "0,1"
newline
bitfld.long 0x0 16. "ENABLE_HINT_16,Enable for Host Int 16" "0,1"
bitfld.long 0x0 15. "ENABLE_HINT_15,Enable for Host Int 15" "0,1"
bitfld.long 0x0 14. "ENABLE_HINT_14,Enable for Host Int 14" "0,1"
newline
bitfld.long 0x0 13. "ENABLE_HINT_13,Enable for Host Int 13" "0,1"
bitfld.long 0x0 12. "ENABLE_HINT_12,Enable for Host Int 12" "0,1"
bitfld.long 0x0 11. "ENABLE_HINT_11,Enable for Host Int 11" "0,1"
newline
bitfld.long 0x0 10. "ENABLE_HINT_10,Enable for Host Int 10" "0,1"
bitfld.long 0x0 9. "ENABLE_HINT_9,Enable for Host Int 9" "0,1"
bitfld.long 0x0 8. "ENABLE_HINT_8,Enable for Host Int 8" "0,1"
newline
bitfld.long 0x0 7. "ENABLE_HINT_7,Enable for Host Int 7" "0,1"
bitfld.long 0x0 6. "ENABLE_HINT_6,Enable for Host Int 6" "0,1"
bitfld.long 0x0 5. "ENABLE_HINT_5,Enable for Host Int 5" "0,1"
newline
bitfld.long 0x0 4. "ENABLE_HINT_4,Enable for Host Int 4" "0,1"
bitfld.long 0x0 3. "ENABLE_HINT_3,Enable for Host Int 3" "0,1"
bitfld.long 0x0 2. "ENABLE_HINT_2,Enable for Host Int 2" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_HINT_1,Enable for Host Int 1" "0,1"
bitfld.long 0x0 0. "ENABLE_HINT_0,Enable for Host Int 0" "0,1"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_ICSS_UART_UART_SLV (PRU_ICSSG0_PR1_ICSS_UART_UART_SLV)"
base ad:0x30028000
group.long 0x0++0x13
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_RBR_TBR,RBR_TBR Registers"
hexmask.long.word 0x0 8.--17. 1. "TBR_DATA,Transmit Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR_DATA,Receive Buffer Register"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_INT_EN,UART Interrupt Enable Register"
bitfld.long 0x4 3. "EDSSI,Enable for Modem Status Interrupt" "0,1"
bitfld.long 0x4 2. "ELSI,Enable for Receiver Line Status Interrupt" "0,1"
bitfld.long 0x4 1. "ETBEI,Enable for Transmitter Holding Register Empty Interrupt" "0,1"
bitfld.long 0x4 0. "ERBI,Enable for Receiver Data Available Interrupt" "0,1"
line.long 0x8 "PR1_ICSS_UART__UART_SLV__REGS_INT_FIFO,Interrupt Identification Register / FIFO Control Register"
bitfld.long 0x8 14.--15. "FCR_RXFIFTL,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x8 11. "FCR_DMAMODE1,DMA Mode Select" "0,1"
bitfld.long 0x8 10. "FCR_TXCLR,Transmitter FIFO Reset" "0,1"
bitfld.long 0x8 9. "FCR_RXCLR,Receiver FIFO Reset" "0,1"
bitfld.long 0x8 8. "FCR_FIFOEN,FIFO Enable Register" "0,1"
rbitfld.long 0x8 6.--7. "IIR_FIFOEN,FIFOs enabled" "0,1,2,3"
newline
rbitfld.long 0x8 1.--3. "IIR_INTID,Interrupt Type" "0,1,2,3,4,5,6,7"
rbitfld.long 0x8 0. "IIR_IPEND,Receiver Data Available Interrupt Pending" "0,1"
line.long 0xC "PR1_ICSS_UART__UART_SLV__REGS_LCTR,Line Control Register"
bitfld.long 0xC 7. "DLAB,Divisor Latch Access Bit" "0,1"
bitfld.long 0xC 6. "BC,Break Control" "0,1"
bitfld.long 0xC 5. "SP,Stick Parity" "0,1"
bitfld.long 0xC 4. "EPS,Even Parity Select" "0,1"
bitfld.long 0xC 3. "PEN,Parity Enable" "0,1"
bitfld.long 0xC 2. "STB,Number of Stop Bits" "0,1"
newline
bitfld.long 0xC 1. "WLS1,Word Length Select Bit 1" "0,1"
bitfld.long 0xC 0. "WLS0,Word Length Select Bit 0" "0,1"
line.long 0x10 "PR1_ICSS_UART__UART_SLV__REGS_MCTR,Modem Control Register"
bitfld.long 0x10 5. "AFE,Autoflow Control Enable" "0,1"
bitfld.long 0x10 4. "LOOP,LOOP Bit" "0,1"
bitfld.long 0x10 3. "OUT2,Out2 Bit" "0,1"
bitfld.long 0x10 2. "OUT1,Out1 Bit" "0,1"
bitfld.long 0x10 1. "RTS,Ready to Send" "0,1"
bitfld.long 0x10 0. "DTR,Data Terminal Ready" "0,1"
rgroup.long 0x14++0x7
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_LSR1,Line Status Register1"
bitfld.long 0x0 7. "RXFIFOE,Receiver FIFO Error" "0,1"
bitfld.long 0x0 6. "TEMT,Transmitter Empty" "0,1"
bitfld.long 0x0 5. "THRE,Transmitter Holding Register" "0,1"
bitfld.long 0x0 4. "BI,Break Interrupt" "0,1"
bitfld.long 0x0 3. "FE,Framing Error" "0,1"
bitfld.long 0x0 2. "PE,Parity Error" "0,1"
newline
bitfld.long 0x0 1. "OE,Overrun Error" "0,1"
bitfld.long 0x0 0. "DR,Data Ready" "0,1"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_MSR,Modem Status Register"
bitfld.long 0x4 7. "CD,Carrier Detect" "0,1"
bitfld.long 0x4 6. "RI,Ring Indicator" "0,1"
bitfld.long 0x4 5. "DSR,Data Set Ready" "0,1"
bitfld.long 0x4 4. "CTS,Clear To Send" "0,1"
bitfld.long 0x4 3. "DCD,Delta Carrier Detect" "0,1"
bitfld.long 0x4 2. "TERI,Trailing Edge Ring Indicator" "0,1"
newline
bitfld.long 0x4 1. "DDSR,Delta Set Ready" "0,1"
bitfld.long 0x4 0. "DCTS,Delta Clear To Send" "0,1"
group.long 0x1C++0xB
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_SCRATCH,UART Scratch Register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,Scratch Register Bits"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_DIVLSB,UART Divisor Register"
hexmask.long.byte 0x4 0.--7. 1. "DLL,Divisor Latch [LSB]"
line.long 0x8 "PR1_ICSS_UART__UART_SLV__REGS_DIVMSB,UART Divisor Register"
hexmask.long.byte 0x8 0.--7. 1. "DLH,Divisor Latch [MSB]"
rgroup.long 0x28++0x3
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_PID,Peripheral ID Register"
hexmask.long 0x0 0.--31. 1. "PID,"
group.long 0x30++0x7
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_PWR,UART PowerManagement and Emulation Register"
bitfld.long 0x0 15. "URST,UART Reset Bit" "0,1"
bitfld.long 0x0 14. "UTRST,UART Transmitter Reset Bit" "0,1"
bitfld.long 0x0 13. "URRST,UART Receiver Reset Bit" "0,1"
rbitfld.long 0x0 1. "RES,Free Bit" "0,1"
bitfld.long 0x0 0. "FREE,Free Bit" "0,1"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_MODE,UART Mode Definition Register"
bitfld.long 0x4 0. "OSM_SEL,Oversampling Mode Select" "0,1"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV (PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV)"
base ad:0x30030000
group.long 0x0++0x17
line.long 0x0 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_TSCNT,TIME STAMP COUNTER REGISTER"
hexmask.long 0x0 0.--31. 1. "TSCNT,ACTIVE 32 BIT COUNTER REGISTER WHICH IS USED AS THE CAPTURE TIME-BASE"
line.long 0x4 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CNTPHS,COUNTER PHASE CONTROL REGISTER"
hexmask.long 0x4 0.--31. 1. "CNTPHS,COUNTER PHASE VALUE REGISTER THAT CAN BE PROGRAMMED FOR PHASE LAG/LEAD THIS REGISTER SHADOWS TSCNT AND IS LOADED INTO TSCNT UPON EITHER A SYNCI EVENT OR S/W FORCE VIA A CONTROL BITUSED TO ACHIEVE PHASE CONTROL SYNC WITH RESPECT TO OTHER ECAP AND.."
line.long 0x8 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP1,CAPTURE-1 REGISTER"
hexmask.long 0x8 0.--31. 1. "CAP1,THIS REGISTER CAN BE LOADED [WRITTEN] BY :TIME-STAMP [IE COUNTER VALUE] DURING A CAPTURE EVENTS/W MAY BE USEFUL FOR TEST PURPOSES / INITIALISATIONAPRD SHADOW REGISTER [IE CAP3] WHEN USED IN APWM MODE"
line.long 0xC "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP2,CAPTURE-2 REGISTER"
hexmask.long 0xC 0.--31. 1. "CAP2,THIS REGISTER CAN BE LOADED [WRITTEN] BY :TIME-STAMP [IE COUNTER VALUE] DURING A CAPTURE EVENTS/W MAY BE USEFUL FOR TEST PURPOSESACMP SHADOW REGISTER [IE CAP4] WHEN USED IN APWM MODE"
line.long 0x10 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP3,CAPTURE-3 REGISTER"
hexmask.long 0x10 0.--31. 1. "CAP3,IN CMP MODE THIS IS A TIME-STAMP CAPTURE REGISTERIN APMW MODE THIS IS THE PERIOD SHADOW [APER] REGISTER USER UPDATES THE PWM PERIOD VALUE VIA THIS REGISTER IN THIS MODE CAP3 [APRD] SHADOWS CAP1"
line.long 0x14 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP4,CAPTURE-4 REGISTER"
hexmask.long 0x14 0.--31. 1. "CAP4,IN CMP MODE THIS IS A TIME-STAMP CAPTURE REGISTERIN APMW MODE THIS IS THE COMPARE SHADOW [ACMP] REGISTER USER UPDATES THE PWM COMPARE VALUE VIA THIS REGISTER IN THIS MODE CAP4 [ACMP] SHADOWS CAP2"
group.long 0x28++0x7
line.long 0x0 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECCTL2_ECCTL1,ECAP CONTROL REGISTER 1"
hexmask.long.byte 0x0 27.--31. 1. "FILTER,"
bitfld.long 0x0 26. "APWMPOL,APWM OUTPUT POLARITY SELECT:0OUTPUT IS ACTIVE HIGH [IE COMPARE VALUE DEFINES HIGH TIME]1OUTPUT IS ACTIVE LOW [IE COMPARE VALUE DEFINES LOW TIME]NOTE: THIS IS APPLICABLE ONLY IN APWM OPERATING MODE" "0,1"
bitfld.long 0x0 25. "CAP_APWM,CAP/APWM OPERATING MODE SELECT:0ECAP MODULE OPERATES IN CAPTURE MODETHIS MODE FORCES THE FOLLOWING CONFIGURATION:1] INHIBITS TSCNT RESETS VIA PRD_EQ EVENT2] INHIBITS SHADOW LOADS ON CAP1 &AMP" "0,1"
newline
bitfld.long 0x0 24. "SWSYNC,SOFTWARE FORCED COUNTER [TSCNT] SYNCING:0WRITING A ZERO HAS NO EFFECT WILL ALWAYS RETURN A ZERO1WRITING A ONE WILL FORCE A TSCNT SHADOW LOAD OF CURRENT ECAP MODULE AND ANY ECAP MODULES DOWN-STREAM PROVIDING THE SYNCO_SEL BITS ARE 0 0 AFTER WRITING.." "0,1"
bitfld.long 0x0 22.--23. "SYNCO_SEL,SYNC-OUT SELECT:0 0SELECT SYNC-IN EVENT TO BE THE SYNC-OUT SIGNAL [PASS THROUGH]0 1SELECT PRD_EQ EVENT TO BE THE SYNC-OUT SIGNAL1 0DISABLE SYNC OUT SIGNAL1 1DISABLE SYNC OUT SIGNALNOTE: SELECTION PRD_EQ IS MEANINGFUL ONLY IN APWM MODE  HOWEVER.." "0,1,2,3"
bitfld.long 0x0 21. "SYNCI_EN,COUNTER [TSCNT] SYNC-IN SELECT MODE:0DISABLE SYNC-IN OPTION1ENABLE COUNTER [TSCNT] TO BE LOADED FROM CNTPHS REGISTER UPON EITHER A SYNCI SIGNAL OR A S/W FORCE EVENT" "0,1"
newline
bitfld.long 0x0 20. "TSCNTSTP,COUNTER STOP [FREEZE] CONTROL:0COUNTER STOPPED1COUNTER FREE RUNNING" "0,1"
bitfld.long 0x0 19. "REARM_RESET,ONE-SHOT RE-ARMING  IE WAIT FOR STOP TRIGGER:WRITING A ONE ARMS THE ONE-SHOT SEQUENCE  IE:1] RESETS THE MOD4 COUNTER TO ZERO2] UN-FREEZES THE MOD4 COUNTER3] ENABLES CAPTURE REGISTER LOADSWRITING A ZERO HAS NO EFFECT ALWAYS RETURNS A 0NOTE:.." "0,1"
bitfld.long 0x0 17.--18. "STOPVALUE,STOP VALUE FOR ONE-SHOT MODE:THIS IS THE NUMBER [BETWEEN 1-4] OF CAPTURES ALLOWED TO OCCUR BEFORE THE CAP[1-4] REGISTERS ARE FROZEN  IECAPTURE SEQUENCE IS STOPPED0 0STOP AFTER CAPTURE EVENT 10 1STOP AFTER CAPTURE EVENT 21 0STOP AFTER CAPTURE.." "0,1,2,3"
newline
bitfld.long 0x0 16. "CONT_ONESHT,CONTINUOUS OR ONESHOT MODE CONTROL:[APPLICABLE ONLY IN CAPTURE MODE]0OPERATE IN CONTINUOUS MODE1OPERATE IN ONE-SHOT MODE" "0,1"
bitfld.long 0x0 15. "FREE,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1"
bitfld.long 0x0 14. "SOFT,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1"
newline
hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,EVENT FILTER PRESCALE SELECT:0 0 0 0 0DIVIDE BY 1 [IE NO PRESCALE  BY-PASS THE PRESCALER]0 0 0 0 1DIVIDE BY 20 0 0 1 0DIVIDE BY 40 0 0 1 1DIVIDE BY 60 0 1 0 0DIVIDE BY 80 0 1 0 1DIVIDE BY 10 1 1 1 1 0DIVIDE BY 601 1 1 1 1DIVIDE BY 62"
bitfld.long 0x0 8. "CAPLDEN,ENABLE LOADING OF CAP1-4 REGISTERS ON A CAPTURE EVENT:0DISABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME1ENABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME" "0,1"
bitfld.long 0x0 7. "CTRRST4,COUNTER RESET ON CAPTURE EVENT 4:0DO NOT RESET COUNTER ON CAPTURE EVENT 4 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 4 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,?"
newline
bitfld.long 0x0 6. "CAP4POL,CAPTURE EVENT 4 POLARITY SELECT:0CAPTURE EVENT 4 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 4 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
bitfld.long 0x0 5. "CTRRST3,COUNTER RESET ON CAPTURE EVENT 3:0DO NOT RESET COUNTER ON CAPTURE EVENT 3 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 3 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,?"
bitfld.long 0x0 4. "CAP3POL,CAPTURE EVENT 3 POLARITY SELECT:0CAPTURE EVENT 3 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 3 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
newline
bitfld.long 0x0 3. "CTRRST2,COUNTER RESET ON CAPTURE EVENT 2:0DO NOT RESET COUNTER ON CAPTURE EVENT 2 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 2 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,?"
bitfld.long 0x0 2. "CAP2POL,CAPTURE EVENT 2 POLARITY SELECT:0CAPTURE EVENT 2 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 2 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
bitfld.long 0x0 1. "CTRRST1,COUNTER RESET ON CAPTURE EVENT 1:0DO NOT RESET COUNTER ON CAPTURE EVENT 1 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 1 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,1: 0DO NOT RESET COUNTER ON CAPTURE EVENT 1.."
newline
bitfld.long 0x0 0. "CAP1POL,CAPTURE EVENT 1 POLARITY SELECT:0CAPTURE EVENT 1 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 1 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
line.long 0x4 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECFLG_ECEINT,ECAP INTERRUPT ENABLE REGISTER"
hexmask.long.byte 0x4 24.--31. 1. "FLAG_RESV0,"
rbitfld.long 0x4 23. "FLAG_CMPEQ,COMPARE EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE COMPARE REGISTER VALUE [ACMP]READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1"
rbitfld.long 0x4 22. "FLAG_PRDEQ,PERIOD EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE PERIOD REGISTER VALUE [APER] AND WAS RESETREADING A 0 INDICATES NO EVENT OCCURREDNOTES: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1"
newline
rbitfld.long 0x4 21. "FLAG_CNTOVF,COUNTER OVERFLOW STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] HAS MADE THE TRANSITION FROM FFFFFFFF 00000000READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ACTIVE IN CAP &AMP" "0,1"
rbitfld.long 0x4 20. "FLAG_CEVT4,CAPTURE EVENT 4 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FOURTH EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x4 19. "FLAG_CEVT3,CAPTURE EVENT 3 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE THIRD EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
newline
rbitfld.long 0x4 18. "FLAG_CEVT2,CAPTURE EVENT 2 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE SECOND EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x4 17. "FLAG_CEVT1,CAPTURE EVENT 1 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FIRST EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x4 16. "FLAG_INT,GLOBAL INTERRUPT STATUS FLAG: READING A 1 ON THIS BIT INDICATES THAT AN INTERRUPT WAS GENERATED FROM ONE OF THE FOLLOWING EVENTSREADING A 0 INDICATES NO INTERRUPT GENERATED" "0,1"
newline
hexmask.long.byte 0x4 8.--15. 1. "EN__RESV1,"
bitfld.long 0x4 7. "EN_CMPEQ,COMPARE EQUAL INTERRUPT ENABLE: 0DISABLED COMPARE EQUAL AS AN INTERRUPT SOURCE1ENABLE COMPARE EQUAL AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 6. "EN_PRDEQ,PERIOD EQUAL INTERRUPT ENABLE: 0DISABLED PERIOD EQUAL AS AN INTERRUPT SOURCE1ENABLE PERIOD EQUAL AS AN INTERRUPT SOURCE" "0,1"
newline
bitfld.long 0x4 5. "EN_CNTOVF,COUNTER OVERFLOW INTERRUPT ENABLE: 0DISABLED COUNTER OVERFLOW AS AN INTERRUPT SOURCE1ENABLE COUNTER OVERFLOW AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 4. "EN_CEVT4,CAPTURE EVENT 4 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 3. "EN_CEVT3,CAPTURE EVENT 3 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
newline
bitfld.long 0x4 2. "EN_CEVT2,CAPTURE EVENT 2 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 1. "EN_CEVT1,CAPTURE EVENT 1 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
rbitfld.long 0x4 0. "EN_RESV0," "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_PID,ECAP PERIPHERAL ID REGISTER"
hexmask.long 0x0 0.--31. 1. "REVID,"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV"
base ad:0x20000
rgroup.long 0x0++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_REVISION_REG,"
bitfld.long 0x0 30.--31. "REV_SCHEME,Scheme" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "REV_MODULE,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REV_RTL,RTL revisions"
newline
bitfld.long 0x0 8.--10. "REV_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "REV_CUSTOM,Custom revision" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REV_MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_CONTROL_REG,"
bitfld.long 0x0 4. "PRIORITY_HOLD_MODE,Priority Holding Mode" "0,1"
bitfld.long 0x0 2.--3. "NEST_MODE,Nesting Mode" "0,1,2,3"
bitfld.long 0x0 1. "WAKEUP_MODE,Wakeup mode enable" "0,1"
group.long 0x10++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_GLOBAL_ENABLE_HINT_REG,"
bitfld.long 0x0 0. "ENABLE_HINT_ANY,Global Enable for all Host Ints" "0,1"
group.long 0x1C++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_GLB_NEST_LEVEL_REG,"
bitfld.long 0x0 31. "GLB_NEST_AUTO_OVR,Global Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x0 0.--8. 1. "GLB_NEST_LEVEL,Global Nesting Level"
wgroup.long 0x20++0x7
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_STATUS_SET_INDEX_REG,"
hexmask.long.word 0x0 0.--9. 1. "STATUS_SET_INDEX,Status Set Index Register (write index to set status of)"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_STATUS_CLR_INDEX_REG,"
hexmask.long.word 0x4 0.--9. 1. "STATUS_CLR_INDEX,Status Clear Index Register (write index to clear status of)"
group.long 0x28++0x7
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_SET_INDEX_REG,"
hexmask.long.word 0x0 0.--9. 1. "ENABLE_SET_INDEX,Enable Set Index Register (write index to set enable of)"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_INDEX_REG,"
hexmask.long.word 0x4 0.--9. 1. "ENABLE_CLR_INDEX,Enable Clear Index Register (write index to clear enable of)"
group.long 0x34++0x7
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_ENABLE_SET_INDEX_REG,"
hexmask.long.word 0x0 0.--9. 1. "HINT_ENABLE_SET_INDEX,Enable set for Host Interrupts"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_ENABLE_CLR_INDEX_REG,"
hexmask.long.word 0x4 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Enable clear for Host Interrupts"
rgroup.long 0x80++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_GLB_PRI_INTR_REG,"
bitfld.long 0x0 31. "GLB_NONE,No interrupt pending flag" "0,1"
hexmask.long.word 0x0 0.--9. 1. "GLB_PRI_INTR,Prioritized Interrupt"
group.long 0x200++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG0,"
bitfld.long 0x0 31. "RAW_STATUS_31,Raw Status (write 1 to set) for intr_in[31]" "0,1"
bitfld.long 0x0 30. "RAW_STATUS_30,Raw Status (write 1 to set) for intr_in[30]" "0,1"
bitfld.long 0x0 29. "RAW_STATUS_29,Raw Status (write 1 to set) for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "RAW_STATUS_28,Raw Status (write 1 to set) for intr_in[28]" "0,1"
bitfld.long 0x0 27. "RAW_STATUS_27,Raw Status (write 1 to set) for intr_in[27]" "0,1"
bitfld.long 0x0 26. "RAW_STATUS_26,Raw Status (write 1 to set) for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "RAW_STATUS_25,Raw Status (write 1 to set) for intr_in[25]" "0,1"
bitfld.long 0x0 24. "RAW_STATUS_24,Raw Status (write 1 to set) for intr_in[24]" "0,1"
bitfld.long 0x0 23. "RAW_STATUS_23,Raw Status (write 1 to set) for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "RAW_STATUS_22,Raw Status (write 1 to set) for intr_in[22]" "0,1"
bitfld.long 0x0 21. "RAW_STATUS_21,Raw Status (write 1 to set) for intr_in[21]" "0,1"
bitfld.long 0x0 20. "RAW_STATUS_20,Raw Status (write 1 to set) for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "RAW_STATUS_19,Raw Status (write 1 to set) for intr_in[19]" "0,1"
bitfld.long 0x0 18. "RAW_STATUS_18,Raw Status (write 1 to set) for intr_in[18]" "0,1"
bitfld.long 0x0 17. "RAW_STATUS_17,Raw Status (write 1 to set) for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "RAW_STATUS_16,Raw Status (write 1 to set) for intr_in[16]" "0,1"
bitfld.long 0x0 15. "RAW_STATUS_15,Raw Status (write 1 to set) for intr_in[15]" "0,1"
bitfld.long 0x0 14. "RAW_STATUS_14,Raw Status (write 1 to set) for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "RAW_STATUS_13,Raw Status (write 1 to set) for intr_in[13]" "0,1"
bitfld.long 0x0 12. "RAW_STATUS_12,Raw Status (write 1 to set) for intr_in[12]" "0,1"
bitfld.long 0x0 11. "RAW_STATUS_11,Raw Status (write 1 to set) for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "RAW_STATUS_10,Raw Status (write 1 to set) for intr_in[10]" "0,1"
bitfld.long 0x0 9. "RAW_STATUS_9,Raw Status (write 1 to set) for intr_in[9]" "0,1"
bitfld.long 0x0 8. "RAW_STATUS_8,Raw Status (write 1 to set) for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "RAW_STATUS_7,Raw Status (write 1 to set) for intr_in[7]" "0,1"
bitfld.long 0x0 6. "RAW_STATUS_6,Raw Status (write 1 to set) for intr_in[6]" "0,1"
bitfld.long 0x0 5. "RAW_STATUS_5,Raw Status (write 1 to set) for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "RAW_STATUS_4,Raw Status (write 1 to set) for intr_in[4]" "0,1"
bitfld.long 0x0 3. "RAW_STATUS_3,Raw Status (write 1 to set) for intr_in[3]" "0,1"
bitfld.long 0x0 2. "RAW_STATUS_2,Raw Status (write 1 to set) for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "RAW_STATUS_1,Raw Status (write 1 to set) for intr_in[1]" "0,1"
bitfld.long 0x0 0. "RAW_STATUS_0,Raw Status (write 1 to set) for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG1,"
bitfld.long 0x4 31. "RAW_STATUS_63,Raw Status (write 1 to set) for intr_in[63]" "0,1"
bitfld.long 0x4 30. "RAW_STATUS_62,Raw Status (write 1 to set) for intr_in[62]" "0,1"
bitfld.long 0x4 29. "RAW_STATUS_61,Raw Status (write 1 to set) for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "RAW_STATUS_60,Raw Status (write 1 to set) for intr_in[60]" "0,1"
bitfld.long 0x4 27. "RAW_STATUS_59,Raw Status (write 1 to set) for intr_in[59]" "0,1"
bitfld.long 0x4 26. "RAW_STATUS_58,Raw Status (write 1 to set) for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "RAW_STATUS_57,Raw Status (write 1 to set) for intr_in[57]" "0,1"
bitfld.long 0x4 24. "RAW_STATUS_56,Raw Status (write 1 to set) for intr_in[56]" "0,1"
bitfld.long 0x4 23. "RAW_STATUS_55,Raw Status (write 1 to set) for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "RAW_STATUS_54,Raw Status (write 1 to set) for intr_in[54]" "0,1"
bitfld.long 0x4 21. "RAW_STATUS_53,Raw Status (write 1 to set) for intr_in[53]" "0,1"
bitfld.long 0x4 20. "RAW_STATUS_52,Raw Status (write 1 to set) for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "RAW_STATUS_51,Raw Status (write 1 to set) for intr_in[51]" "0,1"
bitfld.long 0x4 18. "RAW_STATUS_50,Raw Status (write 1 to set) for intr_in[50]" "0,1"
bitfld.long 0x4 17. "RAW_STATUS_49,Raw Status (write 1 to set) for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "RAW_STATUS_48,Raw Status (write 1 to set) for intr_in[48]" "0,1"
bitfld.long 0x4 15. "RAW_STATUS_47,Raw Status (write 1 to set) for intr_in[47]" "0,1"
bitfld.long 0x4 14. "RAW_STATUS_46,Raw Status (write 1 to set) for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "RAW_STATUS_45,Raw Status (write 1 to set) for intr_in[45]" "0,1"
bitfld.long 0x4 12. "RAW_STATUS_44,Raw Status (write 1 to set) for intr_in[44]" "0,1"
bitfld.long 0x4 11. "RAW_STATUS_43,Raw Status (write 1 to set) for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "RAW_STATUS_42,Raw Status (write 1 to set) for intr_in[42]" "0,1"
bitfld.long 0x4 9. "RAW_STATUS_41,Raw Status (write 1 to set) for intr_in[41]" "0,1"
bitfld.long 0x4 8. "RAW_STATUS_40,Raw Status (write 1 to set) for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "RAW_STATUS_39,Raw Status (write 1 to set) for intr_in[39]" "0,1"
bitfld.long 0x4 6. "RAW_STATUS_38,Raw Status (write 1 to set) for intr_in[38]" "0,1"
bitfld.long 0x4 5. "RAW_STATUS_37,Raw Status (write 1 to set) for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "RAW_STATUS_36,Raw Status (write 1 to set) for intr_in[36]" "0,1"
bitfld.long 0x4 3. "RAW_STATUS_35,Raw Status (write 1 to set) for intr_in[35]" "0,1"
bitfld.long 0x4 2. "RAW_STATUS_34,Raw Status (write 1 to set) for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "RAW_STATUS_33,Raw Status (write 1 to set) for intr_in[33]" "0,1"
bitfld.long 0x4 0. "RAW_STATUS_32,Raw Status (write 1 to set) for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG2,"
bitfld.long 0x8 31. "RAW_STATUS_95,Raw Status (write 1 to set) for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "RAW_STATUS_94,Raw Status (write 1 to set) for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "RAW_STATUS_93,Raw Status (write 1 to set) for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "RAW_STATUS_92,Raw Status (write 1 to set) for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "RAW_STATUS_91,Raw Status (write 1 to set) for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "RAW_STATUS_90,Raw Status (write 1 to set) for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "RAW_STATUS_89,Raw Status (write 1 to set) for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "RAW_STATUS_88,Raw Status (write 1 to set) for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "RAW_STATUS_87,Raw Status (write 1 to set) for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "RAW_STATUS_86,Raw Status (write 1 to set) for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "RAW_STATUS_85,Raw Status (write 1 to set) for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "RAW_STATUS_84,Raw Status (write 1 to set) for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "RAW_STATUS_83,Raw Status (write 1 to set) for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "RAW_STATUS_82,Raw Status (write 1 to set) for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "RAW_STATUS_81,Raw Status (write 1 to set) for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "RAW_STATUS_80,Raw Status (write 1 to set) for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "RAW_STATUS_79,Raw Status (write 1 to set) for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "RAW_STATUS_78,Raw Status (write 1 to set) for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "RAW_STATUS_77,Raw Status (write 1 to set) for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "RAW_STATUS_76,Raw Status (write 1 to set) for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "RAW_STATUS_75,Raw Status (write 1 to set) for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "RAW_STATUS_74,Raw Status (write 1 to set) for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "RAW_STATUS_73,Raw Status (write 1 to set) for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "RAW_STATUS_72,Raw Status (write 1 to set) for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "RAW_STATUS_71,Raw Status (write 1 to set) for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "RAW_STATUS_70,Raw Status (write 1 to set) for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "RAW_STATUS_69,Raw Status (write 1 to set) for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "RAW_STATUS_68,Raw Status (write 1 to set) for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "RAW_STATUS_67,Raw Status (write 1 to set) for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "RAW_STATUS_66,Raw Status (write 1 to set) for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "RAW_STATUS_65,Raw Status (write 1 to set) for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "RAW_STATUS_64,Raw Status (write 1 to set) for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG3,"
bitfld.long 0xC 31. "RAW_STATUS_127,Raw Status (write 1 to set) for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "RAW_STATUS_126,Raw Status (write 1 to set) for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "RAW_STATUS_125,Raw Status (write 1 to set) for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "RAW_STATUS_124,Raw Status (write 1 to set) for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "RAW_STATUS_123,Raw Status (write 1 to set) for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "RAW_STATUS_122,Raw Status (write 1 to set) for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "RAW_STATUS_121,Raw Status (write 1 to set) for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "RAW_STATUS_120,Raw Status (write 1 to set) for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "RAW_STATUS_119,Raw Status (write 1 to set) for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "RAW_STATUS_118,Raw Status (write 1 to set) for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "RAW_STATUS_117,Raw Status (write 1 to set) for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "RAW_STATUS_116,Raw Status (write 1 to set) for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "RAW_STATUS_115,Raw Status (write 1 to set) for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "RAW_STATUS_114,Raw Status (write 1 to set) for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "RAW_STATUS_113,Raw Status (write 1 to set) for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "RAW_STATUS_112,Raw Status (write 1 to set) for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "RAW_STATUS_111,Raw Status (write 1 to set) for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "RAW_STATUS_110,Raw Status (write 1 to set) for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "RAW_STATUS_109,Raw Status (write 1 to set) for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "RAW_STATUS_108,Raw Status (write 1 to set) for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "RAW_STATUS_107,Raw Status (write 1 to set) for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "RAW_STATUS_106,Raw Status (write 1 to set) for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "RAW_STATUS_105,Raw Status (write 1 to set) for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "RAW_STATUS_104,Raw Status (write 1 to set) for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "RAW_STATUS_103,Raw Status (write 1 to set) for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "RAW_STATUS_102,Raw Status (write 1 to set) for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "RAW_STATUS_101,Raw Status (write 1 to set) for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "RAW_STATUS_100,Raw Status (write 1 to set) for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "RAW_STATUS_99,Raw Status (write 1 to set) for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "RAW_STATUS_98,Raw Status (write 1 to set) for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "RAW_STATUS_97,Raw Status (write 1 to set) for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "RAW_STATUS_96,Raw Status (write 1 to set) for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG4,"
bitfld.long 0x10 31. "RAW_STATUS_159,Raw Status (write 1 to set) for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "RAW_STATUS_158,Raw Status (write 1 to set) for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "RAW_STATUS_157,Raw Status (write 1 to set) for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "RAW_STATUS_156,Raw Status (write 1 to set) for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "RAW_STATUS_155,Raw Status (write 1 to set) for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "RAW_STATUS_154,Raw Status (write 1 to set) for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "RAW_STATUS_153,Raw Status (write 1 to set) for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "RAW_STATUS_152,Raw Status (write 1 to set) for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "RAW_STATUS_151,Raw Status (write 1 to set) for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "RAW_STATUS_150,Raw Status (write 1 to set) for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "RAW_STATUS_149,Raw Status (write 1 to set) for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "RAW_STATUS_148,Raw Status (write 1 to set) for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "RAW_STATUS_147,Raw Status (write 1 to set) for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "RAW_STATUS_146,Raw Status (write 1 to set) for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "RAW_STATUS_145,Raw Status (write 1 to set) for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "RAW_STATUS_144,Raw Status (write 1 to set) for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "RAW_STATUS_143,Raw Status (write 1 to set) for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "RAW_STATUS_142,Raw Status (write 1 to set) for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "RAW_STATUS_141,Raw Status (write 1 to set) for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "RAW_STATUS_140,Raw Status (write 1 to set) for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "RAW_STATUS_139,Raw Status (write 1 to set) for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "RAW_STATUS_138,Raw Status (write 1 to set) for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "RAW_STATUS_137,Raw Status (write 1 to set) for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "RAW_STATUS_136,Raw Status (write 1 to set) for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "RAW_STATUS_135,Raw Status (write 1 to set) for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "RAW_STATUS_134,Raw Status (write 1 to set) for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "RAW_STATUS_133,Raw Status (write 1 to set) for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "RAW_STATUS_132,Raw Status (write 1 to set) for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "RAW_STATUS_131,Raw Status (write 1 to set) for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "RAW_STATUS_130,Raw Status (write 1 to set) for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "RAW_STATUS_129,Raw Status (write 1 to set) for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "RAW_STATUS_128,Raw Status (write 1 to set) for slv_events_in[64]" "0,1"
group.long 0x280++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG0,"
bitfld.long 0x0 31. "ENA_STATUS_31,Enabled Status for intr_in[31]" "0,1"
bitfld.long 0x0 30. "ENA_STATUS_30,Enabled Status for intr_in[30]" "0,1"
bitfld.long 0x0 29. "ENA_STATUS_29,Enabled Status for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "ENA_STATUS_28,Enabled Status for intr_in[28]" "0,1"
bitfld.long 0x0 27. "ENA_STATUS_27,Enabled Status for intr_in[27]" "0,1"
bitfld.long 0x0 26. "ENA_STATUS_26,Enabled Status for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "ENA_STATUS_25,Enabled Status for intr_in[25]" "0,1"
bitfld.long 0x0 24. "ENA_STATUS_24,Enabled Status for intr_in[24]" "0,1"
bitfld.long 0x0 23. "ENA_STATUS_23,Enabled Status for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "ENA_STATUS_22,Enabled Status for intr_in[22]" "0,1"
bitfld.long 0x0 21. "ENA_STATUS_21,Enabled Status for intr_in[21]" "0,1"
bitfld.long 0x0 20. "ENA_STATUS_20,Enabled Status for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "ENA_STATUS_19,Enabled Status for intr_in[19]" "0,1"
bitfld.long 0x0 18. "ENA_STATUS_18,Enabled Status for intr_in[18]" "0,1"
bitfld.long 0x0 17. "ENA_STATUS_17,Enabled Status for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "ENA_STATUS_16,Enabled Status for intr_in[16]" "0,1"
bitfld.long 0x0 15. "ENA_STATUS_15,Enabled Status for intr_in[15]" "0,1"
bitfld.long 0x0 14. "ENA_STATUS_14,Enabled Status for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "ENA_STATUS_13,Enabled Status for intr_in[13]" "0,1"
bitfld.long 0x0 12. "ENA_STATUS_12,Enabled Status for intr_in[12]" "0,1"
bitfld.long 0x0 11. "ENA_STATUS_11,Enabled Status for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "ENA_STATUS_10,Enabled Status for intr_in[10]" "0,1"
bitfld.long 0x0 9. "ENA_STATUS_9,Enabled Status for intr_in[9]" "0,1"
bitfld.long 0x0 8. "ENA_STATUS_8,Enabled Status for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "ENA_STATUS_7,Enabled Status for intr_in[7]" "0,1"
bitfld.long 0x0 6. "ENA_STATUS_6,Enabled Status for intr_in[6]" "0,1"
bitfld.long 0x0 5. "ENA_STATUS_5,Enabled Status for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "ENA_STATUS_4,Enabled Status for intr_in[4]" "0,1"
bitfld.long 0x0 3. "ENA_STATUS_3,Enabled Status for intr_in[3]" "0,1"
bitfld.long 0x0 2. "ENA_STATUS_2,Enabled Status for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "ENA_STATUS_1,Enabled Status for intr_in[1]" "0,1"
bitfld.long 0x0 0. "ENA_STATUS_0,Enabled Status for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG1,"
bitfld.long 0x4 31. "ENA_STATUS_63,Enabled Status for intr_in[63]" "0,1"
bitfld.long 0x4 30. "ENA_STATUS_62,Enabled Status for intr_in[62]" "0,1"
bitfld.long 0x4 29. "ENA_STATUS_61,Enabled Status for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "ENA_STATUS_60,Enabled Status for intr_in[60]" "0,1"
bitfld.long 0x4 27. "ENA_STATUS_59,Enabled Status for intr_in[59]" "0,1"
bitfld.long 0x4 26. "ENA_STATUS_58,Enabled Status for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "ENA_STATUS_57,Enabled Status for intr_in[57]" "0,1"
bitfld.long 0x4 24. "ENA_STATUS_56,Enabled Status for intr_in[56]" "0,1"
bitfld.long 0x4 23. "ENA_STATUS_55,Enabled Status for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "ENA_STATUS_54,Enabled Status for intr_in[54]" "0,1"
bitfld.long 0x4 21. "ENA_STATUS_53,Enabled Status for intr_in[53]" "0,1"
bitfld.long 0x4 20. "ENA_STATUS_52,Enabled Status for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "ENA_STATUS_51,Enabled Status for intr_in[51]" "0,1"
bitfld.long 0x4 18. "ENA_STATUS_50,Enabled Status for intr_in[50]" "0,1"
bitfld.long 0x4 17. "ENA_STATUS_49,Enabled Status for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "ENA_STATUS_48,Enabled Status for intr_in[48]" "0,1"
bitfld.long 0x4 15. "ENA_STATUS_47,Enabled Status for intr_in[47]" "0,1"
bitfld.long 0x4 14. "ENA_STATUS_46,Enabled Status for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "ENA_STATUS_45,Enabled Status for intr_in[45]" "0,1"
bitfld.long 0x4 12. "ENA_STATUS_44,Enabled Status for intr_in[44]" "0,1"
bitfld.long 0x4 11. "ENA_STATUS_43,Enabled Status for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "ENA_STATUS_42,Enabled Status for intr_in[42]" "0,1"
bitfld.long 0x4 9. "ENA_STATUS_41,Enabled Status for intr_in[41]" "0,1"
bitfld.long 0x4 8. "ENA_STATUS_40,Enabled Status for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "ENA_STATUS_39,Enabled Status for intr_in[39]" "0,1"
bitfld.long 0x4 6. "ENA_STATUS_38,Enabled Status for intr_in[38]" "0,1"
bitfld.long 0x4 5. "ENA_STATUS_37,Enabled Status for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "ENA_STATUS_36,Enabled Status for intr_in[36]" "0,1"
bitfld.long 0x4 3. "ENA_STATUS_35,Enabled Status for intr_in[35]" "0,1"
bitfld.long 0x4 2. "ENA_STATUS_34,Enabled Status for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "ENA_STATUS_33,Enabled Status for intr_in[33]" "0,1"
bitfld.long 0x4 0. "ENA_STATUS_32,Enabled Status for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG2,"
bitfld.long 0x8 31. "ENA_STATUS_95,Enabled Status for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "ENA_STATUS_94,Enabled Status for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "ENA_STATUS_93,Enabled Status for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "ENA_STATUS_92,Enabled Status for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "ENA_STATUS_91,Enabled Status for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "ENA_STATUS_90,Enabled Status for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "ENA_STATUS_89,Enabled Status for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "ENA_STATUS_88,Enabled Status for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "ENA_STATUS_87,Enabled Status for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "ENA_STATUS_86,Enabled Status for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "ENA_STATUS_85,Enabled Status for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "ENA_STATUS_84,Enabled Status for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "ENA_STATUS_83,Enabled Status for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "ENA_STATUS_82,Enabled Status for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "ENA_STATUS_81,Enabled Status for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "ENA_STATUS_80,Enabled Status for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "ENA_STATUS_79,Enabled Status for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "ENA_STATUS_78,Enabled Status for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "ENA_STATUS_77,Enabled Status for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "ENA_STATUS_76,Enabled Status for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "ENA_STATUS_75,Enabled Status for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "ENA_STATUS_74,Enabled Status for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "ENA_STATUS_73,Enabled Status for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "ENA_STATUS_72,Enabled Status for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "ENA_STATUS_71,Enabled Status for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "ENA_STATUS_70,Enabled Status for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "ENA_STATUS_69,Enabled Status for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "ENA_STATUS_68,Enabled Status for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "ENA_STATUS_67,Enabled Status for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "ENA_STATUS_66,Enabled Status for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "ENA_STATUS_65,Enabled Status for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "ENA_STATUS_64,Enabled Status for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG3,"
bitfld.long 0xC 31. "ENA_STATUS_127,Enabled Status for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "ENA_STATUS_126,Enabled Status for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "ENA_STATUS_125,Enabled Status for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "ENA_STATUS_124,Enabled Status for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "ENA_STATUS_123,Enabled Status for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "ENA_STATUS_122,Enabled Status for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "ENA_STATUS_121,Enabled Status for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "ENA_STATUS_120,Enabled Status for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "ENA_STATUS_119,Enabled Status for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "ENA_STATUS_118,Enabled Status for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "ENA_STATUS_117,Enabled Status for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "ENA_STATUS_116,Enabled Status for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "ENA_STATUS_115,Enabled Status for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "ENA_STATUS_114,Enabled Status for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "ENA_STATUS_113,Enabled Status for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "ENA_STATUS_112,Enabled Status for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "ENA_STATUS_111,Enabled Status for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "ENA_STATUS_110,Enabled Status for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "ENA_STATUS_109,Enabled Status for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "ENA_STATUS_108,Enabled Status for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "ENA_STATUS_107,Enabled Status for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "ENA_STATUS_106,Enabled Status for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "ENA_STATUS_105,Enabled Status for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "ENA_STATUS_104,Enabled Status for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "ENA_STATUS_103,Enabled Status for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "ENA_STATUS_102,Enabled Status for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "ENA_STATUS_101,Enabled Status for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "ENA_STATUS_100,Enabled Status for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "ENA_STATUS_99,Enabled Status for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "ENA_STATUS_98,Enabled Status for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "ENA_STATUS_97,Enabled Status for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "ENA_STATUS_96,Enabled Status for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG4,"
bitfld.long 0x10 31. "ENA_STATUS_159,Enabled Status for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENA_STATUS_158,Enabled Status for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENA_STATUS_157,Enabled Status for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "ENA_STATUS_156,Enabled Status for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "ENA_STATUS_155,Enabled Status for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENA_STATUS_154,Enabled Status for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "ENA_STATUS_153,Enabled Status for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENA_STATUS_152,Enabled Status for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "ENA_STATUS_151,Enabled Status for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "ENA_STATUS_150,Enabled Status for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENA_STATUS_149,Enabled Status for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENA_STATUS_148,Enabled Status for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENA_STATUS_147,Enabled Status for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENA_STATUS_146,Enabled Status for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENA_STATUS_145,Enabled Status for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "ENA_STATUS_144,Enabled Status for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "ENA_STATUS_143,Enabled Status for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENA_STATUS_142,Enabled Status for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "ENA_STATUS_141,Enabled Status for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENA_STATUS_140,Enabled Status for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "ENA_STATUS_139,Enabled Status for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "ENA_STATUS_138,Enabled Status for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENA_STATUS_137,Enabled Status for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENA_STATUS_136,Enabled Status for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENA_STATUS_135,Enabled Status for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENA_STATUS_134,Enabled Status for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENA_STATUS_133,Enabled Status for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "ENA_STATUS_132,Enabled Status for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "ENA_STATUS_131,Enabled Status for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENA_STATUS_130,Enabled Status for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "ENA_STATUS_129,Enabled Status for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENA_STATUS_128,Enabled Status for slv_events_in[64]" "0,1"
group.long 0x300++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG0,"
bitfld.long 0x0 31. "ENABLE_31,Enable (set) for intr_in[31]" "0,1"
bitfld.long 0x0 30. "ENABLE_30,Enable (set) for intr_in[30]" "0,1"
bitfld.long 0x0 29. "ENABLE_29,Enable (set) for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "ENABLE_28,Enable (set) for intr_in[28]" "0,1"
bitfld.long 0x0 27. "ENABLE_27,Enable (set) for intr_in[27]" "0,1"
bitfld.long 0x0 26. "ENABLE_26,Enable (set) for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "ENABLE_25,Enable (set) for intr_in[25]" "0,1"
bitfld.long 0x0 24. "ENABLE_24,Enable (set) for intr_in[24]" "0,1"
bitfld.long 0x0 23. "ENABLE_23,Enable (set) for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "ENABLE_22,Enable (set) for intr_in[22]" "0,1"
bitfld.long 0x0 21. "ENABLE_21,Enable (set) for intr_in[21]" "0,1"
bitfld.long 0x0 20. "ENABLE_20,Enable (set) for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "ENABLE_19,Enable (set) for intr_in[19]" "0,1"
bitfld.long 0x0 18. "ENABLE_18,Enable (set) for intr_in[18]" "0,1"
bitfld.long 0x0 17. "ENABLE_17,Enable (set) for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "ENABLE_16,Enable (set) for intr_in[16]" "0,1"
bitfld.long 0x0 15. "ENABLE_15,Enable (set) for intr_in[15]" "0,1"
bitfld.long 0x0 14. "ENABLE_14,Enable (set) for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "ENABLE_13,Enable (set) for intr_in[13]" "0,1"
bitfld.long 0x0 12. "ENABLE_12,Enable (set) for intr_in[12]" "0,1"
bitfld.long 0x0 11. "ENABLE_11,Enable (set) for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "ENABLE_10,Enable (set) for intr_in[10]" "0,1"
bitfld.long 0x0 9. "ENABLE_9,Enable (set) for intr_in[9]" "0,1"
bitfld.long 0x0 8. "ENABLE_8,Enable (set) for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "ENABLE_7,Enable (set) for intr_in[7]" "0,1"
bitfld.long 0x0 6. "ENABLE_6,Enable (set) for intr_in[6]" "0,1"
bitfld.long 0x0 5. "ENABLE_5,Enable (set) for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "ENABLE_4,Enable (set) for intr_in[4]" "0,1"
bitfld.long 0x0 3. "ENABLE_3,Enable (set) for intr_in[3]" "0,1"
bitfld.long 0x0 2. "ENABLE_2,Enable (set) for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_1,Enable (set) for intr_in[1]" "0,1"
bitfld.long 0x0 0. "ENABLE_0,Enable (set) for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG1,"
bitfld.long 0x4 31. "ENABLE_63,Enable (set) for intr_in[63]" "0,1"
bitfld.long 0x4 30. "ENABLE_62,Enable (set) for intr_in[62]" "0,1"
bitfld.long 0x4 29. "ENABLE_61,Enable (set) for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "ENABLE_60,Enable (set) for intr_in[60]" "0,1"
bitfld.long 0x4 27. "ENABLE_59,Enable (set) for intr_in[59]" "0,1"
bitfld.long 0x4 26. "ENABLE_58,Enable (set) for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "ENABLE_57,Enable (set) for intr_in[57]" "0,1"
bitfld.long 0x4 24. "ENABLE_56,Enable (set) for intr_in[56]" "0,1"
bitfld.long 0x4 23. "ENABLE_55,Enable (set) for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "ENABLE_54,Enable (set) for intr_in[54]" "0,1"
bitfld.long 0x4 21. "ENABLE_53,Enable (set) for intr_in[53]" "0,1"
bitfld.long 0x4 20. "ENABLE_52,Enable (set) for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "ENABLE_51,Enable (set) for intr_in[51]" "0,1"
bitfld.long 0x4 18. "ENABLE_50,Enable (set) for intr_in[50]" "0,1"
bitfld.long 0x4 17. "ENABLE_49,Enable (set) for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "ENABLE_48,Enable (set) for intr_in[48]" "0,1"
bitfld.long 0x4 15. "ENABLE_47,Enable (set) for intr_in[47]" "0,1"
bitfld.long 0x4 14. "ENABLE_46,Enable (set) for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "ENABLE_45,Enable (set) for intr_in[45]" "0,1"
bitfld.long 0x4 12. "ENABLE_44,Enable (set) for intr_in[44]" "0,1"
bitfld.long 0x4 11. "ENABLE_43,Enable (set) for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "ENABLE_42,Enable (set) for intr_in[42]" "0,1"
bitfld.long 0x4 9. "ENABLE_41,Enable (set) for intr_in[41]" "0,1"
bitfld.long 0x4 8. "ENABLE_40,Enable (set) for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "ENABLE_39,Enable (set) for intr_in[39]" "0,1"
bitfld.long 0x4 6. "ENABLE_38,Enable (set) for intr_in[38]" "0,1"
bitfld.long 0x4 5. "ENABLE_37,Enable (set) for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "ENABLE_36,Enable (set) for intr_in[36]" "0,1"
bitfld.long 0x4 3. "ENABLE_35,Enable (set) for intr_in[35]" "0,1"
bitfld.long 0x4 2. "ENABLE_34,Enable (set) for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "ENABLE_33,Enable (set) for intr_in[33]" "0,1"
bitfld.long 0x4 0. "ENABLE_32,Enable (set) for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG2,"
bitfld.long 0x8 31. "ENABLE_95,Enable (set) for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "ENABLE_94,Enable (set) for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "ENABLE_93,Enable (set) for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "ENABLE_92,Enable (set) for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "ENABLE_91,Enable (set) for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "ENABLE_90,Enable (set) for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "ENABLE_89,Enable (set) for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "ENABLE_88,Enable (set) for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "ENABLE_87,Enable (set) for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "ENABLE_86,Enable (set) for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "ENABLE_85,Enable (set) for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "ENABLE_84,Enable (set) for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "ENABLE_83,Enable (set) for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "ENABLE_82,Enable (set) for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "ENABLE_81,Enable (set) for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "ENABLE_80,Enable (set) for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "ENABLE_79,Enable (set) for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "ENABLE_78,Enable (set) for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "ENABLE_77,Enable (set) for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "ENABLE_76,Enable (set) for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "ENABLE_75,Enable (set) for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "ENABLE_74,Enable (set) for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "ENABLE_73,Enable (set) for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "ENABLE_72,Enable (set) for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "ENABLE_71,Enable (set) for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "ENABLE_70,Enable (set) for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "ENABLE_69,Enable (set) for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "ENABLE_68,Enable (set) for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "ENABLE_67,Enable (set) for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "ENABLE_66,Enable (set) for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "ENABLE_65,Enable (set) for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "ENABLE_64,Enable (set) for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG3,"
bitfld.long 0xC 31. "ENABLE_127,Enable (set) for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "ENABLE_126,Enable (set) for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "ENABLE_125,Enable (set) for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "ENABLE_124,Enable (set) for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "ENABLE_123,Enable (set) for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "ENABLE_122,Enable (set) for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "ENABLE_121,Enable (set) for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "ENABLE_120,Enable (set) for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "ENABLE_119,Enable (set) for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "ENABLE_118,Enable (set) for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "ENABLE_117,Enable (set) for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "ENABLE_116,Enable (set) for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "ENABLE_115,Enable (set) for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "ENABLE_114,Enable (set) for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "ENABLE_113,Enable (set) for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "ENABLE_112,Enable (set) for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "ENABLE_111,Enable (set) for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "ENABLE_110,Enable (set) for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "ENABLE_109,Enable (set) for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "ENABLE_108,Enable (set) for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "ENABLE_107,Enable (set) for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "ENABLE_106,Enable (set) for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "ENABLE_105,Enable (set) for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "ENABLE_104,Enable (set) for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "ENABLE_103,Enable (set) for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "ENABLE_102,Enable (set) for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "ENABLE_101,Enable (set) for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "ENABLE_100,Enable (set) for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "ENABLE_99,Enable (set) for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "ENABLE_98,Enable (set) for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "ENABLE_97,Enable (set) for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "ENABLE_96,Enable (set) for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG4,"
bitfld.long 0x10 31. "ENABLE_159,Enable (set) for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENABLE_158,Enable (set) for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENABLE_157,Enable (set) for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_156,Enable (set) for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "ENABLE_155,Enable (set) for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENABLE_154,Enable (set) for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_153,Enable (set) for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENABLE_152,Enable (set) for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "ENABLE_151,Enable (set) for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_150,Enable (set) for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENABLE_149,Enable (set) for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENABLE_148,Enable (set) for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_147,Enable (set) for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENABLE_146,Enable (set) for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENABLE_145,Enable (set) for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_144,Enable (set) for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "ENABLE_143,Enable (set) for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENABLE_142,Enable (set) for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_141,Enable (set) for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENABLE_140,Enable (set) for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "ENABLE_139,Enable (set) for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_138,Enable (set) for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENABLE_137,Enable (set) for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENABLE_136,Enable (set) for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_135,Enable (set) for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENABLE_134,Enable (set) for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENABLE_133,Enable (set) for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_132,Enable (set) for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "ENABLE_131,Enable (set) for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENABLE_130,Enable (set) for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_129,Enable (set) for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENABLE_128,Enable (set) for slv_events_in[64]" "0,1"
group.long 0x380++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG0,"
bitfld.long 0x0 31. "ENABLE_31_CLR,Enable clear for intr_in[31]" "0,1"
bitfld.long 0x0 30. "ENABLE_30_CLR,Enable clear for intr_in[30]" "0,1"
bitfld.long 0x0 29. "ENABLE_29_CLR,Enable clear for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "ENABLE_28_CLR,Enable clear for intr_in[28]" "0,1"
bitfld.long 0x0 27. "ENABLE_27_CLR,Enable clear for intr_in[27]" "0,1"
bitfld.long 0x0 26. "ENABLE_26_CLR,Enable clear for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "ENABLE_25_CLR,Enable clear for intr_in[25]" "0,1"
bitfld.long 0x0 24. "ENABLE_24_CLR,Enable clear for intr_in[24]" "0,1"
bitfld.long 0x0 23. "ENABLE_23_CLR,Enable clear for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "ENABLE_22_CLR,Enable clear for intr_in[22]" "0,1"
bitfld.long 0x0 21. "ENABLE_21_CLR,Enable clear for intr_in[21]" "0,1"
bitfld.long 0x0 20. "ENABLE_20_CLR,Enable clear for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "ENABLE_19_CLR,Enable clear for intr_in[19]" "0,1"
bitfld.long 0x0 18. "ENABLE_18_CLR,Enable clear for intr_in[18]" "0,1"
bitfld.long 0x0 17. "ENABLE_17_CLR,Enable clear for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "ENABLE_16_CLR,Enable clear for intr_in[16]" "0,1"
bitfld.long 0x0 15. "ENABLE_15_CLR,Enable clear for intr_in[15]" "0,1"
bitfld.long 0x0 14. "ENABLE_14_CLR,Enable clear for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "ENABLE_13_CLR,Enable clear for intr_in[13]" "0,1"
bitfld.long 0x0 12. "ENABLE_12_CLR,Enable clear for intr_in[12]" "0,1"
bitfld.long 0x0 11. "ENABLE_11_CLR,Enable clear for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "ENABLE_10_CLR,Enable clear for intr_in[10]" "0,1"
bitfld.long 0x0 9. "ENABLE_9_CLR,Enable clear for intr_in[9]" "0,1"
bitfld.long 0x0 8. "ENABLE_8_CLR,Enable clear for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "ENABLE_7_CLR,Enable clear for intr_in[7]" "0,1"
bitfld.long 0x0 6. "ENABLE_6_CLR,Enable clear for intr_in[6]" "0,1"
bitfld.long 0x0 5. "ENABLE_5_CLR,Enable clear for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "ENABLE_4_CLR,Enable clear for intr_in[4]" "0,1"
bitfld.long 0x0 3. "ENABLE_3_CLR,Enable clear for intr_in[3]" "0,1"
bitfld.long 0x0 2. "ENABLE_2_CLR,Enable clear for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_1_CLR,Enable clear for intr_in[1]" "0,1"
bitfld.long 0x0 0. "ENABLE_0_CLR,Enable clear for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG1,"
bitfld.long 0x4 31. "ENABLE_63_CLR,Enable clear for intr_in[63]" "0,1"
bitfld.long 0x4 30. "ENABLE_62_CLR,Enable clear for intr_in[62]" "0,1"
bitfld.long 0x4 29. "ENABLE_61_CLR,Enable clear for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "ENABLE_60_CLR,Enable clear for intr_in[60]" "0,1"
bitfld.long 0x4 27. "ENABLE_59_CLR,Enable clear for intr_in[59]" "0,1"
bitfld.long 0x4 26. "ENABLE_58_CLR,Enable clear for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "ENABLE_57_CLR,Enable clear for intr_in[57]" "0,1"
bitfld.long 0x4 24. "ENABLE_56_CLR,Enable clear for intr_in[56]" "0,1"
bitfld.long 0x4 23. "ENABLE_55_CLR,Enable clear for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "ENABLE_54_CLR,Enable clear for intr_in[54]" "0,1"
bitfld.long 0x4 21. "ENABLE_53_CLR,Enable clear for intr_in[53]" "0,1"
bitfld.long 0x4 20. "ENABLE_52_CLR,Enable clear for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "ENABLE_51_CLR,Enable clear for intr_in[51]" "0,1"
bitfld.long 0x4 18. "ENABLE_50_CLR,Enable clear for intr_in[50]" "0,1"
bitfld.long 0x4 17. "ENABLE_49_CLR,Enable clear for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "ENABLE_48_CLR,Enable clear for intr_in[48]" "0,1"
bitfld.long 0x4 15. "ENABLE_47_CLR,Enable clear for intr_in[47]" "0,1"
bitfld.long 0x4 14. "ENABLE_46_CLR,Enable clear for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "ENABLE_45_CLR,Enable clear for intr_in[45]" "0,1"
bitfld.long 0x4 12. "ENABLE_44_CLR,Enable clear for intr_in[44]" "0,1"
bitfld.long 0x4 11. "ENABLE_43_CLR,Enable clear for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "ENABLE_42_CLR,Enable clear for intr_in[42]" "0,1"
bitfld.long 0x4 9. "ENABLE_41_CLR,Enable clear for intr_in[41]" "0,1"
bitfld.long 0x4 8. "ENABLE_40_CLR,Enable clear for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "ENABLE_39_CLR,Enable clear for intr_in[39]" "0,1"
bitfld.long 0x4 6. "ENABLE_38_CLR,Enable clear for intr_in[38]" "0,1"
bitfld.long 0x4 5. "ENABLE_37_CLR,Enable clear for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "ENABLE_36_CLR,Enable clear for intr_in[36]" "0,1"
bitfld.long 0x4 3. "ENABLE_35_CLR,Enable clear for intr_in[35]" "0,1"
bitfld.long 0x4 2. "ENABLE_34_CLR,Enable clear for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "ENABLE_33_CLR,Enable clear for intr_in[33]" "0,1"
bitfld.long 0x4 0. "ENABLE_32_CLR,Enable clear for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG2,"
bitfld.long 0x8 31. "ENABLE_95_CLR,Enable clear for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "ENABLE_94_CLR,Enable clear for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "ENABLE_93_CLR,Enable clear for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "ENABLE_92_CLR,Enable clear for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "ENABLE_91_CLR,Enable clear for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "ENABLE_90_CLR,Enable clear for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "ENABLE_89_CLR,Enable clear for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "ENABLE_88_CLR,Enable clear for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "ENABLE_87_CLR,Enable clear for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "ENABLE_86_CLR,Enable clear for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "ENABLE_85_CLR,Enable clear for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "ENABLE_84_CLR,Enable clear for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "ENABLE_83_CLR,Enable clear for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "ENABLE_82_CLR,Enable clear for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "ENABLE_81_CLR,Enable clear for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "ENABLE_80_CLR,Enable clear for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "ENABLE_79_CLR,Enable clear for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "ENABLE_78_CLR,Enable clear for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "ENABLE_77_CLR,Enable clear for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "ENABLE_76_CLR,Enable clear for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "ENABLE_75_CLR,Enable clear for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "ENABLE_74_CLR,Enable clear for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "ENABLE_73_CLR,Enable clear for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "ENABLE_72_CLR,Enable clear for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "ENABLE_71_CLR,Enable clear for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "ENABLE_70_CLR,Enable clear for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "ENABLE_69_CLR,Enable clear for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "ENABLE_68_CLR,Enable clear for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "ENABLE_67_CLR,Enable clear for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "ENABLE_66_CLR,Enable clear for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "ENABLE_65_CLR,Enable clear for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "ENABLE_64_CLR,Enable clear for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG3,"
bitfld.long 0xC 31. "ENABLE_127_CLR,Enable clear for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "ENABLE_126_CLR,Enable clear for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "ENABLE_125_CLR,Enable clear for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "ENABLE_124_CLR,Enable clear for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "ENABLE_123_CLR,Enable clear for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "ENABLE_122_CLR,Enable clear for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "ENABLE_121_CLR,Enable clear for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "ENABLE_120_CLR,Enable clear for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "ENABLE_119_CLR,Enable clear for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "ENABLE_118_CLR,Enable clear for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "ENABLE_117_CLR,Enable clear for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "ENABLE_116_CLR,Enable clear for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "ENABLE_115_CLR,Enable clear for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "ENABLE_114_CLR,Enable clear for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "ENABLE_113_CLR,Enable clear for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "ENABLE_112_CLR,Enable clear for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "ENABLE_111_CLR,Enable clear for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "ENABLE_110_CLR,Enable clear for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "ENABLE_109_CLR,Enable clear for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "ENABLE_108_CLR,Enable clear for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "ENABLE_107_CLR,Enable clear for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "ENABLE_106_CLR,Enable clear for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "ENABLE_105_CLR,Enable clear for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "ENABLE_104_CLR,Enable clear for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "ENABLE_103_CLR,Enable clear for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "ENABLE_102_CLR,Enable clear for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "ENABLE_101_CLR,Enable clear for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "ENABLE_100_CLR,Enable clear for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "ENABLE_99_CLR,Enable clear for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "ENABLE_98_CLR,Enable clear for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "ENABLE_97_CLR,Enable clear for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "ENABLE_96_CLR,Enable clear for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG4,"
bitfld.long 0x10 31. "ENABLE_159_CLR,Enable clear for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENABLE_158_CLR,Enable clear for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENABLE_157_CLR,Enable clear for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_156_CLR,Enable clear for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "ENABLE_155_CLR,Enable clear for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENABLE_154_CLR,Enable clear for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_153_CLR,Enable clear for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENABLE_152_CLR,Enable clear for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "ENABLE_151_CLR,Enable clear for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_150_CLR,Enable clear for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENABLE_149_CLR,Enable clear for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENABLE_148_CLR,Enable clear for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_147_CLR,Enable clear for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENABLE_146_CLR,Enable clear for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENABLE_145_CLR,Enable clear for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_144_CLR,Enable clear for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "ENABLE_143_CLR,Enable clear for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENABLE_142_CLR,Enable clear for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_141_CLR,Enable clear for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENABLE_140_CLR,Enable clear for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "ENABLE_139_CLR,Enable clear for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_138_CLR,Enable clear for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENABLE_137_CLR,Enable clear for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENABLE_136_CLR,Enable clear for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_135_CLR,Enable clear for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENABLE_134_CLR,Enable clear for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENABLE_133_CLR,Enable clear for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_132_CLR,Enable clear for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "ENABLE_131_CLR,Enable clear for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENABLE_130_CLR,Enable clear for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_129_CLR,Enable clear for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENABLE_128_CLR,Enable clear for slv_events_in[64]" "0,1"
group.long 0x400++0x9F
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG0,"
hexmask.long.byte 0x0 24.--28. 1. "CH_MAP_3,Interrupt Channel Map for intr_in[3]"
hexmask.long.byte 0x0 16.--20. 1. "CH_MAP_2,Interrupt Channel Map for intr_in[2]"
hexmask.long.byte 0x0 8.--12. 1. "CH_MAP_1,Interrupt Channel Map for intr_in[1]"
newline
hexmask.long.byte 0x0 0.--4. 1. "CH_MAP_0,Interrupt Channel Map for intr_in[0]"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG1,"
hexmask.long.byte 0x4 24.--28. 1. "CH_MAP_7,Interrupt Channel Map for intr_in[7]"
hexmask.long.byte 0x4 16.--20. 1. "CH_MAP_6,Interrupt Channel Map for intr_in[6]"
hexmask.long.byte 0x4 8.--12. 1. "CH_MAP_5,Interrupt Channel Map for intr_in[5]"
newline
hexmask.long.byte 0x4 0.--4. 1. "CH_MAP_4,Interrupt Channel Map for intr_in[4]"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG2,"
hexmask.long.byte 0x8 24.--28. 1. "CH_MAP_11,Interrupt Channel Map for intr_in[11]"
hexmask.long.byte 0x8 16.--20. 1. "CH_MAP_10,Interrupt Channel Map for intr_in[10]"
hexmask.long.byte 0x8 8.--12. 1. "CH_MAP_9,Interrupt Channel Map for intr_in[9]"
newline
hexmask.long.byte 0x8 0.--4. 1. "CH_MAP_8,Interrupt Channel Map for intr_in[8]"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG3,"
hexmask.long.byte 0xC 24.--28. 1. "CH_MAP_15,Interrupt Channel Map for intr_in[15]"
hexmask.long.byte 0xC 16.--20. 1. "CH_MAP_14,Interrupt Channel Map for intr_in[14]"
hexmask.long.byte 0xC 8.--12. 1. "CH_MAP_13,Interrupt Channel Map for intr_in[13]"
newline
hexmask.long.byte 0xC 0.--4. 1. "CH_MAP_12,Interrupt Channel Map for intr_in[12]"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG4,"
hexmask.long.byte 0x10 24.--28. 1. "CH_MAP_19,Interrupt Channel Map for intr_in[19]"
hexmask.long.byte 0x10 16.--20. 1. "CH_MAP_18,Interrupt Channel Map for intr_in[18]"
hexmask.long.byte 0x10 8.--12. 1. "CH_MAP_17,Interrupt Channel Map for intr_in[17]"
newline
hexmask.long.byte 0x10 0.--4. 1. "CH_MAP_16,Interrupt Channel Map for intr_in[16]"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG5,"
hexmask.long.byte 0x14 24.--28. 1. "CH_MAP_23,Interrupt Channel Map for intr_in[23]"
hexmask.long.byte 0x14 16.--20. 1. "CH_MAP_22,Interrupt Channel Map for intr_in[22]"
hexmask.long.byte 0x14 8.--12. 1. "CH_MAP_21,Interrupt Channel Map for intr_in[21]"
newline
hexmask.long.byte 0x14 0.--4. 1. "CH_MAP_20,Interrupt Channel Map for intr_in[20]"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG6,"
hexmask.long.byte 0x18 24.--28. 1. "CH_MAP_27,Interrupt Channel Map for intr_in[27]"
hexmask.long.byte 0x18 16.--20. 1. "CH_MAP_26,Interrupt Channel Map for intr_in[26]"
hexmask.long.byte 0x18 8.--12. 1. "CH_MAP_25,Interrupt Channel Map for intr_in[25]"
newline
hexmask.long.byte 0x18 0.--4. 1. "CH_MAP_24,Interrupt Channel Map for intr_in[24]"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG7,"
hexmask.long.byte 0x1C 24.--28. 1. "CH_MAP_31,Interrupt Channel Map for intr_in[31]"
hexmask.long.byte 0x1C 16.--20. 1. "CH_MAP_30,Interrupt Channel Map for intr_in[30]"
hexmask.long.byte 0x1C 8.--12. 1. "CH_MAP_29,Interrupt Channel Map for intr_in[29]"
newline
hexmask.long.byte 0x1C 0.--4. 1. "CH_MAP_28,Interrupt Channel Map for intr_in[28]"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG8,"
hexmask.long.byte 0x20 24.--28. 1. "CH_MAP_35,Interrupt Channel Map for intr_in[35]"
hexmask.long.byte 0x20 16.--20. 1. "CH_MAP_34,Interrupt Channel Map for intr_in[34]"
hexmask.long.byte 0x20 8.--12. 1. "CH_MAP_33,Interrupt Channel Map for intr_in[33]"
newline
hexmask.long.byte 0x20 0.--4. 1. "CH_MAP_32,Interrupt Channel Map for intr_in[32]"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG9,"
hexmask.long.byte 0x24 24.--28. 1. "CH_MAP_39,Interrupt Channel Map for intr_in[39]"
hexmask.long.byte 0x24 16.--20. 1. "CH_MAP_38,Interrupt Channel Map for intr_in[38]"
hexmask.long.byte 0x24 8.--12. 1. "CH_MAP_37,Interrupt Channel Map for intr_in[37]"
newline
hexmask.long.byte 0x24 0.--4. 1. "CH_MAP_36,Interrupt Channel Map for intr_in[36]"
line.long 0x28 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG10,"
hexmask.long.byte 0x28 24.--28. 1. "CH_MAP_43,Interrupt Channel Map for intr_in[43]"
hexmask.long.byte 0x28 16.--20. 1. "CH_MAP_42,Interrupt Channel Map for intr_in[42]"
hexmask.long.byte 0x28 8.--12. 1. "CH_MAP_41,Interrupt Channel Map for intr_in[41]"
newline
hexmask.long.byte 0x28 0.--4. 1. "CH_MAP_40,Interrupt Channel Map for intr_in[40]"
line.long 0x2C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG11,"
hexmask.long.byte 0x2C 24.--28. 1. "CH_MAP_47,Interrupt Channel Map for intr_in[47]"
hexmask.long.byte 0x2C 16.--20. 1. "CH_MAP_46,Interrupt Channel Map for intr_in[46]"
hexmask.long.byte 0x2C 8.--12. 1. "CH_MAP_45,Interrupt Channel Map for intr_in[45]"
newline
hexmask.long.byte 0x2C 0.--4. 1. "CH_MAP_44,Interrupt Channel Map for intr_in[44]"
line.long 0x30 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG12,"
hexmask.long.byte 0x30 24.--28. 1. "CH_MAP_51,Interrupt Channel Map for intr_in[51]"
hexmask.long.byte 0x30 16.--20. 1. "CH_MAP_50,Interrupt Channel Map for intr_in[50]"
hexmask.long.byte 0x30 8.--12. 1. "CH_MAP_49,Interrupt Channel Map for intr_in[49]"
newline
hexmask.long.byte 0x30 0.--4. 1. "CH_MAP_48,Interrupt Channel Map for intr_in[48]"
line.long 0x34 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG13,"
hexmask.long.byte 0x34 24.--28. 1. "CH_MAP_55,Interrupt Channel Map for intr_in[55]"
hexmask.long.byte 0x34 16.--20. 1. "CH_MAP_54,Interrupt Channel Map for intr_in[54]"
hexmask.long.byte 0x34 8.--12. 1. "CH_MAP_53,Interrupt Channel Map for intr_in[53]"
newline
hexmask.long.byte 0x34 0.--4. 1. "CH_MAP_52,Interrupt Channel Map for intr_in[52]"
line.long 0x38 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG14,"
hexmask.long.byte 0x38 24.--28. 1. "CH_MAP_59,Interrupt Channel Map for intr_in[59]"
hexmask.long.byte 0x38 16.--20. 1. "CH_MAP_58,Interrupt Channel Map for intr_in[58]"
hexmask.long.byte 0x38 8.--12. 1. "CH_MAP_57,Interrupt Channel Map for intr_in[57]"
newline
hexmask.long.byte 0x38 0.--4. 1. "CH_MAP_56,Interrupt Channel Map for intr_in[56]"
line.long 0x3C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG15,"
hexmask.long.byte 0x3C 24.--28. 1. "CH_MAP_63,Interrupt Channel Map for intr_in[63]"
hexmask.long.byte 0x3C 16.--20. 1. "CH_MAP_62,Interrupt Channel Map for intr_in[62]"
hexmask.long.byte 0x3C 8.--12. 1. "CH_MAP_61,Interrupt Channel Map for intr_in[61]"
newline
hexmask.long.byte 0x3C 0.--4. 1. "CH_MAP_60,Interrupt Channel Map for intr_in[60]"
line.long 0x40 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG16,"
hexmask.long.byte 0x40 24.--28. 1. "CH_MAP_67,Interrupt Channel Map for slv_events_in[3]"
hexmask.long.byte 0x40 16.--20. 1. "CH_MAP_66,Interrupt Channel Map for slv_events_in[2]"
hexmask.long.byte 0x40 8.--12. 1. "CH_MAP_65,Interrupt Channel Map for slv_events_in[1]"
newline
hexmask.long.byte 0x40 0.--4. 1. "CH_MAP_64,Interrupt Channel Map for slv_events_in[0]"
line.long 0x44 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG17,"
hexmask.long.byte 0x44 24.--28. 1. "CH_MAP_71,Interrupt Channel Map for slv_events_in[7]"
hexmask.long.byte 0x44 16.--20. 1. "CH_MAP_70,Interrupt Channel Map for slv_events_in[6]"
hexmask.long.byte 0x44 8.--12. 1. "CH_MAP_69,Interrupt Channel Map for slv_events_in[5]"
newline
hexmask.long.byte 0x44 0.--4. 1. "CH_MAP_68,Interrupt Channel Map for slv_events_in[4]"
line.long 0x48 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG18,"
hexmask.long.byte 0x48 24.--28. 1. "CH_MAP_75,Interrupt Channel Map for slv_events_in[11]"
hexmask.long.byte 0x48 16.--20. 1. "CH_MAP_74,Interrupt Channel Map for slv_events_in[10]"
hexmask.long.byte 0x48 8.--12. 1. "CH_MAP_73,Interrupt Channel Map for slv_events_in[9]"
newline
hexmask.long.byte 0x48 0.--4. 1. "CH_MAP_72,Interrupt Channel Map for slv_events_in[8]"
line.long 0x4C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG19,"
hexmask.long.byte 0x4C 24.--28. 1. "CH_MAP_79,Interrupt Channel Map for slv_events_in[15]"
hexmask.long.byte 0x4C 16.--20. 1. "CH_MAP_78,Interrupt Channel Map for slv_events_in[14]"
hexmask.long.byte 0x4C 8.--12. 1. "CH_MAP_77,Interrupt Channel Map for slv_events_in[13]"
newline
hexmask.long.byte 0x4C 0.--4. 1. "CH_MAP_76,Interrupt Channel Map for slv_events_in[12]"
line.long 0x50 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG20,"
hexmask.long.byte 0x50 24.--28. 1. "CH_MAP_83,Interrupt Channel Map for slv_events_in[19]"
hexmask.long.byte 0x50 16.--20. 1. "CH_MAP_82,Interrupt Channel Map for slv_events_in[18]"
hexmask.long.byte 0x50 8.--12. 1. "CH_MAP_81,Interrupt Channel Map for slv_events_in[17]"
newline
hexmask.long.byte 0x50 0.--4. 1. "CH_MAP_80,Interrupt Channel Map for slv_events_in[16]"
line.long 0x54 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG21,"
hexmask.long.byte 0x54 24.--28. 1. "CH_MAP_87,Interrupt Channel Map for slv_events_in[23]"
hexmask.long.byte 0x54 16.--20. 1. "CH_MAP_86,Interrupt Channel Map for slv_events_in[22]"
hexmask.long.byte 0x54 8.--12. 1. "CH_MAP_85,Interrupt Channel Map for slv_events_in[21]"
newline
hexmask.long.byte 0x54 0.--4. 1. "CH_MAP_84,Interrupt Channel Map for slv_events_in[20]"
line.long 0x58 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG22,"
hexmask.long.byte 0x58 24.--28. 1. "CH_MAP_91,Interrupt Channel Map for slv_events_in[27]"
hexmask.long.byte 0x58 16.--20. 1. "CH_MAP_90,Interrupt Channel Map for slv_events_in[26]"
hexmask.long.byte 0x58 8.--12. 1. "CH_MAP_89,Interrupt Channel Map for slv_events_in[25]"
newline
hexmask.long.byte 0x58 0.--4. 1. "CH_MAP_88,Interrupt Channel Map for slv_events_in[24]"
line.long 0x5C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG23,"
hexmask.long.byte 0x5C 24.--28. 1. "CH_MAP_95,Interrupt Channel Map for slv_events_in[31]"
hexmask.long.byte 0x5C 16.--20. 1. "CH_MAP_94,Interrupt Channel Map for slv_events_in[30]"
hexmask.long.byte 0x5C 8.--12. 1. "CH_MAP_93,Interrupt Channel Map for slv_events_in[29]"
newline
hexmask.long.byte 0x5C 0.--4. 1. "CH_MAP_92,Interrupt Channel Map for slv_events_in[28]"
line.long 0x60 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG24,"
hexmask.long.byte 0x60 24.--28. 1. "CH_MAP_99,Interrupt Channel Map for slv_events_in[35]"
hexmask.long.byte 0x60 16.--20. 1. "CH_MAP_98,Interrupt Channel Map for slv_events_in[34]"
hexmask.long.byte 0x60 8.--12. 1. "CH_MAP_97,Interrupt Channel Map for slv_events_in[33]"
newline
hexmask.long.byte 0x60 0.--4. 1. "CH_MAP_96,Interrupt Channel Map for slv_events_in[32]"
line.long 0x64 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG25,"
hexmask.long.byte 0x64 24.--28. 1. "CH_MAP_103,Interrupt Channel Map for slv_events_in[39]"
hexmask.long.byte 0x64 16.--20. 1. "CH_MAP_102,Interrupt Channel Map for slv_events_in[38]"
hexmask.long.byte 0x64 8.--12. 1. "CH_MAP_101,Interrupt Channel Map for slv_events_in[37]"
newline
hexmask.long.byte 0x64 0.--4. 1. "CH_MAP_100,Interrupt Channel Map for slv_events_in[36]"
line.long 0x68 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG26,"
hexmask.long.byte 0x68 24.--28. 1. "CH_MAP_107,Interrupt Channel Map for slv_events_in[43]"
hexmask.long.byte 0x68 16.--20. 1. "CH_MAP_106,Interrupt Channel Map for slv_events_in[42]"
hexmask.long.byte 0x68 8.--12. 1. "CH_MAP_105,Interrupt Channel Map for slv_events_in[41]"
newline
hexmask.long.byte 0x68 0.--4. 1. "CH_MAP_104,Interrupt Channel Map for slv_events_in[40]"
line.long 0x6C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG27,"
hexmask.long.byte 0x6C 24.--28. 1. "CH_MAP_111,Interrupt Channel Map for slv_events_in[47]"
hexmask.long.byte 0x6C 16.--20. 1. "CH_MAP_110,Interrupt Channel Map for slv_events_in[46]"
hexmask.long.byte 0x6C 8.--12. 1. "CH_MAP_109,Interrupt Channel Map for slv_events_in[45]"
newline
hexmask.long.byte 0x6C 0.--4. 1. "CH_MAP_108,Interrupt Channel Map for slv_events_in[44]"
line.long 0x70 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG28,"
hexmask.long.byte 0x70 24.--28. 1. "CH_MAP_115,Interrupt Channel Map for slv_events_in[51]"
hexmask.long.byte 0x70 16.--20. 1. "CH_MAP_114,Interrupt Channel Map for slv_events_in[50]"
hexmask.long.byte 0x70 8.--12. 1. "CH_MAP_113,Interrupt Channel Map for slv_events_in[49]"
newline
hexmask.long.byte 0x70 0.--4. 1. "CH_MAP_112,Interrupt Channel Map for slv_events_in[48]"
line.long 0x74 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG29,"
hexmask.long.byte 0x74 24.--28. 1. "CH_MAP_119,Interrupt Channel Map for slv_events_in[55]"
hexmask.long.byte 0x74 16.--20. 1. "CH_MAP_118,Interrupt Channel Map for slv_events_in[54]"
hexmask.long.byte 0x74 8.--12. 1. "CH_MAP_117,Interrupt Channel Map for slv_events_in[53]"
newline
hexmask.long.byte 0x74 0.--4. 1. "CH_MAP_116,Interrupt Channel Map for slv_events_in[52]"
line.long 0x78 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG30,"
hexmask.long.byte 0x78 24.--28. 1. "CH_MAP_123,Interrupt Channel Map for slv_events_in[59]"
hexmask.long.byte 0x78 16.--20. 1. "CH_MAP_122,Interrupt Channel Map for slv_events_in[58]"
hexmask.long.byte 0x78 8.--12. 1. "CH_MAP_121,Interrupt Channel Map for slv_events_in[57]"
newline
hexmask.long.byte 0x78 0.--4. 1. "CH_MAP_120,Interrupt Channel Map for slv_events_in[56]"
line.long 0x7C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG31,"
hexmask.long.byte 0x7C 24.--28. 1. "CH_MAP_127,Interrupt Channel Map for slv_events_in[63]"
hexmask.long.byte 0x7C 16.--20. 1. "CH_MAP_126,Interrupt Channel Map for slv_events_in[62]"
hexmask.long.byte 0x7C 8.--12. 1. "CH_MAP_125,Interrupt Channel Map for slv_events_in[61]"
newline
hexmask.long.byte 0x7C 0.--4. 1. "CH_MAP_124,Interrupt Channel Map for slv_events_in[60]"
line.long 0x80 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG32,"
hexmask.long.byte 0x80 24.--28. 1. "CH_MAP_131,Interrupt Channel Map for slv_events_in[67]"
hexmask.long.byte 0x80 16.--20. 1. "CH_MAP_130,Interrupt Channel Map for slv_events_in[66]"
hexmask.long.byte 0x80 8.--12. 1. "CH_MAP_129,Interrupt Channel Map for slv_events_in[65]"
newline
hexmask.long.byte 0x80 0.--4. 1. "CH_MAP_128,Interrupt Channel Map for slv_events_in[64]"
line.long 0x84 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG33,"
hexmask.long.byte 0x84 24.--28. 1. "CH_MAP_135,Interrupt Channel Map for slv_events_in[71]"
hexmask.long.byte 0x84 16.--20. 1. "CH_MAP_134,Interrupt Channel Map for slv_events_in[70]"
hexmask.long.byte 0x84 8.--12. 1. "CH_MAP_133,Interrupt Channel Map for slv_events_in[69]"
newline
hexmask.long.byte 0x84 0.--4. 1. "CH_MAP_132,Interrupt Channel Map for slv_events_in[68]"
line.long 0x88 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG34,"
hexmask.long.byte 0x88 24.--28. 1. "CH_MAP_139,Interrupt Channel Map for slv_events_in[75]"
hexmask.long.byte 0x88 16.--20. 1. "CH_MAP_138,Interrupt Channel Map for slv_events_in[74]"
hexmask.long.byte 0x88 8.--12. 1. "CH_MAP_137,Interrupt Channel Map for slv_events_in[73]"
newline
hexmask.long.byte 0x88 0.--4. 1. "CH_MAP_136,Interrupt Channel Map for slv_events_in[72]"
line.long 0x8C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG35,"
hexmask.long.byte 0x8C 24.--28. 1. "CH_MAP_143,Interrupt Channel Map for slv_events_in[79]"
hexmask.long.byte 0x8C 16.--20. 1. "CH_MAP_142,Interrupt Channel Map for slv_events_in[78]"
hexmask.long.byte 0x8C 8.--12. 1. "CH_MAP_141,Interrupt Channel Map for slv_events_in[77]"
newline
hexmask.long.byte 0x8C 0.--4. 1. "CH_MAP_140,Interrupt Channel Map for slv_events_in[76]"
line.long 0x90 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG36,"
hexmask.long.byte 0x90 24.--28. 1. "CH_MAP_147,Interrupt Channel Map for slv_events_in[83]"
hexmask.long.byte 0x90 16.--20. 1. "CH_MAP_146,Interrupt Channel Map for slv_events_in[82]"
hexmask.long.byte 0x90 8.--12. 1. "CH_MAP_145,Interrupt Channel Map for slv_events_in[81]"
newline
hexmask.long.byte 0x90 0.--4. 1. "CH_MAP_144,Interrupt Channel Map for slv_events_in[80]"
line.long 0x94 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG37,"
hexmask.long.byte 0x94 24.--28. 1. "CH_MAP_151,Interrupt Channel Map for slv_events_in[87]"
hexmask.long.byte 0x94 16.--20. 1. "CH_MAP_150,Interrupt Channel Map for slv_events_in[86]"
hexmask.long.byte 0x94 8.--12. 1. "CH_MAP_149,Interrupt Channel Map for slv_events_in[85]"
newline
hexmask.long.byte 0x94 0.--4. 1. "CH_MAP_148,Interrupt Channel Map for slv_events_in[84]"
line.long 0x98 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG38,"
hexmask.long.byte 0x98 24.--28. 1. "CH_MAP_155,Interrupt Channel Map for slv_events_in[91]"
hexmask.long.byte 0x98 16.--20. 1. "CH_MAP_154,Interrupt Channel Map for slv_events_in[90]"
hexmask.long.byte 0x98 8.--12. 1. "CH_MAP_153,Interrupt Channel Map for slv_events_in[89]"
newline
hexmask.long.byte 0x98 0.--4. 1. "CH_MAP_152,Interrupt Channel Map for slv_events_in[88]"
line.long 0x9C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG39,"
hexmask.long.byte 0x9C 24.--28. 1. "CH_MAP_159,Interrupt Channel Map for slv_events_in[95]"
hexmask.long.byte 0x9C 16.--20. 1. "CH_MAP_158,Interrupt Channel Map for slv_events_in[94]"
hexmask.long.byte 0x9C 8.--12. 1. "CH_MAP_157,Interrupt Channel Map for slv_events_in[93]"
newline
hexmask.long.byte 0x9C 0.--4. 1. "CH_MAP_156,Interrupt Channel Map for slv_events_in[92]"
group.long 0x800++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG0,"
hexmask.long.byte 0x0 24.--28. 1. "HINT_MAP_3,Host Interrupt Map for Channel 3"
hexmask.long.byte 0x0 16.--20. 1. "HINT_MAP_2,Host Interrupt Map for Channel 2"
hexmask.long.byte 0x0 8.--12. 1. "HINT_MAP_1,Host Interrupt Map for Channel 1"
newline
hexmask.long.byte 0x0 0.--4. 1. "HINT_MAP_0,Host Interrupt Map for Channel 0"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG1,"
hexmask.long.byte 0x4 24.--28. 1. "HINT_MAP_7,Host Interrupt Map for Channel 7"
hexmask.long.byte 0x4 16.--20. 1. "HINT_MAP_6,Host Interrupt Map for Channel 6"
hexmask.long.byte 0x4 8.--12. 1. "HINT_MAP_5,Host Interrupt Map for Channel 5"
newline
hexmask.long.byte 0x4 0.--4. 1. "HINT_MAP_4,Host Interrupt Map for Channel 4"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG2,"
hexmask.long.byte 0x8 24.--28. 1. "HINT_MAP_11,Host Interrupt Map for Channel 11"
hexmask.long.byte 0x8 16.--20. 1. "HINT_MAP_10,Host Interrupt Map for Channel 10"
hexmask.long.byte 0x8 8.--12. 1. "HINT_MAP_9,Host Interrupt Map for Channel 9"
newline
hexmask.long.byte 0x8 0.--4. 1. "HINT_MAP_8,Host Interrupt Map for Channel 8"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG3,"
hexmask.long.byte 0xC 24.--28. 1. "HINT_MAP_15,Host Interrupt Map for Channel 15"
hexmask.long.byte 0xC 16.--20. 1. "HINT_MAP_14,Host Interrupt Map for Channel 14"
hexmask.long.byte 0xC 8.--12. 1. "HINT_MAP_13,Host Interrupt Map for Channel 13"
newline
hexmask.long.byte 0xC 0.--4. 1. "HINT_MAP_12,Host Interrupt Map for Channel 12"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG4,"
hexmask.long.byte 0x10 24.--28. 1. "HINT_MAP_19,Host Interrupt Map for Channel 19"
hexmask.long.byte 0x10 16.--20. 1. "HINT_MAP_18,Host Interrupt Map for Channel 18"
hexmask.long.byte 0x10 8.--12. 1. "HINT_MAP_17,Host Interrupt Map for Channel 17"
newline
hexmask.long.byte 0x10 0.--4. 1. "HINT_MAP_16,Host Interrupt Map for Channel 16"
rgroup.long 0x900++0x4F
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG0,"
bitfld.long 0x0 31. "NONE_HINT_0,No interrupt pending flag" "0,1"
hexmask.long.word 0x0 0.--9. 1. "PRI_HINT_0,Host Int 0 Prioritized Interrupt"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG1,"
bitfld.long 0x4 31. "NONE_HINT_1,No interrupt pending flag" "0,1"
hexmask.long.word 0x4 0.--9. 1. "PRI_HINT_1,Host Int 1 Prioritized Interrupt"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG2,"
bitfld.long 0x8 31. "NONE_HINT_2,No interrupt pending flag" "0,1"
hexmask.long.word 0x8 0.--9. 1. "PRI_HINT_2,Host Int 2 Prioritized Interrupt"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG3,"
bitfld.long 0xC 31. "NONE_HINT_3,No interrupt pending flag" "0,1"
hexmask.long.word 0xC 0.--9. 1. "PRI_HINT_3,Host Int 3 Prioritized Interrupt"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG4,"
bitfld.long 0x10 31. "NONE_HINT_4,No interrupt pending flag" "0,1"
hexmask.long.word 0x10 0.--9. 1. "PRI_HINT_4,Host Int 4 Prioritized Interrupt"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG5,"
bitfld.long 0x14 31. "NONE_HINT_5,No interrupt pending flag" "0,1"
hexmask.long.word 0x14 0.--9. 1. "PRI_HINT_5,Host Int 5 Prioritized Interrupt"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG6,"
bitfld.long 0x18 31. "NONE_HINT_6,No interrupt pending flag" "0,1"
hexmask.long.word 0x18 0.--9. 1. "PRI_HINT_6,Host Int 6 Prioritized Interrupt"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG7,"
bitfld.long 0x1C 31. "NONE_HINT_7,No interrupt pending flag" "0,1"
hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT_7,Host Int 7 Prioritized Interrupt"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG8,"
bitfld.long 0x20 31. "NONE_HINT_8,No interrupt pending flag" "0,1"
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT_8,Host Int 8 Prioritized Interrupt"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG9,"
bitfld.long 0x24 31. "NONE_HINT_9,No interrupt pending flag" "0,1"
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT_9,Host Int 9 Prioritized Interrupt"
line.long 0x28 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG10,"
bitfld.long 0x28 31. "NONE_HINT_10,No interrupt pending flag" "0,1"
hexmask.long.word 0x28 0.--9. 1. "PRI_HINT_10,Host Int 10 Prioritized Interrupt"
line.long 0x2C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG11,"
bitfld.long 0x2C 31. "NONE_HINT_11,No interrupt pending flag" "0,1"
hexmask.long.word 0x2C 0.--9. 1. "PRI_HINT_11,Host Int 11 Prioritized Interrupt"
line.long 0x30 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG12,"
bitfld.long 0x30 31. "NONE_HINT_12,No interrupt pending flag" "0,1"
hexmask.long.word 0x30 0.--9. 1. "PRI_HINT_12,Host Int 12 Prioritized Interrupt"
line.long 0x34 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG13,"
bitfld.long 0x34 31. "NONE_HINT_13,No interrupt pending flag" "0,1"
hexmask.long.word 0x34 0.--9. 1. "PRI_HINT_13,Host Int 13 Prioritized Interrupt"
line.long 0x38 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG14,"
bitfld.long 0x38 31. "NONE_HINT_14,No interrupt pending flag" "0,1"
hexmask.long.word 0x38 0.--9. 1. "PRI_HINT_14,Host Int 14 Prioritized Interrupt"
line.long 0x3C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG15,"
bitfld.long 0x3C 31. "NONE_HINT_15,No interrupt pending flag" "0,1"
hexmask.long.word 0x3C 0.--9. 1. "PRI_HINT_15,Host Int 15 Prioritized Interrupt"
line.long 0x40 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG16,"
bitfld.long 0x40 31. "NONE_HINT_16,No interrupt pending flag" "0,1"
hexmask.long.word 0x40 0.--9. 1. "PRI_HINT_16,Host Int 16 Prioritized Interrupt"
line.long 0x44 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG17,"
bitfld.long 0x44 31. "NONE_HINT_17,No interrupt pending flag" "0,1"
hexmask.long.word 0x44 0.--9. 1. "PRI_HINT_17,Host Int 17 Prioritized Interrupt"
line.long 0x48 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG18,"
bitfld.long 0x48 31. "NONE_HINT_18,No interrupt pending flag" "0,1"
hexmask.long.word 0x48 0.--9. 1. "PRI_HINT_18,Host Int 18 Prioritized Interrupt"
line.long 0x4C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG19,"
bitfld.long 0x4C 31. "NONE_HINT_19,No interrupt pending flag" "0,1"
hexmask.long.word 0x4C 0.--9. 1. "PRI_HINT_19,Host Int 19 Prioritized Interrupt"
group.long 0xD00++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG0,"
bitfld.long 0x0 31. "POLARITY_31,Polarity for intr_in[31] 0=low" "0: low,?"
bitfld.long 0x0 30. "POLARITY_30,Polarity for intr_in[30] 0=low" "0: low,?"
bitfld.long 0x0 29. "POLARITY_29,Polarity for intr_in[29] 0=low" "0: low,?"
newline
bitfld.long 0x0 28. "POLARITY_28,Polarity for intr_in[28] 0=low" "0: low,?"
bitfld.long 0x0 27. "POLARITY_27,Polarity for intr_in[27] 0=low" "0: low,?"
bitfld.long 0x0 26. "POLARITY_26,Polarity for intr_in[26] 0=low" "0: low,?"
newline
bitfld.long 0x0 25. "POLARITY_25,Polarity for intr_in[25] 0=low" "0: low,?"
bitfld.long 0x0 24. "POLARITY_24,Polarity for intr_in[24] 0=low" "0: low,?"
bitfld.long 0x0 23. "POLARITY_23,Polarity for intr_in[23] 0=low" "0: low,?"
newline
bitfld.long 0x0 22. "POLARITY_22,Polarity for intr_in[22] 0=low" "0: low,?"
bitfld.long 0x0 21. "POLARITY_21,Polarity for intr_in[21] 0=low" "0: low,?"
bitfld.long 0x0 20. "POLARITY_20,Polarity for intr_in[20] 0=low" "0: low,?"
newline
bitfld.long 0x0 19. "POLARITY_19,Polarity for intr_in[19] 0=low" "0: low,?"
bitfld.long 0x0 18. "POLARITY_18,Polarity for intr_in[18] 0=low" "0: low,?"
bitfld.long 0x0 17. "POLARITY_17,Polarity for intr_in[17] 0=low" "0: low,?"
newline
bitfld.long 0x0 16. "POLARITY_16,Polarity for intr_in[16] 0=low" "0: low,?"
bitfld.long 0x0 15. "POLARITY_15,Polarity for intr_in[15] 0=low" "0: low,?"
bitfld.long 0x0 14. "POLARITY_14,Polarity for intr_in[14] 0=low" "0: low,?"
newline
bitfld.long 0x0 13. "POLARITY_13,Polarity for intr_in[13] 0=low" "0: low,?"
bitfld.long 0x0 12. "POLARITY_12,Polarity for intr_in[12] 0=low" "0: low,?"
bitfld.long 0x0 11. "POLARITY_11,Polarity for intr_in[11] 0=low" "0: low,?"
newline
bitfld.long 0x0 10. "POLARITY_10,Polarity for intr_in[10] 0=low" "0: low,?"
bitfld.long 0x0 9. "POLARITY_9,Polarity for intr_in[9] 0=low" "0: low,?"
bitfld.long 0x0 8. "POLARITY_8,Polarity for intr_in[8] 0=low" "0: low,?"
newline
bitfld.long 0x0 7. "POLARITY_7,Polarity for intr_in[7] 0=low" "0: low,?"
bitfld.long 0x0 6. "POLARITY_6,Polarity for intr_in[6] 0=low" "0: low,?"
bitfld.long 0x0 5. "POLARITY_5,Polarity for intr_in[5] 0=low" "0: low,?"
newline
bitfld.long 0x0 4. "POLARITY_4,Polarity for intr_in[4] 0=low" "0: low,?"
bitfld.long 0x0 3. "POLARITY_3,Polarity for intr_in[3] 0=low" "0: low,?"
bitfld.long 0x0 2. "POLARITY_2,Polarity for intr_in[2] 0=low" "0: low,?"
newline
bitfld.long 0x0 1. "POLARITY_1,Polarity for intr_in[1] 0=low" "0: low,?"
bitfld.long 0x0 0. "POLARITY_0,Polarity for intr_in[0] 0=low" "0: low,?"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG1,"
bitfld.long 0x4 31. "POLARITY_63,Polarity for intr_in[63] 0=low" "0: low,?"
bitfld.long 0x4 30. "POLARITY_62,Polarity for intr_in[62] 0=low" "0: low,?"
bitfld.long 0x4 29. "POLARITY_61,Polarity for intr_in[61] 0=low" "0: low,?"
newline
bitfld.long 0x4 28. "POLARITY_60,Polarity for intr_in[60] 0=low" "0: low,?"
bitfld.long 0x4 27. "POLARITY_59,Polarity for intr_in[59] 0=low" "0: low,?"
bitfld.long 0x4 26. "POLARITY_58,Polarity for intr_in[58] 0=low" "0: low,?"
newline
bitfld.long 0x4 25. "POLARITY_57,Polarity for intr_in[57] 0=low" "0: low,?"
bitfld.long 0x4 24. "POLARITY_56,Polarity for intr_in[56] 0=low" "0: low,?"
bitfld.long 0x4 23. "POLARITY_55,Polarity for intr_in[55] 0=low" "0: low,?"
newline
bitfld.long 0x4 22. "POLARITY_54,Polarity for intr_in[54] 0=low" "0: low,?"
bitfld.long 0x4 21. "POLARITY_53,Polarity for intr_in[53] 0=low" "0: low,?"
bitfld.long 0x4 20. "POLARITY_52,Polarity for intr_in[52] 0=low" "0: low,?"
newline
bitfld.long 0x4 19. "POLARITY_51,Polarity for intr_in[51] 0=low" "0: low,?"
bitfld.long 0x4 18. "POLARITY_50,Polarity for intr_in[50] 0=low" "0: low,?"
bitfld.long 0x4 17. "POLARITY_49,Polarity for intr_in[49] 0=low" "0: low,?"
newline
bitfld.long 0x4 16. "POLARITY_48,Polarity for intr_in[48] 0=low" "0: low,?"
bitfld.long 0x4 15. "POLARITY_47,Polarity for intr_in[47] 0=low" "0: low,?"
bitfld.long 0x4 14. "POLARITY_46,Polarity for intr_in[46] 0=low" "0: low,?"
newline
bitfld.long 0x4 13. "POLARITY_45,Polarity for intr_in[45] 0=low" "0: low,?"
bitfld.long 0x4 12. "POLARITY_44,Polarity for intr_in[44] 0=low" "0: low,?"
bitfld.long 0x4 11. "POLARITY_43,Polarity for intr_in[43] 0=low" "0: low,?"
newline
bitfld.long 0x4 10. "POLARITY_42,Polarity for intr_in[42] 0=low" "0: low,?"
bitfld.long 0x4 9. "POLARITY_41,Polarity for intr_in[41] 0=low" "0: low,?"
bitfld.long 0x4 8. "POLARITY_40,Polarity for intr_in[40] 0=low" "0: low,?"
newline
bitfld.long 0x4 7. "POLARITY_39,Polarity for intr_in[39] 0=low" "0: low,?"
bitfld.long 0x4 6. "POLARITY_38,Polarity for intr_in[38] 0=low" "0: low,?"
bitfld.long 0x4 5. "POLARITY_37,Polarity for intr_in[37] 0=low" "0: low,?"
newline
bitfld.long 0x4 4. "POLARITY_36,Polarity for intr_in[36] 0=low" "0: low,?"
bitfld.long 0x4 3. "POLARITY_35,Polarity for intr_in[35] 0=low" "0: low,?"
bitfld.long 0x4 2. "POLARITY_34,Polarity for intr_in[34] 0=low" "0: low,?"
newline
bitfld.long 0x4 1. "POLARITY_33,Polarity for intr_in[33] 0=low" "0: low,?"
bitfld.long 0x4 0. "POLARITY_32,Polarity for intr_in[32] 0=low" "0: low,?"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG2,"
bitfld.long 0x8 31. "POLARITY_95,Polarity for slv_events_in[31] 0=low" "0: low,?"
bitfld.long 0x8 30. "POLARITY_94,Polarity for slv_events_in[30] 0=low" "0: low,?"
bitfld.long 0x8 29. "POLARITY_93,Polarity for slv_events_in[29] 0=low" "0: low,?"
newline
bitfld.long 0x8 28. "POLARITY_92,Polarity for slv_events_in[28] 0=low" "0: low,?"
bitfld.long 0x8 27. "POLARITY_91,Polarity for slv_events_in[27] 0=low" "0: low,?"
bitfld.long 0x8 26. "POLARITY_90,Polarity for slv_events_in[26] 0=low" "0: low,?"
newline
bitfld.long 0x8 25. "POLARITY_89,Polarity for slv_events_in[25] 0=low" "0: low,?"
bitfld.long 0x8 24. "POLARITY_88,Polarity for slv_events_in[24] 0=low" "0: low,?"
bitfld.long 0x8 23. "POLARITY_87,Polarity for slv_events_in[23] 0=low" "0: low,?"
newline
bitfld.long 0x8 22. "POLARITY_86,Polarity for slv_events_in[22] 0=low" "0: low,?"
bitfld.long 0x8 21. "POLARITY_85,Polarity for slv_events_in[21] 0=low" "0: low,?"
bitfld.long 0x8 20. "POLARITY_84,Polarity for slv_events_in[20] 0=low" "0: low,?"
newline
bitfld.long 0x8 19. "POLARITY_83,Polarity for slv_events_in[19] 0=low" "0: low,?"
bitfld.long 0x8 18. "POLARITY_82,Polarity for slv_events_in[18] 0=low" "0: low,?"
bitfld.long 0x8 17. "POLARITY_81,Polarity for slv_events_in[17] 0=low" "0: low,?"
newline
bitfld.long 0x8 16. "POLARITY_80,Polarity for slv_events_in[16] 0=low" "0: low,?"
bitfld.long 0x8 15. "POLARITY_79,Polarity for slv_events_in[15] 0=low" "0: low,?"
bitfld.long 0x8 14. "POLARITY_78,Polarity for slv_events_in[14] 0=low" "0: low,?"
newline
bitfld.long 0x8 13. "POLARITY_77,Polarity for slv_events_in[13] 0=low" "0: low,?"
bitfld.long 0x8 12. "POLARITY_76,Polarity for slv_events_in[12] 0=low" "0: low,?"
bitfld.long 0x8 11. "POLARITY_75,Polarity for slv_events_in[11] 0=low" "0: low,?"
newline
bitfld.long 0x8 10. "POLARITY_74,Polarity for slv_events_in[10] 0=low" "0: low,?"
bitfld.long 0x8 9. "POLARITY_73,Polarity for slv_events_in[9] 0=low" "0: low,?"
bitfld.long 0x8 8. "POLARITY_72,Polarity for slv_events_in[8] 0=low" "0: low,?"
newline
bitfld.long 0x8 7. "POLARITY_71,Polarity for slv_events_in[7] 0=low" "0: low,?"
bitfld.long 0x8 6. "POLARITY_70,Polarity for slv_events_in[6] 0=low" "0: low,?"
bitfld.long 0x8 5. "POLARITY_69,Polarity for slv_events_in[5] 0=low" "0: low,?"
newline
bitfld.long 0x8 4. "POLARITY_68,Polarity for slv_events_in[4] 0=low" "0: low,?"
bitfld.long 0x8 3. "POLARITY_67,Polarity for slv_events_in[3] 0=low" "0: low,?"
bitfld.long 0x8 2. "POLARITY_66,Polarity for slv_events_in[2] 0=low" "0: low,?"
newline
bitfld.long 0x8 1. "POLARITY_65,Polarity for slv_events_in[1] 0=low" "0: low,?"
bitfld.long 0x8 0. "POLARITY_64,Polarity for slv_events_in[0] 0=low" "0: low,?"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG3,"
bitfld.long 0xC 31. "POLARITY_127,Polarity for slv_events_in[63] 0=low" "0: low,?"
bitfld.long 0xC 30. "POLARITY_126,Polarity for slv_events_in[62] 0=low" "0: low,?"
bitfld.long 0xC 29. "POLARITY_125,Polarity for slv_events_in[61] 0=low" "0: low,?"
newline
bitfld.long 0xC 28. "POLARITY_124,Polarity for slv_events_in[60] 0=low" "0: low,?"
bitfld.long 0xC 27. "POLARITY_123,Polarity for slv_events_in[59] 0=low" "0: low,?"
bitfld.long 0xC 26. "POLARITY_122,Polarity for slv_events_in[58] 0=low" "0: low,?"
newline
bitfld.long 0xC 25. "POLARITY_121,Polarity for slv_events_in[57] 0=low" "0: low,?"
bitfld.long 0xC 24. "POLARITY_120,Polarity for slv_events_in[56] 0=low" "0: low,?"
bitfld.long 0xC 23. "POLARITY_119,Polarity for slv_events_in[55] 0=low" "0: low,?"
newline
bitfld.long 0xC 22. "POLARITY_118,Polarity for slv_events_in[54] 0=low" "0: low,?"
bitfld.long 0xC 21. "POLARITY_117,Polarity for slv_events_in[53] 0=low" "0: low,?"
bitfld.long 0xC 20. "POLARITY_116,Polarity for slv_events_in[52] 0=low" "0: low,?"
newline
bitfld.long 0xC 19. "POLARITY_115,Polarity for slv_events_in[51] 0=low" "0: low,?"
bitfld.long 0xC 18. "POLARITY_114,Polarity for slv_events_in[50] 0=low" "0: low,?"
bitfld.long 0xC 17. "POLARITY_113,Polarity for slv_events_in[49] 0=low" "0: low,?"
newline
bitfld.long 0xC 16. "POLARITY_112,Polarity for slv_events_in[48] 0=low" "0: low,?"
bitfld.long 0xC 15. "POLARITY_111,Polarity for slv_events_in[47] 0=low" "0: low,?"
bitfld.long 0xC 14. "POLARITY_110,Polarity for slv_events_in[46] 0=low" "0: low,?"
newline
bitfld.long 0xC 13. "POLARITY_109,Polarity for slv_events_in[45] 0=low" "0: low,?"
bitfld.long 0xC 12. "POLARITY_108,Polarity for slv_events_in[44] 0=low" "0: low,?"
bitfld.long 0xC 11. "POLARITY_107,Polarity for slv_events_in[43] 0=low" "0: low,?"
newline
bitfld.long 0xC 10. "POLARITY_106,Polarity for slv_events_in[42] 0=low" "0: low,?"
bitfld.long 0xC 9. "POLARITY_105,Polarity for slv_events_in[41] 0=low" "0: low,?"
bitfld.long 0xC 8. "POLARITY_104,Polarity for slv_events_in[40] 0=low" "0: low,?"
newline
bitfld.long 0xC 7. "POLARITY_103,Polarity for slv_events_in[39] 0=low" "0: low,?"
bitfld.long 0xC 6. "POLARITY_102,Polarity for slv_events_in[38] 0=low" "0: low,?"
bitfld.long 0xC 5. "POLARITY_101,Polarity for slv_events_in[37] 0=low" "0: low,?"
newline
bitfld.long 0xC 4. "POLARITY_100,Polarity for slv_events_in[36] 0=low" "0: low,?"
bitfld.long 0xC 3. "POLARITY_99,Polarity for slv_events_in[35] 0=low" "0: low,?"
bitfld.long 0xC 2. "POLARITY_98,Polarity for slv_events_in[34] 0=low" "0: low,?"
newline
bitfld.long 0xC 1. "POLARITY_97,Polarity for slv_events_in[33] 0=low" "0: low,?"
bitfld.long 0xC 0. "POLARITY_96,Polarity for slv_events_in[32] 0=low" "0: low,?"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG4,"
bitfld.long 0x10 31. "POLARITY_159,Polarity for slv_events_in[95] 0=low" "0: low,?"
bitfld.long 0x10 30. "POLARITY_158,Polarity for slv_events_in[94] 0=low" "0: low,?"
bitfld.long 0x10 29. "POLARITY_157,Polarity for slv_events_in[93] 0=low" "0: low,?"
newline
bitfld.long 0x10 28. "POLARITY_156,Polarity for slv_events_in[92] 0=low" "0: low,?"
bitfld.long 0x10 27. "POLARITY_155,Polarity for slv_events_in[91] 0=low" "0: low,?"
bitfld.long 0x10 26. "POLARITY_154,Polarity for slv_events_in[90] 0=low" "0: low,?"
newline
bitfld.long 0x10 25. "POLARITY_153,Polarity for slv_events_in[89] 0=low" "0: low,?"
bitfld.long 0x10 24. "POLARITY_152,Polarity for slv_events_in[88] 0=low" "0: low,?"
bitfld.long 0x10 23. "POLARITY_151,Polarity for slv_events_in[87] 0=low" "0: low,?"
newline
bitfld.long 0x10 22. "POLARITY_150,Polarity for slv_events_in[86] 0=low" "0: low,?"
bitfld.long 0x10 21. "POLARITY_149,Polarity for slv_events_in[85] 0=low" "0: low,?"
bitfld.long 0x10 20. "POLARITY_148,Polarity for slv_events_in[84] 0=low" "0: low,?"
newline
bitfld.long 0x10 19. "POLARITY_147,Polarity for slv_events_in[83] 0=low" "0: low,?"
bitfld.long 0x10 18. "POLARITY_146,Polarity for slv_events_in[82] 0=low" "0: low,?"
bitfld.long 0x10 17. "POLARITY_145,Polarity for slv_events_in[81] 0=low" "0: low,?"
newline
bitfld.long 0x10 16. "POLARITY_144,Polarity for slv_events_in[80] 0=low" "0: low,?"
bitfld.long 0x10 15. "POLARITY_143,Polarity for slv_events_in[79] 0=low" "0: low,?"
bitfld.long 0x10 14. "POLARITY_142,Polarity for slv_events_in[78] 0=low" "0: low,?"
newline
bitfld.long 0x10 13. "POLARITY_141,Polarity for slv_events_in[77] 0=low" "0: low,?"
bitfld.long 0x10 12. "POLARITY_140,Polarity for slv_events_in[76] 0=low" "0: low,?"
bitfld.long 0x10 11. "POLARITY_139,Polarity for slv_events_in[75] 0=low" "0: low,?"
newline
bitfld.long 0x10 10. "POLARITY_138,Polarity for slv_events_in[74] 0=low" "0: low,?"
bitfld.long 0x10 9. "POLARITY_137,Polarity for slv_events_in[73] 0=low" "0: low,?"
bitfld.long 0x10 8. "POLARITY_136,Polarity for slv_events_in[72] 0=low" "0: low,?"
newline
bitfld.long 0x10 7. "POLARITY_135,Polarity for slv_events_in[71] 0=low" "0: low,?"
bitfld.long 0x10 6. "POLARITY_134,Polarity for slv_events_in[70] 0=low" "0: low,?"
bitfld.long 0x10 5. "POLARITY_133,Polarity for slv_events_in[69] 0=low" "0: low,?"
newline
bitfld.long 0x10 4. "POLARITY_132,Polarity for slv_events_in[68] 0=low" "0: low,?"
bitfld.long 0x10 3. "POLARITY_131,Polarity for slv_events_in[67] 0=low" "0: low,?"
bitfld.long 0x10 2. "POLARITY_130,Polarity for slv_events_in[66] 0=low" "0: low,?"
newline
bitfld.long 0x10 1. "POLARITY_129,Polarity for slv_events_in[65] 0=low" "0: low,?"
bitfld.long 0x10 0. "POLARITY_128,Polarity for slv_events_in[64] 0=low" "0: low,?"
group.long 0xD80++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG0,"
bitfld.long 0x0 31. "TYPE_31,Type for intr_in[31] 0=level" "0: level,?"
bitfld.long 0x0 30. "TYPE_30,Type for intr_in[30] 0=level" "0: level,?"
bitfld.long 0x0 29. "TYPE_29,Type for intr_in[29] 0=level" "0: level,?"
newline
bitfld.long 0x0 28. "TYPE_28,Type for intr_in[28] 0=level" "0: level,?"
bitfld.long 0x0 27. "TYPE_27,Type for intr_in[27] 0=level" "0: level,?"
bitfld.long 0x0 26. "TYPE_26,Type for intr_in[26] 0=level" "0: level,?"
newline
bitfld.long 0x0 25. "TYPE_25,Type for intr_in[25] 0=level" "0: level,?"
bitfld.long 0x0 24. "TYPE_24,Type for intr_in[24] 0=level" "0: level,?"
bitfld.long 0x0 23. "TYPE_23,Type for intr_in[23] 0=level" "0: level,?"
newline
bitfld.long 0x0 22. "TYPE_22,Type for intr_in[22] 0=level" "0: level,?"
bitfld.long 0x0 21. "TYPE_21,Type for intr_in[21] 0=level" "0: level,?"
bitfld.long 0x0 20. "TYPE_20,Type for intr_in[20] 0=level" "0: level,?"
newline
bitfld.long 0x0 19. "TYPE_19,Type for intr_in[19] 0=level" "0: level,?"
bitfld.long 0x0 18. "TYPE_18,Type for intr_in[18] 0=level" "0: level,?"
bitfld.long 0x0 17. "TYPE_17,Type for intr_in[17] 0=level" "0: level,?"
newline
bitfld.long 0x0 16. "TYPE_16,Type for intr_in[16] 0=level" "0: level,?"
bitfld.long 0x0 15. "TYPE_15,Type for intr_in[15] 0=level" "0: level,?"
bitfld.long 0x0 14. "TYPE_14,Type for intr_in[14] 0=level" "0: level,?"
newline
bitfld.long 0x0 13. "TYPE_13,Type for intr_in[13] 0=level" "0: level,?"
bitfld.long 0x0 12. "TYPE_12,Type for intr_in[12] 0=level" "0: level,?"
bitfld.long 0x0 11. "TYPE_11,Type for intr_in[11] 0=level" "0: level,?"
newline
bitfld.long 0x0 10. "TYPE_10,Type for intr_in[10] 0=level" "0: level,?"
bitfld.long 0x0 9. "TYPE_9,Type for intr_in[9] 0=level" "0: level,?"
bitfld.long 0x0 8. "TYPE_8,Type for intr_in[8] 0=level" "0: level,?"
newline
bitfld.long 0x0 7. "TYPE_7,Type for intr_in[7] 0=level" "0: level,?"
bitfld.long 0x0 6. "TYPE_6,Type for intr_in[6] 0=level" "0: level,?"
bitfld.long 0x0 5. "TYPE_5,Type for intr_in[5] 0=level" "0: level,?"
newline
bitfld.long 0x0 4. "TYPE_4,Type for intr_in[4] 0=level" "0: level,?"
bitfld.long 0x0 3. "TYPE_3,Type for intr_in[3] 0=level" "0: level,?"
bitfld.long 0x0 2. "TYPE_2,Type for intr_in[2] 0=level" "0: level,?"
newline
bitfld.long 0x0 1. "TYPE_1,Type for intr_in[1] 0=level" "0: level,?"
bitfld.long 0x0 0. "TYPE_0,Type for intr_in[0] 0=level" "0: level,?"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG1,"
bitfld.long 0x4 31. "TYPE_63,Type for intr_in[63] 0=level" "0: level,?"
bitfld.long 0x4 30. "TYPE_62,Type for intr_in[62] 0=level" "0: level,?"
bitfld.long 0x4 29. "TYPE_61,Type for intr_in[61] 0=level" "0: level,?"
newline
bitfld.long 0x4 28. "TYPE_60,Type for intr_in[60] 0=level" "0: level,?"
bitfld.long 0x4 27. "TYPE_59,Type for intr_in[59] 0=level" "0: level,?"
bitfld.long 0x4 26. "TYPE_58,Type for intr_in[58] 0=level" "0: level,?"
newline
bitfld.long 0x4 25. "TYPE_57,Type for intr_in[57] 0=level" "0: level,?"
bitfld.long 0x4 24. "TYPE_56,Type for intr_in[56] 0=level" "0: level,?"
bitfld.long 0x4 23. "TYPE_55,Type for intr_in[55] 0=level" "0: level,?"
newline
bitfld.long 0x4 22. "TYPE_54,Type for intr_in[54] 0=level" "0: level,?"
bitfld.long 0x4 21. "TYPE_53,Type for intr_in[53] 0=level" "0: level,?"
bitfld.long 0x4 20. "TYPE_52,Type for intr_in[52] 0=level" "0: level,?"
newline
bitfld.long 0x4 19. "TYPE_51,Type for intr_in[51] 0=level" "0: level,?"
bitfld.long 0x4 18. "TYPE_50,Type for intr_in[50] 0=level" "0: level,?"
bitfld.long 0x4 17. "TYPE_49,Type for intr_in[49] 0=level" "0: level,?"
newline
bitfld.long 0x4 16. "TYPE_48,Type for intr_in[48] 0=level" "0: level,?"
bitfld.long 0x4 15. "TYPE_47,Type for intr_in[47] 0=level" "0: level,?"
bitfld.long 0x4 14. "TYPE_46,Type for intr_in[46] 0=level" "0: level,?"
newline
bitfld.long 0x4 13. "TYPE_45,Type for intr_in[45] 0=level" "0: level,?"
bitfld.long 0x4 12. "TYPE_44,Type for intr_in[44] 0=level" "0: level,?"
bitfld.long 0x4 11. "TYPE_43,Type for intr_in[43] 0=level" "0: level,?"
newline
bitfld.long 0x4 10. "TYPE_42,Type for intr_in[42] 0=level" "0: level,?"
bitfld.long 0x4 9. "TYPE_41,Type for intr_in[41] 0=level" "0: level,?"
bitfld.long 0x4 8. "TYPE_40,Type for intr_in[40] 0=level" "0: level,?"
newline
bitfld.long 0x4 7. "TYPE_39,Type for intr_in[39] 0=level" "0: level,?"
bitfld.long 0x4 6. "TYPE_38,Type for intr_in[38] 0=level" "0: level,?"
bitfld.long 0x4 5. "TYPE_37,Type for intr_in[37] 0=level" "0: level,?"
newline
bitfld.long 0x4 4. "TYPE_36,Type for intr_in[36] 0=level" "0: level,?"
bitfld.long 0x4 3. "TYPE_35,Type for intr_in[35] 0=level" "0: level,?"
bitfld.long 0x4 2. "TYPE_34,Type for intr_in[34] 0=level" "0: level,?"
newline
bitfld.long 0x4 1. "TYPE_33,Type for intr_in[33] 0=level" "0: level,?"
bitfld.long 0x4 0. "TYPE_32,Type for intr_in[32] 0=level" "0: level,?"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG2,"
bitfld.long 0x8 31. "TYPE_95,Type for slv_events_in[31] 0=level" "0: level,?"
bitfld.long 0x8 30. "TYPE_94,Type for slv_events_in[30] 0=level" "0: level,?"
bitfld.long 0x8 29. "TYPE_93,Type for slv_events_in[29] 0=level" "0: level,?"
newline
bitfld.long 0x8 28. "TYPE_92,Type for slv_events_in[28] 0=level" "0: level,?"
bitfld.long 0x8 27. "TYPE_91,Type for slv_events_in[27] 0=level" "0: level,?"
bitfld.long 0x8 26. "TYPE_90,Type for slv_events_in[26] 0=level" "0: level,?"
newline
bitfld.long 0x8 25. "TYPE_89,Type for slv_events_in[25] 0=level" "0: level,?"
bitfld.long 0x8 24. "TYPE_88,Type for slv_events_in[24] 0=level" "0: level,?"
bitfld.long 0x8 23. "TYPE_87,Type for slv_events_in[23] 0=level" "0: level,?"
newline
bitfld.long 0x8 22. "TYPE_86,Type for slv_events_in[22] 0=level" "0: level,?"
bitfld.long 0x8 21. "TYPE_85,Type for slv_events_in[21] 0=level" "0: level,?"
bitfld.long 0x8 20. "TYPE_84,Type for slv_events_in[20] 0=level" "0: level,?"
newline
bitfld.long 0x8 19. "TYPE_83,Type for slv_events_in[19] 0=level" "0: level,?"
bitfld.long 0x8 18. "TYPE_82,Type for slv_events_in[18] 0=level" "0: level,?"
bitfld.long 0x8 17. "TYPE_81,Type for slv_events_in[17] 0=level" "0: level,?"
newline
bitfld.long 0x8 16. "TYPE_80,Type for slv_events_in[16] 0=level" "0: level,?"
bitfld.long 0x8 15. "TYPE_79,Type for slv_events_in[15] 0=level" "0: level,?"
bitfld.long 0x8 14. "TYPE_78,Type for slv_events_in[14] 0=level" "0: level,?"
newline
bitfld.long 0x8 13. "TYPE_77,Type for slv_events_in[13] 0=level" "0: level,?"
bitfld.long 0x8 12. "TYPE_76,Type for slv_events_in[12] 0=level" "0: level,?"
bitfld.long 0x8 11. "TYPE_75,Type for slv_events_in[11] 0=level" "0: level,?"
newline
bitfld.long 0x8 10. "TYPE_74,Type for slv_events_in[10] 0=level" "0: level,?"
bitfld.long 0x8 9. "TYPE_73,Type for slv_events_in[9] 0=level" "0: level,?"
bitfld.long 0x8 8. "TYPE_72,Type for slv_events_in[8] 0=level" "0: level,?"
newline
bitfld.long 0x8 7. "TYPE_71,Type for slv_events_in[7] 0=level" "0: level,?"
bitfld.long 0x8 6. "TYPE_70,Type for slv_events_in[6] 0=level" "0: level,?"
bitfld.long 0x8 5. "TYPE_69,Type for slv_events_in[5] 0=level" "0: level,?"
newline
bitfld.long 0x8 4. "TYPE_68,Type for slv_events_in[4] 0=level" "0: level,?"
bitfld.long 0x8 3. "TYPE_67,Type for slv_events_in[3] 0=level" "0: level,?"
bitfld.long 0x8 2. "TYPE_66,Type for slv_events_in[2] 0=level" "0: level,?"
newline
bitfld.long 0x8 1. "TYPE_65,Type for slv_events_in[1] 0=level" "0: level,?"
bitfld.long 0x8 0. "TYPE_64,Type for slv_events_in[0] 0=level" "0: level,?"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG3,"
bitfld.long 0xC 31. "TYPE_127,Type for slv_events_in[63] 0=level" "0: level,?"
bitfld.long 0xC 30. "TYPE_126,Type for slv_events_in[62] 0=level" "0: level,?"
bitfld.long 0xC 29. "TYPE_125,Type for slv_events_in[61] 0=level" "0: level,?"
newline
bitfld.long 0xC 28. "TYPE_124,Type for slv_events_in[60] 0=level" "0: level,?"
bitfld.long 0xC 27. "TYPE_123,Type for slv_events_in[59] 0=level" "0: level,?"
bitfld.long 0xC 26. "TYPE_122,Type for slv_events_in[58] 0=level" "0: level,?"
newline
bitfld.long 0xC 25. "TYPE_121,Type for slv_events_in[57] 0=level" "0: level,?"
bitfld.long 0xC 24. "TYPE_120,Type for slv_events_in[56] 0=level" "0: level,?"
bitfld.long 0xC 23. "TYPE_119,Type for slv_events_in[55] 0=level" "0: level,?"
newline
bitfld.long 0xC 22. "TYPE_118,Type for slv_events_in[54] 0=level" "0: level,?"
bitfld.long 0xC 21. "TYPE_117,Type for slv_events_in[53] 0=level" "0: level,?"
bitfld.long 0xC 20. "TYPE_116,Type for slv_events_in[52] 0=level" "0: level,?"
newline
bitfld.long 0xC 19. "TYPE_115,Type for slv_events_in[51] 0=level" "0: level,?"
bitfld.long 0xC 18. "TYPE_114,Type for slv_events_in[50] 0=level" "0: level,?"
bitfld.long 0xC 17. "TYPE_113,Type for slv_events_in[49] 0=level" "0: level,?"
newline
bitfld.long 0xC 16. "TYPE_112,Type for slv_events_in[48] 0=level" "0: level,?"
bitfld.long 0xC 15. "TYPE_111,Type for slv_events_in[47] 0=level" "0: level,?"
bitfld.long 0xC 14. "TYPE_110,Type for slv_events_in[46] 0=level" "0: level,?"
newline
bitfld.long 0xC 13. "TYPE_109,Type for slv_events_in[45] 0=level" "0: level,?"
bitfld.long 0xC 12. "TYPE_108,Type for slv_events_in[44] 0=level" "0: level,?"
bitfld.long 0xC 11. "TYPE_107,Type for slv_events_in[43] 0=level" "0: level,?"
newline
bitfld.long 0xC 10. "TYPE_106,Type for slv_events_in[42] 0=level" "0: level,?"
bitfld.long 0xC 9. "TYPE_105,Type for slv_events_in[41] 0=level" "0: level,?"
bitfld.long 0xC 8. "TYPE_104,Type for slv_events_in[40] 0=level" "0: level,?"
newline
bitfld.long 0xC 7. "TYPE_103,Type for slv_events_in[39] 0=level" "0: level,?"
bitfld.long 0xC 6. "TYPE_102,Type for slv_events_in[38] 0=level" "0: level,?"
bitfld.long 0xC 5. "TYPE_101,Type for slv_events_in[37] 0=level" "0: level,?"
newline
bitfld.long 0xC 4. "TYPE_100,Type for slv_events_in[36] 0=level" "0: level,?"
bitfld.long 0xC 3. "TYPE_99,Type for slv_events_in[35] 0=level" "0: level,?"
bitfld.long 0xC 2. "TYPE_98,Type for slv_events_in[34] 0=level" "0: level,?"
newline
bitfld.long 0xC 1. "TYPE_97,Type for slv_events_in[33] 0=level" "0: level,?"
bitfld.long 0xC 0. "TYPE_96,Type for slv_events_in[32] 0=level" "0: level,?"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG4,"
bitfld.long 0x10 31. "TYPE_159,Type for slv_events_in[95] 0=level" "0: level,?"
bitfld.long 0x10 30. "TYPE_158,Type for slv_events_in[94] 0=level" "0: level,?"
bitfld.long 0x10 29. "TYPE_157,Type for slv_events_in[93] 0=level" "0: level,?"
newline
bitfld.long 0x10 28. "TYPE_156,Type for slv_events_in[92] 0=level" "0: level,?"
bitfld.long 0x10 27. "TYPE_155,Type for slv_events_in[91] 0=level" "0: level,?"
bitfld.long 0x10 26. "TYPE_154,Type for slv_events_in[90] 0=level" "0: level,?"
newline
bitfld.long 0x10 25. "TYPE_153,Type for slv_events_in[89] 0=level" "0: level,?"
bitfld.long 0x10 24. "TYPE_152,Type for slv_events_in[88] 0=level" "0: level,?"
bitfld.long 0x10 23. "TYPE_151,Type for slv_events_in[87] 0=level" "0: level,?"
newline
bitfld.long 0x10 22. "TYPE_150,Type for slv_events_in[86] 0=level" "0: level,?"
bitfld.long 0x10 21. "TYPE_149,Type for slv_events_in[85] 0=level" "0: level,?"
bitfld.long 0x10 20. "TYPE_148,Type for slv_events_in[84] 0=level" "0: level,?"
newline
bitfld.long 0x10 19. "TYPE_147,Type for slv_events_in[83] 0=level" "0: level,?"
bitfld.long 0x10 18. "TYPE_146,Type for slv_events_in[82] 0=level" "0: level,?"
bitfld.long 0x10 17. "TYPE_145,Type for slv_events_in[81] 0=level" "0: level,?"
newline
bitfld.long 0x10 16. "TYPE_144,Type for slv_events_in[80] 0=level" "0: level,?"
bitfld.long 0x10 15. "TYPE_143,Type for slv_events_in[79] 0=level" "0: level,?"
bitfld.long 0x10 14. "TYPE_142,Type for slv_events_in[78] 0=level" "0: level,?"
newline
bitfld.long 0x10 13. "TYPE_141,Type for slv_events_in[77] 0=level" "0: level,?"
bitfld.long 0x10 12. "TYPE_140,Type for slv_events_in[76] 0=level" "0: level,?"
bitfld.long 0x10 11. "TYPE_139,Type for slv_events_in[75] 0=level" "0: level,?"
newline
bitfld.long 0x10 10. "TYPE_138,Type for slv_events_in[74] 0=level" "0: level,?"
bitfld.long 0x10 9. "TYPE_137,Type for slv_events_in[73] 0=level" "0: level,?"
bitfld.long 0x10 8. "TYPE_136,Type for slv_events_in[72] 0=level" "0: level,?"
newline
bitfld.long 0x10 7. "TYPE_135,Type for slv_events_in[71] 0=level" "0: level,?"
bitfld.long 0x10 6. "TYPE_134,Type for slv_events_in[70] 0=level" "0: level,?"
bitfld.long 0x10 5. "TYPE_133,Type for slv_events_in[69] 0=level" "0: level,?"
newline
bitfld.long 0x10 4. "TYPE_132,Type for slv_events_in[68] 0=level" "0: level,?"
bitfld.long 0x10 3. "TYPE_131,Type for slv_events_in[67] 0=level" "0: level,?"
bitfld.long 0x10 2. "TYPE_130,Type for slv_events_in[66] 0=level" "0: level,?"
newline
bitfld.long 0x10 1. "TYPE_129,Type for slv_events_in[65] 0=level" "0: level,?"
bitfld.long 0x10 0. "TYPE_128,Type for slv_events_in[64] 0=level" "0: level,?"
group.long 0x1100++0x4F
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG0,"
bitfld.long 0x0 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x0 0.--8. 1. "NEST_HINT_0,Host Int 0 Nesting Level"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG1,"
bitfld.long 0x4 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x4 0.--8. 1. "NEST_HINT_1,Host Int 1 Nesting Level"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG2,"
bitfld.long 0x8 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x8 0.--8. 1. "NEST_HINT_2,Host Int 2 Nesting Level"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG3,"
bitfld.long 0xC 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0xC 0.--8. 1. "NEST_HINT_3,Host Int 3 Nesting Level"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG4,"
bitfld.long 0x10 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT_4,Host Int 4 Nesting Level"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG5,"
bitfld.long 0x14 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT_5,Host Int 5 Nesting Level"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG6,"
bitfld.long 0x18 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT_6,Host Int 6 Nesting Level"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG7,"
bitfld.long 0x1C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT_7,Host Int 7 Nesting Level"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG8,"
bitfld.long 0x20 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT_8,Host Int 8 Nesting Level"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG9,"
bitfld.long 0x24 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT_9,Host Int 9 Nesting Level"
line.long 0x28 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG10,"
bitfld.long 0x28 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x28 0.--8. 1. "NEST_HINT_10,Host Int 10 Nesting Level"
line.long 0x2C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG11,"
bitfld.long 0x2C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x2C 0.--8. 1. "NEST_HINT_11,Host Int 11 Nesting Level"
line.long 0x30 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG12,"
bitfld.long 0x30 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x30 0.--8. 1. "NEST_HINT_12,Host Int 12 Nesting Level"
line.long 0x34 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG13,"
bitfld.long 0x34 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x34 0.--8. 1. "NEST_HINT_13,Host Int 13 Nesting Level"
line.long 0x38 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG14,"
bitfld.long 0x38 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x38 0.--8. 1. "NEST_HINT_14,Host Int 14 Nesting Level"
line.long 0x3C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG15,"
bitfld.long 0x3C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x3C 0.--8. 1. "NEST_HINT_15,Host Int 15 Nesting Level"
line.long 0x40 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG16,"
bitfld.long 0x40 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x40 0.--8. 1. "NEST_HINT_16,Host Int 16 Nesting Level"
line.long 0x44 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG17,"
bitfld.long 0x44 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x44 0.--8. 1. "NEST_HINT_17,Host Int 17 Nesting Level"
line.long 0x48 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG18,"
bitfld.long 0x48 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x48 0.--8. 1. "NEST_HINT_18,Host Int 18 Nesting Level"
line.long 0x4C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG19,"
bitfld.long 0x4C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x4C 0.--8. 1. "NEST_HINT_19,Host Int 19 Nesting Level"
group.long 0x1500++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_HINT_REG0,"
bitfld.long 0x0 19. "ENABLE_HINT_19,Enable for Host Int 19" "0,1"
bitfld.long 0x0 18. "ENABLE_HINT_18,Enable for Host Int 18" "0,1"
bitfld.long 0x0 17. "ENABLE_HINT_17,Enable for Host Int 17" "0,1"
newline
bitfld.long 0x0 16. "ENABLE_HINT_16,Enable for Host Int 16" "0,1"
bitfld.long 0x0 15. "ENABLE_HINT_15,Enable for Host Int 15" "0,1"
bitfld.long 0x0 14. "ENABLE_HINT_14,Enable for Host Int 14" "0,1"
newline
bitfld.long 0x0 13. "ENABLE_HINT_13,Enable for Host Int 13" "0,1"
bitfld.long 0x0 12. "ENABLE_HINT_12,Enable for Host Int 12" "0,1"
bitfld.long 0x0 11. "ENABLE_HINT_11,Enable for Host Int 11" "0,1"
newline
bitfld.long 0x0 10. "ENABLE_HINT_10,Enable for Host Int 10" "0,1"
bitfld.long 0x0 9. "ENABLE_HINT_9,Enable for Host Int 9" "0,1"
bitfld.long 0x0 8. "ENABLE_HINT_8,Enable for Host Int 8" "0,1"
newline
bitfld.long 0x0 7. "ENABLE_HINT_7,Enable for Host Int 7" "0,1"
bitfld.long 0x0 6. "ENABLE_HINT_6,Enable for Host Int 6" "0,1"
bitfld.long 0x0 5. "ENABLE_HINT_5,Enable for Host Int 5" "0,1"
newline
bitfld.long 0x0 4. "ENABLE_HINT_4,Enable for Host Int 4" "0,1"
bitfld.long 0x0 3. "ENABLE_HINT_3,Enable for Host Int 3" "0,1"
bitfld.long 0x0 2. "ENABLE_HINT_2,Enable for Host Int 2" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_HINT_1,Enable for Host Int 1" "0,1"
bitfld.long 0x0 0. "ENABLE_HINT_0,Enable for Host Int 0" "0,1"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_ICSS_UART_UART_SLV"
base ad:0x28000
group.long 0x0++0x13
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_RBR_TBR,RBR_TBR Registers"
hexmask.long.word 0x0 8.--17. 1. "TBR_DATA,Transmit Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR_DATA,Receive Buffer Register"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_INT_EN,UART Interrupt Enable Register"
bitfld.long 0x4 3. "EDSSI,Enable for Modem Status Interrupt" "0,1"
bitfld.long 0x4 2. "ELSI,Enable for Receiver Line Status Interrupt" "0,1"
bitfld.long 0x4 1. "ETBEI,Enable for Transmitter Holding Register Empty Interrupt" "0,1"
bitfld.long 0x4 0. "ERBI,Enable for Receiver Data Available Interrupt" "0,1"
line.long 0x8 "PR1_ICSS_UART__UART_SLV__REGS_INT_FIFO,Interrupt Identification Register / FIFO Control Register"
bitfld.long 0x8 14.--15. "FCR_RXFIFTL,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x8 11. "FCR_DMAMODE1,DMA Mode Select" "0,1"
bitfld.long 0x8 10. "FCR_TXCLR,Transmitter FIFO Reset" "0,1"
bitfld.long 0x8 9. "FCR_RXCLR,Receiver FIFO Reset" "0,1"
bitfld.long 0x8 8. "FCR_FIFOEN,FIFO Enable Register" "0,1"
rbitfld.long 0x8 6.--7. "IIR_FIFOEN,FIFOs enabled" "0,1,2,3"
newline
rbitfld.long 0x8 1.--3. "IIR_INTID,Interrupt Type" "0,1,2,3,4,5,6,7"
rbitfld.long 0x8 0. "IIR_IPEND,Receiver Data Available Interrupt Pending" "0,1"
line.long 0xC "PR1_ICSS_UART__UART_SLV__REGS_LCTR,Line Control Register"
bitfld.long 0xC 7. "DLAB,Divisor Latch Access Bit" "0,1"
bitfld.long 0xC 6. "BC,Break Control" "0,1"
bitfld.long 0xC 5. "SP,Stick Parity" "0,1"
bitfld.long 0xC 4. "EPS,Even Parity Select" "0,1"
bitfld.long 0xC 3. "PEN,Parity Enable" "0,1"
bitfld.long 0xC 2. "STB,Number of Stop Bits" "0,1"
newline
bitfld.long 0xC 1. "WLS1,Word Length Select Bit 1" "0,1"
bitfld.long 0xC 0. "WLS0,Word Length Select Bit 0" "0,1"
line.long 0x10 "PR1_ICSS_UART__UART_SLV__REGS_MCTR,Modem Control Register"
bitfld.long 0x10 5. "AFE,Autoflow Control Enable" "0,1"
bitfld.long 0x10 4. "LOOP,LOOP Bit" "0,1"
bitfld.long 0x10 3. "OUT2,Out2 Bit" "0,1"
bitfld.long 0x10 2. "OUT1,Out1 Bit" "0,1"
bitfld.long 0x10 1. "RTS,Ready to Send" "0,1"
bitfld.long 0x10 0. "DTR,Data Terminal Ready" "0,1"
rgroup.long 0x14++0x7
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_LSR1,Line Status Register1"
bitfld.long 0x0 7. "RXFIFOE,Receiver FIFO Error" "0,1"
bitfld.long 0x0 6. "TEMT,Transmitter Empty" "0,1"
bitfld.long 0x0 5. "THRE,Transmitter Holding Register" "0,1"
bitfld.long 0x0 4. "BI,Break Interrupt" "0,1"
bitfld.long 0x0 3. "FE,Framing Error" "0,1"
bitfld.long 0x0 2. "PE,Parity Error" "0,1"
newline
bitfld.long 0x0 1. "OE,Overrun Error" "0,1"
bitfld.long 0x0 0. "DR,Data Ready" "0,1"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_MSR,Modem Status Register"
bitfld.long 0x4 7. "CD,Carrier Detect" "0,1"
bitfld.long 0x4 6. "RI,Ring Indicator" "0,1"
bitfld.long 0x4 5. "DSR,Data Set Ready" "0,1"
bitfld.long 0x4 4. "CTS,Clear To Send" "0,1"
bitfld.long 0x4 3. "DCD,Delta Carrier Detect" "0,1"
bitfld.long 0x4 2. "TERI,Trailing Edge Ring Indicator" "0,1"
newline
bitfld.long 0x4 1. "DDSR,Delta Set Ready" "0,1"
bitfld.long 0x4 0. "DCTS,Delta Clear To Send" "0,1"
group.long 0x1C++0xB
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_SCRATCH,UART Scratch Register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,Scratch Register Bits"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_DIVLSB,UART Divisor Register"
hexmask.long.byte 0x4 0.--7. 1. "DLL,Divisor Latch [LSB]"
line.long 0x8 "PR1_ICSS_UART__UART_SLV__REGS_DIVMSB,UART Divisor Register"
hexmask.long.byte 0x8 0.--7. 1. "DLH,Divisor Latch [MSB]"
rgroup.long 0x28++0x3
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_PID,Peripheral ID Register"
hexmask.long 0x0 0.--31. 1. "PID,"
group.long 0x30++0x7
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_PWR,UART PowerManagement and Emulation Register"
bitfld.long 0x0 15. "URST,UART Reset Bit" "0,1"
bitfld.long 0x0 14. "UTRST,UART Transmitter Reset Bit" "0,1"
bitfld.long 0x0 13. "URRST,UART Receiver Reset Bit" "0,1"
rbitfld.long 0x0 1. "RES,Free Bit" "0,1"
bitfld.long 0x0 0. "FREE,Free Bit" "0,1"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_MODE,UART Mode Definition Register"
bitfld.long 0x4 0. "OSM_SEL,Oversampling Mode Select" "0,1"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV"
base ad:0x30000
group.long 0x0++0x17
line.long 0x0 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_TSCNT,TIME STAMP COUNTER REGISTER"
hexmask.long 0x0 0.--31. 1. "TSCNT,ACTIVE 32 BIT COUNTER REGISTER WHICH IS USED AS THE CAPTURE TIME-BASE"
line.long 0x4 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CNTPHS,COUNTER PHASE CONTROL REGISTER"
hexmask.long 0x4 0.--31. 1. "CNTPHS,COUNTER PHASE VALUE REGISTER THAT CAN BE PROGRAMMED FOR PHASE LAG/LEAD THIS REGISTER SHADOWS TSCNT AND IS LOADED INTO TSCNT UPON EITHER A SYNCI EVENT OR S/W FORCE VIA A CONTROL BITUSED TO ACHIEVE PHASE CONTROL SYNC WITH RESPECT TO OTHER ECAP AND.."
line.long 0x8 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP1,CAPTURE-1 REGISTER"
hexmask.long 0x8 0.--31. 1. "CAP1,THIS REGISTER CAN BE LOADED [WRITTEN] BY :TIME-STAMP [IE COUNTER VALUE] DURING A CAPTURE EVENTS/W MAY BE USEFUL FOR TEST PURPOSES / INITIALISATIONAPRD SHADOW REGISTER [IE CAP3] WHEN USED IN APWM MODE"
line.long 0xC "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP2,CAPTURE-2 REGISTER"
hexmask.long 0xC 0.--31. 1. "CAP2,THIS REGISTER CAN BE LOADED [WRITTEN] BY :TIME-STAMP [IE COUNTER VALUE] DURING A CAPTURE EVENTS/W MAY BE USEFUL FOR TEST PURPOSESACMP SHADOW REGISTER [IE CAP4] WHEN USED IN APWM MODE"
line.long 0x10 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP3,CAPTURE-3 REGISTER"
hexmask.long 0x10 0.--31. 1. "CAP3,IN CMP MODE THIS IS A TIME-STAMP CAPTURE REGISTERIN APMW MODE THIS IS THE PERIOD SHADOW [APER] REGISTER USER UPDATES THE PWM PERIOD VALUE VIA THIS REGISTER IN THIS MODE CAP3 [APRD] SHADOWS CAP1"
line.long 0x14 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP4,CAPTURE-4 REGISTER"
hexmask.long 0x14 0.--31. 1. "CAP4,IN CMP MODE THIS IS A TIME-STAMP CAPTURE REGISTERIN APMW MODE THIS IS THE COMPARE SHADOW [ACMP] REGISTER USER UPDATES THE PWM COMPARE VALUE VIA THIS REGISTER IN THIS MODE CAP4 [ACMP] SHADOWS CAP2"
group.long 0x28++0x7
line.long 0x0 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECCTL2_ECCTL1,ECAP CONTROL REGISTER 1"
hexmask.long.byte 0x0 27.--31. 1. "FILTER,"
bitfld.long 0x0 26. "APWMPOL,APWM OUTPUT POLARITY SELECT:0OUTPUT IS ACTIVE HIGH [IE COMPARE VALUE DEFINES HIGH TIME]1OUTPUT IS ACTIVE LOW [IE COMPARE VALUE DEFINES LOW TIME]NOTE: THIS IS APPLICABLE ONLY IN APWM OPERATING MODE" "0,1"
bitfld.long 0x0 25. "CAP_APWM,CAP/APWM OPERATING MODE SELECT:0ECAP MODULE OPERATES IN CAPTURE MODETHIS MODE FORCES THE FOLLOWING CONFIGURATION:1] INHIBITS TSCNT RESETS VIA PRD_EQ EVENT2] INHIBITS SHADOW LOADS ON CAP1 &AMP" "0,1"
newline
bitfld.long 0x0 24. "SWSYNC,SOFTWARE FORCED COUNTER [TSCNT] SYNCING:0WRITING A ZERO HAS NO EFFECT WILL ALWAYS RETURN A ZERO1WRITING A ONE WILL FORCE A TSCNT SHADOW LOAD OF CURRENT ECAP MODULE AND ANY ECAP MODULES DOWN-STREAM PROVIDING THE SYNCO_SEL BITS ARE 0 0 AFTER WRITING.." "0,1"
bitfld.long 0x0 22.--23. "SYNCO_SEL,SYNC-OUT SELECT:0 0SELECT SYNC-IN EVENT TO BE THE SYNC-OUT SIGNAL [PASS THROUGH]0 1SELECT PRD_EQ EVENT TO BE THE SYNC-OUT SIGNAL1 0DISABLE SYNC OUT SIGNAL1 1DISABLE SYNC OUT SIGNALNOTE: SELECTION PRD_EQ IS MEANINGFUL ONLY IN APWM MODE  HOWEVER.." "0,1,2,3"
bitfld.long 0x0 21. "SYNCI_EN,COUNTER [TSCNT] SYNC-IN SELECT MODE:0DISABLE SYNC-IN OPTION1ENABLE COUNTER [TSCNT] TO BE LOADED FROM CNTPHS REGISTER UPON EITHER A SYNCI SIGNAL OR A S/W FORCE EVENT" "0,1"
newline
bitfld.long 0x0 20. "TSCNTSTP,COUNTER STOP [FREEZE] CONTROL:0COUNTER STOPPED1COUNTER FREE RUNNING" "0,1"
bitfld.long 0x0 19. "REARM_RESET,ONE-SHOT RE-ARMING  IE WAIT FOR STOP TRIGGER:WRITING A ONE ARMS THE ONE-SHOT SEQUENCE  IE:1] RESETS THE MOD4 COUNTER TO ZERO2] UN-FREEZES THE MOD4 COUNTER3] ENABLES CAPTURE REGISTER LOADSWRITING A ZERO HAS NO EFFECT ALWAYS RETURNS A 0NOTE:.." "0,1"
bitfld.long 0x0 17.--18. "STOPVALUE,STOP VALUE FOR ONE-SHOT MODE:THIS IS THE NUMBER [BETWEEN 1-4] OF CAPTURES ALLOWED TO OCCUR BEFORE THE CAP[1-4] REGISTERS ARE FROZEN  IECAPTURE SEQUENCE IS STOPPED0 0STOP AFTER CAPTURE EVENT 10 1STOP AFTER CAPTURE EVENT 21 0STOP AFTER CAPTURE.." "0,1,2,3"
newline
bitfld.long 0x0 16. "CONT_ONESHT,CONTINUOUS OR ONESHOT MODE CONTROL:[APPLICABLE ONLY IN CAPTURE MODE]0OPERATE IN CONTINUOUS MODE1OPERATE IN ONE-SHOT MODE" "0,1"
bitfld.long 0x0 15. "FREE,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1"
bitfld.long 0x0 14. "SOFT,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1"
newline
hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,EVENT FILTER PRESCALE SELECT:0 0 0 0 0DIVIDE BY 1 [IE NO PRESCALE  BY-PASS THE PRESCALER]0 0 0 0 1DIVIDE BY 20 0 0 1 0DIVIDE BY 40 0 0 1 1DIVIDE BY 60 0 1 0 0DIVIDE BY 80 0 1 0 1DIVIDE BY 10 1 1 1 1 0DIVIDE BY 601 1 1 1 1DIVIDE BY 62"
bitfld.long 0x0 8. "CAPLDEN,ENABLE LOADING OF CAP1-4 REGISTERS ON A CAPTURE EVENT:0DISABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME1ENABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME" "0,1"
bitfld.long 0x0 7. "CTRRST4,COUNTER RESET ON CAPTURE EVENT 4:0DO NOT RESET COUNTER ON CAPTURE EVENT 4 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 4 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,?"
newline
bitfld.long 0x0 6. "CAP4POL,CAPTURE EVENT 4 POLARITY SELECT:0CAPTURE EVENT 4 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 4 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
bitfld.long 0x0 5. "CTRRST3,COUNTER RESET ON CAPTURE EVENT 3:0DO NOT RESET COUNTER ON CAPTURE EVENT 3 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 3 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,?"
bitfld.long 0x0 4. "CAP3POL,CAPTURE EVENT 3 POLARITY SELECT:0CAPTURE EVENT 3 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 3 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
newline
bitfld.long 0x0 3. "CTRRST2,COUNTER RESET ON CAPTURE EVENT 2:0DO NOT RESET COUNTER ON CAPTURE EVENT 2 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 2 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,?"
bitfld.long 0x0 2. "CAP2POL,CAPTURE EVENT 2 POLARITY SELECT:0CAPTURE EVENT 2 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 2 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
bitfld.long 0x0 1. "CTRRST1,COUNTER RESET ON CAPTURE EVENT 1:0DO NOT RESET COUNTER ON CAPTURE EVENT 1 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 1 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,1: 0DO NOT RESET COUNTER ON CAPTURE EVENT 1.."
newline
bitfld.long 0x0 0. "CAP1POL,CAPTURE EVENT 1 POLARITY SELECT:0CAPTURE EVENT 1 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 1 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
line.long 0x4 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECFLG_ECEINT,ECAP INTERRUPT ENABLE REGISTER"
hexmask.long.byte 0x4 24.--31. 1. "FLAG_RESV0,"
rbitfld.long 0x4 23. "FLAG_CMPEQ,COMPARE EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE COMPARE REGISTER VALUE [ACMP]READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1"
rbitfld.long 0x4 22. "FLAG_PRDEQ,PERIOD EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE PERIOD REGISTER VALUE [APER] AND WAS RESETREADING A 0 INDICATES NO EVENT OCCURREDNOTES: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1"
newline
rbitfld.long 0x4 21. "FLAG_CNTOVF,COUNTER OVERFLOW STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] HAS MADE THE TRANSITION FROM FFFFFFFF 00000000READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ACTIVE IN CAP &AMP" "0,1"
rbitfld.long 0x4 20. "FLAG_CEVT4,CAPTURE EVENT 4 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FOURTH EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x4 19. "FLAG_CEVT3,CAPTURE EVENT 3 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE THIRD EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
newline
rbitfld.long 0x4 18. "FLAG_CEVT2,CAPTURE EVENT 2 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE SECOND EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x4 17. "FLAG_CEVT1,CAPTURE EVENT 1 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FIRST EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x4 16. "FLAG_INT,GLOBAL INTERRUPT STATUS FLAG: READING A 1 ON THIS BIT INDICATES THAT AN INTERRUPT WAS GENERATED FROM ONE OF THE FOLLOWING EVENTSREADING A 0 INDICATES NO INTERRUPT GENERATED" "0,1"
newline
hexmask.long.byte 0x4 8.--15. 1. "EN__RESV1,"
bitfld.long 0x4 7. "EN_CMPEQ,COMPARE EQUAL INTERRUPT ENABLE: 0DISABLED COMPARE EQUAL AS AN INTERRUPT SOURCE1ENABLE COMPARE EQUAL AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 6. "EN_PRDEQ,PERIOD EQUAL INTERRUPT ENABLE: 0DISABLED PERIOD EQUAL AS AN INTERRUPT SOURCE1ENABLE PERIOD EQUAL AS AN INTERRUPT SOURCE" "0,1"
newline
bitfld.long 0x4 5. "EN_CNTOVF,COUNTER OVERFLOW INTERRUPT ENABLE: 0DISABLED COUNTER OVERFLOW AS AN INTERRUPT SOURCE1ENABLE COUNTER OVERFLOW AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 4. "EN_CEVT4,CAPTURE EVENT 4 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 3. "EN_CEVT3,CAPTURE EVENT 3 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
newline
bitfld.long 0x4 2. "EN_CEVT2,CAPTURE EVENT 2 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 1. "EN_CEVT1,CAPTURE EVENT 1 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
rbitfld.long 0x4 0. "EN_RESV0," "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_PID,ECAP PERIPHERAL ID REGISTER"
hexmask.long 0x0 0.--31. 1. "REVID,"
tree.end
endif
tree.end
tree "PRU_ICSSG0_PR1_MII"
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG (PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG)"
base ad:0x30032000
group.long 0x0++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rxcfg0,MIIRXCFG0Register"
bitfld.long 0x0 9. "RX_EOF_SCLR_DIS0," "0,1"
bitfld.long 0x0 8. "RX_ERR_RAW0," "0,1"
bitfld.long 0x0 7. "RX_SFD_RAW0," "0,1"
newline
bitfld.long 0x0 6. "RX_AUTO_FWD_PRE0," "0,1"
bitfld.long 0x0 5. "RX_BYTE_SWAP0," "0,1"
bitfld.long 0x0 4. "RX_L2_EN0," "0,1"
newline
bitfld.long 0x0 3. "RX_MUX_SEL0," "0,1"
bitfld.long 0x0 2. "RX_CUT_PREAMBLE0," "0,1"
bitfld.long 0x0 1. "RX_DATA_RDY_MODE_DIS0," "0,1"
newline
bitfld.long 0x0 0. "RX_ENABLE0," "0,1"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rxcfg1,MIIRXCFG1Register"
bitfld.long 0x4 9. "RX_EOF_SCLR_DIS1," "0,1"
bitfld.long 0x4 8. "RX_ERR_RAW1," "0,1"
bitfld.long 0x4 7. "RX_SFD_RAW1," "0,1"
newline
bitfld.long 0x4 6. "RX_AUTO_FWD_PRE1," "0,1"
bitfld.long 0x4 5. "RX_BYTE_SWAP1," "0,1"
bitfld.long 0x4 4. "RX_L2_EN1," "0,1"
newline
bitfld.long 0x4 3. "RX_MUX_SEL1," "0,1"
bitfld.long 0x4 2. "RX_CUT_PREAMBLE1," "0,1"
bitfld.long 0x4 1. "RX_DATA_RDY_MODE_DIS1," "0,1"
newline
bitfld.long 0x4 0. "RX_ENABLE1," "0,1"
group.long 0x10++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_txcfg0,MIITXCFG0Register"
bitfld.long 0x0 28.--30. "TX_CLK_DELAY0," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 16.--25. 1. "TX_START_DELAY0,"
bitfld.long 0x0 12. "TX_IPG_WIRE_CLK_EN0," "0,1"
newline
bitfld.long 0x0 11. "TX_32_MODE_EN0," "0,1"
bitfld.long 0x0 10. "PRE_TX_AUTO_ESC_ERR0," "0,1"
bitfld.long 0x0 9. "PRE_TX_AUTO_SEQUENCE0," "0,1"
newline
bitfld.long 0x0 8. "TX_MUX_SEL0," "0,1"
bitfld.long 0x0 3. "TX_BYTE_SWAP0," "0,1"
bitfld.long 0x0 2. "TX_EN_MODE0," "0,1"
newline
bitfld.long 0x0 1. "TX_AUTO_PREAMBLE0," "0,1"
bitfld.long 0x0 0. "TX_ENABLE0," "0,1"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_txcfg1,MIITXCFG1Register"
bitfld.long 0x4 28.--30. "TX_CLK_DELAY1," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 16.--25. 1. "TX_START_DELAY1,"
bitfld.long 0x4 12. "TX_IPG_WIRE_CLK_EN1," "0,1"
newline
bitfld.long 0x4 11. "TX_32_MODE_EN1," "0,1"
bitfld.long 0x4 10. "PRE_TX_AUTO_ESC_ERR1," "0,1"
bitfld.long 0x4 9. "PRE_TX_AUTO_SEQUENCE1," "0,1"
newline
bitfld.long 0x4 8. "TX_MUX_SEL1," "0,1"
bitfld.long 0x4 3. "TX_BYTE_SWAP1," "0,1"
bitfld.long 0x4 2. "TX_EN_MODE1," "0,1"
newline
bitfld.long 0x4 1. "TX_AUTO_PREAMBLE1," "0,1"
bitfld.long 0x4 0. "TX_ENABLE1," "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_crc0,MIITXCRC0Register"
hexmask.long 0x0 0.--31. 1. "TX_CRC0,Transmit CRC for last packet"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_crc1,MIITXCRC1Register"
hexmask.long 0x4 0.--31. 1. "TX_CRC1,Transmit CRC for last packet"
group.long 0x30++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_ipg0,MIITXIPG0Register"
hexmask.long.word 0x0 0.--15. 1. "TX_IPG0,Transmit IPG"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_ipg1,MIITXIPG1Register"
hexmask.long.word 0x4 0.--15. 1. "TX_IPG1,Transmit IPG"
rgroup.long 0x38++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_prs0,MIIPortStatus0Register"
bitfld.long 0x0 1. "SYNC_PORT0_CRS,sync_port0_crs" "0,1"
bitfld.long 0x0 0. "SYNC_PORT0_COL,sync_port0_col" "0,1"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_prs1,MIIPortStatus1Register"
bitfld.long 0x4 1. "SYNC_PORT1_CRS,sync_port1_crs" "0,1"
bitfld.long 0x4 0. "SYNC_PORT1_COL,sync_port1_col" "0,1"
group.long 0x40++0x17
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_frms0,MIIRXFRMS0Register"
hexmask.long.word 0x0 16.--31. 1. "RX_MAX_FRM0,rx_max_frm0"
hexmask.long.word 0x0 0.--15. 1. "RX_MIN_FRM0,rx_min_frm0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_frms1,MIIRXFRMS1Register"
hexmask.long.word 0x4 16.--31. 1. "RX_MAX_FRM1,rx_max_frm1"
hexmask.long.word 0x4 0.--15. 1. "RX_MIN_FRM1,rx_min_frm1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_pcnt0,MIIRXPCNT0Register"
hexmask.long.byte 0x8 4.--8. 1. "RX_MAX_PCNT0,rx_max_pcnt0"
hexmask.long.byte 0x8 0.--3. 1. "RX_MIN_PCNT0,rx_min_pcnt0"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_pcnt1,MIIRXPCNT1Register"
hexmask.long.byte 0xC 4.--8. 1. "RX_MAX_PCNT1,rx_max_pcnt1"
hexmask.long.byte 0xC 0.--3. 1. "RX_MIN_PCNT1,rx_min_pcnt1"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_err0,MIIRXERR0Register"
bitfld.long 0x10 3. "RX_MAX_FRM_ERR0,rx_max_frm_err0" "0,1"
bitfld.long 0x10 2. "RX_MIN_FRM_ERR0,rx_min_frm_err0" "0,1"
bitfld.long 0x10 1. "RX_MAX_PCNT_ERR0,rx_max_pcnt_err0" "0,1"
newline
bitfld.long 0x10 0. "RX_MIN_PCNT_ERR0,rx_min_pcnt_err0" "0,1"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_err1,MIIRXERR1Register"
bitfld.long 0x14 3. "RX_MAX_FRM_ERR1,rx_max_frm_err1" "0,1"
bitfld.long 0x14 2. "RX_MIN_FRM_ERR1,rx_min_frm_err1" "0,1"
bitfld.long 0x14 1. "RX_MAX_PCNT_ERR1,rx_max_pcnt_err1" "0,1"
newline
bitfld.long 0x14 0. "RX_MIN_PCNT_ERR1,rx_min_pcnt_err1" "0,1"
rgroup.long 0x60++0xF
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_fifo_level0,MIIRXFIFOLEVEL0Register"
hexmask.long.byte 0x0 0.--7. 1. "RX_FIFO_LEVEL0,rx_fifo_level0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_fifo_level1,MIIRXFIFOLEVEL1Register"
hexmask.long.byte 0x4 0.--7. 1. "RX_FIFO_LEVEL1,rx_fifo_level1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_fifo_level0,MIIRXFIFOLEVEL0Register"
hexmask.long.byte 0x8 0.--7. 1. "TX_FIFO_LEVEL0,tx_fifo_level0"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_fifo_level1,MIIRXFIFOLEVEL1Register"
hexmask.long.byte 0xC 0.--7. 1. "TX_FIFO_LEVEL1,tx_fifo_level1"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G (PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G)"
base ad:0x30033000
group.long 0x8++0x23
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru0_0,"
hexmask.long 0x0 0.--31. 1. "MAC_PRU0_0,MAC pru0 DA3:DA0 Used for SAV and DA match"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru0_1,"
hexmask.long.word 0x4 0.--15. 1. "MAC_PRU0_1,MAC pru0 DA5:DA4 Used for SAV and DA match"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru1_0,"
hexmask.long 0x8 0.--31. 1. "MAC_PRU1_0,MAC pru1 DA3:DA0 Used for SAV and DA match"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru1_1,"
hexmask.long.word 0xC 0.--15. 1. "MAC_PRU1_1,MAC pru1 DA5:DA4 Used for SAV and DA match"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_interface_0,"
hexmask.long 0x10 0.--31. 1. "MAC_INF_0,MAC Host interface DA3:DA0 Used for SAV and DA match"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_interface_1,"
hexmask.long.word 0x14 0.--15. 1. "MAC_INF_1,MAC Host interface DA5:DA4 Used for SAV and DA match"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_preempt_cfg,"
hexmask.long.byte 0x18 24.--31. 1. "SMD_R,Response frame TAG"
hexmask.long.byte 0x18 16.--23. 1. "SMD_V,Verification frame TAG"
newline
hexmask.long.byte 0x18 8.--15. 1. "EXP_SMD,None preemptable frame start  or express frame"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_smdt1s_cfg,"
hexmask.long.byte 0x1C 24.--31. 1. "SMDT1S_3,SMDT1S3 pattern"
hexmask.long.byte 0x1C 16.--23. 1. "SMDT1S_2,SMDT1S2 pattern"
newline
hexmask.long.byte 0x1C 8.--15. 1. "SMDT1S_1,SMDT1S1 pattern"
hexmask.long.byte 0x1C 0.--7. 1. "SMDT1S_0,SMDT1S0 pattern"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_smdt1c_cfg,"
hexmask.long.byte 0x20 24.--31. 1. "SMDT1C_3,SMDT1C3 pattern"
hexmask.long.byte 0x20 16.--23. 1. "SMDT1C_2,SMDT1C2 pattern"
newline
hexmask.long.byte 0x20 8.--15. 1. "SMDT1C_1,SMDT1C1 pattern"
hexmask.long.byte 0x20 0.--7. 1. "SMDT1C_0,SMDT1C0 pattern"
group.long 0x34++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_frag_cnt_cfg,"
hexmask.long.byte 0x0 24.--31. 1. "FRAG_CNT_3,FRAG Cnt3 pattern"
hexmask.long.byte 0x0 16.--23. 1. "FRAG_CNT_2,FRAG Cnt2 pattern"
newline
hexmask.long.byte 0x0 8.--15. 1. "FRAG_CNT_1,FRAG Cnt1 pattern"
hexmask.long.byte 0x0 0.--7. 1. "FRAG_CNT_0,FRAG Cnt0 pattern"
group.long 0x40++0xF
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push0,"
hexmask.long.byte 0x0 24.--31. 1. "PA_STAT_PUSH3_0,pa stat push3"
hexmask.long.byte 0x0 16.--23. 1. "PA_STAT_PUSH2_0,pa stat push2"
newline
hexmask.long.byte 0x0 8.--15. 1. "PA_STAT_PUSH1_0,pa stat push1"
hexmask.long.byte 0x0 0.--7. 1. "PA_STAT_PUSH0_0,pa stat push0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push1,"
hexmask.long.byte 0x4 24.--31. 1. "PA_STAT_PUSH3_1,pa stat push3"
hexmask.long.byte 0x4 16.--23. 1. "PA_STAT_PUSH2_1,pa stat push2"
newline
hexmask.long.byte 0x4 8.--15. 1. "PA_STAT_PUSH1_1,pa stat push1"
hexmask.long.byte 0x4 0.--7. 1. "PA_STAT_PUSH0_1,pa stat push0"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push2,"
hexmask.long.byte 0x8 24.--31. 1. "PA_STAT_PUSH3_2,pa stat push3"
hexmask.long.byte 0x8 16.--23. 1. "PA_STAT_PUSH2_2,pa stat push2"
newline
hexmask.long.byte 0x8 8.--15. 1. "PA_STAT_PUSH1_2,pa stat push1"
hexmask.long.byte 0x8 0.--7. 1. "PA_STAT_PUSH0_2,pa stat push0"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push3,"
hexmask.long.byte 0xC 24.--31. 1. "PA_STAT_PUSH3_3,pa stat push3"
hexmask.long.byte 0xC 16.--23. 1. "PA_STAT_PUSH2_3,pa stat push2"
newline
hexmask.long.byte 0xC 8.--15. 1. "PA_STAT_PUSH1_3,pa stat push1"
hexmask.long.byte 0xC 0.--7. 1. "PA_STAT_PUSH0_3,pa stat push0"
group.long 0x60++0xAB
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_gen_cfg1,"
hexmask.long.tbyte 0x0 8.--25. 1. "SMEM_VLAN_OFFSET,SMEM VLAN FID table base address"
hexmask.long.byte 0x0 3.--6. 1. "FDB_HASH_SIZE,FDB hash size 0:64 1:128 2:256 3:512 4:1024 5:2048"
newline
bitfld.long 0x0 0.--1. "FDB_BUCKET_SIZE,FDB buket size 0:1 1:2 2:4 3:8" "0: 1,1: 2,2: 4,3: 8"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_gen_cfg2,"
hexmask.long.byte 0x4 9.--12. 1. "FDB_GEN_MODE_BYTE_EN,FDB General Mode Byte compare size 0 = 1 Byte  15 = 16 Bytes"
bitfld.long 0x4 8. "FDB_GEN_MODE_EN_BK1,FDB General Mode Enable Bank1 if set PRU0/PRU1/HOST will get disabled" "0,1"
newline
bitfld.long 0x4 7. "FDB_GEN_MODE_EN_BK0,FDB General Mode Enable Bank0 if set PRU0/PRU1/HOST will get disabled" "0,1"
bitfld.long 0x4 6. "FDB_VLAN_EN,FDB Global VLAN Enable" "0,1"
newline
bitfld.long 0x4 5. "FDB_HSR_EN,FDB Global HSR Enable note VLAN most be disabled" "0,1"
bitfld.long 0x4 2. "FDB_HOST_EN,FDB HOST Enable" "0,1"
newline
bitfld.long 0x4 1. "FDB_PRU1_EN,FDB PRU1 Enable" "0,1"
bitfld.long 0x4 0. "FDB_PRU0_EN,FDB PRU0 Enable" "0,1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_gen_status,"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_df_vlan,"
hexmask.long.word 0xC 16.--27. 1. "FDB_PRU1_DF_VLAN,FDB Default VLAN for PRU1"
hexmask.long.word 0xC 0.--11. 1. "FDB_PRU0_DF_VLAN,FDB Default VLAN for PRU0"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_da0,"
hexmask.long 0x10 0.--31. 1. "FDB_HOST_DA0,FDB HOST DA3:0"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_da1,"
hexmask.long.word 0x14 0.--15. 1. "FDB_HOST_DA1,FDB HOST DA5:4"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_sa0,"
hexmask.long 0x18 0.--31. 1. "FDB_HOST_SA0,FDB HOST SA3:0"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_vlan_sa1,"
hexmask.long.word 0x1C 16.--31. 1. "FDB_HOST_VLAN_HSR,FDB HOST VLAN[11:0] OR HSR[15:0]"
hexmask.long.word 0x1C 0.--15. 1. "FDB_HOST_SA1,FDB HOST SA5:4"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_start_len_pru0,"
hexmask.long.byte 0x20 16.--19. 1. "FT1_LEN,Defines the total number of Bytes Filter1 will check before Valid bit is set"
hexmask.long.word 0x20 0.--14. 1. "FT1_START,Byte count start for Filter1. Any wrt will clear all Filter1 Status Bits"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_cfg_pru0,"
bitfld.long 0x24 14.--15. "FT1_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 12.--13. "FT1_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x24 10.--11. "FT1_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 8.--9. "FT1_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x24 6.--7. "FT1_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 4.--5. "FT1_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x24 2.--3. "FT1_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 0.--1. "FT1_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da0_pru0,"
hexmask.long 0x28 0.--31. 1. "FT1_0_DA0,Filter1 DA4:DA1"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da1_pru0,"
hexmask.long.word 0x2C 0.--15. 1. "FT1_0_DA1,Filter1 DA6:DA5"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask0_pru0,"
hexmask.long 0x30 0.--31. 1. "FT1_0_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask1_pru0,"
hexmask.long.word 0x34 0.--15. 1. "FT1_0_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da0_pru0,"
hexmask.long 0x38 0.--31. 1. "FT1_1_DA0,Filter1 DA4:DA1"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da1_pru0,"
hexmask.long.word 0x3C 0.--15. 1. "FT1_1_DA1,Filter1 DA6:DA5"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask0_pru0,"
hexmask.long 0x40 0.--31. 1. "FT1_1_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask1_pru0,"
hexmask.long.word 0x44 0.--15. 1. "FT1_1_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da0_pru0,"
hexmask.long 0x48 0.--31. 1. "FT1_2_DA0,Filter1 DA4:DA1"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da1_pru0,"
hexmask.long.word 0x4C 0.--15. 1. "FT1_2_DA1,Filter1 DA6:DA5"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask0_pru0,"
hexmask.long 0x50 0.--31. 1. "FT1_2_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask1_pru0,"
hexmask.long.word 0x54 0.--15. 1. "FT1_2_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da0_pru0,"
hexmask.long 0x58 0.--31. 1. "FT1_3_DA0,Filter1 DA4:DA1"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da1_pru0,"
hexmask.long.word 0x5C 0.--15. 1. "FT1_3_DA1,Filter1 DA6:DA5"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask0_pru0,"
hexmask.long 0x60 0.--31. 1. "FT1_3_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask1_pru0,"
hexmask.long.word 0x64 0.--15. 1. "FT1_3_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da0_pru0,"
hexmask.long 0x68 0.--31. 1. "FT1_4_DA0,Filter1 DA4:DA1"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da1_pru0,"
hexmask.long.word 0x6C 0.--15. 1. "FT1_4_DA1,Filter1 DA6:DA5"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask0_pru0,"
hexmask.long 0x70 0.--31. 1. "FT1_4_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask1_pru0,"
hexmask.long.word 0x74 0.--15. 1. "FT1_4_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da0_pru0,"
hexmask.long 0x78 0.--31. 1. "FT1_5_DA0,Filter1 DA4:DA1"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da1_pru0,"
hexmask.long.word 0x7C 0.--15. 1. "FT1_5_DA1,Filter1 DA6:DA5"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask0_pru0,"
hexmask.long 0x80 0.--31. 1. "FT1_5_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask1_pru0,"
hexmask.long.word 0x84 0.--15. 1. "FT1_5_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da0_pru0,"
hexmask.long 0x88 0.--31. 1. "FT1_6_DA0,Filter1 DA4:DA1"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da1_pru0,"
hexmask.long.word 0x8C 0.--15. 1. "FT1_6_DA1,Filter1 DA6:DA5"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask0_pru0,"
hexmask.long 0x90 0.--31. 1. "FT1_6_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask1_pru0,"
hexmask.long.word 0x94 0.--15. 1. "FT1_6_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da0_pru0,"
hexmask.long 0x98 0.--31. 1. "FT1_7_DA0,Filter1 DA4:DA1"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da1_pru0,"
hexmask.long.word 0x9C 0.--15. 1. "FT1_7_DA1,Filter1 DA6:DA5"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask0_pru0,"
hexmask.long 0xA0 0.--31. 1. "FT1_7_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask1_pru0,"
hexmask.long.word 0xA4 0.--15. 1. "FT1_7_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_pru0,"
hexmask.long.word 0xA8 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x10C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x110++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_0_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_0_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_len_pru0,"
bitfld.long 0x8 24. "FT3_0_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_0_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_0_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_0_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_0_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_0_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_0_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x12C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x130++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_1_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_1_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_len_pru0,"
bitfld.long 0x8 24. "FT3_1_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_1_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_1_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_1_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_1_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_1_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_1_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x14C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x150++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_2_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_2_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_len_pru0,"
bitfld.long 0x8 24. "FT3_2_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_2_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_2_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_2_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_2_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_2_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_2_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x16C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x170++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_3_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_3_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_len_pru0,"
bitfld.long 0x8 24. "FT3_3_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_3_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_3_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_3_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_3_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_3_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_3_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x18C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x190++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_4_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_4_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_len_pru0,"
bitfld.long 0x8 24. "FT3_4_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_4_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_4_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_4_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_4_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_4_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_4_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1AC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x1B0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_5_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_5_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_len_pru0,"
bitfld.long 0x8 24. "FT3_5_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_5_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_5_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_5_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_5_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_5_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_5_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1CC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x1D0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_6_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_6_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_len_pru0,"
bitfld.long 0x8 24. "FT3_6_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_6_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_6_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_6_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_6_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_6_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_6_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1EC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x1F0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_7_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_7_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_len_pru0,"
bitfld.long 0x8 24. "FT3_7_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_7_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_7_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_7_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_7_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_7_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_7_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x20C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x210++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_8_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_8_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_len_pru0,"
bitfld.long 0x8 24. "FT3_8_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_8_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_8_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_8_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_8_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_8CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_8_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_8_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x22C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x230++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_9_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_9_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_len_pru0,"
bitfld.long 0x8 24. "FT3_9_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_9_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_9_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_9_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_9_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_9CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_9_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_9_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x24C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x250++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_10_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_10_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_len_pru0,"
bitfld.long 0x8 24. "FT3_10_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_10_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_10_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_10_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_10_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_10CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_10_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_10_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x26C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x270++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_11_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_11_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_len_pru0,"
bitfld.long 0x8 24. "FT3_11_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_11_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_11_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_11_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_11_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_11CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_11_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_11_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x28C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x290++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_12_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_12_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_len_pru0,"
bitfld.long 0x8 24. "FT3_12_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_12_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_12_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_12_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_12_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_12CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_12_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_12_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2AC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x2B0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_13_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_13_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_len_pru0,"
bitfld.long 0x8 24. "FT3_13_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_13_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_13_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_13_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_13_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_13CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_13_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_13_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2CC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x2D0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_14_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_14_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_len_pru0,"
bitfld.long 0x8 24. "FT3_14_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_14_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_14_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_14_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_14_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_14CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_14_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_14_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2EC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x2F0++0x3E7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_15_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_15_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_len_pru0,"
bitfld.long 0x8 24. "FT3_15_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_15_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_15_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_15_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_15_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_15CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_15_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_15_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p0_pru0,"
hexmask.long 0x18 0.--31. 1. "FT3_0_P0,Filter3 P4:P1"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p1_pru0,"
hexmask.long 0x1C 0.--31. 1. "FT3_0_P1,Filter3 P8:P5"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask0_pru0,"
hexmask.long 0x20 0.--31. 1. "FT3_0_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask1_pru0,"
hexmask.long 0x24 0.--31. 1. "FT3_0_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p0_pru0,"
hexmask.long 0x28 0.--31. 1. "FT3_1_P0,Filter3 P4:P1"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p1_pru0,"
hexmask.long 0x2C 0.--31. 1. "FT3_1_P1,Filter3 P8:P5"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask0_pru0,"
hexmask.long 0x30 0.--31. 1. "FT3_1_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask1_pru0,"
hexmask.long 0x34 0.--31. 1. "FT3_1_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p0_pru0,"
hexmask.long 0x38 0.--31. 1. "FT3_2_P0,Filter3 P4:P1"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p1_pru0,"
hexmask.long 0x3C 0.--31. 1. "FT3_2_P1,Filter3 P8:P5"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask0_pru0,"
hexmask.long 0x40 0.--31. 1. "FT3_2_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask1_pru0,"
hexmask.long 0x44 0.--31. 1. "FT3_2_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p0_pru0,"
hexmask.long 0x48 0.--31. 1. "FT3_3_P0,Filter3 P4:P1"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p1_pru0,"
hexmask.long 0x4C 0.--31. 1. "FT3_3_P1,Filter3 P8:P5"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask0_pru0,"
hexmask.long 0x50 0.--31. 1. "FT3_3_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask1_pru0,"
hexmask.long 0x54 0.--31. 1. "FT3_3_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p0_pru0,"
hexmask.long 0x58 0.--31. 1. "FT3_4_P0,Filter3 P4:P1"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p1_pru0,"
hexmask.long 0x5C 0.--31. 1. "FT3_4_P1,Filter3 P8:P5"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask0_pru0,"
hexmask.long 0x60 0.--31. 1. "FT3_4_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask1_pru0,"
hexmask.long 0x64 0.--31. 1. "FT3_4_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p0_pru0,"
hexmask.long 0x68 0.--31. 1. "FT3_5_P0,Filter3 P4:P1"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p1_pru0,"
hexmask.long 0x6C 0.--31. 1. "FT3_5_P1,Filter3 P8:P5"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask0_pru0,"
hexmask.long 0x70 0.--31. 1. "FT3_5_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask1_pru0,"
hexmask.long 0x74 0.--31. 1. "FT3_5_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p0_pru0,"
hexmask.long 0x78 0.--31. 1. "FT3_6_P0,Filter3 P4:P1"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p1_pru0,"
hexmask.long 0x7C 0.--31. 1. "FT3_6_P1,Filter3 P8:P5"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask0_pru0,"
hexmask.long 0x80 0.--31. 1. "FT3_6_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask1_pru0,"
hexmask.long 0x84 0.--31. 1. "FT3_6_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p0_pru0,"
hexmask.long 0x88 0.--31. 1. "FT3_7_P0,Filter3 P4:P1"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p1_pru0,"
hexmask.long 0x8C 0.--31. 1. "FT3_7_P1,Filter3 P8:P5"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask0_pru0,"
hexmask.long 0x90 0.--31. 1. "FT3_7_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask1_pru0,"
hexmask.long 0x94 0.--31. 1. "FT3_7_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p0_pru0,"
hexmask.long 0x98 0.--31. 1. "FT3_8_P0,Filter3 P4:P1"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p1_pru0,"
hexmask.long 0x9C 0.--31. 1. "FT3_8_P1,Filter3 P8:P5"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask0_pru0,"
hexmask.long 0xA0 0.--31. 1. "FT3_8_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask1_pru0,"
hexmask.long 0xA4 0.--31. 1. "FT3_8_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p0_pru0,"
hexmask.long 0xA8 0.--31. 1. "FT3_9_P0,Filter3 P4:P1"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p1_pru0,"
hexmask.long 0xAC 0.--31. 1. "FT3_9_P1,Filter3 P8:P5"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask0_pru0,"
hexmask.long 0xB0 0.--31. 1. "FT3_9_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask1_pru0,"
hexmask.long 0xB4 0.--31. 1. "FT3_9_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p0_pru0,"
hexmask.long 0xB8 0.--31. 1. "FT3_10_P0,Filter3 P4:P1"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p1_pru0,"
hexmask.long 0xBC 0.--31. 1. "FT3_10_P1,Filter3 P8:P5"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask0_pru0,"
hexmask.long 0xC0 0.--31. 1. "FT3_10_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask1_pru0,"
hexmask.long 0xC4 0.--31. 1. "FT3_10_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p0_pru0,"
hexmask.long 0xC8 0.--31. 1. "FT3_11_P0,Filter3 P4:P1"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p1_pru0,"
hexmask.long 0xCC 0.--31. 1. "FT3_11_P1,Filter3 P8:P5"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask0_pru0,"
hexmask.long 0xD0 0.--31. 1. "FT3_11_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask1_pru0,"
hexmask.long 0xD4 0.--31. 1. "FT3_11_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p0_pru0,"
hexmask.long 0xD8 0.--31. 1. "FT3_12_P0,Filter3 P4:P1"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p1_pru0,"
hexmask.long 0xDC 0.--31. 1. "FT3_12_P1,Filter3 P8:P5"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask0_pru0,"
hexmask.long 0xE0 0.--31. 1. "FT3_12_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask1_pru0,"
hexmask.long 0xE4 0.--31. 1. "FT3_12_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p0_pru0,"
hexmask.long 0xE8 0.--31. 1. "FT3_13_P0,Filter3 P4:P1"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p1_pru0,"
hexmask.long 0xEC 0.--31. 1. "FT3_13_P1,Filter3 P8:P5"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask0_pru0,"
hexmask.long 0xF0 0.--31. 1. "FT3_13_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask1_pru0,"
hexmask.long 0xF4 0.--31. 1. "FT3_13_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p0_pru0,"
hexmask.long 0xF8 0.--31. 1. "FT3_14_P0,Filter3 P4:P1"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p1_pru0,"
hexmask.long 0xFC 0.--31. 1. "FT3_14_P1,Filter3 P8:P5"
line.long 0x100 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask0_pru0,"
hexmask.long 0x100 0.--31. 1. "FT3_14_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x104 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask1_pru0,"
hexmask.long 0x104 0.--31. 1. "FT3_14_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x108 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p0_pru0,"
hexmask.long 0x108 0.--31. 1. "FT3_15_P0,Filter3 P4:P1"
line.long 0x10C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p1_pru0,"
hexmask.long 0x10C 0.--31. 1. "FT3_15_P1,Filter3 P8:P5"
line.long 0x110 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask0_pru0,"
hexmask.long 0x110 0.--31. 1. "FT3_15_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x114 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask1_pru0,"
hexmask.long 0x114 0.--31. 1. "FT3_15_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x118 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft_rx_ptr_pru0,"
hexmask.long 0x118 0.--31. 1. "FT_RX_PTR_PRU0,RX current filter Byte Count"
line.long 0x11C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_and_en_pru0,"
hexmask.long 0x11C 0.--31. 1. "RX_CLASS0_AND_EN,rx class and enabels"
line.long 0x120 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_or_en_pru0,"
hexmask.long 0x120 0.--31. 1. "RX_CLASS0_OR_EN,rx class or enabels"
line.long 0x124 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_and_en_pru0,"
hexmask.long 0x124 0.--31. 1. "RX_CLASS1_AND_EN,rx class and enabels"
line.long 0x128 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_or_en_pru0,"
hexmask.long 0x128 0.--31. 1. "RX_CLASS1_OR_EN,rx class or enabels"
line.long 0x12C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_and_en_pru0,"
hexmask.long 0x12C 0.--31. 1. "RX_CLASS2_AND_EN,rx class and enabels"
line.long 0x130 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_or_en_pru0,"
hexmask.long 0x130 0.--31. 1. "RX_CLASS2_OR_EN,rx class or enabels"
line.long 0x134 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_and_en_pru0,"
hexmask.long 0x134 0.--31. 1. "RX_CLASS3_AND_EN,rx class and enabels"
line.long 0x138 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_or_en_pru0,"
hexmask.long 0x138 0.--31. 1. "RX_CLASS3_OR_EN,rx class or enabels"
line.long 0x13C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_and_en_pru0,"
hexmask.long 0x13C 0.--31. 1. "RX_CLASS4_AND_EN,rx class and enabels"
line.long 0x140 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_or_en_pru0,"
hexmask.long 0x140 0.--31. 1. "RX_CLASS4_OR_EN,rx class or enabels"
line.long 0x144 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_and_en_pru0,"
hexmask.long 0x144 0.--31. 1. "RX_CLASS5_AND_EN,rx class and enabels"
line.long 0x148 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_or_en_pru0,"
hexmask.long 0x148 0.--31. 1. "RX_CLASS5_OR_EN,rx class or enabels"
line.long 0x14C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_and_en_pru0,"
hexmask.long 0x14C 0.--31. 1. "RX_CLASS6_AND_EN,rx class and enabels"
line.long 0x150 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_or_en_pru0,"
hexmask.long 0x150 0.--31. 1. "RX_CLASS6_OR_EN,rx class or enabels"
line.long 0x154 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_and_en_pru0,"
hexmask.long 0x154 0.--31. 1. "RX_CLASS7_AND_EN,rx class and enabels"
line.long 0x158 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_or_en_pru0,"
hexmask.long 0x158 0.--31. 1. "RX_CLASS7_OR_EN,rx class or enabels"
line.long 0x15C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_and_en_pru0,"
hexmask.long 0x15C 0.--31. 1. "RX_CLASS8_AND_EN,rx class and enabels"
line.long 0x160 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_or_en_pru0,"
hexmask.long 0x160 0.--31. 1. "RX_CLASS8_OR_EN,rx class or enabels"
line.long 0x164 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_and_en_pru0,"
hexmask.long 0x164 0.--31. 1. "RX_CLASS9_AND_EN,rx class and enabels"
line.long 0x168 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_or_en_pru0,"
hexmask.long 0x168 0.--31. 1. "RX_CLASS9_OR_EN,rx class or enabels"
line.long 0x16C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_and_en_pru0,"
hexmask.long 0x16C 0.--31. 1. "RX_CLASS10_AND_EN,rx class and enabels"
line.long 0x170 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_or_en_pru0,"
hexmask.long 0x170 0.--31. 1. "RX_CLASS10_OR_EN,rx class or enabels"
line.long 0x174 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_and_en_pru0,"
hexmask.long 0x174 0.--31. 1. "RX_CLASS11_AND_EN,rx class and enabels"
line.long 0x178 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_or_en_pru0,"
hexmask.long 0x178 0.--31. 1. "RX_CLASS11_OR_EN,rx class or enabels"
line.long 0x17C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_and_en_pru0,"
hexmask.long 0x17C 0.--31. 1. "RX_CLASS12_AND_EN,rx class and enabels"
line.long 0x180 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_or_en_pru0,"
hexmask.long 0x180 0.--31. 1. "RX_CLASS12_OR_EN,rx class or enabels"
line.long 0x184 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_and_en_pru0,"
hexmask.long 0x184 0.--31. 1. "RX_CLASS13_AND_EN,rx class and enabels"
line.long 0x188 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_or_en_pru0,"
hexmask.long 0x188 0.--31. 1. "RX_CLASS13_OR_EN,rx class or enabels"
line.long 0x18C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_and_en_pru0,"
hexmask.long 0x18C 0.--31. 1. "RX_CLASS14_AND_EN,rx class and enabels"
line.long 0x190 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_or_en_pru0,"
hexmask.long 0x190 0.--31. 1. "RX_CLASS14_OR_EN,rx class or enabels"
line.long 0x194 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_and_en_pru0,"
hexmask.long 0x194 0.--31. 1. "RX_CLASS15_AND_EN,rx class and enabels"
line.long 0x198 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_or_en_pru0,"
hexmask.long 0x198 0.--31. 1. "RX_CLASS15_OR_EN,rx class or enabels"
line.long 0x19C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg1_pru0,"
bitfld.long 0x19C 30.--31. "RX_CLASS15_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 28.--29. "RX_CLASS14_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 26.--27. "RX_CLASS13_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 24.--25. "RX_CLASS12_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 22.--23. "RX_CLASS11_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 20.--21. "RX_CLASS10_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 18.--19. "RX_CLASS9_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 16.--17. "RX_CLASS8_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 14.--15. "RX_CLASS7_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 12.--13. "RX_CLASS6_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 10.--11. "RX_CLASS5_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 8.--9. "RX_CLASS4_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 6.--7. "RX_CLASS3_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 4.--5. "RX_CLASS2_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 2.--3. "RX_CLASS1_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 0.--1. "RX_CLASS0_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
line.long 0x1A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg2_pru0,"
hexmask.long.word 0x1A0 16.--31. 1. "RX_CLASS_OR_NV,rx class or nv enable"
hexmask.long.word 0x1A0 0.--15. 1. "RX_CLASS_AND_NV,rx class and nv enable"
line.long 0x1A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates0_pru0,"
bitfld.long 0x1A4 8. "RX_RED_PHASE_EN0,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A4 6. "RX_ALLOW_MASK0,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A4 5. "RX_CLASS_RAW_MASK0,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A4 4. "RX_PHASE_MASK0,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A4 0.--2. "RX_RATE_GATE_SEL0,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates1_pru0,"
bitfld.long 0x1A8 8. "RX_RED_PHASE_EN1,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A8 6. "RX_ALLOW_MASK1,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A8 5. "RX_CLASS_RAW_MASK1,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A8 4. "RX_PHASE_MASK1,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A8 0.--2. "RX_RATE_GATE_SEL1,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates2_pru0,"
bitfld.long 0x1AC 8. "RX_RED_PHASE_EN2,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1AC 6. "RX_ALLOW_MASK2,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1AC 5. "RX_CLASS_RAW_MASK2,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1AC 4. "RX_PHASE_MASK2,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1AC 0.--2. "RX_RATE_GATE_SEL2,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates3_pru0,"
bitfld.long 0x1B0 8. "RX_RED_PHASE_EN3,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B0 6. "RX_ALLOW_MASK3,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B0 5. "RX_CLASS_RAW_MASK3,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B0 4. "RX_PHASE_MASK3,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B0 0.--2. "RX_RATE_GATE_SEL3,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates4_pru0,"
bitfld.long 0x1B4 8. "RX_RED_PHASE_EN4,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B4 6. "RX_ALLOW_MASK4,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B4 5. "RX_CLASS_RAW_MASK4,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B4 4. "RX_PHASE_MASK4,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B4 0.--2. "RX_RATE_GATE_SEL4,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates5_pru0,"
bitfld.long 0x1B8 8. "RX_RED_PHASE_EN5,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B8 6. "RX_ALLOW_MASK5,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B8 5. "RX_CLASS_RAW_MASK5,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B8 4. "RX_PHASE_MASK5,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B8 0.--2. "RX_RATE_GATE_SEL5,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates6_pru0,"
bitfld.long 0x1BC 8. "RX_RED_PHASE_EN6,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1BC 6. "RX_ALLOW_MASK6,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1BC 5. "RX_CLASS_RAW_MASK6,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1BC 4. "RX_PHASE_MASK6,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1BC 0.--2. "RX_RATE_GATE_SEL6,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates7_pru0,"
bitfld.long 0x1C0 8. "RX_RED_PHASE_EN7,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C0 6. "RX_ALLOW_MASK7,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C0 5. "RX_CLASS_RAW_MASK7,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C0 4. "RX_PHASE_MASK7,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C0 0.--2. "RX_RATE_GATE_SEL7,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates8_pru0,"
bitfld.long 0x1C4 8. "RX_RED_PHASE_EN8,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C4 6. "RX_ALLOW_MASK8,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C4 5. "RX_CLASS_RAW_MASK8,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C4 4. "RX_PHASE_MASK8,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C4 0.--2. "RX_RATE_GATE_SEL8,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates9_pru0,"
bitfld.long 0x1C8 8. "RX_RED_PHASE_EN9,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C8 6. "RX_ALLOW_MASK9,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C8 5. "RX_CLASS_RAW_MASK9,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C8 4. "RX_PHASE_MASK9,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C8 0.--2. "RX_RATE_GATE_SEL9,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates10_pru0,"
bitfld.long 0x1CC 8. "RX_RED_PHASE_EN10,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1CC 6. "RX_ALLOW_MASK10,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1CC 5. "RX_CLASS_RAW_MASK10,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1CC 4. "RX_PHASE_MASK10,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1CC 0.--2. "RX_RATE_GATE_SEL10,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates11_pru0,"
bitfld.long 0x1D0 8. "RX_RED_PHASE_EN11,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D0 6. "RX_ALLOW_MASK11,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 5. "RX_CLASS_RAW_MASK11,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D0 4. "RX_PHASE_MASK11,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 0.--2. "RX_RATE_GATE_SEL11,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates12_pru0,"
bitfld.long 0x1D4 8. "RX_RED_PHASE_EN12,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D4 6. "RX_ALLOW_MASK12,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D4 5. "RX_CLASS_RAW_MASK12,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D4 4. "RX_PHASE_MASK12,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D4 0.--2. "RX_RATE_GATE_SEL12,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates13_pru0,"
bitfld.long 0x1D8 8. "RX_RED_PHASE_EN13,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D8 6. "RX_ALLOW_MASK13,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D8 5. "RX_CLASS_RAW_MASK13,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D8 4. "RX_PHASE_MASK13,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D8 0.--2. "RX_RATE_GATE_SEL13,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates14_pru0,"
bitfld.long 0x1DC 8. "RX_RED_PHASE_EN14,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1DC 6. "RX_ALLOW_MASK14,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1DC 5. "RX_CLASS_RAW_MASK14,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1DC 4. "RX_PHASE_MASK14,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1DC 0.--2. "RX_RATE_GATE_SEL14,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates15_pru0,"
bitfld.long 0x1E0 8. "RX_RED_PHASE_EN15,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1E0 6. "RX_ALLOW_MASK15,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 5. "RX_CLASS_RAW_MASK15,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1E0 4. "RX_PHASE_MASK15,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 0.--2. "RX_RATE_GATE_SEL15,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_green_pru0,"
rbitfld.long 0x1E4 4. "RX_GREEN_VAL,0 RED 1 GREEN status" "0,1"
hexmask.long.byte 0x1E4 0.--3. 1. "RX_GREEN_CMP_SEL,define which IEP CMP start green"
line.long 0x1E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_sa_hash_pru0,"
hexmask.long.word 0x1E8 0.--9. 1. "SA_HASH_SEED,SA Hash Seed"
line.long 0x1EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_pru0,"
hexmask.long.word 0x1EC 0.--9. 1. "CONN_HASH_SEED,Connection Hash Seed"
line.long 0x1F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_start_pru0,"
hexmask.long.word 0x1F0 0.--14. 1. "CONN_HASH_START,Connection Hash Start which 4 Bytes to hash"
line.long 0x1F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg0_pru0,"
hexmask.long 0x1F4 0.--31. 1. "RX_RATE_CIR_IDLE0,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg1_pru0,"
hexmask.long 0x1F8 0.--31. 1. "RX_RATE_CIR_IDLE1,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg2_pru0,"
hexmask.long 0x1FC 0.--31. 1. "RX_RATE_CIR_IDLE2,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x200 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg3_pru0,"
hexmask.long 0x200 0.--31. 1. "RX_RATE_CIR_IDLE3,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x204 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg4_pru0,"
hexmask.long 0x204 0.--31. 1. "RX_RATE_CIR_IDLE4,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x208 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg5_pru0,"
hexmask.long 0x208 0.--31. 1. "RX_RATE_CIR_IDLE5,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x20C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg6_pru0,"
hexmask.long 0x20C 0.--31. 1. "RX_RATE_CIR_IDLE6,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x210 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg7_pru0,"
hexmask.long 0x210 0.--31. 1. "RX_RATE_CIR_IDLE7,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x214 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel0_pru0,"
hexmask.long.byte 0x214 24.--29. 1. "RX_RATE_SRC_SEL3,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 16.--21. 1. "RX_RATE_SRC_SEL2,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x214 8.--13. 1. "RX_RATE_SRC_SEL1,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 0.--5. 1. "RX_RATE_SRC_SEL0,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x218 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel1_pru0,"
hexmask.long.byte 0x218 24.--29. 1. "RX_RATE_SRC_SEL7,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 16.--21. 1. "RX_RATE_SRC_SEL6,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x218 8.--13. 1. "RX_RATE_SRC_SEL5,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 0.--5. 1. "RX_RATE_SRC_SEL4,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x21C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_0_pru0,"
hexmask.long 0x21C 0.--31. 1. "TX_RATE_CIR_IDLE0,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x220 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_0_pru0,"
rbitfld.long 0x220 17. "TX_RATE_ALLOW0,TX Rate Pkt Enable" "0,1"
bitfld.long 0x220 16. "TX_RATE_EN0,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x220 0.--15. 1. "TX_RATE_LEN0,TX Rate Pkt Length"
line.long 0x224 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_1_pru0,"
hexmask.long 0x224 0.--31. 1. "TX_RATE_CIR_IDLE1,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x228 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_1_pru0,"
rbitfld.long 0x228 17. "TX_RATE_ALLOW1,TX Rate Pkt Enable" "0,1"
bitfld.long 0x228 16. "TX_RATE_EN1,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x228 0.--15. 1. "TX_RATE_LEN1,TX Rate Pkt Length"
line.long 0x22C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_2_pru0,"
hexmask.long 0x22C 0.--31. 1. "TX_RATE_CIR_IDLE2,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x230 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_2_pru0,"
rbitfld.long 0x230 17. "TX_RATE_ALLOW2,TX Rate Pkt Enable" "0,1"
bitfld.long 0x230 16. "TX_RATE_EN2,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x230 0.--15. 1. "TX_RATE_LEN2,TX Rate Pkt Length"
line.long 0x234 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_3_pru0,"
hexmask.long 0x234 0.--31. 1. "TX_RATE_CIR_IDLE3,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x238 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_3_pru0,"
rbitfld.long 0x238 17. "TX_RATE_ALLOW3,TX Rate Pkt Enable" "0,1"
bitfld.long 0x238 16. "TX_RATE_EN3,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x238 0.--15. 1. "TX_RATE_LEN3,TX Rate Pkt Length"
line.long 0x23C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_4_pru0,"
hexmask.long 0x23C 0.--31. 1. "TX_RATE_CIR_IDLE4,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x240 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_4_pru0,"
rbitfld.long 0x240 17. "TX_RATE_ALLOW4,TX Rate Pkt Enable" "0,1"
bitfld.long 0x240 16. "TX_RATE_EN4,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x240 0.--15. 1. "TX_RATE_LEN4,TX Rate Pkt Length"
line.long 0x244 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_5_pru0,"
hexmask.long 0x244 0.--31. 1. "TX_RATE_CIR_IDLE5,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x248 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_5_pru0,"
rbitfld.long 0x248 17. "TX_RATE_ALLOW5,TX Rate Pkt Enable" "0,1"
bitfld.long 0x248 16. "TX_RATE_EN5,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x248 0.--15. 1. "TX_RATE_LEN5,TX Rate Pkt Length"
line.long 0x24C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_6_pru0,"
hexmask.long 0x24C 0.--31. 1. "TX_RATE_CIR_IDLE6,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x250 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_6_pru0,"
rbitfld.long 0x250 17. "TX_RATE_ALLOW6,TX Rate Pkt Enable" "0,1"
bitfld.long 0x250 16. "TX_RATE_EN6,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x250 0.--15. 1. "TX_RATE_LEN6,TX Rate Pkt Length"
line.long 0x254 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_7_pru0,"
hexmask.long 0x254 0.--31. 1. "TX_RATE_CIR_IDLE7,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x258 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_7_pru0,"
rbitfld.long 0x258 17. "TX_RATE_ALLOW7,TX Rate Pkt Enable" "0,1"
bitfld.long 0x258 16. "TX_RATE_EN7,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x258 0.--15. 1. "TX_RATE_LEN7,TX Rate Pkt Length"
line.long 0x25C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_good_pru0,"
hexmask.long 0x25C 0.--31. 1. "RX_GOOD_FRM_CNT,RX Good Frame Count Inc on none min err max err crc err odd err  Wrt subtracts"
line.long 0x260 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bc_pru0,"
hexmask.long.word 0x260 0.--15. 1. "RX_BC_FRM_CNT,RX BC Frame Count Inc on BC type  Wrt subtracts"
line.long 0x264 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mc_pru0,"
hexmask.long.word 0x264 0.--15. 1. "RX_MC_FRM_CNT,RX MC Frame Count Inc on MC type  Wrt subtracts"
line.long 0x268 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_crc_err_pru0,"
hexmask.long.word 0x268 0.--15. 1. "RX_CRC_ERR_FRM_CNT,RX CRC Err Frame Count Inc on crc err  Wrt subtracts"
line.long 0x26C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mii_err_pru0,"
hexmask.long.word 0x26C 0.--15. 1. "RX_MII_ERR_FRM_CNT,RX MII Err Frame Count Inc on mii sgmii rgmii err  Wrt subtracts"
line.long 0x270 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_odd_err_pru0,"
hexmask.long.word 0x270 0.--15. 1. "RX_ODD_ERR_FRM_CNT,RX Odd Nibble Frame Count Inc on odd nibble mii  Wrt subtracts"
line.long 0x274 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_size_pru0,"
hexmask.long.word 0x274 0.--15. 1. "RX_MAX_SIZE_FRM,RX MAX Size Frame Count Limit"
line.long 0x278 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_err_pru0,"
hexmask.long.word 0x278 0.--15. 1. "RX_MAX_ERR_FRM_CNT,RX MAX Size Err Frame Count Inc if > than Limit  Wrt subtracts"
line.long 0x27C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_size_pru0,"
hexmask.long.word 0x27C 0.--15. 1. "RX_MIN_SIZE_FRM,RX MIN Size Frame Limit"
line.long 0x280 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_err_pru0,"
hexmask.long.word 0x280 0.--15. 1. "RX_MIN_ERR_FRM_CNT,RX MIN Size Frame Count Inc if < than limit  Wrt subtracts"
line.long 0x284 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_overrun_err_pru0,"
hexmask.long.word 0x284 0.--15. 1. "RX_OVERRUN_ERR_FRM_CNT,RX L1 FIFO overflow Frame Count Inc on overflow event  Wrt subtracts"
line.long 0x288 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class0_hit_pru0,"
hexmask.long 0x288 0.--31. 1. "RX_STAT_CLASS0_PRU0,RX Class0 Hit Count  Wrt subtracts"
line.long 0x28C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class1_hit_pru0,"
hexmask.long 0x28C 0.--31. 1. "RX_STAT_CLASS1_PRU0,RX Class1 Hit Count  Wrt subtracts"
line.long 0x290 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class2_hit_pru0,"
hexmask.long 0x290 0.--31. 1. "RX_STAT_CLASS2_PRU0,RX Class2 Hit Count  Wrt subtracts"
line.long 0x294 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class3_hit_pru0,"
hexmask.long 0x294 0.--31. 1. "RX_STAT_CLASS3_PRU0,RX Class3 Hit Count  Wrt subtracts"
line.long 0x298 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class4_hit_pru0,"
hexmask.long 0x298 0.--31. 1. "RX_STAT_CLASS4_PRU0,RX Class4 Hit Count  Wrt subtracts"
line.long 0x29C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class5_hit_pru0,"
hexmask.long 0x29C 0.--31. 1. "RX_STAT_CLASS5_PRU0,RX Class5 Hit Count  Wrt subtracts"
line.long 0x2A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class6_hit_pru0,"
hexmask.long 0x2A0 0.--31. 1. "RX_STAT_CLASS6_PRU0,RX Class6 Hit Count  Wrt subtracts"
line.long 0x2A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class7_hit_pru0,"
hexmask.long 0x2A4 0.--31. 1. "RX_STAT_CLASS7_PRU0,RX Class7 Hit Count  Wrt subtracts"
line.long 0x2A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class8_hit_pru0,"
hexmask.long 0x2A8 0.--31. 1. "RX_STAT_CLASS8_PRU0,RX Class8 Hit Count  Wrt subtracts"
line.long 0x2AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class9_hit_pru0,"
hexmask.long 0x2AC 0.--31. 1. "RX_STAT_CLASS9_PRU0,RX Class9 Hit Count  Wrt subtracts"
line.long 0x2B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class10_hit_pru0,"
hexmask.long 0x2B0 0.--31. 1. "RX_STAT_CLASS10_PRU0,RX Class10 Hit Count  Wrt subtracts"
line.long 0x2B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class11_hit_pru0,"
hexmask.long 0x2B4 0.--31. 1. "RX_STAT_CLASS11_PRU0,RX Class11 Hit Count  Wrt subtracts"
line.long 0x2B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class12_hit_pru0,"
hexmask.long 0x2B8 0.--31. 1. "RX_STAT_CLASS12_PRU0,RX Class12 Hit Count  Wrt subtracts"
line.long 0x2BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class13_hit_pru0,"
hexmask.long 0x2BC 0.--31. 1. "RX_STAT_CLASS13_PRU0,RX Class13 Hit Count  Wrt subtracts"
line.long 0x2C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class14_hit_pru0,"
hexmask.long 0x2C0 0.--31. 1. "RX_STAT_CLASS14_PRU0,RX Class14 Hit Count  Wrt subtracts"
line.long 0x2C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class15_hit_pru0,"
hexmask.long 0x2C4 0.--31. 1. "RX_STAT_CLASS15_PRU0,RX Class15 Hit Count  Wrt subtracts"
line.long 0x2C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_smd_frag_err_pru0,"
hexmask.long.byte 0x2C8 24.--31. 1. "RX_STAT_SMD_ERR_PRU0,RX SMDS Error Count  Inc when first none 0x55 does not match any valid SMD  Wrt subtracts"
hexmask.long.byte 0x2C8 16.--23. 1. "RX_STAT_FRAG_ERR_PRU0,RX Frag_Cnt Seq Error Count  Wrt subtracts"
newline
hexmask.long.byte 0x2C8 8.--15. 1. "RX_STAT_SMDC_ERR_PRU0,RX SMDCx Seq Error Count  Wrt subtracts"
hexmask.long.byte 0x2C8 0.--7. 1. "RX_STAT_SMDS_ERR_PRU0,RX SMDSx Seq Error Count  Wrt subtracts"
line.long 0x2CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_size_pru0,"
hexmask.long.word 0x2CC 0.--13. 1. "RX_STAT_BKT1_SIZE,RX Bucket1 Byte Size"
line.long 0x2D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_size_pru0,"
hexmask.long.word 0x2D0 0.--13. 1. "RX_STAT_BKT2_SIZE,RX Bucket2 Byte Size"
line.long 0x2D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_size_pru0,"
hexmask.long.word 0x2D4 0.--13. 1. "RX_STAT_BKT3_SIZE,RX Bucket3 Byte Size"
line.long 0x2D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_size_pru0,"
hexmask.long.word 0x2D8 0.--13. 1. "RX_STAT_BKT4_SIZE,RX Bucket4 Byte Size"
line.long 0x2DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_64_pru0,"
hexmask.long.word 0x2DC 0.--15. 1. "RX_64_FRM_CNT,RX 64Byte Frame Count Inc if 64B size"
line.long 0x2E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_pru0,"
hexmask.long.word 0x2E0 0.--15. 1. "RX_STAT_BKT1,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
line.long 0x2E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_pru0,"
hexmask.long.word 0x2E4 0.--15. 1. "RX_STAT_BKT2,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x2E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_pru0,"
hexmask.long.word 0x2E8 0.--15. 1. "RX_STAT_BKT3,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x2EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_pru0,"
hexmask.long.word 0x2EC 0.--15. 1. "RX_STAT_BKT4,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x2F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt5_pru0,"
hexmask.long.word 0x2F0 0.--15. 1. "RX_STAT_BKT5,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
line.long 0x2F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_total_bytes_pru0,"
hexmask.long 0x2F4 0.--31. 1. "RX_STAT_TOTAL_BYTES_PRU,RX Total Byte Count"
line.long 0x2F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rxtx_stat_total_bytes_pru0,"
hexmask.long 0x2F8 0.--31. 1. "RXTX_STAT_TOTAL_BYTES_PRU,RX and TX Total Byte Count"
line.long 0x2FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_good_port0,"
hexmask.long 0x2FC 0.--31. 1. "TX_GOOD_FRM_CNT,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
line.long 0x300 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bc_port0,"
hexmask.long.word 0x300 0.--15. 1. "TX_BC_FRM_CNT,TX BC Frame Count Inc if BC"
line.long 0x304 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_mc_port0,"
hexmask.long.word 0x304 0.--15. 1. "TX_MC_FRM_CNT,TX MC Frame Count Inc if MC"
line.long 0x308 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_odd_err_port0,"
hexmask.long.word 0x308 0.--15. 1. "TX_ODD_ERR_FRM_CNT,TX Odd Nibble Frame Count Inc if mii odd nibble"
line.long 0x30C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_underflow_err_port0,"
hexmask.long.word 0x30C 0.--15. 1. "TX_UNDERFLOW_CNT,TX MAX Underflow Error Cnt"
line.long 0x310 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_size_port0,"
hexmask.long.word 0x310 0.--15. 1. "TX_MAX_SIZE_FRM,TX MAX Size Frame Count Limit"
line.long 0x314 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_err_port0,"
hexmask.long.word 0x314 0.--15. 1. "TX_MAX_ERR_FRM_CNT,TX MAX Size Err Frame Count Inc if > max Limit"
line.long 0x318 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_size_port0,"
hexmask.long.word 0x318 0.--15. 1. "TX_MIN_SIZE_FRM,TX MIN Size Frame Count Limit"
line.long 0x31C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_err_port0,"
hexmask.long.word 0x31C 0.--15. 1. "TX_MIN_ERR_FRM_CNT,TX MIN Size Err Frame Count Inc if < min Limit"
line.long 0x320 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_size_port0,"
hexmask.long.word 0x320 0.--13. 1. "TX_STAT_BKT1_SIZE,TX Bucket1 Byte Size"
line.long 0x324 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_size_port0,"
hexmask.long.word 0x324 0.--13. 1. "TX_STAT_BKT2_SIZE,TX Bucket2 Byte Size"
line.long 0x328 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_size_port0,"
hexmask.long.word 0x328 0.--13. 1. "TX_STAT_BKT3_SIZE,TX Bucket3 Byte Size"
line.long 0x32C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_size_port0,"
hexmask.long.word 0x32C 0.--13. 1. "TX_STAT_BKT4_SIZE,TX Bucket4 Byte Size"
line.long 0x330 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_64_port0,"
hexmask.long.word 0x330 0.--15. 1. "TX_64_FRM_CNT,TX 64Byte Frame Count Inc if 64B"
line.long 0x334 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_port0,"
hexmask.long.word 0x334 0.--15. 1. "TX_STAT_BKT1,TX Bucket1 Inc if <= than Bucket1"
line.long 0x338 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_port0,"
hexmask.long.word 0x338 0.--15. 1. "TX_STAT_BKT2,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x33C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_port0,"
hexmask.long.word 0x33C 0.--15. 1. "TX_STAT_BKT3,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x340 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_port0,"
hexmask.long.word 0x340 0.--15. 1. "TX_STAT_BKT4,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x344 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt5_port0,"
hexmask.long.word 0x344 0.--15. 1. "TX_STAT_BKT5,TX Bucket5 Inc if > than Bucket4 Byte Size"
line.long 0x348 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_total_bytes_port0,"
hexmask.long 0x348 0.--31. 1. "TX_TOTAL_STAT_BYTES_PORT,TX Total Byte Count of all Frames"
line.long 0x34C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_tag_port0,"
hexmask.long 0x34C 0.--31. 1. "TX_HSR_TAG,HSR TAG"
line.long 0x350 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_seq_port0,"
hexmask.long.word 0x350 0.--15. 1. "TX_HSR_SEQ,HSR Seq count. It will incr for every HSR type"
line.long 0x354 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_type_tag_port0,"
hexmask.long.word 0x354 0.--15. 1. "TX_VLAN_TYPE_TAG,TX VLAN Type Tag  match to enable VLAN removal"
line.long 0x358 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_ins_tag_port0,"
hexmask.long 0x358 0.--31. 1. "TX_VLAN_INS_TAG,TX VLAN Insertion"
line.long 0x35C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_start_len_pru1,"
hexmask.long.byte 0x35C 16.--19. 1. "FT1_LEN,Defines the total number of Bytes Filter1 will check before Valid bit is set"
hexmask.long.word 0x35C 0.--14. 1. "FT1_START,Byte count start for Filter1. Any wrt will clear all Filter1 Status Bits"
line.long 0x360 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_cfg_pru1,"
bitfld.long 0x360 14.--15. "FT1_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 12.--13. "FT1_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x360 10.--11. "FT1_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 8.--9. "FT1_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x360 6.--7. "FT1_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 4.--5. "FT1_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x360 2.--3. "FT1_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 0.--1. "FT1_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x364 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da0_pru1,"
hexmask.long 0x364 0.--31. 1. "FT1_0_DA0,Filter1 DA4:DA1"
line.long 0x368 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da1_pru1,"
hexmask.long.word 0x368 0.--15. 1. "FT1_0_DA1,Filter1 DA6:DA5"
line.long 0x36C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask0_pru1,"
hexmask.long 0x36C 0.--31. 1. "FT1_0_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x370 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask1_pru1,"
hexmask.long.word 0x370 0.--15. 1. "FT1_0_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x374 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da0_pru1,"
hexmask.long 0x374 0.--31. 1. "FT1_1_DA0,Filter1 DA4:DA1"
line.long 0x378 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da1_pru1,"
hexmask.long.word 0x378 0.--15. 1. "FT1_1_DA1,Filter1 DA6:DA5"
line.long 0x37C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask0_pru1,"
hexmask.long 0x37C 0.--31. 1. "FT1_1_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x380 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask1_pru1,"
hexmask.long.word 0x380 0.--15. 1. "FT1_1_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x384 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da0_pru1,"
hexmask.long 0x384 0.--31. 1. "FT1_2_DA0,Filter1 DA4:DA1"
line.long 0x388 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da1_pru1,"
hexmask.long.word 0x388 0.--15. 1. "FT1_2_DA1,Filter1 DA6:DA5"
line.long 0x38C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask0_pru1,"
hexmask.long 0x38C 0.--31. 1. "FT1_2_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x390 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask1_pru1,"
hexmask.long.word 0x390 0.--15. 1. "FT1_2_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x394 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da0_pru1,"
hexmask.long 0x394 0.--31. 1. "FT1_3_DA0,Filter1 DA4:DA1"
line.long 0x398 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da1_pru1,"
hexmask.long.word 0x398 0.--15. 1. "FT1_3_DA1,Filter1 DA6:DA5"
line.long 0x39C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask0_pru1,"
hexmask.long 0x39C 0.--31. 1. "FT1_3_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask1_pru1,"
hexmask.long.word 0x3A0 0.--15. 1. "FT1_3_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da0_pru1,"
hexmask.long 0x3A4 0.--31. 1. "FT1_4_DA0,Filter1 DA4:DA1"
line.long 0x3A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da1_pru1,"
hexmask.long.word 0x3A8 0.--15. 1. "FT1_4_DA1,Filter1 DA6:DA5"
line.long 0x3AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask0_pru1,"
hexmask.long 0x3AC 0.--31. 1. "FT1_4_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask1_pru1,"
hexmask.long.word 0x3B0 0.--15. 1. "FT1_4_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da0_pru1,"
hexmask.long 0x3B4 0.--31. 1. "FT1_5_DA0,Filter1 DA4:DA1"
line.long 0x3B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da1_pru1,"
hexmask.long.word 0x3B8 0.--15. 1. "FT1_5_DA1,Filter1 DA6:DA5"
line.long 0x3BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask0_pru1,"
hexmask.long 0x3BC 0.--31. 1. "FT1_5_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask1_pru1,"
hexmask.long.word 0x3C0 0.--15. 1. "FT1_5_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da0_pru1,"
hexmask.long 0x3C4 0.--31. 1. "FT1_6_DA0,Filter1 DA4:DA1"
line.long 0x3C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da1_pru1,"
hexmask.long.word 0x3C8 0.--15. 1. "FT1_6_DA1,Filter1 DA6:DA5"
line.long 0x3CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask0_pru1,"
hexmask.long 0x3CC 0.--31. 1. "FT1_6_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask1_pru1,"
hexmask.long.word 0x3D0 0.--15. 1. "FT1_6_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da0_pru1,"
hexmask.long 0x3D4 0.--31. 1. "FT1_7_DA0,Filter1 DA4:DA1"
line.long 0x3D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da1_pru1,"
hexmask.long.word 0x3D8 0.--15. 1. "FT1_7_DA1,Filter1 DA6:DA5"
line.long 0x3DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask0_pru1,"
hexmask.long 0x3DC 0.--31. 1. "FT1_7_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask1_pru1,"
hexmask.long.word 0x3E0 0.--15. 1. "FT1_7_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_pru1,"
hexmask.long.word 0x3E4 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6D8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x6DC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_0_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_0_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_len_pru1,"
bitfld.long 0x8 24. "FT3_0_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_0_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_0_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_0_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_0_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_0_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_0_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6F8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x6FC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_1_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_1_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_len_pru1,"
bitfld.long 0x8 24. "FT3_1_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_1_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_1_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_1_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_1_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_1_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_1_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x718++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x71C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_2_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_2_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_len_pru1,"
bitfld.long 0x8 24. "FT3_2_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_2_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_2_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_2_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_2_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_2_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_2_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x738++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x73C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_3_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_3_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_len_pru1,"
bitfld.long 0x8 24. "FT3_3_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_3_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_3_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_3_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_3_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_3_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_3_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x758++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x75C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_4_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_4_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_len_pru1,"
bitfld.long 0x8 24. "FT3_4_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_4_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_4_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_4_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_4_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_4_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_4_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x778++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x77C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_5_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_5_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_len_pru1,"
bitfld.long 0x8 24. "FT3_5_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_5_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_5_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_5_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_5_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_5_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_5_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x798++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x79C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_6_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_6_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_len_pru1,"
bitfld.long 0x8 24. "FT3_6_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_6_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_6_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_6_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_6_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_6_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_6_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7B8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x7BC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_7_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_7_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_len_pru1,"
bitfld.long 0x8 24. "FT3_7_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_7_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_7_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_7_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_7_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_7_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_7_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7D8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x7DC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_8_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_8_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_len_pru1,"
bitfld.long 0x8 24. "FT3_8_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_8_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_8_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_8_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_8_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_8CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_8_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_8_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7F8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x7FC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_9_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_9_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_len_pru1,"
bitfld.long 0x8 24. "FT3_9_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_9_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_9_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_9_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_9_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_9CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_9_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_9_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x818++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x81C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_10_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_10_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_len_pru1,"
bitfld.long 0x8 24. "FT3_10_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_10_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_10_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_10_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_10_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_10CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_10_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_10_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x838++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x83C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_11_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_11_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_len_pru1,"
bitfld.long 0x8 24. "FT3_11_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_11_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_11_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_11_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_11_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_11CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_11_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_11_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x858++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x85C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_12_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_12_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_len_pru1,"
bitfld.long 0x8 24. "FT3_12_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_12_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_12_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_12_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_12_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_12CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_12_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_12_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x878++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x87C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_13_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_13_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_len_pru1,"
bitfld.long 0x8 24. "FT3_13_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_13_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_13_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_13_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_13_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_13CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_13_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_13_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x898++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x89C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_14_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_14_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_len_pru1,"
bitfld.long 0x8 24. "FT3_14_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_14_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_14_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_14_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_14_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_14CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_14_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_14_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x8B8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x8BC++0x35B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_15_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_15_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_len_pru1,"
bitfld.long 0x8 24. "FT3_15_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_15_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_15_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_15_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_15_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_15CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_15_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_15_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p0_pru1,"
hexmask.long 0x18 0.--31. 1. "FT3_0_P0,Filter3 P4:P1"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p1_pru1,"
hexmask.long 0x1C 0.--31. 1. "FT3_0_P1,Filter3 P8:P5"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask0_pru1,"
hexmask.long 0x20 0.--31. 1. "FT3_0_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask1_pru1,"
hexmask.long 0x24 0.--31. 1. "FT3_0_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p0_pru1,"
hexmask.long 0x28 0.--31. 1. "FT3_1_P0,Filter3 P4:P1"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p1_pru1,"
hexmask.long 0x2C 0.--31. 1. "FT3_1_P1,Filter3 P8:P5"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask0_pru1,"
hexmask.long 0x30 0.--31. 1. "FT3_1_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask1_pru1,"
hexmask.long 0x34 0.--31. 1. "FT3_1_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p0_pru1,"
hexmask.long 0x38 0.--31. 1. "FT3_2_P0,Filter3 P4:P1"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p1_pru1,"
hexmask.long 0x3C 0.--31. 1. "FT3_2_P1,Filter3 P8:P5"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask0_pru1,"
hexmask.long 0x40 0.--31. 1. "FT3_2_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask1_pru1,"
hexmask.long 0x44 0.--31. 1. "FT3_2_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p0_pru1,"
hexmask.long 0x48 0.--31. 1. "FT3_3_P0,Filter3 P4:P1"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p1_pru1,"
hexmask.long 0x4C 0.--31. 1. "FT3_3_P1,Filter3 P8:P5"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask0_pru1,"
hexmask.long 0x50 0.--31. 1. "FT3_3_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask1_pru1,"
hexmask.long 0x54 0.--31. 1. "FT3_3_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p0_pru1,"
hexmask.long 0x58 0.--31. 1. "FT3_4_P0,Filter3 P4:P1"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p1_pru1,"
hexmask.long 0x5C 0.--31. 1. "FT3_4_P1,Filter3 P8:P5"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask0_pru1,"
hexmask.long 0x60 0.--31. 1. "FT3_4_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask1_pru1,"
hexmask.long 0x64 0.--31. 1. "FT3_4_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p0_pru1,"
hexmask.long 0x68 0.--31. 1. "FT3_5_P0,Filter3 P4:P1"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p1_pru1,"
hexmask.long 0x6C 0.--31. 1. "FT3_5_P1,Filter3 P8:P5"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask0_pru1,"
hexmask.long 0x70 0.--31. 1. "FT3_5_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask1_pru1,"
hexmask.long 0x74 0.--31. 1. "FT3_5_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p0_pru1,"
hexmask.long 0x78 0.--31. 1. "FT3_6_P0,Filter3 P4:P1"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p1_pru1,"
hexmask.long 0x7C 0.--31. 1. "FT3_6_P1,Filter3 P8:P5"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask0_pru1,"
hexmask.long 0x80 0.--31. 1. "FT3_6_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask1_pru1,"
hexmask.long 0x84 0.--31. 1. "FT3_6_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p0_pru1,"
hexmask.long 0x88 0.--31. 1. "FT3_7_P0,Filter3 P4:P1"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p1_pru1,"
hexmask.long 0x8C 0.--31. 1. "FT3_7_P1,Filter3 P8:P5"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask0_pru1,"
hexmask.long 0x90 0.--31. 1. "FT3_7_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask1_pru1,"
hexmask.long 0x94 0.--31. 1. "FT3_7_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p0_pru1,"
hexmask.long 0x98 0.--31. 1. "FT3_8_P0,Filter3 P4:P1"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p1_pru1,"
hexmask.long 0x9C 0.--31. 1. "FT3_8_P1,Filter3 P8:P5"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask0_pru1,"
hexmask.long 0xA0 0.--31. 1. "FT3_8_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask1_pru1,"
hexmask.long 0xA4 0.--31. 1. "FT3_8_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p0_pru1,"
hexmask.long 0xA8 0.--31. 1. "FT3_9_P0,Filter3 P4:P1"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p1_pru1,"
hexmask.long 0xAC 0.--31. 1. "FT3_9_P1,Filter3 P8:P5"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask0_pru1,"
hexmask.long 0xB0 0.--31. 1. "FT3_9_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask1_pru1,"
hexmask.long 0xB4 0.--31. 1. "FT3_9_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p0_pru1,"
hexmask.long 0xB8 0.--31. 1. "FT3_10_P0,Filter3 P4:P1"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p1_pru1,"
hexmask.long 0xBC 0.--31. 1. "FT3_10_P1,Filter3 P8:P5"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask0_pru1,"
hexmask.long 0xC0 0.--31. 1. "FT3_10_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask1_pru1,"
hexmask.long 0xC4 0.--31. 1. "FT3_10_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p0_pru1,"
hexmask.long 0xC8 0.--31. 1. "FT3_11_P0,Filter3 P4:P1"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p1_pru1,"
hexmask.long 0xCC 0.--31. 1. "FT3_11_P1,Filter3 P8:P5"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask0_pru1,"
hexmask.long 0xD0 0.--31. 1. "FT3_11_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask1_pru1,"
hexmask.long 0xD4 0.--31. 1. "FT3_11_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p0_pru1,"
hexmask.long 0xD8 0.--31. 1. "FT3_12_P0,Filter3 P4:P1"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p1_pru1,"
hexmask.long 0xDC 0.--31. 1. "FT3_12_P1,Filter3 P8:P5"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask0_pru1,"
hexmask.long 0xE0 0.--31. 1. "FT3_12_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask1_pru1,"
hexmask.long 0xE4 0.--31. 1. "FT3_12_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p0_pru1,"
hexmask.long 0xE8 0.--31. 1. "FT3_13_P0,Filter3 P4:P1"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p1_pru1,"
hexmask.long 0xEC 0.--31. 1. "FT3_13_P1,Filter3 P8:P5"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask0_pru1,"
hexmask.long 0xF0 0.--31. 1. "FT3_13_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask1_pru1,"
hexmask.long 0xF4 0.--31. 1. "FT3_13_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p0_pru1,"
hexmask.long 0xF8 0.--31. 1. "FT3_14_P0,Filter3 P4:P1"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p1_pru1,"
hexmask.long 0xFC 0.--31. 1. "FT3_14_P1,Filter3 P8:P5"
line.long 0x100 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask0_pru1,"
hexmask.long 0x100 0.--31. 1. "FT3_14_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x104 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask1_pru1,"
hexmask.long 0x104 0.--31. 1. "FT3_14_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x108 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p0_pru1,"
hexmask.long 0x108 0.--31. 1. "FT3_15_P0,Filter3 P4:P1"
line.long 0x10C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p1_pru1,"
hexmask.long 0x10C 0.--31. 1. "FT3_15_P1,Filter3 P8:P5"
line.long 0x110 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask0_pru1,"
hexmask.long 0x110 0.--31. 1. "FT3_15_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x114 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask1_pru1,"
hexmask.long 0x114 0.--31. 1. "FT3_15_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x118 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft_rx_ptr_pru1,"
hexmask.long 0x118 0.--31. 1. "FT_RX_PTR_PRU1,RX current filter Byte Count"
line.long 0x11C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_and_en_pru1,"
hexmask.long 0x11C 0.--31. 1. "RX_CLASS0_AND_EN,rx class and enabels"
line.long 0x120 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_or_en_pru1,"
hexmask.long 0x120 0.--31. 1. "RX_CLASS0_OR_EN,rx class or enabels"
line.long 0x124 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_and_en_pru1,"
hexmask.long 0x124 0.--31. 1. "RX_CLASS1_AND_EN,rx class and enabels"
line.long 0x128 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_or_en_pru1,"
hexmask.long 0x128 0.--31. 1. "RX_CLASS1_OR_EN,rx class or enabels"
line.long 0x12C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_and_en_pru1,"
hexmask.long 0x12C 0.--31. 1. "RX_CLASS2_AND_EN,rx class and enabels"
line.long 0x130 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_or_en_pru1,"
hexmask.long 0x130 0.--31. 1. "RX_CLASS2_OR_EN,rx class or enabels"
line.long 0x134 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_and_en_pru1,"
hexmask.long 0x134 0.--31. 1. "RX_CLASS3_AND_EN,rx class and enabels"
line.long 0x138 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_or_en_pru1,"
hexmask.long 0x138 0.--31. 1. "RX_CLASS3_OR_EN,rx class or enabels"
line.long 0x13C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_and_en_pru1,"
hexmask.long 0x13C 0.--31. 1. "RX_CLASS4_AND_EN,rx class and enabels"
line.long 0x140 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_or_en_pru1,"
hexmask.long 0x140 0.--31. 1. "RX_CLASS4_OR_EN,rx class or enabels"
line.long 0x144 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_and_en_pru1,"
hexmask.long 0x144 0.--31. 1. "RX_CLASS5_AND_EN,rx class and enabels"
line.long 0x148 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_or_en_pru1,"
hexmask.long 0x148 0.--31. 1. "RX_CLASS5_OR_EN,rx class or enabels"
line.long 0x14C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_and_en_pru1,"
hexmask.long 0x14C 0.--31. 1. "RX_CLASS6_AND_EN,rx class and enabels"
line.long 0x150 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_or_en_pru1,"
hexmask.long 0x150 0.--31. 1. "RX_CLASS6_OR_EN,rx class or enabels"
line.long 0x154 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_and_en_pru1,"
hexmask.long 0x154 0.--31. 1. "RX_CLASS7_AND_EN,rx class and enabels"
line.long 0x158 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_or_en_pru1,"
hexmask.long 0x158 0.--31. 1. "RX_CLASS7_OR_EN,rx class or enabels"
line.long 0x15C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_and_en_pru1,"
hexmask.long 0x15C 0.--31. 1. "RX_CLASS8_AND_EN,rx class and enabels"
line.long 0x160 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_or_en_pru1,"
hexmask.long 0x160 0.--31. 1. "RX_CLASS8_OR_EN,rx class or enabels"
line.long 0x164 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_and_en_pru1,"
hexmask.long 0x164 0.--31. 1. "RX_CLASS9_AND_EN,rx class and enabels"
line.long 0x168 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_or_en_pru1,"
hexmask.long 0x168 0.--31. 1. "RX_CLASS9_OR_EN,rx class or enabels"
line.long 0x16C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_and_en_pru1,"
hexmask.long 0x16C 0.--31. 1. "RX_CLASS10_AND_EN,rx class and enabels"
line.long 0x170 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_or_en_pru1,"
hexmask.long 0x170 0.--31. 1. "RX_CLASS10_OR_EN,rx class or enabels"
line.long 0x174 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_and_en_pru1,"
hexmask.long 0x174 0.--31. 1. "RX_CLASS11_AND_EN,rx class and enabels"
line.long 0x178 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_or_en_pru1,"
hexmask.long 0x178 0.--31. 1. "RX_CLASS11_OR_EN,rx class or enabels"
line.long 0x17C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_and_en_pru1,"
hexmask.long 0x17C 0.--31. 1. "RX_CLASS12_AND_EN,rx class and enabels"
line.long 0x180 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_or_en_pru1,"
hexmask.long 0x180 0.--31. 1. "RX_CLASS12_OR_EN,rx class or enabels"
line.long 0x184 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_and_en_pru1,"
hexmask.long 0x184 0.--31. 1. "RX_CLASS13_AND_EN,rx class and enabels"
line.long 0x188 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_or_en_pru1,"
hexmask.long 0x188 0.--31. 1. "RX_CLASS13_OR_EN,rx class or enabels"
line.long 0x18C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_and_en_pru1,"
hexmask.long 0x18C 0.--31. 1. "RX_CLASS14_AND_EN,rx class and enabels"
line.long 0x190 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_or_en_pru1,"
hexmask.long 0x190 0.--31. 1. "RX_CLASS14_OR_EN,rx class or enabels"
line.long 0x194 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_and_en_pru1,"
hexmask.long 0x194 0.--31. 1. "RX_CLASS15_AND_EN,rx class and enabels"
line.long 0x198 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_or_en_pru1,"
hexmask.long 0x198 0.--31. 1. "RX_CLASS15_OR_EN,rx class or enabels"
line.long 0x19C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg1_pru1,"
bitfld.long 0x19C 30.--31. "RX_CLASS15_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 28.--29. "RX_CLASS14_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 26.--27. "RX_CLASS13_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 24.--25. "RX_CLASS12_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 22.--23. "RX_CLASS11_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 20.--21. "RX_CLASS10_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 18.--19. "RX_CLASS9_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 16.--17. "RX_CLASS8_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 14.--15. "RX_CLASS7_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 12.--13. "RX_CLASS6_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 10.--11. "RX_CLASS5_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 8.--9. "RX_CLASS4_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 6.--7. "RX_CLASS3_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 4.--5. "RX_CLASS2_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 2.--3. "RX_CLASS1_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 0.--1. "RX_CLASS0_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
line.long 0x1A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg2_pru1,"
hexmask.long.word 0x1A0 16.--31. 1. "RX_CLASS_OR_NV,rx class or nv enable"
hexmask.long.word 0x1A0 0.--15. 1. "RX_CLASS_AND_NV,rx class and nv enable"
line.long 0x1A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates0_pru1,"
bitfld.long 0x1A4 8. "RX_RED_PHASE_EN0,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A4 6. "RX_ALLOW_MASK0,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A4 5. "RX_CLASS_RAW_MASK0,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A4 4. "RX_PHASE_MASK0,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A4 0.--2. "RX_RATE_GATE_SEL0,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates1_pru1,"
bitfld.long 0x1A8 8. "RX_RED_PHASE_EN1,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A8 6. "RX_ALLOW_MASK1,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A8 5. "RX_CLASS_RAW_MASK1,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A8 4. "RX_PHASE_MASK1,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A8 0.--2. "RX_RATE_GATE_SEL1,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates2_pru1,"
bitfld.long 0x1AC 8. "RX_RED_PHASE_EN2,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1AC 6. "RX_ALLOW_MASK2,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1AC 5. "RX_CLASS_RAW_MASK2,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1AC 4. "RX_PHASE_MASK2,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1AC 0.--2. "RX_RATE_GATE_SEL2,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates3_pru1,"
bitfld.long 0x1B0 8. "RX_RED_PHASE_EN3,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B0 6. "RX_ALLOW_MASK3,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B0 5. "RX_CLASS_RAW_MASK3,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B0 4. "RX_PHASE_MASK3,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B0 0.--2. "RX_RATE_GATE_SEL3,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates4_pru1,"
bitfld.long 0x1B4 8. "RX_RED_PHASE_EN4,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B4 6. "RX_ALLOW_MASK4,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B4 5. "RX_CLASS_RAW_MASK4,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B4 4. "RX_PHASE_MASK4,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B4 0.--2. "RX_RATE_GATE_SEL4,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates5_pru1,"
bitfld.long 0x1B8 8. "RX_RED_PHASE_EN5,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B8 6. "RX_ALLOW_MASK5,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B8 5. "RX_CLASS_RAW_MASK5,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B8 4. "RX_PHASE_MASK5,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B8 0.--2. "RX_RATE_GATE_SEL5,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates6_pru1,"
bitfld.long 0x1BC 8. "RX_RED_PHASE_EN6,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1BC 6. "RX_ALLOW_MASK6,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1BC 5. "RX_CLASS_RAW_MASK6,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1BC 4. "RX_PHASE_MASK6,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1BC 0.--2. "RX_RATE_GATE_SEL6,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates7_pru1,"
bitfld.long 0x1C0 8. "RX_RED_PHASE_EN7,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C0 6. "RX_ALLOW_MASK7,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C0 5. "RX_CLASS_RAW_MASK7,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C0 4. "RX_PHASE_MASK7,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C0 0.--2. "RX_RATE_GATE_SEL7,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates8_pru1,"
bitfld.long 0x1C4 8. "RX_RED_PHASE_EN8,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C4 6. "RX_ALLOW_MASK8,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C4 5. "RX_CLASS_RAW_MASK8,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C4 4. "RX_PHASE_MASK8,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C4 0.--2. "RX_RATE_GATE_SEL8,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates9_pru1,"
bitfld.long 0x1C8 8. "RX_RED_PHASE_EN9,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C8 6. "RX_ALLOW_MASK9,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C8 5. "RX_CLASS_RAW_MASK9,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C8 4. "RX_PHASE_MASK9,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C8 0.--2. "RX_RATE_GATE_SEL9,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates10_pru1,"
bitfld.long 0x1CC 8. "RX_RED_PHASE_EN10,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1CC 6. "RX_ALLOW_MASK10,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1CC 5. "RX_CLASS_RAW_MASK10,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1CC 4. "RX_PHASE_MASK10,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1CC 0.--2. "RX_RATE_GATE_SEL10,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates11_pru1,"
bitfld.long 0x1D0 8. "RX_RED_PHASE_EN11,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D0 6. "RX_ALLOW_MASK11,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1D0 5. "RX_CLASS_RAW_MASK11,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D0 4. "RX_PHASE_MASK11,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 0.--2. "RX_RATE_GATE_SEL11,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates12_pru1,"
bitfld.long 0x1D4 8. "RX_RED_PHASE_EN12,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D4 6. "RX_ALLOW_MASK12,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1D4 5. "RX_CLASS_RAW_MASK12,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D4 4. "RX_PHASE_MASK12,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1D4 0.--2. "RX_RATE_GATE_SEL12,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates13_pru1,"
bitfld.long 0x1D8 8. "RX_RED_PHASE_EN13,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D8 6. "RX_ALLOW_MASK13,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1D8 5. "RX_CLASS_RAW_MASK13,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D8 4. "RX_PHASE_MASK13,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1D8 0.--2. "RX_RATE_GATE_SEL13,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates14_pru1,"
bitfld.long 0x1DC 8. "RX_RED_PHASE_EN14,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1DC 6. "RX_ALLOW_MASK14,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1DC 5. "RX_CLASS_RAW_MASK14,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1DC 4. "RX_PHASE_MASK14,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1DC 0.--2. "RX_RATE_GATE_SEL14,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates15_pru1,"
bitfld.long 0x1E0 8. "RX_RED_PHASE_EN15,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1E0 6. "RX_ALLOW_MASK15,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1E0 5. "RX_CLASS_RAW_MASK15,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1E0 4. "RX_PHASE_MASK15,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 0.--2. "RX_RATE_GATE_SEL15,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_green_pru1,"
rbitfld.long 0x1E4 4. "RX_GREEN_VAL,0 RED 1 GREEN status" "0,1"
hexmask.long.byte 0x1E4 0.--3. 1. "RX_GREEN_CMP_SEL,define which IEP CMP start green"
line.long 0x1E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_sa_hash_pru1,"
hexmask.long.word 0x1E8 0.--9. 1. "SA_HASH_SEED,SA Hash Seed"
line.long 0x1EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_pru1,"
hexmask.long.word 0x1EC 0.--9. 1. "CONN_HASH_SEED,Connection Hash Seed"
line.long 0x1F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_start_pru1,"
hexmask.long.word 0x1F0 0.--14. 1. "CONN_HASH_START,Connection Hash Start which 4 Bytes to hash"
line.long 0x1F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg0_pru1,"
hexmask.long 0x1F4 0.--31. 1. "RX_RATE_CIR_IDLE0,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg1_pru1,"
hexmask.long 0x1F8 0.--31. 1. "RX_RATE_CIR_IDLE1,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg2_pru1,"
hexmask.long 0x1FC 0.--31. 1. "RX_RATE_CIR_IDLE2,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x200 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg3_pru1,"
hexmask.long 0x200 0.--31. 1. "RX_RATE_CIR_IDLE3,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x204 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg4_pru1,"
hexmask.long 0x204 0.--31. 1. "RX_RATE_CIR_IDLE4,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x208 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg5_pru1,"
hexmask.long 0x208 0.--31. 1. "RX_RATE_CIR_IDLE5,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x20C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg6_pru1,"
hexmask.long 0x20C 0.--31. 1. "RX_RATE_CIR_IDLE6,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x210 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg7_pru1,"
hexmask.long 0x210 0.--31. 1. "RX_RATE_CIR_IDLE7,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x214 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel0_pru1,"
hexmask.long.byte 0x214 24.--29. 1. "RX_RATE_SRC_SEL3,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 16.--21. 1. "RX_RATE_SRC_SEL2,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x214 8.--13. 1. "RX_RATE_SRC_SEL1,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 0.--5. 1. "RX_RATE_SRC_SEL0,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x218 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel1_pru1,"
hexmask.long.byte 0x218 24.--29. 1. "RX_RATE_SRC_SEL7,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 16.--21. 1. "RX_RATE_SRC_SEL6,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x218 8.--13. 1. "RX_RATE_SRC_SEL5,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 0.--5. 1. "RX_RATE_SRC_SEL4,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x21C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_0_pru1,"
hexmask.long 0x21C 0.--31. 1. "TX_RATE_CIR_IDLE0,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x220 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_0_pru1,"
rbitfld.long 0x220 17. "TX_RATE_ALLOW0,TX Rate Pkt Enable" "0,1"
bitfld.long 0x220 16. "TX_RATE_EN0,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x220 0.--15. 1. "TX_RATE_LEN0,TX Rate Pkt Length"
line.long 0x224 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_1_pru1,"
hexmask.long 0x224 0.--31. 1. "TX_RATE_CIR_IDLE1,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x228 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_1_pru1,"
rbitfld.long 0x228 17. "TX_RATE_ALLOW1,TX Rate Pkt Enable" "0,1"
bitfld.long 0x228 16. "TX_RATE_EN1,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x228 0.--15. 1. "TX_RATE_LEN1,TX Rate Pkt Length"
line.long 0x22C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_2_pru1,"
hexmask.long 0x22C 0.--31. 1. "TX_RATE_CIR_IDLE2,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x230 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_2_pru1,"
rbitfld.long 0x230 17. "TX_RATE_ALLOW2,TX Rate Pkt Enable" "0,1"
bitfld.long 0x230 16. "TX_RATE_EN2,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x230 0.--15. 1. "TX_RATE_LEN2,TX Rate Pkt Length"
line.long 0x234 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_3_pru1,"
hexmask.long 0x234 0.--31. 1. "TX_RATE_CIR_IDLE3,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x238 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_3_pru1,"
rbitfld.long 0x238 17. "TX_RATE_ALLOW3,TX Rate Pkt Enable" "0,1"
bitfld.long 0x238 16. "TX_RATE_EN3,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x238 0.--15. 1. "TX_RATE_LEN3,TX Rate Pkt Length"
line.long 0x23C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_4_pru1,"
hexmask.long 0x23C 0.--31. 1. "TX_RATE_CIR_IDLE4,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x240 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_4_pru1,"
rbitfld.long 0x240 17. "TX_RATE_ALLOW4,TX Rate Pkt Enable" "0,1"
bitfld.long 0x240 16. "TX_RATE_EN4,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x240 0.--15. 1. "TX_RATE_LEN4,TX Rate Pkt Length"
line.long 0x244 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_5_pru1,"
hexmask.long 0x244 0.--31. 1. "TX_RATE_CIR_IDLE5,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x248 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_5_pru1,"
rbitfld.long 0x248 17. "TX_RATE_ALLOW5,TX Rate Pkt Enable" "0,1"
bitfld.long 0x248 16. "TX_RATE_EN5,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x248 0.--15. 1. "TX_RATE_LEN5,TX Rate Pkt Length"
line.long 0x24C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_6_pru1,"
hexmask.long 0x24C 0.--31. 1. "TX_RATE_CIR_IDLE6,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x250 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_6_pru1,"
rbitfld.long 0x250 17. "TX_RATE_ALLOW6,TX Rate Pkt Enable" "0,1"
bitfld.long 0x250 16. "TX_RATE_EN6,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x250 0.--15. 1. "TX_RATE_LEN6,TX Rate Pkt Length"
line.long 0x254 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_7_pru1,"
hexmask.long 0x254 0.--31. 1. "TX_RATE_CIR_IDLE7,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x258 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_7_pru1,"
rbitfld.long 0x258 17. "TX_RATE_ALLOW7,TX Rate Pkt Enable" "0,1"
bitfld.long 0x258 16. "TX_RATE_EN7,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x258 0.--15. 1. "TX_RATE_LEN7,TX Rate Pkt Length"
line.long 0x25C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_good_pru1,"
hexmask.long 0x25C 0.--31. 1. "RX_GOOD_FRM_CNT,RX Good Frame Count Inc on none min err max err crc err odd err  Wrt subtracts"
line.long 0x260 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bc_pru1,"
hexmask.long.word 0x260 0.--15. 1. "RX_BC_FRM_CNT,RX BC Frame Count Inc on BC type  Wrt subtracts"
line.long 0x264 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mc_pru1,"
hexmask.long.word 0x264 0.--15. 1. "RX_MC_FRM_CNT,RX MC Frame Count Inc on MC type  Wrt subtracts"
line.long 0x268 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_crc_err_pru1,"
hexmask.long.word 0x268 0.--15. 1. "RX_CRC_ERR_FRM_CNT,RX CRC Err Frame Count Inc on crc err  Wrt subtracts"
line.long 0x26C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mii_err_pru1,"
hexmask.long.word 0x26C 0.--15. 1. "RX_MII_ERR_FRM_CNT,RX MII Err Frame Count Inc on mii sgmii rgmii err  Wrt subtracts"
line.long 0x270 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_odd_err_pru1,"
hexmask.long.word 0x270 0.--15. 1. "RX_ODD_ERR_FRM_CNT,RX Odd Nibble Frame Count Inc on odd nibble mii  Wrt subtracts"
line.long 0x274 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_size_pru1,"
hexmask.long.word 0x274 0.--15. 1. "RX_MAX_SIZE_FRM,RX MAX Size Frame Count Limit"
line.long 0x278 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_err_pru1,"
hexmask.long.word 0x278 0.--15. 1. "RX_MAX_ERR_FRM_CNT,RX MAX Size Err Frame Count Inc if > than Limit  Wrt subtracts"
line.long 0x27C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_size_pru1,"
hexmask.long.word 0x27C 0.--15. 1. "RX_MIN_SIZE_FRM,RX MIN Size Frame Limit"
line.long 0x280 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_err_pru1,"
hexmask.long.word 0x280 0.--15. 1. "RX_MIN_ERR_FRM_CNT,RX MIN Size Frame Count Inc if < than limit  Wrt subtracts"
line.long 0x284 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_overrun_err_pru1,"
hexmask.long.word 0x284 0.--15. 1. "RX_OVERRUN_ERR_FRM_CNT,RX L1 FIFO overflow Frame Count Inc on overflow event  Wrt subtracts"
line.long 0x288 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class0_hit_pru1,"
hexmask.long 0x288 0.--31. 1. "RX_STAT_CLASS0_PRU1,RX Class0 Hit Count  Wrt subtracts"
line.long 0x28C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class1_hit_pru1,"
hexmask.long 0x28C 0.--31. 1. "RX_STAT_CLASS1_PRU1,RX Class1 Hit Count  Wrt subtracts"
line.long 0x290 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class2_hit_pru1,"
hexmask.long 0x290 0.--31. 1. "RX_STAT_CLASS2_PRU1,RX Class2 Hit Count  Wrt subtracts"
line.long 0x294 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class3_hit_pru1,"
hexmask.long 0x294 0.--31. 1. "RX_STAT_CLASS3_PRU1,RX Class3 Hit Count  Wrt subtracts"
line.long 0x298 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class4_hit_pru1,"
hexmask.long 0x298 0.--31. 1. "RX_STAT_CLASS4_PRU1,RX Class4 Hit Count  Wrt subtracts"
line.long 0x29C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class5_hit_pru1,"
hexmask.long 0x29C 0.--31. 1. "RX_STAT_CLASS5_PRU1,RX Class5 Hit Count  Wrt subtracts"
line.long 0x2A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class6_hit_pru1,"
hexmask.long 0x2A0 0.--31. 1. "RX_STAT_CLASS6_PRU1,RX Class6 Hit Count  Wrt subtracts"
line.long 0x2A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class7_hit_pru1,"
hexmask.long 0x2A4 0.--31. 1. "RX_STAT_CLASS7_PRU1,RX Class7 Hit Count  Wrt subtracts"
line.long 0x2A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class8_hit_pru1,"
hexmask.long 0x2A8 0.--31. 1. "RX_STAT_CLASS8_PRU1,RX Class8 Hit Count  Wrt subtracts"
line.long 0x2AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class9_hit_pru1,"
hexmask.long 0x2AC 0.--31. 1. "RX_STAT_CLASS9_PRU1,RX Class9 Hit Count  Wrt subtracts"
line.long 0x2B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class10_hit_pru1,"
hexmask.long 0x2B0 0.--31. 1. "RX_STAT_CLASS10_PRU1,RX Class10 Hit Count  Wrt subtracts"
line.long 0x2B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class11_hit_pru1,"
hexmask.long 0x2B4 0.--31. 1. "RX_STAT_CLASS11_PRU1,RX Class11 Hit Count  Wrt subtracts"
line.long 0x2B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class12_hit_pru1,"
hexmask.long 0x2B8 0.--31. 1. "RX_STAT_CLASS12_PRU1,RX Class12 Hit Count  Wrt subtracts"
line.long 0x2BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class13_hit_pru1,"
hexmask.long 0x2BC 0.--31. 1. "RX_STAT_CLASS13_PRU1,RX Class13 Hit Count  Wrt subtracts"
line.long 0x2C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class14_hit_pru1,"
hexmask.long 0x2C0 0.--31. 1. "RX_STAT_CLASS14_PRU1,RX Class14 Hit Count  Wrt subtracts"
line.long 0x2C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class15_hit_pru1,"
hexmask.long 0x2C4 0.--31. 1. "RX_STAT_CLASS15_PRU1,RX Class15 Hit Count  Wrt subtracts"
line.long 0x2C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_smd_frag_err_pru1,"
hexmask.long.byte 0x2C8 24.--31. 1. "RX_STAT_SMD_ERR_PRU1,RX SMDS Error Count  Inc when first none 0x55 does not match any valid SMD  Wrt subtracts"
hexmask.long.byte 0x2C8 16.--23. 1. "RX_STAT_FRAG_ERR_PRU1,RX Frag_Cnt Seq Error Count  Wrt subtracts"
newline
hexmask.long.byte 0x2C8 8.--15. 1. "RX_STAT_SMDC_ERR_PRU1,RX SMDCx Seq Error Count  Wrt subtracts"
hexmask.long.byte 0x2C8 0.--7. 1. "RX_STAT_SMDS_ERR_PRU1,RX SMDSx Seq Error Count  Wrt subtracts"
line.long 0x2CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_size_pru1,"
hexmask.long.word 0x2CC 0.--13. 1. "RX_STAT_BKT1_SIZE,RX Bucket1 Byte Size"
line.long 0x2D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_size_pru1,"
hexmask.long.word 0x2D0 0.--13. 1. "RX_STAT_BKT2_SIZE,RX Bucket2 Byte Size"
line.long 0x2D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_size_pru1,"
hexmask.long.word 0x2D4 0.--13. 1. "RX_STAT_BKT3_SIZE,RX Bucket3 Byte Size"
line.long 0x2D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_size_pru1,"
hexmask.long.word 0x2D8 0.--13. 1. "RX_STAT_BKT4_SIZE,RX Bucket4 Byte Size"
line.long 0x2DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_64_pru1,"
hexmask.long.word 0x2DC 0.--15. 1. "RX_64_FRM_CNT,RX 64Byte Frame Count Inc if 64B size"
line.long 0x2E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_pru1,"
hexmask.long.word 0x2E0 0.--15. 1. "RX_STAT_BKT1,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
line.long 0x2E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_pru1,"
hexmask.long.word 0x2E4 0.--15. 1. "RX_STAT_BKT2,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x2E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_pru1,"
hexmask.long.word 0x2E8 0.--15. 1. "RX_STAT_BKT3,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x2EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_pru1,"
hexmask.long.word 0x2EC 0.--15. 1. "RX_STAT_BKT4,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x2F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt5_pru1,"
hexmask.long.word 0x2F0 0.--15. 1. "RX_STAT_BKT5,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
line.long 0x2F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_total_bytes_pru1,"
hexmask.long 0x2F4 0.--31. 1. "RX_STAT_TOTAL_BYTES_PRU,RX Total Byte Count"
line.long 0x2F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rxtx_stat_total_bytes_pru1,"
hexmask.long 0x2F8 0.--31. 1. "RXTX_STAT_TOTAL_BYTES_PRU,RX and TX Total Byte Count"
line.long 0x2FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_good_port1,"
hexmask.long 0x2FC 0.--31. 1. "TX_GOOD_FRM_CNT,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
line.long 0x300 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bc_port1,"
hexmask.long.word 0x300 0.--15. 1. "TX_BC_FRM_CNT,TX BC Frame Count Inc if BC"
line.long 0x304 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_mc_port1,"
hexmask.long.word 0x304 0.--15. 1. "TX_MC_FRM_CNT,TX MC Frame Count Inc if MC"
line.long 0x308 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_odd_err_port1,"
hexmask.long.word 0x308 0.--15. 1. "TX_ODD_ERR_FRM_CNT,TX Odd Nibble Frame Count Inc if mii odd nibble"
line.long 0x30C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_underflow_err_port1,"
hexmask.long.word 0x30C 0.--15. 1. "TX_UNDERFLOW_CNT,TX MAX Underflow Error Cnt"
line.long 0x310 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_size_port1,"
hexmask.long.word 0x310 0.--15. 1. "TX_MAX_SIZE_FRM,TX MAX Size Frame Count Limit"
line.long 0x314 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_err_port1,"
hexmask.long.word 0x314 0.--15. 1. "TX_MAX_ERR_FRM_CNT,TX MAX Size Err Frame Count Inc if > max Limit"
line.long 0x318 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_size_port1,"
hexmask.long.word 0x318 0.--15. 1. "TX_MIN_SIZE_FRM,TX MIN Size Frame Count Limit"
line.long 0x31C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_err_port1,"
hexmask.long.word 0x31C 0.--15. 1. "TX_MIN_ERR_FRM_CNT,TX MIN Size Err Frame Count Inc if < min Limit"
line.long 0x320 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_size_port1,"
hexmask.long.word 0x320 0.--13. 1. "TX_STAT_BKT1_SIZE,TX Bucket1 Byte Size"
line.long 0x324 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_size_port1,"
hexmask.long.word 0x324 0.--13. 1. "TX_STAT_BKT2_SIZE,TX Bucket2 Byte Size"
line.long 0x328 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_size_port1,"
hexmask.long.word 0x328 0.--13. 1. "TX_STAT_BKT3_SIZE,TX Bucket3 Byte Size"
line.long 0x32C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_size_port1,"
hexmask.long.word 0x32C 0.--13. 1. "TX_STAT_BKT4_SIZE,TX Bucket4 Byte Size"
line.long 0x330 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_64_port1,"
hexmask.long.word 0x330 0.--15. 1. "TX_64_FRM_CNT,TX 64Byte Frame Count Inc if 64B"
line.long 0x334 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_port1,"
hexmask.long.word 0x334 0.--15. 1. "TX_STAT_BKT1,TX Bucket1 Inc if <= than Bucket1"
line.long 0x338 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_port1,"
hexmask.long.word 0x338 0.--15. 1. "TX_STAT_BKT2,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x33C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_port1,"
hexmask.long.word 0x33C 0.--15. 1. "TX_STAT_BKT3,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x340 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_port1,"
hexmask.long.word 0x340 0.--15. 1. "TX_STAT_BKT4,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x344 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt5_port1,"
hexmask.long.word 0x344 0.--15. 1. "TX_STAT_BKT5,TX Bucket5 Inc if > than Bucket4 Byte Size"
line.long 0x348 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_total_bytes_port1,"
hexmask.long 0x348 0.--31. 1. "TX_TOTAL_STAT_BYTES_PORT,TX Total Byte Count of all Frames"
line.long 0x34C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_tag_port1,"
hexmask.long 0x34C 0.--31. 1. "TX_HSR_TAG,HSR TAG"
line.long 0x350 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_seq_port1,"
hexmask.long.word 0x350 0.--15. 1. "TX_HSR_SEQ,HSR Seq count. It will incr for every HSR type"
line.long 0x354 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_type_tag_port1,"
hexmask.long.word 0x354 0.--15. 1. "TX_VLAN_TYPE_TAG,TX VLAN Type Tag  match to enable VLAN removal"
line.long 0x358 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_ins_tag_port1,"
hexmask.long 0x358 0.--31. 1. "TX_VLAN_INS_TAG,TX VLAN Insertion"
group.long 0xD00++0xFF
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue0,"
hexmask.long.word 0x0 0.--15. 1. "QUEUE_H_PTR0,Queue 0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue1,"
hexmask.long.word 0x4 0.--15. 1. "QUEUE_H_PTR1,Queue 1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue2,"
hexmask.long.word 0x8 0.--15. 1. "QUEUE_H_PTR2,Queue 2"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue3,"
hexmask.long.word 0xC 0.--15. 1. "QUEUE_H_PTR3,Queue 3"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue4,"
hexmask.long.word 0x10 0.--15. 1. "QUEUE_H_PTR4,Queue 4"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue5,"
hexmask.long.word 0x14 0.--15. 1. "QUEUE_H_PTR5,Queue 5"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue6,"
hexmask.long.word 0x18 0.--15. 1. "QUEUE_H_PTR6,Queue 6"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue7,"
hexmask.long.word 0x1C 0.--15. 1. "QUEUE_H_PTR7,Queue 7"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue8,"
hexmask.long.word 0x20 0.--15. 1. "QUEUE_H_PTR8,Queue 8"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue9,"
hexmask.long.word 0x24 0.--15. 1. "QUEUE_H_PTR9,Queue 9"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue10,"
hexmask.long.word 0x28 0.--15. 1. "QUEUE_H_PTR10,Queue 10"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue11,"
hexmask.long.word 0x2C 0.--15. 1. "QUEUE_H_PTR11,Queue 11"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue12,"
hexmask.long.word 0x30 0.--15. 1. "QUEUE_H_PTR12,Queue 12"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue13,"
hexmask.long.word 0x34 0.--15. 1. "QUEUE_H_PTR13,Queue 13"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue14,"
hexmask.long.word 0x38 0.--15. 1. "QUEUE_H_PTR14,Queue 14"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue15,"
hexmask.long.word 0x3C 0.--15. 1. "QUEUE_H_PTR15,Queue 15"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue16,"
hexmask.long.word 0x40 0.--15. 1. "QUEUE_H_PTR16,Queue 16"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue17,"
hexmask.long.word 0x44 0.--15. 1. "QUEUE_H_PTR17,Queue 17"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue18,"
hexmask.long.word 0x48 0.--15. 1. "QUEUE_H_PTR18,Queue 18"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue19,"
hexmask.long.word 0x4C 0.--15. 1. "QUEUE_H_PTR19,Queue 19"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue20,"
hexmask.long.word 0x50 0.--15. 1. "QUEUE_H_PTR20,Queue 20"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue21,"
hexmask.long.word 0x54 0.--15. 1. "QUEUE_H_PTR21,Queue 21"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue22,"
hexmask.long.word 0x58 0.--15. 1. "QUEUE_H_PTR22,Queue 22"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue23,"
hexmask.long.word 0x5C 0.--15. 1. "QUEUE_H_PTR23,Queue 23"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue24,"
hexmask.long.word 0x60 0.--15. 1. "QUEUE_H_PTR24,Queue 24"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue25,"
hexmask.long.word 0x64 0.--15. 1. "QUEUE_H_PTR25,Queue 25"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue26,"
hexmask.long.word 0x68 0.--15. 1. "QUEUE_H_PTR26,Queue 26"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue27,"
hexmask.long.word 0x6C 0.--15. 1. "QUEUE_H_PTR27,Queue 27"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue28,"
hexmask.long.word 0x70 0.--15. 1. "QUEUE_H_PTR28,Queue 28"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue29,"
hexmask.long.word 0x74 0.--15. 1. "QUEUE_H_PTR29,Queue 29"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue30,"
hexmask.long.word 0x78 0.--15. 1. "QUEUE_H_PTR30,Queue 30"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue31,"
hexmask.long.word 0x7C 0.--15. 1. "QUEUE_H_PTR31,Queue 31"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue32,"
hexmask.long.word 0x80 0.--15. 1. "QUEUE_H_PTR32,Queue 32"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue33,"
hexmask.long.word 0x84 0.--15. 1. "QUEUE_H_PTR33,Queue 33"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue34,"
hexmask.long.word 0x88 0.--15. 1. "QUEUE_H_PTR34,Queue 34"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue35,"
hexmask.long.word 0x8C 0.--15. 1. "QUEUE_H_PTR35,Queue 35"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue36,"
hexmask.long.word 0x90 0.--15. 1. "QUEUE_H_PTR36,Queue 36"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue37,"
hexmask.long.word 0x94 0.--15. 1. "QUEUE_H_PTR37,Queue 37"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue38,"
hexmask.long.word 0x98 0.--15. 1. "QUEUE_H_PTR38,Queue 38"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue39,"
hexmask.long.word 0x9C 0.--15. 1. "QUEUE_H_PTR39,Queue 39"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue40,"
hexmask.long.word 0xA0 0.--15. 1. "QUEUE_H_PTR40,Queue 40"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue41,"
hexmask.long.word 0xA4 0.--15. 1. "QUEUE_H_PTR41,Queue 41"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue42,"
hexmask.long.word 0xA8 0.--15. 1. "QUEUE_H_PTR42,Queue 42"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue43,"
hexmask.long.word 0xAC 0.--15. 1. "QUEUE_H_PTR43,Queue 43"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue44,"
hexmask.long.word 0xB0 0.--15. 1. "QUEUE_H_PTR44,Queue 44"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue45,"
hexmask.long.word 0xB4 0.--15. 1. "QUEUE_H_PTR45,Queue 45"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue46,"
hexmask.long.word 0xB8 0.--15. 1. "QUEUE_H_PTR46,Queue 46"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue47,"
hexmask.long.word 0xBC 0.--15. 1. "QUEUE_H_PTR47,Queue 47"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue48,"
hexmask.long.word 0xC0 0.--15. 1. "QUEUE_H_PTR48,Queue 48"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue49,"
hexmask.long.word 0xC4 0.--15. 1. "QUEUE_H_PTR49,Queue 49"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue50,"
hexmask.long.word 0xC8 0.--15. 1. "QUEUE_H_PTR50,Queue 50"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue51,"
hexmask.long.word 0xCC 0.--15. 1. "QUEUE_H_PTR51,Queue 51"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue52,"
hexmask.long.word 0xD0 0.--15. 1. "QUEUE_H_PTR52,Queue 52"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue53,"
hexmask.long.word 0xD4 0.--15. 1. "QUEUE_H_PTR53,Queue 53"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue54,"
hexmask.long.word 0xD8 0.--15. 1. "QUEUE_H_PTR54,Queue 54"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue55,"
hexmask.long.word 0xDC 0.--15. 1. "QUEUE_H_PTR55,Queue 55"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue56,"
hexmask.long.word 0xE0 0.--15. 1. "QUEUE_H_PTR56,Queue 56"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue57,"
hexmask.long.word 0xE4 0.--15. 1. "QUEUE_H_PTR57,Queue 57"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue58,"
hexmask.long.word 0xE8 0.--15. 1. "QUEUE_H_PTR58,Queue 58"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue59,"
hexmask.long.word 0xEC 0.--15. 1. "QUEUE_H_PTR59,Queue 59"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue60,"
hexmask.long.word 0xF0 0.--15. 1. "QUEUE_H_PTR60,Queue 60"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue61,"
hexmask.long.word 0xF4 0.--15. 1. "QUEUE_H_PTR61,Queue 61"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue62,"
hexmask.long.word 0xF8 0.--15. 1. "QUEUE_H_PTR62,Queue 62"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue63,"
hexmask.long.word 0xFC 0.--15. 1. "QUEUE_H_PTR63,Queue 63"
rgroup.long 0xE00++0x13F
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek0,"
hexmask.long.word 0x0 0.--15. 1. "QUEUE_H_PEEK_PTR0,Queue 0 Peek portal"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek1,"
hexmask.long.word 0x4 0.--15. 1. "QUEUE_H_PEEK_PTR1,Queue 1 Peek portal"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek2,"
hexmask.long.word 0x8 0.--15. 1. "QUEUE_H_PEEK_PTR2,Queue 2 Peek portal"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek3,"
hexmask.long.word 0xC 0.--15. 1. "QUEUE_H_PEEK_PTR3,Queue 3 Peek portal"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek4,"
hexmask.long.word 0x10 0.--15. 1. "QUEUE_H_PEEK_PTR4,Queue 4 Peek portal"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek5,"
hexmask.long.word 0x14 0.--15. 1. "QUEUE_H_PEEK_PTR5,Queue 5 Peek portal"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek6,"
hexmask.long.word 0x18 0.--15. 1. "QUEUE_H_PEEK_PTR6,Queue 6 Peek portal"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek7,"
hexmask.long.word 0x1C 0.--15. 1. "QUEUE_H_PEEK_PTR7,Queue 7 Peek portal"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek8,"
hexmask.long.word 0x20 0.--15. 1. "QUEUE_H_PEEK_PTR8,Queue 8 Peek portal"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek9,"
hexmask.long.word 0x24 0.--15. 1. "QUEUE_H_PEEK_PTR9,Queue 9 Peek portal"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek10,"
hexmask.long.word 0x28 0.--15. 1. "QUEUE_H_PEEK_PTR10,Queue 10 Peek portal"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek11,"
hexmask.long.word 0x2C 0.--15. 1. "QUEUE_H_PEEK_PTR11,Queue 11 Peek portal"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek12,"
hexmask.long.word 0x30 0.--15. 1. "QUEUE_H_PEEK_PTR12,Queue 12 Peek portal"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek13,"
hexmask.long.word 0x34 0.--15. 1. "QUEUE_H_PEEK_PTR13,Queue 13 Peek portal"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek14,"
hexmask.long.word 0x38 0.--15. 1. "QUEUE_H_PEEK_PTR14,Queue 14 Peek portal"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek15,"
hexmask.long.word 0x3C 0.--15. 1. "QUEUE_H_PEEK_PTR15,Queue 15 Peek portal"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt0,"
hexmask.long.word 0x40 0.--15. 1. "QUEUE_CNT_ENTRIES_0,Queue Entry Count0"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt1,"
hexmask.long.word 0x44 0.--15. 1. "QUEUE_CNT_ENTRIES_1,Queue Entry Count1"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt2,"
hexmask.long.word 0x48 0.--15. 1. "QUEUE_CNT_ENTRIES_2,Queue Entry Count2"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt3,"
hexmask.long.word 0x4C 0.--15. 1. "QUEUE_CNT_ENTRIES_3,Queue Entry Count3"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt4,"
hexmask.long.word 0x50 0.--15. 1. "QUEUE_CNT_ENTRIES_4,Queue Entry Count4"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt5,"
hexmask.long.word 0x54 0.--15. 1. "QUEUE_CNT_ENTRIES_5,Queue Entry Count5"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt6,"
hexmask.long.word 0x58 0.--15. 1. "QUEUE_CNT_ENTRIES_6,Queue Entry Count6"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt7,"
hexmask.long.word 0x5C 0.--15. 1. "QUEUE_CNT_ENTRIES_7,Queue Entry Count7"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt8,"
hexmask.long.word 0x60 0.--15. 1. "QUEUE_CNT_ENTRIES_8,Queue Entry Count8"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt9,"
hexmask.long.word 0x64 0.--15. 1. "QUEUE_CNT_ENTRIES_9,Queue Entry Count9"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt10,"
hexmask.long.word 0x68 0.--15. 1. "QUEUE_CNT_ENTRIES_10,Queue Entry Count10"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt11,"
hexmask.long.word 0x6C 0.--15. 1. "QUEUE_CNT_ENTRIES_11,Queue Entry Count11"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt12,"
hexmask.long.word 0x70 0.--15. 1. "QUEUE_CNT_ENTRIES_12,Queue Entry Count12"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt13,"
hexmask.long.word 0x74 0.--15. 1. "QUEUE_CNT_ENTRIES_13,Queue Entry Count13"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt14,"
hexmask.long.word 0x78 0.--15. 1. "QUEUE_CNT_ENTRIES_14,Queue Entry Count14"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt15,"
hexmask.long.word 0x7C 0.--15. 1. "QUEUE_CNT_ENTRIES_15,Queue Entry Count15"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt16,"
hexmask.long.word 0x80 0.--15. 1. "QUEUE_CNT_ENTRIES_16,Queue Entry Count16"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt17,"
hexmask.long.word 0x84 0.--15. 1. "QUEUE_CNT_ENTRIES_17,Queue Entry Count17"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt18,"
hexmask.long.word 0x88 0.--15. 1. "QUEUE_CNT_ENTRIES_18,Queue Entry Count18"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt19,"
hexmask.long.word 0x8C 0.--15. 1. "QUEUE_CNT_ENTRIES_19,Queue Entry Count19"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt20,"
hexmask.long.word 0x90 0.--15. 1. "QUEUE_CNT_ENTRIES_20,Queue Entry Count20"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt21,"
hexmask.long.word 0x94 0.--15. 1. "QUEUE_CNT_ENTRIES_21,Queue Entry Count21"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt22,"
hexmask.long.word 0x98 0.--15. 1. "QUEUE_CNT_ENTRIES_22,Queue Entry Count22"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt23,"
hexmask.long.word 0x9C 0.--15. 1. "QUEUE_CNT_ENTRIES_23,Queue Entry Count23"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt24,"
hexmask.long.word 0xA0 0.--15. 1. "QUEUE_CNT_ENTRIES_24,Queue Entry Count24"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt25,"
hexmask.long.word 0xA4 0.--15. 1. "QUEUE_CNT_ENTRIES_25,Queue Entry Count25"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt26,"
hexmask.long.word 0xA8 0.--15. 1. "QUEUE_CNT_ENTRIES_26,Queue Entry Count26"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt27,"
hexmask.long.word 0xAC 0.--15. 1. "QUEUE_CNT_ENTRIES_27,Queue Entry Count27"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt28,"
hexmask.long.word 0xB0 0.--15. 1. "QUEUE_CNT_ENTRIES_28,Queue Entry Count28"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt29,"
hexmask.long.word 0xB4 0.--15. 1. "QUEUE_CNT_ENTRIES_29,Queue Entry Count29"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt30,"
hexmask.long.word 0xB8 0.--15. 1. "QUEUE_CNT_ENTRIES_30,Queue Entry Count30"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt31,"
hexmask.long.word 0xBC 0.--15. 1. "QUEUE_CNT_ENTRIES_31,Queue Entry Count31"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt32,"
hexmask.long.word 0xC0 0.--15. 1. "QUEUE_CNT_ENTRIES_32,Queue Entry Count32"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt33,"
hexmask.long.word 0xC4 0.--15. 1. "QUEUE_CNT_ENTRIES_33,Queue Entry Count33"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt34,"
hexmask.long.word 0xC8 0.--15. 1. "QUEUE_CNT_ENTRIES_34,Queue Entry Count34"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt35,"
hexmask.long.word 0xCC 0.--15. 1. "QUEUE_CNT_ENTRIES_35,Queue Entry Count35"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt36,"
hexmask.long.word 0xD0 0.--15. 1. "QUEUE_CNT_ENTRIES_36,Queue Entry Count36"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt37,"
hexmask.long.word 0xD4 0.--15. 1. "QUEUE_CNT_ENTRIES_37,Queue Entry Count37"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt38,"
hexmask.long.word 0xD8 0.--15. 1. "QUEUE_CNT_ENTRIES_38,Queue Entry Count38"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt39,"
hexmask.long.word 0xDC 0.--15. 1. "QUEUE_CNT_ENTRIES_39,Queue Entry Count39"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt40,"
hexmask.long.word 0xE0 0.--15. 1. "QUEUE_CNT_ENTRIES_40,Queue Entry Count40"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt41,"
hexmask.long.word 0xE4 0.--15. 1. "QUEUE_CNT_ENTRIES_41,Queue Entry Count41"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt42,"
hexmask.long.word 0xE8 0.--15. 1. "QUEUE_CNT_ENTRIES_42,Queue Entry Count42"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt43,"
hexmask.long.word 0xEC 0.--15. 1. "QUEUE_CNT_ENTRIES_43,Queue Entry Count43"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt44,"
hexmask.long.word 0xF0 0.--15. 1. "QUEUE_CNT_ENTRIES_44,Queue Entry Count44"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt45,"
hexmask.long.word 0xF4 0.--15. 1. "QUEUE_CNT_ENTRIES_45,Queue Entry Count45"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt46,"
hexmask.long.word 0xF8 0.--15. 1. "QUEUE_CNT_ENTRIES_46,Queue Entry Count46"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt47,"
hexmask.long.word 0xFC 0.--15. 1. "QUEUE_CNT_ENTRIES_47,Queue Entry Count47"
line.long 0x100 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt48,"
hexmask.long.word 0x100 0.--15. 1. "QUEUE_CNT_ENTRIES_48,Queue Entry Count48"
line.long 0x104 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt49,"
hexmask.long.word 0x104 0.--15. 1. "QUEUE_CNT_ENTRIES_49,Queue Entry Count49"
line.long 0x108 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt50,"
hexmask.long.word 0x108 0.--15. 1. "QUEUE_CNT_ENTRIES_50,Queue Entry Count50"
line.long 0x10C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt51,"
hexmask.long.word 0x10C 0.--15. 1. "QUEUE_CNT_ENTRIES_51,Queue Entry Count51"
line.long 0x110 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt52,"
hexmask.long.word 0x110 0.--15. 1. "QUEUE_CNT_ENTRIES_52,Queue Entry Count52"
line.long 0x114 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt53,"
hexmask.long.word 0x114 0.--15. 1. "QUEUE_CNT_ENTRIES_53,Queue Entry Count53"
line.long 0x118 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt54,"
hexmask.long.word 0x118 0.--15. 1. "QUEUE_CNT_ENTRIES_54,Queue Entry Count54"
line.long 0x11C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt55,"
hexmask.long.word 0x11C 0.--15. 1. "QUEUE_CNT_ENTRIES_55,Queue Entry Count55"
line.long 0x120 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt56,"
hexmask.long.word 0x120 0.--15. 1. "QUEUE_CNT_ENTRIES_56,Queue Entry Count56"
line.long 0x124 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt57,"
hexmask.long.word 0x124 0.--15. 1. "QUEUE_CNT_ENTRIES_57,Queue Entry Count57"
line.long 0x128 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt58,"
hexmask.long.word 0x128 0.--15. 1. "QUEUE_CNT_ENTRIES_58,Queue Entry Count58"
line.long 0x12C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt59,"
hexmask.long.word 0x12C 0.--15. 1. "QUEUE_CNT_ENTRIES_59,Queue Entry Count59"
line.long 0x130 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt60,"
hexmask.long.word 0x130 0.--15. 1. "QUEUE_CNT_ENTRIES_60,Queue Entry Count60"
line.long 0x134 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt61,"
hexmask.long.word 0x134 0.--15. 1. "QUEUE_CNT_ENTRIES_61,Queue Entry Count61"
line.long 0x138 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt62,"
hexmask.long.word 0x138 0.--15. 1. "QUEUE_CNT_ENTRIES_62,Queue Entry Count62"
line.long 0x13C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt63,"
hexmask.long.word 0x13C 0.--15. 1. "QUEUE_CNT_ENTRIES_63,Queue Entry Count63"
group.long 0xF40++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_reset,"
hexmask.long.byte 0x0 0.--5. 1. "RESET_QUEUE_ID,Reset Queue ID"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG"
base ad:0x32000
group.long 0x0++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rxcfg0,MIIRXCFG0Register"
bitfld.long 0x0 9. "RX_EOF_SCLR_DIS0," "0,1"
bitfld.long 0x0 8. "RX_ERR_RAW0," "0,1"
bitfld.long 0x0 7. "RX_SFD_RAW0," "0,1"
newline
bitfld.long 0x0 6. "RX_AUTO_FWD_PRE0," "0,1"
bitfld.long 0x0 5. "RX_BYTE_SWAP0," "0,1"
bitfld.long 0x0 4. "RX_L2_EN0," "0,1"
newline
bitfld.long 0x0 3. "RX_MUX_SEL0," "0,1"
bitfld.long 0x0 2. "RX_CUT_PREAMBLE0," "0,1"
bitfld.long 0x0 1. "RX_DATA_RDY_MODE_DIS0," "0,1"
newline
bitfld.long 0x0 0. "RX_ENABLE0," "0,1"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rxcfg1,MIIRXCFG1Register"
bitfld.long 0x4 9. "RX_EOF_SCLR_DIS1," "0,1"
bitfld.long 0x4 8. "RX_ERR_RAW1," "0,1"
bitfld.long 0x4 7. "RX_SFD_RAW1," "0,1"
newline
bitfld.long 0x4 6. "RX_AUTO_FWD_PRE1," "0,1"
bitfld.long 0x4 5. "RX_BYTE_SWAP1," "0,1"
bitfld.long 0x4 4. "RX_L2_EN1," "0,1"
newline
bitfld.long 0x4 3. "RX_MUX_SEL1," "0,1"
bitfld.long 0x4 2. "RX_CUT_PREAMBLE1," "0,1"
bitfld.long 0x4 1. "RX_DATA_RDY_MODE_DIS1," "0,1"
newline
bitfld.long 0x4 0. "RX_ENABLE1," "0,1"
group.long 0x10++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_txcfg0,MIITXCFG0Register"
bitfld.long 0x0 28.--30. "TX_CLK_DELAY0," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 16.--25. 1. "TX_START_DELAY0,"
bitfld.long 0x0 12. "TX_IPG_WIRE_CLK_EN0," "0,1"
newline
bitfld.long 0x0 11. "TX_32_MODE_EN0," "0,1"
bitfld.long 0x0 10. "PRE_TX_AUTO_ESC_ERR0," "0,1"
bitfld.long 0x0 9. "PRE_TX_AUTO_SEQUENCE0," "0,1"
newline
bitfld.long 0x0 8. "TX_MUX_SEL0," "0,1"
bitfld.long 0x0 3. "TX_BYTE_SWAP0," "0,1"
bitfld.long 0x0 2. "TX_EN_MODE0," "0,1"
newline
bitfld.long 0x0 1. "TX_AUTO_PREAMBLE0," "0,1"
bitfld.long 0x0 0. "TX_ENABLE0," "0,1"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_txcfg1,MIITXCFG1Register"
bitfld.long 0x4 28.--30. "TX_CLK_DELAY1," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 16.--25. 1. "TX_START_DELAY1,"
bitfld.long 0x4 12. "TX_IPG_WIRE_CLK_EN1," "0,1"
newline
bitfld.long 0x4 11. "TX_32_MODE_EN1," "0,1"
bitfld.long 0x4 10. "PRE_TX_AUTO_ESC_ERR1," "0,1"
bitfld.long 0x4 9. "PRE_TX_AUTO_SEQUENCE1," "0,1"
newline
bitfld.long 0x4 8. "TX_MUX_SEL1," "0,1"
bitfld.long 0x4 3. "TX_BYTE_SWAP1," "0,1"
bitfld.long 0x4 2. "TX_EN_MODE1," "0,1"
newline
bitfld.long 0x4 1. "TX_AUTO_PREAMBLE1," "0,1"
bitfld.long 0x4 0. "TX_ENABLE1," "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_crc0,MIITXCRC0Register"
hexmask.long 0x0 0.--31. 1. "TX_CRC0,Transmit CRC for last packet"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_crc1,MIITXCRC1Register"
hexmask.long 0x4 0.--31. 1. "TX_CRC1,Transmit CRC for last packet"
group.long 0x30++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_ipg0,MIITXIPG0Register"
hexmask.long.word 0x0 0.--15. 1. "TX_IPG0,Transmit IPG"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_ipg1,MIITXIPG1Register"
hexmask.long.word 0x4 0.--15. 1. "TX_IPG1,Transmit IPG"
rgroup.long 0x38++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_prs0,MIIPortStatus0Register"
bitfld.long 0x0 1. "SYNC_PORT0_CRS,sync_port0_crs" "0,1"
bitfld.long 0x0 0. "SYNC_PORT0_COL,sync_port0_col" "0,1"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_prs1,MIIPortStatus1Register"
bitfld.long 0x4 1. "SYNC_PORT1_CRS,sync_port1_crs" "0,1"
bitfld.long 0x4 0. "SYNC_PORT1_COL,sync_port1_col" "0,1"
group.long 0x40++0x17
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_frms0,MIIRXFRMS0Register"
hexmask.long.word 0x0 16.--31. 1. "RX_MAX_FRM0,rx_max_frm0"
hexmask.long.word 0x0 0.--15. 1. "RX_MIN_FRM0,rx_min_frm0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_frms1,MIIRXFRMS1Register"
hexmask.long.word 0x4 16.--31. 1. "RX_MAX_FRM1,rx_max_frm1"
hexmask.long.word 0x4 0.--15. 1. "RX_MIN_FRM1,rx_min_frm1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_pcnt0,MIIRXPCNT0Register"
hexmask.long.byte 0x8 4.--8. 1. "RX_MAX_PCNT0,rx_max_pcnt0"
hexmask.long.byte 0x8 0.--3. 1. "RX_MIN_PCNT0,rx_min_pcnt0"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_pcnt1,MIIRXPCNT1Register"
hexmask.long.byte 0xC 4.--8. 1. "RX_MAX_PCNT1,rx_max_pcnt1"
hexmask.long.byte 0xC 0.--3. 1. "RX_MIN_PCNT1,rx_min_pcnt1"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_err0,MIIRXERR0Register"
bitfld.long 0x10 3. "RX_MAX_FRM_ERR0,rx_max_frm_err0" "0,1"
bitfld.long 0x10 2. "RX_MIN_FRM_ERR0,rx_min_frm_err0" "0,1"
bitfld.long 0x10 1. "RX_MAX_PCNT_ERR0,rx_max_pcnt_err0" "0,1"
newline
bitfld.long 0x10 0. "RX_MIN_PCNT_ERR0,rx_min_pcnt_err0" "0,1"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_err1,MIIRXERR1Register"
bitfld.long 0x14 3. "RX_MAX_FRM_ERR1,rx_max_frm_err1" "0,1"
bitfld.long 0x14 2. "RX_MIN_FRM_ERR1,rx_min_frm_err1" "0,1"
bitfld.long 0x14 1. "RX_MAX_PCNT_ERR1,rx_max_pcnt_err1" "0,1"
newline
bitfld.long 0x14 0. "RX_MIN_PCNT_ERR1,rx_min_pcnt_err1" "0,1"
rgroup.long 0x60++0xF
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_fifo_level0,MIIRXFIFOLEVEL0Register"
hexmask.long.byte 0x0 0.--7. 1. "RX_FIFO_LEVEL0,rx_fifo_level0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_fifo_level1,MIIRXFIFOLEVEL1Register"
hexmask.long.byte 0x4 0.--7. 1. "RX_FIFO_LEVEL1,rx_fifo_level1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_fifo_level0,MIIRXFIFOLEVEL0Register"
hexmask.long.byte 0x8 0.--7. 1. "TX_FIFO_LEVEL0,tx_fifo_level0"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_fifo_level1,MIIRXFIFOLEVEL1Register"
hexmask.long.byte 0xC 0.--7. 1. "TX_FIFO_LEVEL1,tx_fifo_level1"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"
base ad:0x33000
group.long 0x8++0x23
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru0_0,"
hexmask.long 0x0 0.--31. 1. "MAC_PRU0_0,MAC pru0 DA3:DA0 Used for SAV and DA match"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru0_1,"
hexmask.long.word 0x4 0.--15. 1. "MAC_PRU0_1,MAC pru0 DA5:DA4 Used for SAV and DA match"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru1_0,"
hexmask.long 0x8 0.--31. 1. "MAC_PRU1_0,MAC pru1 DA3:DA0 Used for SAV and DA match"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru1_1,"
hexmask.long.word 0xC 0.--15. 1. "MAC_PRU1_1,MAC pru1 DA5:DA4 Used for SAV and DA match"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_interface_0,"
hexmask.long 0x10 0.--31. 1. "MAC_INF_0,MAC Host interface DA3:DA0 Used for SAV and DA match"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_interface_1,"
hexmask.long.word 0x14 0.--15. 1. "MAC_INF_1,MAC Host interface DA5:DA4 Used for SAV and DA match"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_preempt_cfg,"
hexmask.long.byte 0x18 24.--31. 1. "SMD_R,Response frame TAG"
hexmask.long.byte 0x18 16.--23. 1. "SMD_V,Verification frame TAG"
newline
hexmask.long.byte 0x18 8.--15. 1. "EXP_SMD,None preemptable frame start  or express frame"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_smdt1s_cfg,"
hexmask.long.byte 0x1C 24.--31. 1. "SMDT1S_3,SMDT1S3 pattern"
hexmask.long.byte 0x1C 16.--23. 1. "SMDT1S_2,SMDT1S2 pattern"
newline
hexmask.long.byte 0x1C 8.--15. 1. "SMDT1S_1,SMDT1S1 pattern"
hexmask.long.byte 0x1C 0.--7. 1. "SMDT1S_0,SMDT1S0 pattern"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_smdt1c_cfg,"
hexmask.long.byte 0x20 24.--31. 1. "SMDT1C_3,SMDT1C3 pattern"
hexmask.long.byte 0x20 16.--23. 1. "SMDT1C_2,SMDT1C2 pattern"
newline
hexmask.long.byte 0x20 8.--15. 1. "SMDT1C_1,SMDT1C1 pattern"
hexmask.long.byte 0x20 0.--7. 1. "SMDT1C_0,SMDT1C0 pattern"
group.long 0x34++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_frag_cnt_cfg,"
hexmask.long.byte 0x0 24.--31. 1. "FRAG_CNT_3,FRAG Cnt3 pattern"
hexmask.long.byte 0x0 16.--23. 1. "FRAG_CNT_2,FRAG Cnt2 pattern"
newline
hexmask.long.byte 0x0 8.--15. 1. "FRAG_CNT_1,FRAG Cnt1 pattern"
hexmask.long.byte 0x0 0.--7. 1. "FRAG_CNT_0,FRAG Cnt0 pattern"
group.long 0x40++0xF
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push0,"
hexmask.long.byte 0x0 24.--31. 1. "PA_STAT_PUSH3_0,pa stat push3"
hexmask.long.byte 0x0 16.--23. 1. "PA_STAT_PUSH2_0,pa stat push2"
newline
hexmask.long.byte 0x0 8.--15. 1. "PA_STAT_PUSH1_0,pa stat push1"
hexmask.long.byte 0x0 0.--7. 1. "PA_STAT_PUSH0_0,pa stat push0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push1,"
hexmask.long.byte 0x4 24.--31. 1. "PA_STAT_PUSH3_1,pa stat push3"
hexmask.long.byte 0x4 16.--23. 1. "PA_STAT_PUSH2_1,pa stat push2"
newline
hexmask.long.byte 0x4 8.--15. 1. "PA_STAT_PUSH1_1,pa stat push1"
hexmask.long.byte 0x4 0.--7. 1. "PA_STAT_PUSH0_1,pa stat push0"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push2,"
hexmask.long.byte 0x8 24.--31. 1. "PA_STAT_PUSH3_2,pa stat push3"
hexmask.long.byte 0x8 16.--23. 1. "PA_STAT_PUSH2_2,pa stat push2"
newline
hexmask.long.byte 0x8 8.--15. 1. "PA_STAT_PUSH1_2,pa stat push1"
hexmask.long.byte 0x8 0.--7. 1. "PA_STAT_PUSH0_2,pa stat push0"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push3,"
hexmask.long.byte 0xC 24.--31. 1. "PA_STAT_PUSH3_3,pa stat push3"
hexmask.long.byte 0xC 16.--23. 1. "PA_STAT_PUSH2_3,pa stat push2"
newline
hexmask.long.byte 0xC 8.--15. 1. "PA_STAT_PUSH1_3,pa stat push1"
hexmask.long.byte 0xC 0.--7. 1. "PA_STAT_PUSH0_3,pa stat push0"
group.long 0x60++0xAB
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_gen_cfg1,"
hexmask.long.tbyte 0x0 8.--25. 1. "SMEM_VLAN_OFFSET,SMEM VLAN FID table base address"
hexmask.long.byte 0x0 3.--6. 1. "FDB_HASH_SIZE,FDB hash size 0:64 1:128 2:256 3:512 4:1024 5:2048"
newline
bitfld.long 0x0 0.--1. "FDB_BUCKET_SIZE,FDB buket size 0:1 1:2 2:4 3:8" "0: 1,1: 2,2: 4,3: 8"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_gen_cfg2,"
hexmask.long.byte 0x4 9.--12. 1. "FDB_GEN_MODE_BYTE_EN,FDB General Mode Byte compare size 0 = 1 Byte  15 = 16 Bytes"
bitfld.long 0x4 8. "FDB_GEN_MODE_EN_BK1,FDB General Mode Enable Bank1 if set PRU0/PRU1/HOST will get disabled" "0,1"
newline
bitfld.long 0x4 7. "FDB_GEN_MODE_EN_BK0,FDB General Mode Enable Bank0 if set PRU0/PRU1/HOST will get disabled" "0,1"
bitfld.long 0x4 6. "FDB_VLAN_EN,FDB Global VLAN Enable" "0,1"
newline
bitfld.long 0x4 5. "FDB_HSR_EN,FDB Global HSR Enable note VLAN most be disabled" "0,1"
bitfld.long 0x4 2. "FDB_HOST_EN,FDB HOST Enable" "0,1"
newline
bitfld.long 0x4 1. "FDB_PRU1_EN,FDB PRU1 Enable" "0,1"
bitfld.long 0x4 0. "FDB_PRU0_EN,FDB PRU0 Enable" "0,1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_gen_status,"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_df_vlan,"
hexmask.long.word 0xC 16.--27. 1. "FDB_PRU1_DF_VLAN,FDB Default VLAN for PRU1"
hexmask.long.word 0xC 0.--11. 1. "FDB_PRU0_DF_VLAN,FDB Default VLAN for PRU0"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_da0,"
hexmask.long 0x10 0.--31. 1. "FDB_HOST_DA0,FDB HOST DA3:0"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_da1,"
hexmask.long.word 0x14 0.--15. 1. "FDB_HOST_DA1,FDB HOST DA5:4"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_sa0,"
hexmask.long 0x18 0.--31. 1. "FDB_HOST_SA0,FDB HOST SA3:0"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_vlan_sa1,"
hexmask.long.word 0x1C 16.--31. 1. "FDB_HOST_VLAN_HSR,FDB HOST VLAN[11:0] OR HSR[15:0]"
hexmask.long.word 0x1C 0.--15. 1. "FDB_HOST_SA1,FDB HOST SA5:4"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_start_len_pru0,"
hexmask.long.byte 0x20 16.--19. 1. "FT1_LEN,Defines the total number of Bytes Filter1 will check before Valid bit is set"
hexmask.long.word 0x20 0.--14. 1. "FT1_START,Byte count start for Filter1. Any wrt will clear all Filter1 Status Bits"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_cfg_pru0,"
bitfld.long 0x24 14.--15. "FT1_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 12.--13. "FT1_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x24 10.--11. "FT1_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 8.--9. "FT1_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x24 6.--7. "FT1_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 4.--5. "FT1_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x24 2.--3. "FT1_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 0.--1. "FT1_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da0_pru0,"
hexmask.long 0x28 0.--31. 1. "FT1_0_DA0,Filter1 DA4:DA1"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da1_pru0,"
hexmask.long.word 0x2C 0.--15. 1. "FT1_0_DA1,Filter1 DA6:DA5"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask0_pru0,"
hexmask.long 0x30 0.--31. 1. "FT1_0_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask1_pru0,"
hexmask.long.word 0x34 0.--15. 1. "FT1_0_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da0_pru0,"
hexmask.long 0x38 0.--31. 1. "FT1_1_DA0,Filter1 DA4:DA1"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da1_pru0,"
hexmask.long.word 0x3C 0.--15. 1. "FT1_1_DA1,Filter1 DA6:DA5"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask0_pru0,"
hexmask.long 0x40 0.--31. 1. "FT1_1_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask1_pru0,"
hexmask.long.word 0x44 0.--15. 1. "FT1_1_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da0_pru0,"
hexmask.long 0x48 0.--31. 1. "FT1_2_DA0,Filter1 DA4:DA1"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da1_pru0,"
hexmask.long.word 0x4C 0.--15. 1. "FT1_2_DA1,Filter1 DA6:DA5"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask0_pru0,"
hexmask.long 0x50 0.--31. 1. "FT1_2_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask1_pru0,"
hexmask.long.word 0x54 0.--15. 1. "FT1_2_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da0_pru0,"
hexmask.long 0x58 0.--31. 1. "FT1_3_DA0,Filter1 DA4:DA1"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da1_pru0,"
hexmask.long.word 0x5C 0.--15. 1. "FT1_3_DA1,Filter1 DA6:DA5"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask0_pru0,"
hexmask.long 0x60 0.--31. 1. "FT1_3_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask1_pru0,"
hexmask.long.word 0x64 0.--15. 1. "FT1_3_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da0_pru0,"
hexmask.long 0x68 0.--31. 1. "FT1_4_DA0,Filter1 DA4:DA1"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da1_pru0,"
hexmask.long.word 0x6C 0.--15. 1. "FT1_4_DA1,Filter1 DA6:DA5"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask0_pru0,"
hexmask.long 0x70 0.--31. 1. "FT1_4_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask1_pru0,"
hexmask.long.word 0x74 0.--15. 1. "FT1_4_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da0_pru0,"
hexmask.long 0x78 0.--31. 1. "FT1_5_DA0,Filter1 DA4:DA1"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da1_pru0,"
hexmask.long.word 0x7C 0.--15. 1. "FT1_5_DA1,Filter1 DA6:DA5"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask0_pru0,"
hexmask.long 0x80 0.--31. 1. "FT1_5_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask1_pru0,"
hexmask.long.word 0x84 0.--15. 1. "FT1_5_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da0_pru0,"
hexmask.long 0x88 0.--31. 1. "FT1_6_DA0,Filter1 DA4:DA1"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da1_pru0,"
hexmask.long.word 0x8C 0.--15. 1. "FT1_6_DA1,Filter1 DA6:DA5"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask0_pru0,"
hexmask.long 0x90 0.--31. 1. "FT1_6_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask1_pru0,"
hexmask.long.word 0x94 0.--15. 1. "FT1_6_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da0_pru0,"
hexmask.long 0x98 0.--31. 1. "FT1_7_DA0,Filter1 DA4:DA1"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da1_pru0,"
hexmask.long.word 0x9C 0.--15. 1. "FT1_7_DA1,Filter1 DA6:DA5"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask0_pru0,"
hexmask.long 0xA0 0.--31. 1. "FT1_7_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask1_pru0,"
hexmask.long.word 0xA4 0.--15. 1. "FT1_7_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_pru0,"
hexmask.long.word 0xA8 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x10C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x110++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_0_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_0_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_len_pru0,"
bitfld.long 0x8 24. "FT3_0_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_0_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_0_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_0_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_0_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_0_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_0_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x12C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x130++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_1_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_1_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_len_pru0,"
bitfld.long 0x8 24. "FT3_1_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_1_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_1_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_1_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_1_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_1_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_1_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x14C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x150++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_2_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_2_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_len_pru0,"
bitfld.long 0x8 24. "FT3_2_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_2_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_2_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_2_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_2_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_2_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_2_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x16C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x170++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_3_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_3_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_len_pru0,"
bitfld.long 0x8 24. "FT3_3_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_3_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_3_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_3_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_3_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_3_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_3_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x18C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x190++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_4_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_4_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_len_pru0,"
bitfld.long 0x8 24. "FT3_4_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_4_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_4_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_4_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_4_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_4_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_4_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1AC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x1B0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_5_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_5_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_len_pru0,"
bitfld.long 0x8 24. "FT3_5_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_5_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_5_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_5_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_5_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_5_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_5_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1CC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x1D0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_6_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_6_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_len_pru0,"
bitfld.long 0x8 24. "FT3_6_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_6_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_6_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_6_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_6_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_6_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_6_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1EC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x1F0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_7_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_7_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_len_pru0,"
bitfld.long 0x8 24. "FT3_7_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_7_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_7_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_7_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_7_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_7_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_7_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x20C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x210++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_8_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_8_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_len_pru0,"
bitfld.long 0x8 24. "FT3_8_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_8_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_8_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_8_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_8_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_8CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_8_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_8_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x22C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x230++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_9_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_9_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_len_pru0,"
bitfld.long 0x8 24. "FT3_9_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_9_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_9_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_9_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_9_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_9CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_9_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_9_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x24C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x250++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_10_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_10_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_len_pru0,"
bitfld.long 0x8 24. "FT3_10_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_10_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_10_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_10_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_10_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_10CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_10_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_10_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x26C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x270++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_11_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_11_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_len_pru0,"
bitfld.long 0x8 24. "FT3_11_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_11_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_11_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_11_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_11_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_11CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_11_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_11_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x28C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x290++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_12_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_12_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_len_pru0,"
bitfld.long 0x8 24. "FT3_12_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_12_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_12_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_12_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_12_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_12CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_12_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_12_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2AC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x2B0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_13_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_13_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_len_pru0,"
bitfld.long 0x8 24. "FT3_13_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_13_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_13_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_13_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_13_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_13CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_13_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_13_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2CC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x2D0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_14_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_14_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_len_pru0,"
bitfld.long 0x8 24. "FT3_14_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_14_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_14_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_14_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_14_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_14CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_14_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_14_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2EC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x2F0++0x3E7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_15_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_15_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_len_pru0,"
bitfld.long 0x8 24. "FT3_15_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_15_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_15_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_15_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_15_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_15CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_15_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_15_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p0_pru0,"
hexmask.long 0x18 0.--31. 1. "FT3_0_P0,Filter3 P4:P1"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p1_pru0,"
hexmask.long 0x1C 0.--31. 1. "FT3_0_P1,Filter3 P8:P5"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask0_pru0,"
hexmask.long 0x20 0.--31. 1. "FT3_0_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask1_pru0,"
hexmask.long 0x24 0.--31. 1. "FT3_0_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p0_pru0,"
hexmask.long 0x28 0.--31. 1. "FT3_1_P0,Filter3 P4:P1"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p1_pru0,"
hexmask.long 0x2C 0.--31. 1. "FT3_1_P1,Filter3 P8:P5"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask0_pru0,"
hexmask.long 0x30 0.--31. 1. "FT3_1_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask1_pru0,"
hexmask.long 0x34 0.--31. 1. "FT3_1_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p0_pru0,"
hexmask.long 0x38 0.--31. 1. "FT3_2_P0,Filter3 P4:P1"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p1_pru0,"
hexmask.long 0x3C 0.--31. 1. "FT3_2_P1,Filter3 P8:P5"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask0_pru0,"
hexmask.long 0x40 0.--31. 1. "FT3_2_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask1_pru0,"
hexmask.long 0x44 0.--31. 1. "FT3_2_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p0_pru0,"
hexmask.long 0x48 0.--31. 1. "FT3_3_P0,Filter3 P4:P1"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p1_pru0,"
hexmask.long 0x4C 0.--31. 1. "FT3_3_P1,Filter3 P8:P5"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask0_pru0,"
hexmask.long 0x50 0.--31. 1. "FT3_3_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask1_pru0,"
hexmask.long 0x54 0.--31. 1. "FT3_3_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p0_pru0,"
hexmask.long 0x58 0.--31. 1. "FT3_4_P0,Filter3 P4:P1"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p1_pru0,"
hexmask.long 0x5C 0.--31. 1. "FT3_4_P1,Filter3 P8:P5"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask0_pru0,"
hexmask.long 0x60 0.--31. 1. "FT3_4_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask1_pru0,"
hexmask.long 0x64 0.--31. 1. "FT3_4_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p0_pru0,"
hexmask.long 0x68 0.--31. 1. "FT3_5_P0,Filter3 P4:P1"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p1_pru0,"
hexmask.long 0x6C 0.--31. 1. "FT3_5_P1,Filter3 P8:P5"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask0_pru0,"
hexmask.long 0x70 0.--31. 1. "FT3_5_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask1_pru0,"
hexmask.long 0x74 0.--31. 1. "FT3_5_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p0_pru0,"
hexmask.long 0x78 0.--31. 1. "FT3_6_P0,Filter3 P4:P1"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p1_pru0,"
hexmask.long 0x7C 0.--31. 1. "FT3_6_P1,Filter3 P8:P5"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask0_pru0,"
hexmask.long 0x80 0.--31. 1. "FT3_6_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask1_pru0,"
hexmask.long 0x84 0.--31. 1. "FT3_6_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p0_pru0,"
hexmask.long 0x88 0.--31. 1. "FT3_7_P0,Filter3 P4:P1"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p1_pru0,"
hexmask.long 0x8C 0.--31. 1. "FT3_7_P1,Filter3 P8:P5"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask0_pru0,"
hexmask.long 0x90 0.--31. 1. "FT3_7_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask1_pru0,"
hexmask.long 0x94 0.--31. 1. "FT3_7_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p0_pru0,"
hexmask.long 0x98 0.--31. 1. "FT3_8_P0,Filter3 P4:P1"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p1_pru0,"
hexmask.long 0x9C 0.--31. 1. "FT3_8_P1,Filter3 P8:P5"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask0_pru0,"
hexmask.long 0xA0 0.--31. 1. "FT3_8_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask1_pru0,"
hexmask.long 0xA4 0.--31. 1. "FT3_8_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p0_pru0,"
hexmask.long 0xA8 0.--31. 1. "FT3_9_P0,Filter3 P4:P1"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p1_pru0,"
hexmask.long 0xAC 0.--31. 1. "FT3_9_P1,Filter3 P8:P5"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask0_pru0,"
hexmask.long 0xB0 0.--31. 1. "FT3_9_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask1_pru0,"
hexmask.long 0xB4 0.--31. 1. "FT3_9_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p0_pru0,"
hexmask.long 0xB8 0.--31. 1. "FT3_10_P0,Filter3 P4:P1"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p1_pru0,"
hexmask.long 0xBC 0.--31. 1. "FT3_10_P1,Filter3 P8:P5"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask0_pru0,"
hexmask.long 0xC0 0.--31. 1. "FT3_10_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask1_pru0,"
hexmask.long 0xC4 0.--31. 1. "FT3_10_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p0_pru0,"
hexmask.long 0xC8 0.--31. 1. "FT3_11_P0,Filter3 P4:P1"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p1_pru0,"
hexmask.long 0xCC 0.--31. 1. "FT3_11_P1,Filter3 P8:P5"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask0_pru0,"
hexmask.long 0xD0 0.--31. 1. "FT3_11_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask1_pru0,"
hexmask.long 0xD4 0.--31. 1. "FT3_11_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p0_pru0,"
hexmask.long 0xD8 0.--31. 1. "FT3_12_P0,Filter3 P4:P1"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p1_pru0,"
hexmask.long 0xDC 0.--31. 1. "FT3_12_P1,Filter3 P8:P5"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask0_pru0,"
hexmask.long 0xE0 0.--31. 1. "FT3_12_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask1_pru0,"
hexmask.long 0xE4 0.--31. 1. "FT3_12_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p0_pru0,"
hexmask.long 0xE8 0.--31. 1. "FT3_13_P0,Filter3 P4:P1"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p1_pru0,"
hexmask.long 0xEC 0.--31. 1. "FT3_13_P1,Filter3 P8:P5"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask0_pru0,"
hexmask.long 0xF0 0.--31. 1. "FT3_13_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask1_pru0,"
hexmask.long 0xF4 0.--31. 1. "FT3_13_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p0_pru0,"
hexmask.long 0xF8 0.--31. 1. "FT3_14_P0,Filter3 P4:P1"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p1_pru0,"
hexmask.long 0xFC 0.--31. 1. "FT3_14_P1,Filter3 P8:P5"
line.long 0x100 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask0_pru0,"
hexmask.long 0x100 0.--31. 1. "FT3_14_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x104 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask1_pru0,"
hexmask.long 0x104 0.--31. 1. "FT3_14_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x108 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p0_pru0,"
hexmask.long 0x108 0.--31. 1. "FT3_15_P0,Filter3 P4:P1"
line.long 0x10C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p1_pru0,"
hexmask.long 0x10C 0.--31. 1. "FT3_15_P1,Filter3 P8:P5"
line.long 0x110 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask0_pru0,"
hexmask.long 0x110 0.--31. 1. "FT3_15_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x114 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask1_pru0,"
hexmask.long 0x114 0.--31. 1. "FT3_15_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x118 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft_rx_ptr_pru0,"
hexmask.long 0x118 0.--31. 1. "FT_RX_PTR_PRU0,RX current filter Byte Count"
line.long 0x11C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_and_en_pru0,"
hexmask.long 0x11C 0.--31. 1. "RX_CLASS0_AND_EN,rx class and enabels"
line.long 0x120 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_or_en_pru0,"
hexmask.long 0x120 0.--31. 1. "RX_CLASS0_OR_EN,rx class or enabels"
line.long 0x124 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_and_en_pru0,"
hexmask.long 0x124 0.--31. 1. "RX_CLASS1_AND_EN,rx class and enabels"
line.long 0x128 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_or_en_pru0,"
hexmask.long 0x128 0.--31. 1. "RX_CLASS1_OR_EN,rx class or enabels"
line.long 0x12C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_and_en_pru0,"
hexmask.long 0x12C 0.--31. 1. "RX_CLASS2_AND_EN,rx class and enabels"
line.long 0x130 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_or_en_pru0,"
hexmask.long 0x130 0.--31. 1. "RX_CLASS2_OR_EN,rx class or enabels"
line.long 0x134 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_and_en_pru0,"
hexmask.long 0x134 0.--31. 1. "RX_CLASS3_AND_EN,rx class and enabels"
line.long 0x138 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_or_en_pru0,"
hexmask.long 0x138 0.--31. 1. "RX_CLASS3_OR_EN,rx class or enabels"
line.long 0x13C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_and_en_pru0,"
hexmask.long 0x13C 0.--31. 1. "RX_CLASS4_AND_EN,rx class and enabels"
line.long 0x140 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_or_en_pru0,"
hexmask.long 0x140 0.--31. 1. "RX_CLASS4_OR_EN,rx class or enabels"
line.long 0x144 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_and_en_pru0,"
hexmask.long 0x144 0.--31. 1. "RX_CLASS5_AND_EN,rx class and enabels"
line.long 0x148 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_or_en_pru0,"
hexmask.long 0x148 0.--31. 1. "RX_CLASS5_OR_EN,rx class or enabels"
line.long 0x14C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_and_en_pru0,"
hexmask.long 0x14C 0.--31. 1. "RX_CLASS6_AND_EN,rx class and enabels"
line.long 0x150 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_or_en_pru0,"
hexmask.long 0x150 0.--31. 1. "RX_CLASS6_OR_EN,rx class or enabels"
line.long 0x154 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_and_en_pru0,"
hexmask.long 0x154 0.--31. 1. "RX_CLASS7_AND_EN,rx class and enabels"
line.long 0x158 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_or_en_pru0,"
hexmask.long 0x158 0.--31. 1. "RX_CLASS7_OR_EN,rx class or enabels"
line.long 0x15C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_and_en_pru0,"
hexmask.long 0x15C 0.--31. 1. "RX_CLASS8_AND_EN,rx class and enabels"
line.long 0x160 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_or_en_pru0,"
hexmask.long 0x160 0.--31. 1. "RX_CLASS8_OR_EN,rx class or enabels"
line.long 0x164 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_and_en_pru0,"
hexmask.long 0x164 0.--31. 1. "RX_CLASS9_AND_EN,rx class and enabels"
line.long 0x168 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_or_en_pru0,"
hexmask.long 0x168 0.--31. 1. "RX_CLASS9_OR_EN,rx class or enabels"
line.long 0x16C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_and_en_pru0,"
hexmask.long 0x16C 0.--31. 1. "RX_CLASS10_AND_EN,rx class and enabels"
line.long 0x170 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_or_en_pru0,"
hexmask.long 0x170 0.--31. 1. "RX_CLASS10_OR_EN,rx class or enabels"
line.long 0x174 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_and_en_pru0,"
hexmask.long 0x174 0.--31. 1. "RX_CLASS11_AND_EN,rx class and enabels"
line.long 0x178 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_or_en_pru0,"
hexmask.long 0x178 0.--31. 1. "RX_CLASS11_OR_EN,rx class or enabels"
line.long 0x17C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_and_en_pru0,"
hexmask.long 0x17C 0.--31. 1. "RX_CLASS12_AND_EN,rx class and enabels"
line.long 0x180 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_or_en_pru0,"
hexmask.long 0x180 0.--31. 1. "RX_CLASS12_OR_EN,rx class or enabels"
line.long 0x184 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_and_en_pru0,"
hexmask.long 0x184 0.--31. 1. "RX_CLASS13_AND_EN,rx class and enabels"
line.long 0x188 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_or_en_pru0,"
hexmask.long 0x188 0.--31. 1. "RX_CLASS13_OR_EN,rx class or enabels"
line.long 0x18C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_and_en_pru0,"
hexmask.long 0x18C 0.--31. 1. "RX_CLASS14_AND_EN,rx class and enabels"
line.long 0x190 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_or_en_pru0,"
hexmask.long 0x190 0.--31. 1. "RX_CLASS14_OR_EN,rx class or enabels"
line.long 0x194 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_and_en_pru0,"
hexmask.long 0x194 0.--31. 1. "RX_CLASS15_AND_EN,rx class and enabels"
line.long 0x198 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_or_en_pru0,"
hexmask.long 0x198 0.--31. 1. "RX_CLASS15_OR_EN,rx class or enabels"
line.long 0x19C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg1_pru0,"
bitfld.long 0x19C 30.--31. "RX_CLASS15_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 28.--29. "RX_CLASS14_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
newline
bitfld.long 0x19C 26.--27. "RX_CLASS13_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 24.--25. "RX_CLASS12_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
newline
bitfld.long 0x19C 22.--23. "RX_CLASS11_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 20.--21. "RX_CLASS10_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
newline
bitfld.long 0x19C 18.--19. "RX_CLASS9_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 16.--17. "RX_CLASS8_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
newline
bitfld.long 0x19C 14.--15. "RX_CLASS7_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 12.--13. "RX_CLASS6_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 10.--11. "RX_CLASS5_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 8.--9. "RX_CLASS4_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 6.--7. "RX_CLASS3_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 4.--5. "RX_CLASS2_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
newline
bitfld.long 0x19C 2.--3. "RX_CLASS1_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 0.--1. "RX_CLASS0_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
line.long 0x1A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg2_pru0,"
hexmask.long.word 0x1A0 16.--31. 1. "RX_CLASS_OR_NV,rx class or nv enable"
hexmask.long.word 0x1A0 0.--15. 1. "RX_CLASS_AND_NV,rx class and nv enable"
line.long 0x1A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates0_pru0,"
bitfld.long 0x1A4 8. "RX_RED_PHASE_EN0,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A4 6. "RX_ALLOW_MASK0,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1A4 5. "RX_CLASS_RAW_MASK0,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A4 4. "RX_PHASE_MASK0,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1A4 0.--2. "RX_RATE_GATE_SEL0,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates1_pru0,"
bitfld.long 0x1A8 8. "RX_RED_PHASE_EN1,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A8 6. "RX_ALLOW_MASK1,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1A8 5. "RX_CLASS_RAW_MASK1,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A8 4. "RX_PHASE_MASK1,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1A8 0.--2. "RX_RATE_GATE_SEL1,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates2_pru0,"
bitfld.long 0x1AC 8. "RX_RED_PHASE_EN2,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1AC 6. "RX_ALLOW_MASK2,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1AC 5. "RX_CLASS_RAW_MASK2,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1AC 4. "RX_PHASE_MASK2,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1AC 0.--2. "RX_RATE_GATE_SEL2,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates3_pru0,"
bitfld.long 0x1B0 8. "RX_RED_PHASE_EN3,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B0 6. "RX_ALLOW_MASK3,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1B0 5. "RX_CLASS_RAW_MASK3,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B0 4. "RX_PHASE_MASK3,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1B0 0.--2. "RX_RATE_GATE_SEL3,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates4_pru0,"
bitfld.long 0x1B4 8. "RX_RED_PHASE_EN4,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B4 6. "RX_ALLOW_MASK4,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1B4 5. "RX_CLASS_RAW_MASK4,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B4 4. "RX_PHASE_MASK4,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1B4 0.--2. "RX_RATE_GATE_SEL4,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates5_pru0,"
bitfld.long 0x1B8 8. "RX_RED_PHASE_EN5,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B8 6. "RX_ALLOW_MASK5,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1B8 5. "RX_CLASS_RAW_MASK5,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B8 4. "RX_PHASE_MASK5,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1B8 0.--2. "RX_RATE_GATE_SEL5,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates6_pru0,"
bitfld.long 0x1BC 8. "RX_RED_PHASE_EN6,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1BC 6. "RX_ALLOW_MASK6,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1BC 5. "RX_CLASS_RAW_MASK6,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1BC 4. "RX_PHASE_MASK6,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1BC 0.--2. "RX_RATE_GATE_SEL6,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates7_pru0,"
bitfld.long 0x1C0 8. "RX_RED_PHASE_EN7,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C0 6. "RX_ALLOW_MASK7,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C0 5. "RX_CLASS_RAW_MASK7,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C0 4. "RX_PHASE_MASK7,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C0 0.--2. "RX_RATE_GATE_SEL7,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates8_pru0,"
bitfld.long 0x1C4 8. "RX_RED_PHASE_EN8,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C4 6. "RX_ALLOW_MASK8,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C4 5. "RX_CLASS_RAW_MASK8,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C4 4. "RX_PHASE_MASK8,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C4 0.--2. "RX_RATE_GATE_SEL8,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates9_pru0,"
bitfld.long 0x1C8 8. "RX_RED_PHASE_EN9,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C8 6. "RX_ALLOW_MASK9,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C8 5. "RX_CLASS_RAW_MASK9,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C8 4. "RX_PHASE_MASK9,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C8 0.--2. "RX_RATE_GATE_SEL9,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates10_pru0,"
bitfld.long 0x1CC 8. "RX_RED_PHASE_EN10,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1CC 6. "RX_ALLOW_MASK10,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1CC 5. "RX_CLASS_RAW_MASK10,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1CC 4. "RX_PHASE_MASK10,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1CC 0.--2. "RX_RATE_GATE_SEL10,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates11_pru0,"
bitfld.long 0x1D0 8. "RX_RED_PHASE_EN11,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D0 6. "RX_ALLOW_MASK11,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 5. "RX_CLASS_RAW_MASK11,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D0 4. "RX_PHASE_MASK11,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 0.--2. "RX_RATE_GATE_SEL11,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates12_pru0,"
bitfld.long 0x1D4 8. "RX_RED_PHASE_EN12,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D4 6. "RX_ALLOW_MASK12,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D4 5. "RX_CLASS_RAW_MASK12,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D4 4. "RX_PHASE_MASK12,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D4 0.--2. "RX_RATE_GATE_SEL12,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates13_pru0,"
bitfld.long 0x1D8 8. "RX_RED_PHASE_EN13,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D8 6. "RX_ALLOW_MASK13,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D8 5. "RX_CLASS_RAW_MASK13,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D8 4. "RX_PHASE_MASK13,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D8 0.--2. "RX_RATE_GATE_SEL13,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates14_pru0,"
bitfld.long 0x1DC 8. "RX_RED_PHASE_EN14,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1DC 6. "RX_ALLOW_MASK14,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1DC 5. "RX_CLASS_RAW_MASK14,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1DC 4. "RX_PHASE_MASK14,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1DC 0.--2. "RX_RATE_GATE_SEL14,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates15_pru0,"
bitfld.long 0x1E0 8. "RX_RED_PHASE_EN15,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1E0 6. "RX_ALLOW_MASK15,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 5. "RX_CLASS_RAW_MASK15,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1E0 4. "RX_PHASE_MASK15,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 0.--2. "RX_RATE_GATE_SEL15,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_green_pru0,"
rbitfld.long 0x1E4 4. "RX_GREEN_VAL,0 RED 1 GREEN status" "0,1"
hexmask.long.byte 0x1E4 0.--3. 1. "RX_GREEN_CMP_SEL,define which IEP CMP start green"
line.long 0x1E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_sa_hash_pru0,"
hexmask.long.word 0x1E8 0.--9. 1. "SA_HASH_SEED,SA Hash Seed"
line.long 0x1EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_pru0,"
hexmask.long.word 0x1EC 0.--9. 1. "CONN_HASH_SEED,Connection Hash Seed"
line.long 0x1F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_start_pru0,"
hexmask.long.word 0x1F0 0.--14. 1. "CONN_HASH_START,Connection Hash Start which 4 Bytes to hash"
line.long 0x1F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg0_pru0,"
hexmask.long 0x1F4 0.--31. 1. "RX_RATE_CIR_IDLE0,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg1_pru0,"
hexmask.long 0x1F8 0.--31. 1. "RX_RATE_CIR_IDLE1,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg2_pru0,"
hexmask.long 0x1FC 0.--31. 1. "RX_RATE_CIR_IDLE2,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x200 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg3_pru0,"
hexmask.long 0x200 0.--31. 1. "RX_RATE_CIR_IDLE3,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x204 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg4_pru0,"
hexmask.long 0x204 0.--31. 1. "RX_RATE_CIR_IDLE4,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x208 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg5_pru0,"
hexmask.long 0x208 0.--31. 1. "RX_RATE_CIR_IDLE5,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x20C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg6_pru0,"
hexmask.long 0x20C 0.--31. 1. "RX_RATE_CIR_IDLE6,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x210 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg7_pru0,"
hexmask.long 0x210 0.--31. 1. "RX_RATE_CIR_IDLE7,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x214 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel0_pru0,"
hexmask.long.byte 0x214 24.--29. 1. "RX_RATE_SRC_SEL3,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 16.--21. 1. "RX_RATE_SRC_SEL2,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x214 8.--13. 1. "RX_RATE_SRC_SEL1,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 0.--5. 1. "RX_RATE_SRC_SEL0,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x218 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel1_pru0,"
hexmask.long.byte 0x218 24.--29. 1. "RX_RATE_SRC_SEL7,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 16.--21. 1. "RX_RATE_SRC_SEL6,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x218 8.--13. 1. "RX_RATE_SRC_SEL5,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 0.--5. 1. "RX_RATE_SRC_SEL4,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x21C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_0_pru0,"
hexmask.long 0x21C 0.--31. 1. "TX_RATE_CIR_IDLE0,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x220 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_0_pru0,"
rbitfld.long 0x220 17. "TX_RATE_ALLOW0,TX Rate Pkt Enable" "0,1"
bitfld.long 0x220 16. "TX_RATE_EN0,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x220 0.--15. 1. "TX_RATE_LEN0,TX Rate Pkt Length"
line.long 0x224 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_1_pru0,"
hexmask.long 0x224 0.--31. 1. "TX_RATE_CIR_IDLE1,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x228 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_1_pru0,"
rbitfld.long 0x228 17. "TX_RATE_ALLOW1,TX Rate Pkt Enable" "0,1"
bitfld.long 0x228 16. "TX_RATE_EN1,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x228 0.--15. 1. "TX_RATE_LEN1,TX Rate Pkt Length"
line.long 0x22C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_2_pru0,"
hexmask.long 0x22C 0.--31. 1. "TX_RATE_CIR_IDLE2,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x230 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_2_pru0,"
rbitfld.long 0x230 17. "TX_RATE_ALLOW2,TX Rate Pkt Enable" "0,1"
bitfld.long 0x230 16. "TX_RATE_EN2,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x230 0.--15. 1. "TX_RATE_LEN2,TX Rate Pkt Length"
line.long 0x234 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_3_pru0,"
hexmask.long 0x234 0.--31. 1. "TX_RATE_CIR_IDLE3,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x238 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_3_pru0,"
rbitfld.long 0x238 17. "TX_RATE_ALLOW3,TX Rate Pkt Enable" "0,1"
bitfld.long 0x238 16. "TX_RATE_EN3,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x238 0.--15. 1. "TX_RATE_LEN3,TX Rate Pkt Length"
line.long 0x23C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_4_pru0,"
hexmask.long 0x23C 0.--31. 1. "TX_RATE_CIR_IDLE4,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x240 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_4_pru0,"
rbitfld.long 0x240 17. "TX_RATE_ALLOW4,TX Rate Pkt Enable" "0,1"
bitfld.long 0x240 16. "TX_RATE_EN4,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x240 0.--15. 1. "TX_RATE_LEN4,TX Rate Pkt Length"
line.long 0x244 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_5_pru0,"
hexmask.long 0x244 0.--31. 1. "TX_RATE_CIR_IDLE5,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x248 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_5_pru0,"
rbitfld.long 0x248 17. "TX_RATE_ALLOW5,TX Rate Pkt Enable" "0,1"
bitfld.long 0x248 16. "TX_RATE_EN5,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x248 0.--15. 1. "TX_RATE_LEN5,TX Rate Pkt Length"
line.long 0x24C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_6_pru0,"
hexmask.long 0x24C 0.--31. 1. "TX_RATE_CIR_IDLE6,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x250 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_6_pru0,"
rbitfld.long 0x250 17. "TX_RATE_ALLOW6,TX Rate Pkt Enable" "0,1"
bitfld.long 0x250 16. "TX_RATE_EN6,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x250 0.--15. 1. "TX_RATE_LEN6,TX Rate Pkt Length"
line.long 0x254 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_7_pru0,"
hexmask.long 0x254 0.--31. 1. "TX_RATE_CIR_IDLE7,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x258 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_7_pru0,"
rbitfld.long 0x258 17. "TX_RATE_ALLOW7,TX Rate Pkt Enable" "0,1"
bitfld.long 0x258 16. "TX_RATE_EN7,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x258 0.--15. 1. "TX_RATE_LEN7,TX Rate Pkt Length"
line.long 0x25C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_good_pru0,"
hexmask.long 0x25C 0.--31. 1. "RX_GOOD_FRM_CNT,RX Good Frame Count Inc on none min err max err crc err odd err  Wrt subtracts"
line.long 0x260 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bc_pru0,"
hexmask.long.word 0x260 0.--15. 1. "RX_BC_FRM_CNT,RX BC Frame Count Inc on BC type  Wrt subtracts"
line.long 0x264 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mc_pru0,"
hexmask.long.word 0x264 0.--15. 1. "RX_MC_FRM_CNT,RX MC Frame Count Inc on MC type  Wrt subtracts"
line.long 0x268 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_crc_err_pru0,"
hexmask.long.word 0x268 0.--15. 1. "RX_CRC_ERR_FRM_CNT,RX CRC Err Frame Count Inc on crc err  Wrt subtracts"
line.long 0x26C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mii_err_pru0,"
hexmask.long.word 0x26C 0.--15. 1. "RX_MII_ERR_FRM_CNT,RX MII Err Frame Count Inc on mii sgmii rgmii err  Wrt subtracts"
line.long 0x270 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_odd_err_pru0,"
hexmask.long.word 0x270 0.--15. 1. "RX_ODD_ERR_FRM_CNT,RX Odd Nibble Frame Count Inc on odd nibble mii  Wrt subtracts"
line.long 0x274 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_size_pru0,"
hexmask.long.word 0x274 0.--15. 1. "RX_MAX_SIZE_FRM,RX MAX Size Frame Count Limit"
line.long 0x278 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_err_pru0,"
hexmask.long.word 0x278 0.--15. 1. "RX_MAX_ERR_FRM_CNT,RX MAX Size Err Frame Count Inc if > than Limit  Wrt subtracts"
line.long 0x27C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_size_pru0,"
hexmask.long.word 0x27C 0.--15. 1. "RX_MIN_SIZE_FRM,RX MIN Size Frame Limit"
line.long 0x280 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_err_pru0,"
hexmask.long.word 0x280 0.--15. 1. "RX_MIN_ERR_FRM_CNT,RX MIN Size Frame Count Inc if < than limit  Wrt subtracts"
line.long 0x284 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_overrun_err_pru0,"
hexmask.long.word 0x284 0.--15. 1. "RX_OVERRUN_ERR_FRM_CNT,RX L1 FIFO overflow Frame Count Inc on overflow event  Wrt subtracts"
line.long 0x288 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class0_hit_pru0,"
hexmask.long 0x288 0.--31. 1. "RX_STAT_CLASS0_PRU0,RX Class0 Hit Count  Wrt subtracts"
line.long 0x28C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class1_hit_pru0,"
hexmask.long 0x28C 0.--31. 1. "RX_STAT_CLASS1_PRU0,RX Class1 Hit Count  Wrt subtracts"
line.long 0x290 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class2_hit_pru0,"
hexmask.long 0x290 0.--31. 1. "RX_STAT_CLASS2_PRU0,RX Class2 Hit Count  Wrt subtracts"
line.long 0x294 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class3_hit_pru0,"
hexmask.long 0x294 0.--31. 1. "RX_STAT_CLASS3_PRU0,RX Class3 Hit Count  Wrt subtracts"
line.long 0x298 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class4_hit_pru0,"
hexmask.long 0x298 0.--31. 1. "RX_STAT_CLASS4_PRU0,RX Class4 Hit Count  Wrt subtracts"
line.long 0x29C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class5_hit_pru0,"
hexmask.long 0x29C 0.--31. 1. "RX_STAT_CLASS5_PRU0,RX Class5 Hit Count  Wrt subtracts"
line.long 0x2A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class6_hit_pru0,"
hexmask.long 0x2A0 0.--31. 1. "RX_STAT_CLASS6_PRU0,RX Class6 Hit Count  Wrt subtracts"
line.long 0x2A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class7_hit_pru0,"
hexmask.long 0x2A4 0.--31. 1. "RX_STAT_CLASS7_PRU0,RX Class7 Hit Count  Wrt subtracts"
line.long 0x2A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class8_hit_pru0,"
hexmask.long 0x2A8 0.--31. 1. "RX_STAT_CLASS8_PRU0,RX Class8 Hit Count  Wrt subtracts"
line.long 0x2AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class9_hit_pru0,"
hexmask.long 0x2AC 0.--31. 1. "RX_STAT_CLASS9_PRU0,RX Class9 Hit Count  Wrt subtracts"
line.long 0x2B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class10_hit_pru0,"
hexmask.long 0x2B0 0.--31. 1. "RX_STAT_CLASS10_PRU0,RX Class10 Hit Count  Wrt subtracts"
line.long 0x2B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class11_hit_pru0,"
hexmask.long 0x2B4 0.--31. 1. "RX_STAT_CLASS11_PRU0,RX Class11 Hit Count  Wrt subtracts"
line.long 0x2B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class12_hit_pru0,"
hexmask.long 0x2B8 0.--31. 1. "RX_STAT_CLASS12_PRU0,RX Class12 Hit Count  Wrt subtracts"
line.long 0x2BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class13_hit_pru0,"
hexmask.long 0x2BC 0.--31. 1. "RX_STAT_CLASS13_PRU0,RX Class13 Hit Count  Wrt subtracts"
line.long 0x2C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class14_hit_pru0,"
hexmask.long 0x2C0 0.--31. 1. "RX_STAT_CLASS14_PRU0,RX Class14 Hit Count  Wrt subtracts"
line.long 0x2C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class15_hit_pru0,"
hexmask.long 0x2C4 0.--31. 1. "RX_STAT_CLASS15_PRU0,RX Class15 Hit Count  Wrt subtracts"
line.long 0x2C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_smd_frag_err_pru0,"
hexmask.long.byte 0x2C8 24.--31. 1. "RX_STAT_SMD_ERR_PRU0,RX SMDS Error Count  Inc when first none 0x55 does not match any valid SMD  Wrt subtracts"
hexmask.long.byte 0x2C8 16.--23. 1. "RX_STAT_FRAG_ERR_PRU0,RX Frag_Cnt Seq Error Count  Wrt subtracts"
newline
hexmask.long.byte 0x2C8 8.--15. 1. "RX_STAT_SMDC_ERR_PRU0,RX SMDCx Seq Error Count  Wrt subtracts"
hexmask.long.byte 0x2C8 0.--7. 1. "RX_STAT_SMDS_ERR_PRU0,RX SMDSx Seq Error Count  Wrt subtracts"
line.long 0x2CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_size_pru0,"
hexmask.long.word 0x2CC 0.--13. 1. "RX_STAT_BKT1_SIZE,RX Bucket1 Byte Size"
line.long 0x2D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_size_pru0,"
hexmask.long.word 0x2D0 0.--13. 1. "RX_STAT_BKT2_SIZE,RX Bucket2 Byte Size"
line.long 0x2D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_size_pru0,"
hexmask.long.word 0x2D4 0.--13. 1. "RX_STAT_BKT3_SIZE,RX Bucket3 Byte Size"
line.long 0x2D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_size_pru0,"
hexmask.long.word 0x2D8 0.--13. 1. "RX_STAT_BKT4_SIZE,RX Bucket4 Byte Size"
line.long 0x2DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_64_pru0,"
hexmask.long.word 0x2DC 0.--15. 1. "RX_64_FRM_CNT,RX 64Byte Frame Count Inc if 64B size"
line.long 0x2E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_pru0,"
hexmask.long.word 0x2E0 0.--15. 1. "RX_STAT_BKT1,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
line.long 0x2E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_pru0,"
hexmask.long.word 0x2E4 0.--15. 1. "RX_STAT_BKT2,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x2E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_pru0,"
hexmask.long.word 0x2E8 0.--15. 1. "RX_STAT_BKT3,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x2EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_pru0,"
hexmask.long.word 0x2EC 0.--15. 1. "RX_STAT_BKT4,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x2F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt5_pru0,"
hexmask.long.word 0x2F0 0.--15. 1. "RX_STAT_BKT5,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
line.long 0x2F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_total_bytes_pru0,"
hexmask.long 0x2F4 0.--31. 1. "RX_STAT_TOTAL_BYTES_PRU,RX Total Byte Count"
line.long 0x2F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rxtx_stat_total_bytes_pru0,"
hexmask.long 0x2F8 0.--31. 1. "RXTX_STAT_TOTAL_BYTES_PRU,RX and TX Total Byte Count"
line.long 0x2FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_good_port0,"
hexmask.long 0x2FC 0.--31. 1. "TX_GOOD_FRM_CNT,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
line.long 0x300 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bc_port0,"
hexmask.long.word 0x300 0.--15. 1. "TX_BC_FRM_CNT,TX BC Frame Count Inc if BC"
line.long 0x304 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_mc_port0,"
hexmask.long.word 0x304 0.--15. 1. "TX_MC_FRM_CNT,TX MC Frame Count Inc if MC"
line.long 0x308 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_odd_err_port0,"
hexmask.long.word 0x308 0.--15. 1. "TX_ODD_ERR_FRM_CNT,TX Odd Nibble Frame Count Inc if mii odd nibble"
line.long 0x30C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_underflow_err_port0,"
hexmask.long.word 0x30C 0.--15. 1. "TX_UNDERFLOW_CNT,TX MAX Underflow Error Cnt"
line.long 0x310 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_size_port0,"
hexmask.long.word 0x310 0.--15. 1. "TX_MAX_SIZE_FRM,TX MAX Size Frame Count Limit"
line.long 0x314 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_err_port0,"
hexmask.long.word 0x314 0.--15. 1. "TX_MAX_ERR_FRM_CNT,TX MAX Size Err Frame Count Inc if > max Limit"
line.long 0x318 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_size_port0,"
hexmask.long.word 0x318 0.--15. 1. "TX_MIN_SIZE_FRM,TX MIN Size Frame Count Limit"
line.long 0x31C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_err_port0,"
hexmask.long.word 0x31C 0.--15. 1. "TX_MIN_ERR_FRM_CNT,TX MIN Size Err Frame Count Inc if < min Limit"
line.long 0x320 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_size_port0,"
hexmask.long.word 0x320 0.--13. 1. "TX_STAT_BKT1_SIZE,TX Bucket1 Byte Size"
line.long 0x324 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_size_port0,"
hexmask.long.word 0x324 0.--13. 1. "TX_STAT_BKT2_SIZE,TX Bucket2 Byte Size"
line.long 0x328 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_size_port0,"
hexmask.long.word 0x328 0.--13. 1. "TX_STAT_BKT3_SIZE,TX Bucket3 Byte Size"
line.long 0x32C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_size_port0,"
hexmask.long.word 0x32C 0.--13. 1. "TX_STAT_BKT4_SIZE,TX Bucket4 Byte Size"
line.long 0x330 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_64_port0,"
hexmask.long.word 0x330 0.--15. 1. "TX_64_FRM_CNT,TX 64Byte Frame Count Inc if 64B"
line.long 0x334 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_port0,"
hexmask.long.word 0x334 0.--15. 1. "TX_STAT_BKT1,TX Bucket1 Inc if <= than Bucket1"
line.long 0x338 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_port0,"
hexmask.long.word 0x338 0.--15. 1. "TX_STAT_BKT2,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x33C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_port0,"
hexmask.long.word 0x33C 0.--15. 1. "TX_STAT_BKT3,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x340 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_port0,"
hexmask.long.word 0x340 0.--15. 1. "TX_STAT_BKT4,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x344 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt5_port0,"
hexmask.long.word 0x344 0.--15. 1. "TX_STAT_BKT5,TX Bucket5 Inc if > than Bucket4 Byte Size"
line.long 0x348 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_total_bytes_port0,"
hexmask.long 0x348 0.--31. 1. "TX_TOTAL_STAT_BYTES_PORT,TX Total Byte Count of all Frames"
line.long 0x34C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_tag_port0,"
hexmask.long 0x34C 0.--31. 1. "TX_HSR_TAG,HSR TAG"
line.long 0x350 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_seq_port0,"
hexmask.long.word 0x350 0.--15. 1. "TX_HSR_SEQ,HSR Seq count. It will incr for every HSR type"
line.long 0x354 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_type_tag_port0,"
hexmask.long.word 0x354 0.--15. 1. "TX_VLAN_TYPE_TAG,TX VLAN Type Tag  match to enable VLAN removal"
line.long 0x358 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_ins_tag_port0,"
hexmask.long 0x358 0.--31. 1. "TX_VLAN_INS_TAG,TX VLAN Insertion"
line.long 0x35C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_start_len_pru1,"
hexmask.long.byte 0x35C 16.--19. 1. "FT1_LEN,Defines the total number of Bytes Filter1 will check before Valid bit is set"
hexmask.long.word 0x35C 0.--14. 1. "FT1_START,Byte count start for Filter1. Any wrt will clear all Filter1 Status Bits"
line.long 0x360 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_cfg_pru1,"
bitfld.long 0x360 14.--15. "FT1_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 12.--13. "FT1_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x360 10.--11. "FT1_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 8.--9. "FT1_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x360 6.--7. "FT1_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 4.--5. "FT1_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x360 2.--3. "FT1_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 0.--1. "FT1_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x364 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da0_pru1,"
hexmask.long 0x364 0.--31. 1. "FT1_0_DA0,Filter1 DA4:DA1"
line.long 0x368 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da1_pru1,"
hexmask.long.word 0x368 0.--15. 1. "FT1_0_DA1,Filter1 DA6:DA5"
line.long 0x36C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask0_pru1,"
hexmask.long 0x36C 0.--31. 1. "FT1_0_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x370 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask1_pru1,"
hexmask.long.word 0x370 0.--15. 1. "FT1_0_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x374 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da0_pru1,"
hexmask.long 0x374 0.--31. 1. "FT1_1_DA0,Filter1 DA4:DA1"
line.long 0x378 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da1_pru1,"
hexmask.long.word 0x378 0.--15. 1. "FT1_1_DA1,Filter1 DA6:DA5"
line.long 0x37C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask0_pru1,"
hexmask.long 0x37C 0.--31. 1. "FT1_1_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x380 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask1_pru1,"
hexmask.long.word 0x380 0.--15. 1. "FT1_1_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x384 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da0_pru1,"
hexmask.long 0x384 0.--31. 1. "FT1_2_DA0,Filter1 DA4:DA1"
line.long 0x388 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da1_pru1,"
hexmask.long.word 0x388 0.--15. 1. "FT1_2_DA1,Filter1 DA6:DA5"
line.long 0x38C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask0_pru1,"
hexmask.long 0x38C 0.--31. 1. "FT1_2_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x390 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask1_pru1,"
hexmask.long.word 0x390 0.--15. 1. "FT1_2_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x394 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da0_pru1,"
hexmask.long 0x394 0.--31. 1. "FT1_3_DA0,Filter1 DA4:DA1"
line.long 0x398 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da1_pru1,"
hexmask.long.word 0x398 0.--15. 1. "FT1_3_DA1,Filter1 DA6:DA5"
line.long 0x39C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask0_pru1,"
hexmask.long 0x39C 0.--31. 1. "FT1_3_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask1_pru1,"
hexmask.long.word 0x3A0 0.--15. 1. "FT1_3_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da0_pru1,"
hexmask.long 0x3A4 0.--31. 1. "FT1_4_DA0,Filter1 DA4:DA1"
line.long 0x3A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da1_pru1,"
hexmask.long.word 0x3A8 0.--15. 1. "FT1_4_DA1,Filter1 DA6:DA5"
line.long 0x3AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask0_pru1,"
hexmask.long 0x3AC 0.--31. 1. "FT1_4_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask1_pru1,"
hexmask.long.word 0x3B0 0.--15. 1. "FT1_4_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da0_pru1,"
hexmask.long 0x3B4 0.--31. 1. "FT1_5_DA0,Filter1 DA4:DA1"
line.long 0x3B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da1_pru1,"
hexmask.long.word 0x3B8 0.--15. 1. "FT1_5_DA1,Filter1 DA6:DA5"
line.long 0x3BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask0_pru1,"
hexmask.long 0x3BC 0.--31. 1. "FT1_5_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask1_pru1,"
hexmask.long.word 0x3C0 0.--15. 1. "FT1_5_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da0_pru1,"
hexmask.long 0x3C4 0.--31. 1. "FT1_6_DA0,Filter1 DA4:DA1"
line.long 0x3C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da1_pru1,"
hexmask.long.word 0x3C8 0.--15. 1. "FT1_6_DA1,Filter1 DA6:DA5"
line.long 0x3CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask0_pru1,"
hexmask.long 0x3CC 0.--31. 1. "FT1_6_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask1_pru1,"
hexmask.long.word 0x3D0 0.--15. 1. "FT1_6_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da0_pru1,"
hexmask.long 0x3D4 0.--31. 1. "FT1_7_DA0,Filter1 DA4:DA1"
line.long 0x3D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da1_pru1,"
hexmask.long.word 0x3D8 0.--15. 1. "FT1_7_DA1,Filter1 DA6:DA5"
line.long 0x3DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask0_pru1,"
hexmask.long 0x3DC 0.--31. 1. "FT1_7_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask1_pru1,"
hexmask.long.word 0x3E0 0.--15. 1. "FT1_7_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_pru1,"
hexmask.long.word 0x3E4 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6D8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x6DC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_0_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_0_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_len_pru1,"
bitfld.long 0x8 24. "FT3_0_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_0_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_0_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_0_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_0_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_0_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_0_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6F8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x6FC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_1_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_1_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_len_pru1,"
bitfld.long 0x8 24. "FT3_1_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_1_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_1_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_1_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_1_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_1_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_1_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x718++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x71C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_2_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_2_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_len_pru1,"
bitfld.long 0x8 24. "FT3_2_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_2_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_2_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_2_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_2_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_2_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_2_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x738++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x73C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_3_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_3_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_len_pru1,"
bitfld.long 0x8 24. "FT3_3_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_3_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_3_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_3_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_3_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_3_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_3_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x758++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x75C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_4_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_4_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_len_pru1,"
bitfld.long 0x8 24. "FT3_4_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_4_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_4_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_4_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_4_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_4_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_4_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x778++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x77C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_5_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_5_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_len_pru1,"
bitfld.long 0x8 24. "FT3_5_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_5_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_5_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_5_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_5_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_5_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_5_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x798++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x79C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_6_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_6_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_len_pru1,"
bitfld.long 0x8 24. "FT3_6_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_6_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_6_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_6_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_6_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_6_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_6_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7B8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x7BC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_7_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_7_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_len_pru1,"
bitfld.long 0x8 24. "FT3_7_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_7_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_7_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_7_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_7_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_7_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_7_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7D8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x7DC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_8_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_8_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_len_pru1,"
bitfld.long 0x8 24. "FT3_8_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_8_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_8_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_8_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_8_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_8CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_8_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_8_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7F8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x7FC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_9_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_9_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_len_pru1,"
bitfld.long 0x8 24. "FT3_9_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_9_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_9_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_9_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_9_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_9CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_9_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_9_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x818++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x81C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_10_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_10_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_len_pru1,"
bitfld.long 0x8 24. "FT3_10_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_10_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_10_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_10_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_10_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_10CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_10_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_10_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x838++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x83C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_11_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_11_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_len_pru1,"
bitfld.long 0x8 24. "FT3_11_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_11_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_11_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_11_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_11_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_11CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_11_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_11_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x858++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x85C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_12_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_12_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_len_pru1,"
bitfld.long 0x8 24. "FT3_12_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_12_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_12_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_12_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_12_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_12CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_12_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_12_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x878++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x87C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_13_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_13_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_len_pru1,"
bitfld.long 0x8 24. "FT3_13_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_13_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_13_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_13_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_13_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_13CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_13_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_13_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x898++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x89C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_14_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_14_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_len_pru1,"
bitfld.long 0x8 24. "FT3_14_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_14_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_14_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_14_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_14_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_14CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_14_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_14_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x8B8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x8BC++0x35B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_15_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_15_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_len_pru1,"
bitfld.long 0x8 24. "FT3_15_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_15_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_15_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_15_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_15_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_15CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_15_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_15_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p0_pru1,"
hexmask.long 0x18 0.--31. 1. "FT3_0_P0,Filter3 P4:P1"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p1_pru1,"
hexmask.long 0x1C 0.--31. 1. "FT3_0_P1,Filter3 P8:P5"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask0_pru1,"
hexmask.long 0x20 0.--31. 1. "FT3_0_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask1_pru1,"
hexmask.long 0x24 0.--31. 1. "FT3_0_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p0_pru1,"
hexmask.long 0x28 0.--31. 1. "FT3_1_P0,Filter3 P4:P1"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p1_pru1,"
hexmask.long 0x2C 0.--31. 1. "FT3_1_P1,Filter3 P8:P5"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask0_pru1,"
hexmask.long 0x30 0.--31. 1. "FT3_1_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask1_pru1,"
hexmask.long 0x34 0.--31. 1. "FT3_1_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p0_pru1,"
hexmask.long 0x38 0.--31. 1. "FT3_2_P0,Filter3 P4:P1"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p1_pru1,"
hexmask.long 0x3C 0.--31. 1. "FT3_2_P1,Filter3 P8:P5"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask0_pru1,"
hexmask.long 0x40 0.--31. 1. "FT3_2_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask1_pru1,"
hexmask.long 0x44 0.--31. 1. "FT3_2_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p0_pru1,"
hexmask.long 0x48 0.--31. 1. "FT3_3_P0,Filter3 P4:P1"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p1_pru1,"
hexmask.long 0x4C 0.--31. 1. "FT3_3_P1,Filter3 P8:P5"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask0_pru1,"
hexmask.long 0x50 0.--31. 1. "FT3_3_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask1_pru1,"
hexmask.long 0x54 0.--31. 1. "FT3_3_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p0_pru1,"
hexmask.long 0x58 0.--31. 1. "FT3_4_P0,Filter3 P4:P1"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p1_pru1,"
hexmask.long 0x5C 0.--31. 1. "FT3_4_P1,Filter3 P8:P5"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask0_pru1,"
hexmask.long 0x60 0.--31. 1. "FT3_4_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask1_pru1,"
hexmask.long 0x64 0.--31. 1. "FT3_4_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p0_pru1,"
hexmask.long 0x68 0.--31. 1. "FT3_5_P0,Filter3 P4:P1"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p1_pru1,"
hexmask.long 0x6C 0.--31. 1. "FT3_5_P1,Filter3 P8:P5"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask0_pru1,"
hexmask.long 0x70 0.--31. 1. "FT3_5_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask1_pru1,"
hexmask.long 0x74 0.--31. 1. "FT3_5_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p0_pru1,"
hexmask.long 0x78 0.--31. 1. "FT3_6_P0,Filter3 P4:P1"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p1_pru1,"
hexmask.long 0x7C 0.--31. 1. "FT3_6_P1,Filter3 P8:P5"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask0_pru1,"
hexmask.long 0x80 0.--31. 1. "FT3_6_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask1_pru1,"
hexmask.long 0x84 0.--31. 1. "FT3_6_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p0_pru1,"
hexmask.long 0x88 0.--31. 1. "FT3_7_P0,Filter3 P4:P1"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p1_pru1,"
hexmask.long 0x8C 0.--31. 1. "FT3_7_P1,Filter3 P8:P5"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask0_pru1,"
hexmask.long 0x90 0.--31. 1. "FT3_7_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask1_pru1,"
hexmask.long 0x94 0.--31. 1. "FT3_7_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p0_pru1,"
hexmask.long 0x98 0.--31. 1. "FT3_8_P0,Filter3 P4:P1"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p1_pru1,"
hexmask.long 0x9C 0.--31. 1. "FT3_8_P1,Filter3 P8:P5"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask0_pru1,"
hexmask.long 0xA0 0.--31. 1. "FT3_8_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask1_pru1,"
hexmask.long 0xA4 0.--31. 1. "FT3_8_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p0_pru1,"
hexmask.long 0xA8 0.--31. 1. "FT3_9_P0,Filter3 P4:P1"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p1_pru1,"
hexmask.long 0xAC 0.--31. 1. "FT3_9_P1,Filter3 P8:P5"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask0_pru1,"
hexmask.long 0xB0 0.--31. 1. "FT3_9_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask1_pru1,"
hexmask.long 0xB4 0.--31. 1. "FT3_9_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p0_pru1,"
hexmask.long 0xB8 0.--31. 1. "FT3_10_P0,Filter3 P4:P1"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p1_pru1,"
hexmask.long 0xBC 0.--31. 1. "FT3_10_P1,Filter3 P8:P5"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask0_pru1,"
hexmask.long 0xC0 0.--31. 1. "FT3_10_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask1_pru1,"
hexmask.long 0xC4 0.--31. 1. "FT3_10_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p0_pru1,"
hexmask.long 0xC8 0.--31. 1. "FT3_11_P0,Filter3 P4:P1"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p1_pru1,"
hexmask.long 0xCC 0.--31. 1. "FT3_11_P1,Filter3 P8:P5"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask0_pru1,"
hexmask.long 0xD0 0.--31. 1. "FT3_11_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask1_pru1,"
hexmask.long 0xD4 0.--31. 1. "FT3_11_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p0_pru1,"
hexmask.long 0xD8 0.--31. 1. "FT3_12_P0,Filter3 P4:P1"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p1_pru1,"
hexmask.long 0xDC 0.--31. 1. "FT3_12_P1,Filter3 P8:P5"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask0_pru1,"
hexmask.long 0xE0 0.--31. 1. "FT3_12_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask1_pru1,"
hexmask.long 0xE4 0.--31. 1. "FT3_12_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p0_pru1,"
hexmask.long 0xE8 0.--31. 1. "FT3_13_P0,Filter3 P4:P1"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p1_pru1,"
hexmask.long 0xEC 0.--31. 1. "FT3_13_P1,Filter3 P8:P5"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask0_pru1,"
hexmask.long 0xF0 0.--31. 1. "FT3_13_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask1_pru1,"
hexmask.long 0xF4 0.--31. 1. "FT3_13_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p0_pru1,"
hexmask.long 0xF8 0.--31. 1. "FT3_14_P0,Filter3 P4:P1"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p1_pru1,"
hexmask.long 0xFC 0.--31. 1. "FT3_14_P1,Filter3 P8:P5"
line.long 0x100 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask0_pru1,"
hexmask.long 0x100 0.--31. 1. "FT3_14_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x104 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask1_pru1,"
hexmask.long 0x104 0.--31. 1. "FT3_14_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x108 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p0_pru1,"
hexmask.long 0x108 0.--31. 1. "FT3_15_P0,Filter3 P4:P1"
line.long 0x10C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p1_pru1,"
hexmask.long 0x10C 0.--31. 1. "FT3_15_P1,Filter3 P8:P5"
line.long 0x110 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask0_pru1,"
hexmask.long 0x110 0.--31. 1. "FT3_15_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x114 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask1_pru1,"
hexmask.long 0x114 0.--31. 1. "FT3_15_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x118 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft_rx_ptr_pru1,"
hexmask.long 0x118 0.--31. 1. "FT_RX_PTR_PRU1,RX current filter Byte Count"
line.long 0x11C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_and_en_pru1,"
hexmask.long 0x11C 0.--31. 1. "RX_CLASS0_AND_EN,rx class and enabels"
line.long 0x120 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_or_en_pru1,"
hexmask.long 0x120 0.--31. 1. "RX_CLASS0_OR_EN,rx class or enabels"
line.long 0x124 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_and_en_pru1,"
hexmask.long 0x124 0.--31. 1. "RX_CLASS1_AND_EN,rx class and enabels"
line.long 0x128 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_or_en_pru1,"
hexmask.long 0x128 0.--31. 1. "RX_CLASS1_OR_EN,rx class or enabels"
line.long 0x12C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_and_en_pru1,"
hexmask.long 0x12C 0.--31. 1. "RX_CLASS2_AND_EN,rx class and enabels"
line.long 0x130 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_or_en_pru1,"
hexmask.long 0x130 0.--31. 1. "RX_CLASS2_OR_EN,rx class or enabels"
line.long 0x134 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_and_en_pru1,"
hexmask.long 0x134 0.--31. 1. "RX_CLASS3_AND_EN,rx class and enabels"
line.long 0x138 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_or_en_pru1,"
hexmask.long 0x138 0.--31. 1. "RX_CLASS3_OR_EN,rx class or enabels"
line.long 0x13C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_and_en_pru1,"
hexmask.long 0x13C 0.--31. 1. "RX_CLASS4_AND_EN,rx class and enabels"
line.long 0x140 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_or_en_pru1,"
hexmask.long 0x140 0.--31. 1. "RX_CLASS4_OR_EN,rx class or enabels"
line.long 0x144 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_and_en_pru1,"
hexmask.long 0x144 0.--31. 1. "RX_CLASS5_AND_EN,rx class and enabels"
line.long 0x148 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_or_en_pru1,"
hexmask.long 0x148 0.--31. 1. "RX_CLASS5_OR_EN,rx class or enabels"
line.long 0x14C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_and_en_pru1,"
hexmask.long 0x14C 0.--31. 1. "RX_CLASS6_AND_EN,rx class and enabels"
line.long 0x150 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_or_en_pru1,"
hexmask.long 0x150 0.--31. 1. "RX_CLASS6_OR_EN,rx class or enabels"
line.long 0x154 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_and_en_pru1,"
hexmask.long 0x154 0.--31. 1. "RX_CLASS7_AND_EN,rx class and enabels"
line.long 0x158 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_or_en_pru1,"
hexmask.long 0x158 0.--31. 1. "RX_CLASS7_OR_EN,rx class or enabels"
line.long 0x15C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_and_en_pru1,"
hexmask.long 0x15C 0.--31. 1. "RX_CLASS8_AND_EN,rx class and enabels"
line.long 0x160 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_or_en_pru1,"
hexmask.long 0x160 0.--31. 1. "RX_CLASS8_OR_EN,rx class or enabels"
line.long 0x164 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_and_en_pru1,"
hexmask.long 0x164 0.--31. 1. "RX_CLASS9_AND_EN,rx class and enabels"
line.long 0x168 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_or_en_pru1,"
hexmask.long 0x168 0.--31. 1. "RX_CLASS9_OR_EN,rx class or enabels"
line.long 0x16C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_and_en_pru1,"
hexmask.long 0x16C 0.--31. 1. "RX_CLASS10_AND_EN,rx class and enabels"
line.long 0x170 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_or_en_pru1,"
hexmask.long 0x170 0.--31. 1. "RX_CLASS10_OR_EN,rx class or enabels"
line.long 0x174 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_and_en_pru1,"
hexmask.long 0x174 0.--31. 1. "RX_CLASS11_AND_EN,rx class and enabels"
line.long 0x178 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_or_en_pru1,"
hexmask.long 0x178 0.--31. 1. "RX_CLASS11_OR_EN,rx class or enabels"
line.long 0x17C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_and_en_pru1,"
hexmask.long 0x17C 0.--31. 1. "RX_CLASS12_AND_EN,rx class and enabels"
line.long 0x180 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_or_en_pru1,"
hexmask.long 0x180 0.--31. 1. "RX_CLASS12_OR_EN,rx class or enabels"
line.long 0x184 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_and_en_pru1,"
hexmask.long 0x184 0.--31. 1. "RX_CLASS13_AND_EN,rx class and enabels"
line.long 0x188 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_or_en_pru1,"
hexmask.long 0x188 0.--31. 1. "RX_CLASS13_OR_EN,rx class or enabels"
line.long 0x18C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_and_en_pru1,"
hexmask.long 0x18C 0.--31. 1. "RX_CLASS14_AND_EN,rx class and enabels"
line.long 0x190 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_or_en_pru1,"
hexmask.long 0x190 0.--31. 1. "RX_CLASS14_OR_EN,rx class or enabels"
line.long 0x194 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_and_en_pru1,"
hexmask.long 0x194 0.--31. 1. "RX_CLASS15_AND_EN,rx class and enabels"
line.long 0x198 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_or_en_pru1,"
hexmask.long 0x198 0.--31. 1. "RX_CLASS15_OR_EN,rx class or enabels"
line.long 0x19C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg1_pru1,"
bitfld.long 0x19C 30.--31. "RX_CLASS15_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 28.--29. "RX_CLASS14_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 26.--27. "RX_CLASS13_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 24.--25. "RX_CLASS12_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 22.--23. "RX_CLASS11_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 20.--21. "RX_CLASS10_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 18.--19. "RX_CLASS9_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 16.--17. "RX_CLASS8_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 14.--15. "RX_CLASS7_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 12.--13. "RX_CLASS6_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 10.--11. "RX_CLASS5_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 8.--9. "RX_CLASS4_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 6.--7. "RX_CLASS3_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 4.--5. "RX_CLASS2_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 2.--3. "RX_CLASS1_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 0.--1. "RX_CLASS0_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
line.long 0x1A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg2_pru1,"
hexmask.long.word 0x1A0 16.--31. 1. "RX_CLASS_OR_NV,rx class or nv enable"
hexmask.long.word 0x1A0 0.--15. 1. "RX_CLASS_AND_NV,rx class and nv enable"
line.long 0x1A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates0_pru1,"
bitfld.long 0x1A4 8. "RX_RED_PHASE_EN0,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A4 6. "RX_ALLOW_MASK0,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A4 5. "RX_CLASS_RAW_MASK0,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A4 4. "RX_PHASE_MASK0,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A4 0.--2. "RX_RATE_GATE_SEL0,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates1_pru1,"
bitfld.long 0x1A8 8. "RX_RED_PHASE_EN1,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A8 6. "RX_ALLOW_MASK1,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A8 5. "RX_CLASS_RAW_MASK1,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A8 4. "RX_PHASE_MASK1,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A8 0.--2. "RX_RATE_GATE_SEL1,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates2_pru1,"
bitfld.long 0x1AC 8. "RX_RED_PHASE_EN2,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1AC 6. "RX_ALLOW_MASK2,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1AC 5. "RX_CLASS_RAW_MASK2,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1AC 4. "RX_PHASE_MASK2,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1AC 0.--2. "RX_RATE_GATE_SEL2,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates3_pru1,"
bitfld.long 0x1B0 8. "RX_RED_PHASE_EN3,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B0 6. "RX_ALLOW_MASK3,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B0 5. "RX_CLASS_RAW_MASK3,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B0 4. "RX_PHASE_MASK3,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B0 0.--2. "RX_RATE_GATE_SEL3,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates4_pru1,"
bitfld.long 0x1B4 8. "RX_RED_PHASE_EN4,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B4 6. "RX_ALLOW_MASK4,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B4 5. "RX_CLASS_RAW_MASK4,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B4 4. "RX_PHASE_MASK4,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B4 0.--2. "RX_RATE_GATE_SEL4,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates5_pru1,"
bitfld.long 0x1B8 8. "RX_RED_PHASE_EN5,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B8 6. "RX_ALLOW_MASK5,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B8 5. "RX_CLASS_RAW_MASK5,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B8 4. "RX_PHASE_MASK5,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B8 0.--2. "RX_RATE_GATE_SEL5,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates6_pru1,"
bitfld.long 0x1BC 8. "RX_RED_PHASE_EN6,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1BC 6. "RX_ALLOW_MASK6,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1BC 5. "RX_CLASS_RAW_MASK6,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1BC 4. "RX_PHASE_MASK6,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1BC 0.--2. "RX_RATE_GATE_SEL6,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates7_pru1,"
bitfld.long 0x1C0 8. "RX_RED_PHASE_EN7,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C0 6. "RX_ALLOW_MASK7,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C0 5. "RX_CLASS_RAW_MASK7,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C0 4. "RX_PHASE_MASK7,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C0 0.--2. "RX_RATE_GATE_SEL7,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates8_pru1,"
bitfld.long 0x1C4 8. "RX_RED_PHASE_EN8,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C4 6. "RX_ALLOW_MASK8,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C4 5. "RX_CLASS_RAW_MASK8,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C4 4. "RX_PHASE_MASK8,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C4 0.--2. "RX_RATE_GATE_SEL8,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates9_pru1,"
bitfld.long 0x1C8 8. "RX_RED_PHASE_EN9,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C8 6. "RX_ALLOW_MASK9,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C8 5. "RX_CLASS_RAW_MASK9,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C8 4. "RX_PHASE_MASK9,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C8 0.--2. "RX_RATE_GATE_SEL9,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates10_pru1,"
bitfld.long 0x1CC 8. "RX_RED_PHASE_EN10,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1CC 6. "RX_ALLOW_MASK10,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1CC 5. "RX_CLASS_RAW_MASK10,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1CC 4. "RX_PHASE_MASK10,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1CC 0.--2. "RX_RATE_GATE_SEL10,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates11_pru1,"
bitfld.long 0x1D0 8. "RX_RED_PHASE_EN11,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D0 6. "RX_ALLOW_MASK11,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 5. "RX_CLASS_RAW_MASK11,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D0 4. "RX_PHASE_MASK11,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 0.--2. "RX_RATE_GATE_SEL11,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates12_pru1,"
bitfld.long 0x1D4 8. "RX_RED_PHASE_EN12,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D4 6. "RX_ALLOW_MASK12,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D4 5. "RX_CLASS_RAW_MASK12,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D4 4. "RX_PHASE_MASK12,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D4 0.--2. "RX_RATE_GATE_SEL12,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates13_pru1,"
bitfld.long 0x1D8 8. "RX_RED_PHASE_EN13,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D8 6. "RX_ALLOW_MASK13,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D8 5. "RX_CLASS_RAW_MASK13,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D8 4. "RX_PHASE_MASK13,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D8 0.--2. "RX_RATE_GATE_SEL13,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates14_pru1,"
bitfld.long 0x1DC 8. "RX_RED_PHASE_EN14,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1DC 6. "RX_ALLOW_MASK14,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1DC 5. "RX_CLASS_RAW_MASK14,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1DC 4. "RX_PHASE_MASK14,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1DC 0.--2. "RX_RATE_GATE_SEL14,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates15_pru1,"
bitfld.long 0x1E0 8. "RX_RED_PHASE_EN15,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1E0 6. "RX_ALLOW_MASK15,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 5. "RX_CLASS_RAW_MASK15,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1E0 4. "RX_PHASE_MASK15,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 0.--2. "RX_RATE_GATE_SEL15,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_green_pru1,"
rbitfld.long 0x1E4 4. "RX_GREEN_VAL,0 RED 1 GREEN status" "0,1"
hexmask.long.byte 0x1E4 0.--3. 1. "RX_GREEN_CMP_SEL,define which IEP CMP start green"
line.long 0x1E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_sa_hash_pru1,"
hexmask.long.word 0x1E8 0.--9. 1. "SA_HASH_SEED,SA Hash Seed"
line.long 0x1EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_pru1,"
hexmask.long.word 0x1EC 0.--9. 1. "CONN_HASH_SEED,Connection Hash Seed"
line.long 0x1F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_start_pru1,"
hexmask.long.word 0x1F0 0.--14. 1. "CONN_HASH_START,Connection Hash Start which 4 Bytes to hash"
line.long 0x1F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg0_pru1,"
hexmask.long 0x1F4 0.--31. 1. "RX_RATE_CIR_IDLE0,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg1_pru1,"
hexmask.long 0x1F8 0.--31. 1. "RX_RATE_CIR_IDLE1,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg2_pru1,"
hexmask.long 0x1FC 0.--31. 1. "RX_RATE_CIR_IDLE2,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x200 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg3_pru1,"
hexmask.long 0x200 0.--31. 1. "RX_RATE_CIR_IDLE3,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x204 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg4_pru1,"
hexmask.long 0x204 0.--31. 1. "RX_RATE_CIR_IDLE4,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x208 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg5_pru1,"
hexmask.long 0x208 0.--31. 1. "RX_RATE_CIR_IDLE5,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x20C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg6_pru1,"
hexmask.long 0x20C 0.--31. 1. "RX_RATE_CIR_IDLE6,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x210 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg7_pru1,"
hexmask.long 0x210 0.--31. 1. "RX_RATE_CIR_IDLE7,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x214 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel0_pru1,"
hexmask.long.byte 0x214 24.--29. 1. "RX_RATE_SRC_SEL3,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 16.--21. 1. "RX_RATE_SRC_SEL2,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x214 8.--13. 1. "RX_RATE_SRC_SEL1,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 0.--5. 1. "RX_RATE_SRC_SEL0,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x218 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel1_pru1,"
hexmask.long.byte 0x218 24.--29. 1. "RX_RATE_SRC_SEL7,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 16.--21. 1. "RX_RATE_SRC_SEL6,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x218 8.--13. 1. "RX_RATE_SRC_SEL5,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 0.--5. 1. "RX_RATE_SRC_SEL4,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x21C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_0_pru1,"
hexmask.long 0x21C 0.--31. 1. "TX_RATE_CIR_IDLE0,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x220 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_0_pru1,"
rbitfld.long 0x220 17. "TX_RATE_ALLOW0,TX Rate Pkt Enable" "0,1"
bitfld.long 0x220 16. "TX_RATE_EN0,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x220 0.--15. 1. "TX_RATE_LEN0,TX Rate Pkt Length"
line.long 0x224 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_1_pru1,"
hexmask.long 0x224 0.--31. 1. "TX_RATE_CIR_IDLE1,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x228 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_1_pru1,"
rbitfld.long 0x228 17. "TX_RATE_ALLOW1,TX Rate Pkt Enable" "0,1"
bitfld.long 0x228 16. "TX_RATE_EN1,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x228 0.--15. 1. "TX_RATE_LEN1,TX Rate Pkt Length"
line.long 0x22C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_2_pru1,"
hexmask.long 0x22C 0.--31. 1. "TX_RATE_CIR_IDLE2,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x230 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_2_pru1,"
rbitfld.long 0x230 17. "TX_RATE_ALLOW2,TX Rate Pkt Enable" "0,1"
bitfld.long 0x230 16. "TX_RATE_EN2,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x230 0.--15. 1. "TX_RATE_LEN2,TX Rate Pkt Length"
line.long 0x234 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_3_pru1,"
hexmask.long 0x234 0.--31. 1. "TX_RATE_CIR_IDLE3,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x238 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_3_pru1,"
rbitfld.long 0x238 17. "TX_RATE_ALLOW3,TX Rate Pkt Enable" "0,1"
bitfld.long 0x238 16. "TX_RATE_EN3,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x238 0.--15. 1. "TX_RATE_LEN3,TX Rate Pkt Length"
line.long 0x23C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_4_pru1,"
hexmask.long 0x23C 0.--31. 1. "TX_RATE_CIR_IDLE4,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x240 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_4_pru1,"
rbitfld.long 0x240 17. "TX_RATE_ALLOW4,TX Rate Pkt Enable" "0,1"
bitfld.long 0x240 16. "TX_RATE_EN4,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x240 0.--15. 1. "TX_RATE_LEN4,TX Rate Pkt Length"
line.long 0x244 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_5_pru1,"
hexmask.long 0x244 0.--31. 1. "TX_RATE_CIR_IDLE5,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x248 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_5_pru1,"
rbitfld.long 0x248 17. "TX_RATE_ALLOW5,TX Rate Pkt Enable" "0,1"
bitfld.long 0x248 16. "TX_RATE_EN5,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x248 0.--15. 1. "TX_RATE_LEN5,TX Rate Pkt Length"
line.long 0x24C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_6_pru1,"
hexmask.long 0x24C 0.--31. 1. "TX_RATE_CIR_IDLE6,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x250 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_6_pru1,"
rbitfld.long 0x250 17. "TX_RATE_ALLOW6,TX Rate Pkt Enable" "0,1"
bitfld.long 0x250 16. "TX_RATE_EN6,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x250 0.--15. 1. "TX_RATE_LEN6,TX Rate Pkt Length"
line.long 0x254 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_7_pru1,"
hexmask.long 0x254 0.--31. 1. "TX_RATE_CIR_IDLE7,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x258 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_7_pru1,"
rbitfld.long 0x258 17. "TX_RATE_ALLOW7,TX Rate Pkt Enable" "0,1"
bitfld.long 0x258 16. "TX_RATE_EN7,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x258 0.--15. 1. "TX_RATE_LEN7,TX Rate Pkt Length"
line.long 0x25C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_good_pru1,"
hexmask.long 0x25C 0.--31. 1. "RX_GOOD_FRM_CNT,RX Good Frame Count Inc on none min err max err crc err odd err  Wrt subtracts"
line.long 0x260 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bc_pru1,"
hexmask.long.word 0x260 0.--15. 1. "RX_BC_FRM_CNT,RX BC Frame Count Inc on BC type  Wrt subtracts"
line.long 0x264 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mc_pru1,"
hexmask.long.word 0x264 0.--15. 1. "RX_MC_FRM_CNT,RX MC Frame Count Inc on MC type  Wrt subtracts"
line.long 0x268 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_crc_err_pru1,"
hexmask.long.word 0x268 0.--15. 1. "RX_CRC_ERR_FRM_CNT,RX CRC Err Frame Count Inc on crc err  Wrt subtracts"
line.long 0x26C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mii_err_pru1,"
hexmask.long.word 0x26C 0.--15. 1. "RX_MII_ERR_FRM_CNT,RX MII Err Frame Count Inc on mii sgmii rgmii err  Wrt subtracts"
line.long 0x270 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_odd_err_pru1,"
hexmask.long.word 0x270 0.--15. 1. "RX_ODD_ERR_FRM_CNT,RX Odd Nibble Frame Count Inc on odd nibble mii  Wrt subtracts"
line.long 0x274 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_size_pru1,"
hexmask.long.word 0x274 0.--15. 1. "RX_MAX_SIZE_FRM,RX MAX Size Frame Count Limit"
line.long 0x278 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_err_pru1,"
hexmask.long.word 0x278 0.--15. 1. "RX_MAX_ERR_FRM_CNT,RX MAX Size Err Frame Count Inc if > than Limit  Wrt subtracts"
line.long 0x27C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_size_pru1,"
hexmask.long.word 0x27C 0.--15. 1. "RX_MIN_SIZE_FRM,RX MIN Size Frame Limit"
line.long 0x280 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_err_pru1,"
hexmask.long.word 0x280 0.--15. 1. "RX_MIN_ERR_FRM_CNT,RX MIN Size Frame Count Inc if < than limit  Wrt subtracts"
line.long 0x284 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_overrun_err_pru1,"
hexmask.long.word 0x284 0.--15. 1. "RX_OVERRUN_ERR_FRM_CNT,RX L1 FIFO overflow Frame Count Inc on overflow event  Wrt subtracts"
line.long 0x288 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class0_hit_pru1,"
hexmask.long 0x288 0.--31. 1. "RX_STAT_CLASS0_PRU1,RX Class0 Hit Count  Wrt subtracts"
line.long 0x28C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class1_hit_pru1,"
hexmask.long 0x28C 0.--31. 1. "RX_STAT_CLASS1_PRU1,RX Class1 Hit Count  Wrt subtracts"
line.long 0x290 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class2_hit_pru1,"
hexmask.long 0x290 0.--31. 1. "RX_STAT_CLASS2_PRU1,RX Class2 Hit Count  Wrt subtracts"
line.long 0x294 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class3_hit_pru1,"
hexmask.long 0x294 0.--31. 1. "RX_STAT_CLASS3_PRU1,RX Class3 Hit Count  Wrt subtracts"
line.long 0x298 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class4_hit_pru1,"
hexmask.long 0x298 0.--31. 1. "RX_STAT_CLASS4_PRU1,RX Class4 Hit Count  Wrt subtracts"
line.long 0x29C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class5_hit_pru1,"
hexmask.long 0x29C 0.--31. 1. "RX_STAT_CLASS5_PRU1,RX Class5 Hit Count  Wrt subtracts"
line.long 0x2A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class6_hit_pru1,"
hexmask.long 0x2A0 0.--31. 1. "RX_STAT_CLASS6_PRU1,RX Class6 Hit Count  Wrt subtracts"
line.long 0x2A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class7_hit_pru1,"
hexmask.long 0x2A4 0.--31. 1. "RX_STAT_CLASS7_PRU1,RX Class7 Hit Count  Wrt subtracts"
line.long 0x2A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class8_hit_pru1,"
hexmask.long 0x2A8 0.--31. 1. "RX_STAT_CLASS8_PRU1,RX Class8 Hit Count  Wrt subtracts"
line.long 0x2AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class9_hit_pru1,"
hexmask.long 0x2AC 0.--31. 1. "RX_STAT_CLASS9_PRU1,RX Class9 Hit Count  Wrt subtracts"
line.long 0x2B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class10_hit_pru1,"
hexmask.long 0x2B0 0.--31. 1. "RX_STAT_CLASS10_PRU1,RX Class10 Hit Count  Wrt subtracts"
line.long 0x2B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class11_hit_pru1,"
hexmask.long 0x2B4 0.--31. 1. "RX_STAT_CLASS11_PRU1,RX Class11 Hit Count  Wrt subtracts"
line.long 0x2B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class12_hit_pru1,"
hexmask.long 0x2B8 0.--31. 1. "RX_STAT_CLASS12_PRU1,RX Class12 Hit Count  Wrt subtracts"
line.long 0x2BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class13_hit_pru1,"
hexmask.long 0x2BC 0.--31. 1. "RX_STAT_CLASS13_PRU1,RX Class13 Hit Count  Wrt subtracts"
line.long 0x2C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class14_hit_pru1,"
hexmask.long 0x2C0 0.--31. 1. "RX_STAT_CLASS14_PRU1,RX Class14 Hit Count  Wrt subtracts"
line.long 0x2C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class15_hit_pru1,"
hexmask.long 0x2C4 0.--31. 1. "RX_STAT_CLASS15_PRU1,RX Class15 Hit Count  Wrt subtracts"
line.long 0x2C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_smd_frag_err_pru1,"
hexmask.long.byte 0x2C8 24.--31. 1. "RX_STAT_SMD_ERR_PRU1,RX SMDS Error Count  Inc when first none 0x55 does not match any valid SMD  Wrt subtracts"
hexmask.long.byte 0x2C8 16.--23. 1. "RX_STAT_FRAG_ERR_PRU1,RX Frag_Cnt Seq Error Count  Wrt subtracts"
newline
hexmask.long.byte 0x2C8 8.--15. 1. "RX_STAT_SMDC_ERR_PRU1,RX SMDCx Seq Error Count  Wrt subtracts"
hexmask.long.byte 0x2C8 0.--7. 1. "RX_STAT_SMDS_ERR_PRU1,RX SMDSx Seq Error Count  Wrt subtracts"
line.long 0x2CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_size_pru1,"
hexmask.long.word 0x2CC 0.--13. 1. "RX_STAT_BKT1_SIZE,RX Bucket1 Byte Size"
line.long 0x2D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_size_pru1,"
hexmask.long.word 0x2D0 0.--13. 1. "RX_STAT_BKT2_SIZE,RX Bucket2 Byte Size"
line.long 0x2D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_size_pru1,"
hexmask.long.word 0x2D4 0.--13. 1. "RX_STAT_BKT3_SIZE,RX Bucket3 Byte Size"
line.long 0x2D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_size_pru1,"
hexmask.long.word 0x2D8 0.--13. 1. "RX_STAT_BKT4_SIZE,RX Bucket4 Byte Size"
line.long 0x2DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_64_pru1,"
hexmask.long.word 0x2DC 0.--15. 1. "RX_64_FRM_CNT,RX 64Byte Frame Count Inc if 64B size"
line.long 0x2E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_pru1,"
hexmask.long.word 0x2E0 0.--15. 1. "RX_STAT_BKT1,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
line.long 0x2E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_pru1,"
hexmask.long.word 0x2E4 0.--15. 1. "RX_STAT_BKT2,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x2E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_pru1,"
hexmask.long.word 0x2E8 0.--15. 1. "RX_STAT_BKT3,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x2EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_pru1,"
hexmask.long.word 0x2EC 0.--15. 1. "RX_STAT_BKT4,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x2F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt5_pru1,"
hexmask.long.word 0x2F0 0.--15. 1. "RX_STAT_BKT5,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
line.long 0x2F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_total_bytes_pru1,"
hexmask.long 0x2F4 0.--31. 1. "RX_STAT_TOTAL_BYTES_PRU,RX Total Byte Count"
line.long 0x2F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rxtx_stat_total_bytes_pru1,"
hexmask.long 0x2F8 0.--31. 1. "RXTX_STAT_TOTAL_BYTES_PRU,RX and TX Total Byte Count"
line.long 0x2FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_good_port1,"
hexmask.long 0x2FC 0.--31. 1. "TX_GOOD_FRM_CNT,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
line.long 0x300 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bc_port1,"
hexmask.long.word 0x300 0.--15. 1. "TX_BC_FRM_CNT,TX BC Frame Count Inc if BC"
line.long 0x304 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_mc_port1,"
hexmask.long.word 0x304 0.--15. 1. "TX_MC_FRM_CNT,TX MC Frame Count Inc if MC"
line.long 0x308 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_odd_err_port1,"
hexmask.long.word 0x308 0.--15. 1. "TX_ODD_ERR_FRM_CNT,TX Odd Nibble Frame Count Inc if mii odd nibble"
line.long 0x30C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_underflow_err_port1,"
hexmask.long.word 0x30C 0.--15. 1. "TX_UNDERFLOW_CNT,TX MAX Underflow Error Cnt"
line.long 0x310 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_size_port1,"
hexmask.long.word 0x310 0.--15. 1. "TX_MAX_SIZE_FRM,TX MAX Size Frame Count Limit"
line.long 0x314 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_err_port1,"
hexmask.long.word 0x314 0.--15. 1. "TX_MAX_ERR_FRM_CNT,TX MAX Size Err Frame Count Inc if > max Limit"
line.long 0x318 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_size_port1,"
hexmask.long.word 0x318 0.--15. 1. "TX_MIN_SIZE_FRM,TX MIN Size Frame Count Limit"
line.long 0x31C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_err_port1,"
hexmask.long.word 0x31C 0.--15. 1. "TX_MIN_ERR_FRM_CNT,TX MIN Size Err Frame Count Inc if < min Limit"
line.long 0x320 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_size_port1,"
hexmask.long.word 0x320 0.--13. 1. "TX_STAT_BKT1_SIZE,TX Bucket1 Byte Size"
line.long 0x324 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_size_port1,"
hexmask.long.word 0x324 0.--13. 1. "TX_STAT_BKT2_SIZE,TX Bucket2 Byte Size"
line.long 0x328 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_size_port1,"
hexmask.long.word 0x328 0.--13. 1. "TX_STAT_BKT3_SIZE,TX Bucket3 Byte Size"
line.long 0x32C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_size_port1,"
hexmask.long.word 0x32C 0.--13. 1. "TX_STAT_BKT4_SIZE,TX Bucket4 Byte Size"
line.long 0x330 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_64_port1,"
hexmask.long.word 0x330 0.--15. 1. "TX_64_FRM_CNT,TX 64Byte Frame Count Inc if 64B"
line.long 0x334 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_port1,"
hexmask.long.word 0x334 0.--15. 1. "TX_STAT_BKT1,TX Bucket1 Inc if <= than Bucket1"
line.long 0x338 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_port1,"
hexmask.long.word 0x338 0.--15. 1. "TX_STAT_BKT2,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x33C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_port1,"
hexmask.long.word 0x33C 0.--15. 1. "TX_STAT_BKT3,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x340 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_port1,"
hexmask.long.word 0x340 0.--15. 1. "TX_STAT_BKT4,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x344 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt5_port1,"
hexmask.long.word 0x344 0.--15. 1. "TX_STAT_BKT5,TX Bucket5 Inc if > than Bucket4 Byte Size"
line.long 0x348 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_total_bytes_port1,"
hexmask.long 0x348 0.--31. 1. "TX_TOTAL_STAT_BYTES_PORT,TX Total Byte Count of all Frames"
line.long 0x34C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_tag_port1,"
hexmask.long 0x34C 0.--31. 1. "TX_HSR_TAG,HSR TAG"
line.long 0x350 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_seq_port1,"
hexmask.long.word 0x350 0.--15. 1. "TX_HSR_SEQ,HSR Seq count. It will incr for every HSR type"
line.long 0x354 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_type_tag_port1,"
hexmask.long.word 0x354 0.--15. 1. "TX_VLAN_TYPE_TAG,TX VLAN Type Tag  match to enable VLAN removal"
line.long 0x358 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_ins_tag_port1,"
hexmask.long 0x358 0.--31. 1. "TX_VLAN_INS_TAG,TX VLAN Insertion"
group.long 0xD00++0xFF
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue0,"
hexmask.long.word 0x0 0.--15. 1. "QUEUE_H_PTR0,Queue 0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue1,"
hexmask.long.word 0x4 0.--15. 1. "QUEUE_H_PTR1,Queue 1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue2,"
hexmask.long.word 0x8 0.--15. 1. "QUEUE_H_PTR2,Queue 2"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue3,"
hexmask.long.word 0xC 0.--15. 1. "QUEUE_H_PTR3,Queue 3"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue4,"
hexmask.long.word 0x10 0.--15. 1. "QUEUE_H_PTR4,Queue 4"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue5,"
hexmask.long.word 0x14 0.--15. 1. "QUEUE_H_PTR5,Queue 5"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue6,"
hexmask.long.word 0x18 0.--15. 1. "QUEUE_H_PTR6,Queue 6"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue7,"
hexmask.long.word 0x1C 0.--15. 1. "QUEUE_H_PTR7,Queue 7"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue8,"
hexmask.long.word 0x20 0.--15. 1. "QUEUE_H_PTR8,Queue 8"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue9,"
hexmask.long.word 0x24 0.--15. 1. "QUEUE_H_PTR9,Queue 9"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue10,"
hexmask.long.word 0x28 0.--15. 1. "QUEUE_H_PTR10,Queue 10"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue11,"
hexmask.long.word 0x2C 0.--15. 1. "QUEUE_H_PTR11,Queue 11"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue12,"
hexmask.long.word 0x30 0.--15. 1. "QUEUE_H_PTR12,Queue 12"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue13,"
hexmask.long.word 0x34 0.--15. 1. "QUEUE_H_PTR13,Queue 13"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue14,"
hexmask.long.word 0x38 0.--15. 1. "QUEUE_H_PTR14,Queue 14"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue15,"
hexmask.long.word 0x3C 0.--15. 1. "QUEUE_H_PTR15,Queue 15"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue16,"
hexmask.long.word 0x40 0.--15. 1. "QUEUE_H_PTR16,Queue 16"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue17,"
hexmask.long.word 0x44 0.--15. 1. "QUEUE_H_PTR17,Queue 17"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue18,"
hexmask.long.word 0x48 0.--15. 1. "QUEUE_H_PTR18,Queue 18"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue19,"
hexmask.long.word 0x4C 0.--15. 1. "QUEUE_H_PTR19,Queue 19"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue20,"
hexmask.long.word 0x50 0.--15. 1. "QUEUE_H_PTR20,Queue 20"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue21,"
hexmask.long.word 0x54 0.--15. 1. "QUEUE_H_PTR21,Queue 21"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue22,"
hexmask.long.word 0x58 0.--15. 1. "QUEUE_H_PTR22,Queue 22"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue23,"
hexmask.long.word 0x5C 0.--15. 1. "QUEUE_H_PTR23,Queue 23"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue24,"
hexmask.long.word 0x60 0.--15. 1. "QUEUE_H_PTR24,Queue 24"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue25,"
hexmask.long.word 0x64 0.--15. 1. "QUEUE_H_PTR25,Queue 25"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue26,"
hexmask.long.word 0x68 0.--15. 1. "QUEUE_H_PTR26,Queue 26"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue27,"
hexmask.long.word 0x6C 0.--15. 1. "QUEUE_H_PTR27,Queue 27"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue28,"
hexmask.long.word 0x70 0.--15. 1. "QUEUE_H_PTR28,Queue 28"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue29,"
hexmask.long.word 0x74 0.--15. 1. "QUEUE_H_PTR29,Queue 29"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue30,"
hexmask.long.word 0x78 0.--15. 1. "QUEUE_H_PTR30,Queue 30"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue31,"
hexmask.long.word 0x7C 0.--15. 1. "QUEUE_H_PTR31,Queue 31"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue32,"
hexmask.long.word 0x80 0.--15. 1. "QUEUE_H_PTR32,Queue 32"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue33,"
hexmask.long.word 0x84 0.--15. 1. "QUEUE_H_PTR33,Queue 33"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue34,"
hexmask.long.word 0x88 0.--15. 1. "QUEUE_H_PTR34,Queue 34"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue35,"
hexmask.long.word 0x8C 0.--15. 1. "QUEUE_H_PTR35,Queue 35"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue36,"
hexmask.long.word 0x90 0.--15. 1. "QUEUE_H_PTR36,Queue 36"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue37,"
hexmask.long.word 0x94 0.--15. 1. "QUEUE_H_PTR37,Queue 37"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue38,"
hexmask.long.word 0x98 0.--15. 1. "QUEUE_H_PTR38,Queue 38"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue39,"
hexmask.long.word 0x9C 0.--15. 1. "QUEUE_H_PTR39,Queue 39"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue40,"
hexmask.long.word 0xA0 0.--15. 1. "QUEUE_H_PTR40,Queue 40"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue41,"
hexmask.long.word 0xA4 0.--15. 1. "QUEUE_H_PTR41,Queue 41"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue42,"
hexmask.long.word 0xA8 0.--15. 1. "QUEUE_H_PTR42,Queue 42"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue43,"
hexmask.long.word 0xAC 0.--15. 1. "QUEUE_H_PTR43,Queue 43"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue44,"
hexmask.long.word 0xB0 0.--15. 1. "QUEUE_H_PTR44,Queue 44"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue45,"
hexmask.long.word 0xB4 0.--15. 1. "QUEUE_H_PTR45,Queue 45"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue46,"
hexmask.long.word 0xB8 0.--15. 1. "QUEUE_H_PTR46,Queue 46"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue47,"
hexmask.long.word 0xBC 0.--15. 1. "QUEUE_H_PTR47,Queue 47"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue48,"
hexmask.long.word 0xC0 0.--15. 1. "QUEUE_H_PTR48,Queue 48"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue49,"
hexmask.long.word 0xC4 0.--15. 1. "QUEUE_H_PTR49,Queue 49"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue50,"
hexmask.long.word 0xC8 0.--15. 1. "QUEUE_H_PTR50,Queue 50"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue51,"
hexmask.long.word 0xCC 0.--15. 1. "QUEUE_H_PTR51,Queue 51"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue52,"
hexmask.long.word 0xD0 0.--15. 1. "QUEUE_H_PTR52,Queue 52"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue53,"
hexmask.long.word 0xD4 0.--15. 1. "QUEUE_H_PTR53,Queue 53"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue54,"
hexmask.long.word 0xD8 0.--15. 1. "QUEUE_H_PTR54,Queue 54"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue55,"
hexmask.long.word 0xDC 0.--15. 1. "QUEUE_H_PTR55,Queue 55"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue56,"
hexmask.long.word 0xE0 0.--15. 1. "QUEUE_H_PTR56,Queue 56"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue57,"
hexmask.long.word 0xE4 0.--15. 1. "QUEUE_H_PTR57,Queue 57"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue58,"
hexmask.long.word 0xE8 0.--15. 1. "QUEUE_H_PTR58,Queue 58"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue59,"
hexmask.long.word 0xEC 0.--15. 1. "QUEUE_H_PTR59,Queue 59"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue60,"
hexmask.long.word 0xF0 0.--15. 1. "QUEUE_H_PTR60,Queue 60"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue61,"
hexmask.long.word 0xF4 0.--15. 1. "QUEUE_H_PTR61,Queue 61"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue62,"
hexmask.long.word 0xF8 0.--15. 1. "QUEUE_H_PTR62,Queue 62"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue63,"
hexmask.long.word 0xFC 0.--15. 1. "QUEUE_H_PTR63,Queue 63"
rgroup.long 0xE00++0x13F
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek0,"
hexmask.long.word 0x0 0.--15. 1. "QUEUE_H_PEEK_PTR0,Queue 0 Peek portal"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek1,"
hexmask.long.word 0x4 0.--15. 1. "QUEUE_H_PEEK_PTR1,Queue 1 Peek portal"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek2,"
hexmask.long.word 0x8 0.--15. 1. "QUEUE_H_PEEK_PTR2,Queue 2 Peek portal"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek3,"
hexmask.long.word 0xC 0.--15. 1. "QUEUE_H_PEEK_PTR3,Queue 3 Peek portal"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek4,"
hexmask.long.word 0x10 0.--15. 1. "QUEUE_H_PEEK_PTR4,Queue 4 Peek portal"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek5,"
hexmask.long.word 0x14 0.--15. 1. "QUEUE_H_PEEK_PTR5,Queue 5 Peek portal"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek6,"
hexmask.long.word 0x18 0.--15. 1. "QUEUE_H_PEEK_PTR6,Queue 6 Peek portal"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek7,"
hexmask.long.word 0x1C 0.--15. 1. "QUEUE_H_PEEK_PTR7,Queue 7 Peek portal"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek8,"
hexmask.long.word 0x20 0.--15. 1. "QUEUE_H_PEEK_PTR8,Queue 8 Peek portal"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek9,"
hexmask.long.word 0x24 0.--15. 1. "QUEUE_H_PEEK_PTR9,Queue 9 Peek portal"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek10,"
hexmask.long.word 0x28 0.--15. 1. "QUEUE_H_PEEK_PTR10,Queue 10 Peek portal"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek11,"
hexmask.long.word 0x2C 0.--15. 1. "QUEUE_H_PEEK_PTR11,Queue 11 Peek portal"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek12,"
hexmask.long.word 0x30 0.--15. 1. "QUEUE_H_PEEK_PTR12,Queue 12 Peek portal"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek13,"
hexmask.long.word 0x34 0.--15. 1. "QUEUE_H_PEEK_PTR13,Queue 13 Peek portal"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek14,"
hexmask.long.word 0x38 0.--15. 1. "QUEUE_H_PEEK_PTR14,Queue 14 Peek portal"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek15,"
hexmask.long.word 0x3C 0.--15. 1. "QUEUE_H_PEEK_PTR15,Queue 15 Peek portal"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt0,"
hexmask.long.word 0x40 0.--15. 1. "QUEUE_CNT_ENTRIES_0,Queue Entry Count0"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt1,"
hexmask.long.word 0x44 0.--15. 1. "QUEUE_CNT_ENTRIES_1,Queue Entry Count1"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt2,"
hexmask.long.word 0x48 0.--15. 1. "QUEUE_CNT_ENTRIES_2,Queue Entry Count2"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt3,"
hexmask.long.word 0x4C 0.--15. 1. "QUEUE_CNT_ENTRIES_3,Queue Entry Count3"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt4,"
hexmask.long.word 0x50 0.--15. 1. "QUEUE_CNT_ENTRIES_4,Queue Entry Count4"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt5,"
hexmask.long.word 0x54 0.--15. 1. "QUEUE_CNT_ENTRIES_5,Queue Entry Count5"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt6,"
hexmask.long.word 0x58 0.--15. 1. "QUEUE_CNT_ENTRIES_6,Queue Entry Count6"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt7,"
hexmask.long.word 0x5C 0.--15. 1. "QUEUE_CNT_ENTRIES_7,Queue Entry Count7"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt8,"
hexmask.long.word 0x60 0.--15. 1. "QUEUE_CNT_ENTRIES_8,Queue Entry Count8"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt9,"
hexmask.long.word 0x64 0.--15. 1. "QUEUE_CNT_ENTRIES_9,Queue Entry Count9"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt10,"
hexmask.long.word 0x68 0.--15. 1. "QUEUE_CNT_ENTRIES_10,Queue Entry Count10"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt11,"
hexmask.long.word 0x6C 0.--15. 1. "QUEUE_CNT_ENTRIES_11,Queue Entry Count11"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt12,"
hexmask.long.word 0x70 0.--15. 1. "QUEUE_CNT_ENTRIES_12,Queue Entry Count12"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt13,"
hexmask.long.word 0x74 0.--15. 1. "QUEUE_CNT_ENTRIES_13,Queue Entry Count13"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt14,"
hexmask.long.word 0x78 0.--15. 1. "QUEUE_CNT_ENTRIES_14,Queue Entry Count14"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt15,"
hexmask.long.word 0x7C 0.--15. 1. "QUEUE_CNT_ENTRIES_15,Queue Entry Count15"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt16,"
hexmask.long.word 0x80 0.--15. 1. "QUEUE_CNT_ENTRIES_16,Queue Entry Count16"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt17,"
hexmask.long.word 0x84 0.--15. 1. "QUEUE_CNT_ENTRIES_17,Queue Entry Count17"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt18,"
hexmask.long.word 0x88 0.--15. 1. "QUEUE_CNT_ENTRIES_18,Queue Entry Count18"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt19,"
hexmask.long.word 0x8C 0.--15. 1. "QUEUE_CNT_ENTRIES_19,Queue Entry Count19"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt20,"
hexmask.long.word 0x90 0.--15. 1. "QUEUE_CNT_ENTRIES_20,Queue Entry Count20"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt21,"
hexmask.long.word 0x94 0.--15. 1. "QUEUE_CNT_ENTRIES_21,Queue Entry Count21"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt22,"
hexmask.long.word 0x98 0.--15. 1. "QUEUE_CNT_ENTRIES_22,Queue Entry Count22"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt23,"
hexmask.long.word 0x9C 0.--15. 1. "QUEUE_CNT_ENTRIES_23,Queue Entry Count23"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt24,"
hexmask.long.word 0xA0 0.--15. 1. "QUEUE_CNT_ENTRIES_24,Queue Entry Count24"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt25,"
hexmask.long.word 0xA4 0.--15. 1. "QUEUE_CNT_ENTRIES_25,Queue Entry Count25"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt26,"
hexmask.long.word 0xA8 0.--15. 1. "QUEUE_CNT_ENTRIES_26,Queue Entry Count26"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt27,"
hexmask.long.word 0xAC 0.--15. 1. "QUEUE_CNT_ENTRIES_27,Queue Entry Count27"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt28,"
hexmask.long.word 0xB0 0.--15. 1. "QUEUE_CNT_ENTRIES_28,Queue Entry Count28"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt29,"
hexmask.long.word 0xB4 0.--15. 1. "QUEUE_CNT_ENTRIES_29,Queue Entry Count29"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt30,"
hexmask.long.word 0xB8 0.--15. 1. "QUEUE_CNT_ENTRIES_30,Queue Entry Count30"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt31,"
hexmask.long.word 0xBC 0.--15. 1. "QUEUE_CNT_ENTRIES_31,Queue Entry Count31"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt32,"
hexmask.long.word 0xC0 0.--15. 1. "QUEUE_CNT_ENTRIES_32,Queue Entry Count32"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt33,"
hexmask.long.word 0xC4 0.--15. 1. "QUEUE_CNT_ENTRIES_33,Queue Entry Count33"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt34,"
hexmask.long.word 0xC8 0.--15. 1. "QUEUE_CNT_ENTRIES_34,Queue Entry Count34"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt35,"
hexmask.long.word 0xCC 0.--15. 1. "QUEUE_CNT_ENTRIES_35,Queue Entry Count35"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt36,"
hexmask.long.word 0xD0 0.--15. 1. "QUEUE_CNT_ENTRIES_36,Queue Entry Count36"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt37,"
hexmask.long.word 0xD4 0.--15. 1. "QUEUE_CNT_ENTRIES_37,Queue Entry Count37"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt38,"
hexmask.long.word 0xD8 0.--15. 1. "QUEUE_CNT_ENTRIES_38,Queue Entry Count38"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt39,"
hexmask.long.word 0xDC 0.--15. 1. "QUEUE_CNT_ENTRIES_39,Queue Entry Count39"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt40,"
hexmask.long.word 0xE0 0.--15. 1. "QUEUE_CNT_ENTRIES_40,Queue Entry Count40"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt41,"
hexmask.long.word 0xE4 0.--15. 1. "QUEUE_CNT_ENTRIES_41,Queue Entry Count41"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt42,"
hexmask.long.word 0xE8 0.--15. 1. "QUEUE_CNT_ENTRIES_42,Queue Entry Count42"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt43,"
hexmask.long.word 0xEC 0.--15. 1. "QUEUE_CNT_ENTRIES_43,Queue Entry Count43"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt44,"
hexmask.long.word 0xF0 0.--15. 1. "QUEUE_CNT_ENTRIES_44,Queue Entry Count44"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt45,"
hexmask.long.word 0xF4 0.--15. 1. "QUEUE_CNT_ENTRIES_45,Queue Entry Count45"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt46,"
hexmask.long.word 0xF8 0.--15. 1. "QUEUE_CNT_ENTRIES_46,Queue Entry Count46"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt47,"
hexmask.long.word 0xFC 0.--15. 1. "QUEUE_CNT_ENTRIES_47,Queue Entry Count47"
line.long 0x100 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt48,"
hexmask.long.word 0x100 0.--15. 1. "QUEUE_CNT_ENTRIES_48,Queue Entry Count48"
line.long 0x104 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt49,"
hexmask.long.word 0x104 0.--15. 1. "QUEUE_CNT_ENTRIES_49,Queue Entry Count49"
line.long 0x108 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt50,"
hexmask.long.word 0x108 0.--15. 1. "QUEUE_CNT_ENTRIES_50,Queue Entry Count50"
line.long 0x10C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt51,"
hexmask.long.word 0x10C 0.--15. 1. "QUEUE_CNT_ENTRIES_51,Queue Entry Count51"
line.long 0x110 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt52,"
hexmask.long.word 0x110 0.--15. 1. "QUEUE_CNT_ENTRIES_52,Queue Entry Count52"
line.long 0x114 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt53,"
hexmask.long.word 0x114 0.--15. 1. "QUEUE_CNT_ENTRIES_53,Queue Entry Count53"
line.long 0x118 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt54,"
hexmask.long.word 0x118 0.--15. 1. "QUEUE_CNT_ENTRIES_54,Queue Entry Count54"
line.long 0x11C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt55,"
hexmask.long.word 0x11C 0.--15. 1. "QUEUE_CNT_ENTRIES_55,Queue Entry Count55"
line.long 0x120 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt56,"
hexmask.long.word 0x120 0.--15. 1. "QUEUE_CNT_ENTRIES_56,Queue Entry Count56"
line.long 0x124 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt57,"
hexmask.long.word 0x124 0.--15. 1. "QUEUE_CNT_ENTRIES_57,Queue Entry Count57"
line.long 0x128 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt58,"
hexmask.long.word 0x128 0.--15. 1. "QUEUE_CNT_ENTRIES_58,Queue Entry Count58"
line.long 0x12C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt59,"
hexmask.long.word 0x12C 0.--15. 1. "QUEUE_CNT_ENTRIES_59,Queue Entry Count59"
line.long 0x130 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt60,"
hexmask.long.word 0x130 0.--15. 1. "QUEUE_CNT_ENTRIES_60,Queue Entry Count60"
line.long 0x134 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt61,"
hexmask.long.word 0x134 0.--15. 1. "QUEUE_CNT_ENTRIES_61,Queue Entry Count61"
line.long 0x138 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt62,"
hexmask.long.word 0x138 0.--15. 1. "QUEUE_CNT_ENTRIES_62,Queue Entry Count62"
line.long 0x13C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt63,"
hexmask.long.word 0x13C 0.--15. 1. "QUEUE_CNT_ENTRIES_63,Queue Entry Count63"
group.long 0xF40++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_reset,"
hexmask.long.byte 0x0 0.--5. 1. "RESET_QUEUE_ID,Reset Queue ID"
tree.end
endif
tree.end
tree "PRU_ICSSG0_PR1_TASKS"
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR (PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR)"
base ad:0x3002A000
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR (PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR)"
base ad:0x3002A100
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR (PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR)"
base ad:0x3002A200
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR (PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR)"
base ad:0x3002A300
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR (PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR)"
base ad:0x3002A400
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR (PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR)"
base ad:0x3002A500
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR"
base ad:0x2A000
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR"
base ad:0x2A100
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR"
base ad:0x2A200
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR"
base ad:0x2A300
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR"
base ad:0x2A400
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR"
base ad:0x2A500
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
endif
tree.end
tree.end
tree "PRU_ICSSG0_RAT"
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_RAT_SLICE0_CFG (PRU_ICSSG0_RAT_SLICE0_CFG)"
base ad:0x30008000
rgroup.long 0x0++0x7
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_config,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x3
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
group.long 0x820++0x3
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1"
bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1"
rgroup.long 0x824++0x17
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 4 = RAT."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 1 = Boundary crossing error."
line.long 0x8 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits."
line.long 0x10 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x840++0x13
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1"
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1"
line.long 0x8 "PR1_RAT_SLICE0__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1"
line.long 0xC "PR1_RAT_SLICE0__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1"
line.long 0x10 "PR1_RAT_SLICE0__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
group.long 0x20++0xF
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_ctrl,The Control for Region a"
bitfld.long 0x0 31. "EN,Enable for the Region" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "SIZE,Size of the Region in Address Bits. 0 = 1 byte  1 = 2B  2 = 4B  3 = 8B  etc. up to 32 = 4GB."
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_base,The Base Address for Region a. This is the source address for matching to a region."
hexmask.long 0x4 0.--31. 1. "BASE,Base Address for the Region. It must be aligned to the programmed size."
line.long 0x8 "PR1_RAT_SLICE0__CFG__MMRS_trans_l,The Translated Lower Address Bits for Region a"
hexmask.long 0x8 0.--31. 1. "LOWER,Translated Lower Address Bits for the Region. It must be aligned to the programmed size."
line.long 0xC "PR1_RAT_SLICE0__CFG__MMRS_trans_u,The Translated Upper Address Bits for Region a"
hexmask.long.word 0xC 0.--15. 1. "UPPER,Translated Upper Address Bits for the Region"
tree.end
endif
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG0_RAT_SLICE1_CFG (PRU_ICSSG0_RAT_SLICE1_CFG)"
base ad:0x30009000
rgroup.long 0x0++0x7
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_config,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x3
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
group.long 0x820++0x3
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1"
bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1"
rgroup.long 0x824++0x17
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 4 = RAT."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 1 = Boundary crossing error."
line.long 0x8 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits."
line.long 0x10 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x840++0x13
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1"
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1"
line.long 0x8 "PR1_RAT_SLICE1__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1"
line.long 0xC "PR1_RAT_SLICE1__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1"
line.long 0x10 "PR1_RAT_SLICE1__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
group.long 0x20++0xF
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_ctrl,The Control for Region a"
bitfld.long 0x0 31. "EN,Enable for the Region" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "SIZE,Size of the Region in Address Bits. 0 = 1 byte  1 = 2B  2 = 4B  3 = 8B  etc. up to 32 = 4GB."
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_base,The Base Address for Region a. This is the source address for matching to a region."
hexmask.long 0x4 0.--31. 1. "BASE,Base Address for the Region. It must be aligned to the programmed size."
line.long 0x8 "PR1_RAT_SLICE1__CFG__MMRS_trans_l,The Translated Lower Address Bits for Region a"
hexmask.long 0x8 0.--31. 1. "LOWER,Translated Lower Address Bits for the Region. It must be aligned to the programmed size."
line.long 0xC "PR1_RAT_SLICE1__CFG__MMRS_trans_u,The Translated Upper Address Bits for Region a"
hexmask.long.word 0xC 0.--15. 1. "UPPER,Translated Upper Address Bits for the Region"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_RAT_SLICE0_CFG"
base ad:0x8000
rgroup.long 0x0++0x7
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_config,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x3
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
group.long 0x820++0x3
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1"
bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1"
rgroup.long 0x824++0x17
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 4 = RAT."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 1 = Boundary crossing error."
line.long 0x8 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits."
line.long 0x10 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x840++0x13
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1"
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1"
line.long 0x8 "PR1_RAT_SLICE0__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1"
line.long 0xC "PR1_RAT_SLICE0__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1"
line.long 0x10 "PR1_RAT_SLICE0__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
group.long 0x20++0xF
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_ctrl,The Control for Region a"
bitfld.long 0x0 31. "EN,Enable for the Region" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "SIZE,Size of the Region in Address Bits. 0 = 1 byte  1 = 2B  2 = 4B  3 = 8B  etc. up to 32 = 4GB."
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_base,The Base Address for Region a. This is the source address for matching to a region."
hexmask.long 0x4 0.--31. 1. "BASE,Base Address for the Region. It must be aligned to the programmed size."
line.long 0x8 "PR1_RAT_SLICE0__CFG__MMRS_trans_l,The Translated Lower Address Bits for Region a"
hexmask.long 0x8 0.--31. 1. "LOWER,Translated Lower Address Bits for the Region. It must be aligned to the programmed size."
line.long 0xC "PR1_RAT_SLICE0__CFG__MMRS_trans_u,The Translated Upper Address Bits for Region a"
hexmask.long.word 0xC 0.--15. 1. "UPPER,Translated Upper Address Bits for the Region"
tree.end
endif
sif (cpuis("AM243?-ICSS0")||cpuis("AM243?-ICSS0-RTU")||cpuis("AM243?-ICSS0-TX")||cpuis("AM243?-ICSS")||cpuis("AM243?-ICSS1-RTU")||cpuis("AM243?-ICSS1-TX"))
tree "PRU_ICSSG0_RAT_SLICE1_CFG"
base ad:0x9000
rgroup.long 0x0++0x7
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_config,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x3
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
group.long 0x820++0x3
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1"
bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1"
rgroup.long 0x824++0x17
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 4 = RAT."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 1 = Boundary crossing error."
line.long 0x8 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits."
line.long 0x10 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x840++0x13
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1"
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1"
line.long 0x8 "PR1_RAT_SLICE1__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1"
line.long 0xC "PR1_RAT_SLICE1__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1"
line.long 0x10 "PR1_RAT_SLICE1__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
group.long 0x20++0xF
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_ctrl,The Control for Region a"
bitfld.long 0x0 31. "EN,Enable for the Region" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "SIZE,Size of the Region in Address Bits. 0 = 1 byte  1 = 2B  2 = 4B  3 = 8B  etc. up to 32 = 4GB."
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_base,The Base Address for Region a. This is the source address for matching to a region."
hexmask.long 0x4 0.--31. 1. "BASE,Base Address for the Region. It must be aligned to the programmed size."
line.long 0x8 "PR1_RAT_SLICE1__CFG__MMRS_trans_l,The Translated Lower Address Bits for Region a"
hexmask.long 0x8 0.--31. 1. "LOWER,Translated Lower Address Bits for the Region. It must be aligned to the programmed size."
line.long 0xC "PR1_RAT_SLICE1__CFG__MMRS_trans_u,The Translated Upper Address Bits for Region a"
hexmask.long.word 0xC 0.--15. 1. "UPPER,Translated Upper Address Bits for the Region"
tree.end
endif
tree.end
tree.end
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PRU_ICSSG1"
base ad:0x0
tree "PRU_ICSSG1_DRAM0_SLV_RAM (PRU_ICSSG1_DRAM0_SLV_RAM)"
base ad:0x30080000
group.long 0x0++0x3
line.long 0x0 "DRAM0__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "PRU_ICSSG1_DRAM1_SLV_RAM (PRU_ICSSG1_DRAM1_SLV_RAM)"
base ad:0x30082000
group.long 0x0++0x3
line.long 0x0 "DRAM1__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "PRU_ICSSG1_ECC_AGGR (PRU_ICSSG1_ECC_AGGR)"
base ad:0x3F00B000
rgroup.long 0x0++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x7
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "BORG_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 8. "PR1_PDSP_TX1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x4 7. "PR1_PDSP_TX0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x4 6. "PR1_RTU1_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x4 5. "PR1_RTU0_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x4 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x4 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x4 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x4 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1"
bitfld.long 0x4 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 8. "PR1_PDSP_TX1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x0 7. "PR1_PDSP_TX0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x0 6. "PR1_RTU1_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x0 5. "PR1_RTU0_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x0 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 8. "PR1_PDSP_TX1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x0 7. "PR1_PDSP_TX0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x0 6. "PR1_RTU1_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x0 5. "PR1_RTU0_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x0 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1"
bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1"
bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "BORG_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 8. "PR1_PDSP_TX1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x4 7. "PR1_PDSP_TX0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x4 6. "PR1_RTU1_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x4 5. "PR1_RTU0_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x4 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x4 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x4 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x4 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1"
bitfld.long 0x4 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 8. "PR1_PDSP_TX1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x0 7. "PR1_PDSP_TX0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x0 6. "PR1_RTU1_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x0 5. "PR1_RTU0_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x0 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 8. "PR1_PDSP_TX1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x0 7. "PR1_PDSP_TX0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x0 6. "PR1_RTU1_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x0 5. "PR1_RTU0_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x0 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1"
bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1"
bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "BORG_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "BORG_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "BORG_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "BORG_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PRU_ICSSG1_IEP0 (PRU_ICSSG1_IEP0)"
base ad:0x300AE000
group.long 0x0++0x1B
line.long 0x0 "PR1_IEP0__SLV__REGS_global_cfg_reg,"
hexmask.long.word 0x0 8.--19. 1. "CMP_INC,"
hexmask.long.byte 0x0 4.--7. 1. "DEFAULT_INC,"
bitfld.long 0x0 0. "CNT_ENABLE," "0,1"
line.long 0x4 "PR1_IEP0__SLV__REGS_global_status_reg,"
bitfld.long 0x4 0. "CNT_OVF," "0,1"
line.long 0x8 "PR1_IEP0__SLV__REGS_compen_reg,"
hexmask.long.tbyte 0x8 0.--22. 1. "COMPEN_CNT,"
line.long 0xC "PR1_IEP0__SLV__REGS_slow_compen_reg,"
hexmask.long 0xC 0.--31. 1. "SLOW_COMPEN_CNT,"
line.long 0x10 "PR1_IEP0__SLV__REGS_count_reg0,"
hexmask.long 0x10 0.--31. 1. "COUNT_LO,"
line.long 0x14 "PR1_IEP0__SLV__REGS_count_reg1,"
hexmask.long 0x14 0.--31. 1. "COUNT_HI,"
line.long 0x18 "PR1_IEP0__SLV__REGS_cap_cfg_reg,"
hexmask.long.byte 0x18 18.--23. 1. "EXT_CAP_EN,"
hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN,"
hexmask.long.word 0x18 0.--9. 1. "CAP_EN,"
rgroup.long 0x1C++0x53
line.long 0x0 "PR1_IEP0__SLV__REGS_cap_status_reg,"
hexmask.long.byte 0x0 16.--23. 1. "CAP_RAW,"
hexmask.long.word 0x0 0.--10. 1. "CAP_VALID,"
line.long 0x4 "PR1_IEP0__SLV__REGS_capr0_reg0,"
hexmask.long 0x4 0.--31. 1. "CAPR0_0,"
line.long 0x8 "PR1_IEP0__SLV__REGS_capr0_reg1,"
hexmask.long 0x8 0.--31. 1. "CAPR0_1,"
line.long 0xC "PR1_IEP0__SLV__REGS_capr1_reg0,"
hexmask.long 0xC 0.--31. 1. "CAPR1_0,"
line.long 0x10 "PR1_IEP0__SLV__REGS_capr1_reg1,"
hexmask.long 0x10 0.--31. 1. "CAPR1_1,"
line.long 0x14 "PR1_IEP0__SLV__REGS_capr2_reg0,"
hexmask.long 0x14 0.--31. 1. "CAPR2_0,"
line.long 0x18 "PR1_IEP0__SLV__REGS_capr2_reg1,"
hexmask.long 0x18 0.--31. 1. "CAPR2_1,"
line.long 0x1C "PR1_IEP0__SLV__REGS_capr3_reg0,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_0,"
line.long 0x20 "PR1_IEP0__SLV__REGS_capr3_reg1,"
hexmask.long 0x20 0.--31. 1. "CAPR3_1,"
line.long 0x24 "PR1_IEP0__SLV__REGS_capr4_reg0,"
hexmask.long 0x24 0.--31. 1. "CAPR4_0,"
line.long 0x28 "PR1_IEP0__SLV__REGS_capr4_reg1,"
hexmask.long 0x28 0.--31. 1. "CAPR4_1,"
line.long 0x2C "PR1_IEP0__SLV__REGS_capr5_reg0,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_0,"
line.long 0x30 "PR1_IEP0__SLV__REGS_capr5_reg1,"
hexmask.long 0x30 0.--31. 1. "CAPR5_1,"
line.long 0x34 "PR1_IEP0__SLV__REGS_capr6_reg0,"
hexmask.long 0x34 0.--31. 1. "CAPR6_0,"
line.long 0x38 "PR1_IEP0__SLV__REGS_capr6_reg1,"
hexmask.long 0x38 0.--31. 1. "CAPR6_1,"
line.long 0x3C "PR1_IEP0__SLV__REGS_capf6_reg0,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_0,"
line.long 0x40 "PR1_IEP0__SLV__REGS_capf6_reg1,"
hexmask.long 0x40 0.--31. 1. "CAPF6_1,"
line.long 0x44 "PR1_IEP0__SLV__REGS_capr7_reg0,"
hexmask.long 0x44 0.--31. 1. "CAPR7_0,"
line.long 0x48 "PR1_IEP0__SLV__REGS_capr7_reg1,"
hexmask.long 0x48 0.--31. 1. "CAPR7_1,"
line.long 0x4C "PR1_IEP0__SLV__REGS_capf7_reg0,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_0,"
line.long 0x50 "PR1_IEP0__SLV__REGS_capf7_reg1,"
hexmask.long 0x50 0.--31. 1. "CAPF7_1,"
group.long 0x70++0x9B
line.long 0x0 "PR1_IEP0__SLV__REGS_cmp_cfg_reg,"
bitfld.long 0x0 17. "SHADOW_EN," "0,1"
hexmask.long.word 0x0 1.--16. 1. "CMP_EN,"
bitfld.long 0x0 0. "CMP0_RST_CNT_EN," "0,1"
line.long 0x4 "PR1_IEP0__SLV__REGS_cmp_status_reg,"
hexmask.long.word 0x4 0.--15. 1. "CMP_STATUS,"
line.long 0x8 "PR1_IEP0__SLV__REGS_cmp0_reg0,"
hexmask.long 0x8 0.--31. 1. "CMP0_0,"
line.long 0xC "PR1_IEP0__SLV__REGS_cmp0_reg1,"
hexmask.long 0xC 0.--31. 1. "CMP0_1,"
line.long 0x10 "PR1_IEP0__SLV__REGS_cmp1_reg0,"
hexmask.long 0x10 0.--31. 1. "CMP1_0,"
line.long 0x14 "PR1_IEP0__SLV__REGS_cmp1_reg1,"
hexmask.long 0x14 0.--31. 1. "CMP1_1,"
line.long 0x18 "PR1_IEP0__SLV__REGS_cmp2_reg0,"
hexmask.long 0x18 0.--31. 1. "CMP2_0,"
line.long 0x1C "PR1_IEP0__SLV__REGS_cmp2_reg1,"
hexmask.long 0x1C 0.--31. 1. "CMP2_1,"
line.long 0x20 "PR1_IEP0__SLV__REGS_cmp3_reg0,"
hexmask.long 0x20 0.--31. 1. "CMP3_0,"
line.long 0x24 "PR1_IEP0__SLV__REGS_cmp3_reg1,"
hexmask.long 0x24 0.--31. 1. "CMP3_1,"
line.long 0x28 "PR1_IEP0__SLV__REGS_cmp4_reg0,"
hexmask.long 0x28 0.--31. 1. "CMP4_0,"
line.long 0x2C "PR1_IEP0__SLV__REGS_cmp4_reg1,"
hexmask.long 0x2C 0.--31. 1. "CMP4_1,"
line.long 0x30 "PR1_IEP0__SLV__REGS_cmp5_reg0,"
hexmask.long 0x30 0.--31. 1. "CMP5_0,"
line.long 0x34 "PR1_IEP0__SLV__REGS_cmp5_reg1,"
hexmask.long 0x34 0.--31. 1. "CMP5_1,"
line.long 0x38 "PR1_IEP0__SLV__REGS_cmp6_reg0,"
hexmask.long 0x38 0.--31. 1. "CMP6_0,"
line.long 0x3C "PR1_IEP0__SLV__REGS_cmp6_reg1,"
hexmask.long 0x3C 0.--31. 1. "CMP6_1,"
line.long 0x40 "PR1_IEP0__SLV__REGS_cmp7_reg0,"
hexmask.long 0x40 0.--31. 1. "CMP7_0,"
line.long 0x44 "PR1_IEP0__SLV__REGS_cmp7_reg1,"
hexmask.long 0x44 0.--31. 1. "CMP7_1,"
line.long 0x48 "PR1_IEP0__SLV__REGS_rxipg0_reg,"
hexmask.long.word 0x48 16.--31. 1. "RX_MIN_IPG0,"
hexmask.long.word 0x48 0.--15. 1. "RX_IPG0,"
line.long 0x4C "PR1_IEP0__SLV__REGS_rxipg1_reg,"
hexmask.long.word 0x4C 16.--31. 1. "RX_MIN_IPG1,"
hexmask.long.word 0x4C 0.--15. 1. "RX_IPG1,"
line.long 0x50 "PR1_IEP0__SLV__REGS_cmp8_reg0,"
hexmask.long 0x50 0.--31. 1. "CMP8_0,"
line.long 0x54 "PR1_IEP0__SLV__REGS_cmp8_reg1,"
hexmask.long 0x54 0.--31. 1. "CMP8_1,"
line.long 0x58 "PR1_IEP0__SLV__REGS_cmp9_reg0,"
hexmask.long 0x58 0.--31. 1. "CMP9_0,"
line.long 0x5C "PR1_IEP0__SLV__REGS_cmp9_reg1,"
hexmask.long 0x5C 0.--31. 1. "CMP9_1,"
line.long 0x60 "PR1_IEP0__SLV__REGS_cmp10_reg0,"
hexmask.long 0x60 0.--31. 1. "CMP10_0,"
line.long 0x64 "PR1_IEP0__SLV__REGS_cmp10_reg1,"
hexmask.long 0x64 0.--31. 1. "CMP10_1,"
line.long 0x68 "PR1_IEP0__SLV__REGS_cmp11_reg0,"
hexmask.long 0x68 0.--31. 1. "CMP11_0,"
line.long 0x6C "PR1_IEP0__SLV__REGS_cmp11_reg1,"
hexmask.long 0x6C 0.--31. 1. "CMP11_1,"
line.long 0x70 "PR1_IEP0__SLV__REGS_cmp12_reg0,"
hexmask.long 0x70 0.--31. 1. "CMP12_0,"
line.long 0x74 "PR1_IEP0__SLV__REGS_cmp12_reg1,"
hexmask.long 0x74 0.--31. 1. "CMP12_1,"
line.long 0x78 "PR1_IEP0__SLV__REGS_cmp13_reg0,"
hexmask.long 0x78 0.--31. 1. "CMP13_0,"
line.long 0x7C "PR1_IEP0__SLV__REGS_cmp13_reg1,"
hexmask.long 0x7C 0.--31. 1. "CMP13_1,"
line.long 0x80 "PR1_IEP0__SLV__REGS_cmp14_reg0,"
hexmask.long 0x80 0.--31. 1. "CMP14_0,"
line.long 0x84 "PR1_IEP0__SLV__REGS_cmp14_reg1,"
hexmask.long 0x84 0.--31. 1. "CMP14_1,"
line.long 0x88 "PR1_IEP0__SLV__REGS_cmp15_reg0,"
hexmask.long 0x88 0.--31. 1. "CMP15_0,"
line.long 0x8C "PR1_IEP0__SLV__REGS_cmp15_reg1,"
hexmask.long 0x8C 0.--31. 1. "CMP15_1,"
line.long 0x90 "PR1_IEP0__SLV__REGS_count_reset_val_reg0,"
hexmask.long 0x90 0.--31. 1. "RESET_VAL_0,"
line.long 0x94 "PR1_IEP0__SLV__REGS_count_reset_val_reg1,"
hexmask.long 0x94 0.--31. 1. "RESET_VAL_1,"
line.long 0x98 "PR1_IEP0__SLV__REGS_pwm_reg,"
bitfld.long 0x98 3. "PWM3_HIT," "0,1"
bitfld.long 0x98 2. "PWM3_RST_CNT_EN," "0,1"
bitfld.long 0x98 1. "PWM0_HIT," "0,1"
bitfld.long 0x98 0. "PWM0_RST_CNT_EN," "0,1"
rgroup.long 0x10C++0x4F
line.long 0x0 "PR1_IEP0__SLV__REGS_capr0_bi_reg0,"
hexmask.long 0x0 0.--31. 1. "CAPR0_0,"
line.long 0x4 "PR1_IEP0__SLV__REGS_capr0_bi_reg1,"
hexmask.long 0x4 0.--31. 1. "CAPR0_1,"
line.long 0x8 "PR1_IEP0__SLV__REGS_capr1_bi_reg0,"
hexmask.long 0x8 0.--31. 1. "CAPR1_0,"
line.long 0xC "PR1_IEP0__SLV__REGS_capr1_bi_reg1,"
hexmask.long 0xC 0.--31. 1. "CAPR1_1,"
line.long 0x10 "PR1_IEP0__SLV__REGS_capr2_bi_reg0,"
hexmask.long 0x10 0.--31. 1. "CAPR2_0,"
line.long 0x14 "PR1_IEP0__SLV__REGS_capr2_bi_reg1,"
hexmask.long 0x14 0.--31. 1. "CAPR2_1,"
line.long 0x18 "PR1_IEP0__SLV__REGS_capr3_bi_reg0,"
hexmask.long 0x18 0.--31. 1. "CAPR3_0,"
line.long 0x1C "PR1_IEP0__SLV__REGS_capr3_bi_reg1,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_1,"
line.long 0x20 "PR1_IEP0__SLV__REGS_capr4_bi_reg0,"
hexmask.long 0x20 0.--31. 1. "CAPR4_0,"
line.long 0x24 "PR1_IEP0__SLV__REGS_capr4_bi_reg1,"
hexmask.long 0x24 0.--31. 1. "CAPR4_1,"
line.long 0x28 "PR1_IEP0__SLV__REGS_capr5_bi_reg0,"
hexmask.long 0x28 0.--31. 1. "CAPR5_0,"
line.long 0x2C "PR1_IEP0__SLV__REGS_capr5_bi_reg1,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_1,"
line.long 0x30 "PR1_IEP0__SLV__REGS_capr6_bi_reg0,"
hexmask.long 0x30 0.--31. 1. "CAPR6_0,"
line.long 0x34 "PR1_IEP0__SLV__REGS_capr6_bi_reg1,"
hexmask.long 0x34 0.--31. 1. "CAPR6_1,"
line.long 0x38 "PR1_IEP0__SLV__REGS_capf6_bi_reg0,"
hexmask.long 0x38 0.--31. 1. "CAPF6_0,"
line.long 0x3C "PR1_IEP0__SLV__REGS_capf6_bi_reg1,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_1,"
line.long 0x40 "PR1_IEP0__SLV__REGS_capr7_bi_reg0,"
hexmask.long 0x40 0.--31. 1. "CAPR7_0,"
line.long 0x44 "PR1_IEP0__SLV__REGS_capr7_bi_reg1,"
hexmask.long 0x44 0.--31. 1. "CAPR7_1,"
line.long 0x48 "PR1_IEP0__SLV__REGS_capf7_bi_reg0,"
hexmask.long 0x48 0.--31. 1. "CAPF7_0,"
line.long 0x4C "PR1_IEP0__SLV__REGS_capf7_bi_reg1,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_1,"
group.long 0x180++0x3
line.long 0x0 "PR1_IEP0__SLV__REGS_sync_ctrl_reg,"
bitfld.long 0x0 10. "SYNC1_OUT_NV_EN," "0,1"
bitfld.long 0x0 9. "SYNC0_OUT_NV_EN," "0,1"
bitfld.long 0x0 8. "SYNC1_IND_EN," "0,1"
bitfld.long 0x0 7. "SYNC1_CYCLIC_EN," "0,1"
newline
bitfld.long 0x0 6. "SYNC1_ACK_EN," "0,1"
bitfld.long 0x0 5. "SYNC0_CYCLIC_EN," "0,1"
bitfld.long 0x0 4. "SYNC0_ACK_EN," "0,1"
bitfld.long 0x0 2. "SYNC1_EN," "0,1"
newline
bitfld.long 0x0 1. "SYNC0_EN," "0,1"
bitfld.long 0x0 0. "SYNC_EN," "0,1"
rgroup.long 0x184++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_sync_first_stat_reg,"
bitfld.long 0x0 1. "FIRST_SYNC1," "0,1"
bitfld.long 0x0 0. "FIRST_SYNC0," "0,1"
line.long 0x4 "PR1_IEP0__SLV__REGS_sync0_stat_reg,"
bitfld.long 0x4 0. "SYNC0_PEND," "0,1"
line.long 0x8 "PR1_IEP0__SLV__REGS_sync1_stat_reg,"
bitfld.long 0x8 0. "SYNC1_PEND," "0,1"
group.long 0x190++0xF
line.long 0x0 "PR1_IEP0__SLV__REGS_sync_pwidth_reg,"
hexmask.long 0x0 0.--31. 1. "SYNC_HPW,"
line.long 0x4 "PR1_IEP0__SLV__REGS_sync0_period_reg,"
hexmask.long 0x4 0.--31. 1. "SYNC0_PERIOD,"
line.long 0x8 "PR1_IEP0__SLV__REGS_sync1_delay_reg,"
hexmask.long 0x8 0.--31. 1. "SYNC1_DELAY,"
line.long 0xC "PR1_IEP0__SLV__REGS_sync_start_reg,"
hexmask.long 0xC 0.--31. 1. "SYNC_START,"
group.long 0x200++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_wd_prediv_reg,"
hexmask.long.word 0x0 0.--15. 1. "PRE_DIV,"
line.long 0x4 "PR1_IEP0__SLV__REGS_pdi_wd_tim_reg,"
hexmask.long.word 0x4 0.--15. 1. "PDI_WD_TIME,"
line.long 0x8 "PR1_IEP0__SLV__REGS_pd_wd_tim_reg,"
hexmask.long.word 0x8 0.--15. 1. "PD_WD_TIME,"
rgroup.long 0x20C++0x3
line.long 0x0 "PR1_IEP0__SLV__REGS_wd_status_reg,"
bitfld.long 0x0 16. "PDI_WD_STAT," "0,1"
bitfld.long 0x0 0. "PD_WD_STAT," "0,1"
group.long 0x210++0x7
line.long 0x0 "PR1_IEP0__SLV__REGS_wd_exp_cnt_reg,"
hexmask.long.byte 0x0 8.--15. 1. "PD_EXP_CNT,"
hexmask.long.byte 0x0 0.--7. 1. "PDI_EXP_CNT,"
line.long 0x4 "PR1_IEP0__SLV__REGS_wd_ctrl_reg,"
bitfld.long 0x4 16. "PDI_WD_EN," "0,1"
bitfld.long 0x4 0. "PD_WD_EN," "0,1"
group.long 0x300++0x3
line.long 0x0 "PR1_IEP0__SLV__REGS_digio_ctrl_reg,"
bitfld.long 0x0 6.--7. "OUT_MODE," "0,1,2,3"
bitfld.long 0x0 4.--5. "IN_MODE," "0,1,2,3"
bitfld.long 0x0 3. "WD_MODE," "0,1"
rbitfld.long 0x0 2. "BIDI_MODE," "0,1"
newline
bitfld.long 0x0 1. "OUTVALID_MODE," "0,1"
rbitfld.long 0x0 0. "OUTVALID_POL," "0,1"
rgroup.long 0x304++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_digio_status_reg,"
hexmask.long 0x0 0.--31. 1. "DIGIO_STAT,"
line.long 0x4 "PR1_IEP0__SLV__REGS_digio_data_in_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_IN,"
line.long 0x8 "PR1_IEP0__SLV__REGS_digio_data_in_raw_reg,"
hexmask.long 0x8 0.--31. 1. "DATA_IN_RAW,"
group.long 0x310++0xB
line.long 0x0 "PR1_IEP0__SLV__REGS_digio_data_out_reg,"
hexmask.long 0x0 0.--31. 1. "DATA_OUT,"
line.long 0x4 "PR1_IEP0__SLV__REGS_digio_data_out_en_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_OUT_EN,"
line.long 0x8 "PR1_IEP0__SLV__REGS_digio_exp_reg,"
bitfld.long 0x8 13. "EOF_SEL," "0,1"
bitfld.long 0x8 12. "SOF_SEL," "0,1"
hexmask.long.byte 0x8 8.--11. 1. "SOF_DLY,"
hexmask.long.byte 0x8 4.--7. 1. "OUTVALID_DLY,"
newline
bitfld.long 0x8 2. "SW_OUTVALID," "0,1"
bitfld.long 0x8 1. "OUTVALID_OVR_EN," "0,1"
bitfld.long 0x8 0. "SW_DATA_OUT_UP," "0,1"
tree.end
tree "PRU_ICSSG1_IEP1 (PRU_ICSSG1_IEP1)"
base ad:0x300AF000
group.long 0x0++0x1B
line.long 0x0 "PR1_IEP1__SLV__REGS_global_cfg_reg,"
hexmask.long.word 0x0 8.--19. 1. "CMP_INC,"
hexmask.long.byte 0x0 4.--7. 1. "DEFAULT_INC,"
bitfld.long 0x0 0. "CNT_ENABLE," "0,1"
line.long 0x4 "PR1_IEP1__SLV__REGS_global_status_reg,"
bitfld.long 0x4 0. "CNT_OVF," "0,1"
line.long 0x8 "PR1_IEP1__SLV__REGS_compen_reg,"
hexmask.long.tbyte 0x8 0.--22. 1. "COMPEN_CNT,"
line.long 0xC "PR1_IEP1__SLV__REGS_slow_compen_reg,"
hexmask.long 0xC 0.--31. 1. "SLOW_COMPEN_CNT,"
line.long 0x10 "PR1_IEP1__SLV__REGS_count_reg0,"
hexmask.long 0x10 0.--31. 1. "COUNT_LO,"
line.long 0x14 "PR1_IEP1__SLV__REGS_count_reg1,"
hexmask.long 0x14 0.--31. 1. "COUNT_HI,"
line.long 0x18 "PR1_IEP1__SLV__REGS_cap_cfg_reg,"
hexmask.long.byte 0x18 18.--23. 1. "EXT_CAP_EN,"
hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN,"
hexmask.long.word 0x18 0.--9. 1. "CAP_EN,"
rgroup.long 0x1C++0x53
line.long 0x0 "PR1_IEP1__SLV__REGS_cap_status_reg,"
hexmask.long.byte 0x0 16.--23. 1. "CAP_RAW,"
hexmask.long.word 0x0 0.--10. 1. "CAP_VALID,"
line.long 0x4 "PR1_IEP1__SLV__REGS_capr0_reg0,"
hexmask.long 0x4 0.--31. 1. "CAPR0_0,"
line.long 0x8 "PR1_IEP1__SLV__REGS_capr0_reg1,"
hexmask.long 0x8 0.--31. 1. "CAPR0_1,"
line.long 0xC "PR1_IEP1__SLV__REGS_capr1_reg0,"
hexmask.long 0xC 0.--31. 1. "CAPR1_0,"
line.long 0x10 "PR1_IEP1__SLV__REGS_capr1_reg1,"
hexmask.long 0x10 0.--31. 1. "CAPR1_1,"
line.long 0x14 "PR1_IEP1__SLV__REGS_capr2_reg0,"
hexmask.long 0x14 0.--31. 1. "CAPR2_0,"
line.long 0x18 "PR1_IEP1__SLV__REGS_capr2_reg1,"
hexmask.long 0x18 0.--31. 1. "CAPR2_1,"
line.long 0x1C "PR1_IEP1__SLV__REGS_capr3_reg0,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_0,"
line.long 0x20 "PR1_IEP1__SLV__REGS_capr3_reg1,"
hexmask.long 0x20 0.--31. 1. "CAPR3_1,"
line.long 0x24 "PR1_IEP1__SLV__REGS_capr4_reg0,"
hexmask.long 0x24 0.--31. 1. "CAPR4_0,"
line.long 0x28 "PR1_IEP1__SLV__REGS_capr4_reg1,"
hexmask.long 0x28 0.--31. 1. "CAPR4_1,"
line.long 0x2C "PR1_IEP1__SLV__REGS_capr5_reg0,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_0,"
line.long 0x30 "PR1_IEP1__SLV__REGS_capr5_reg1,"
hexmask.long 0x30 0.--31. 1. "CAPR5_1,"
line.long 0x34 "PR1_IEP1__SLV__REGS_capr6_reg0,"
hexmask.long 0x34 0.--31. 1. "CAPR6_0,"
line.long 0x38 "PR1_IEP1__SLV__REGS_capr6_reg1,"
hexmask.long 0x38 0.--31. 1. "CAPR6_1,"
line.long 0x3C "PR1_IEP1__SLV__REGS_capf6_reg0,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_0,"
line.long 0x40 "PR1_IEP1__SLV__REGS_capf6_reg1,"
hexmask.long 0x40 0.--31. 1. "CAPF6_1,"
line.long 0x44 "PR1_IEP1__SLV__REGS_capr7_reg0,"
hexmask.long 0x44 0.--31. 1. "CAPR7_0,"
line.long 0x48 "PR1_IEP1__SLV__REGS_capr7_reg1,"
hexmask.long 0x48 0.--31. 1. "CAPR7_1,"
line.long 0x4C "PR1_IEP1__SLV__REGS_capf7_reg0,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_0,"
line.long 0x50 "PR1_IEP1__SLV__REGS_capf7_reg1,"
hexmask.long 0x50 0.--31. 1. "CAPF7_1,"
group.long 0x70++0x9B
line.long 0x0 "PR1_IEP1__SLV__REGS_cmp_cfg_reg,"
bitfld.long 0x0 17. "SHADOW_EN," "0,1"
hexmask.long.word 0x0 1.--16. 1. "CMP_EN,"
bitfld.long 0x0 0. "CMP0_RST_CNT_EN," "0,1"
line.long 0x4 "PR1_IEP1__SLV__REGS_cmp_status_reg,"
hexmask.long.word 0x4 0.--15. 1. "CMP_STATUS,"
line.long 0x8 "PR1_IEP1__SLV__REGS_cmp0_reg0,"
hexmask.long 0x8 0.--31. 1. "CMP0_0,"
line.long 0xC "PR1_IEP1__SLV__REGS_cmp0_reg1,"
hexmask.long 0xC 0.--31. 1. "CMP0_1,"
line.long 0x10 "PR1_IEP1__SLV__REGS_cmp1_reg0,"
hexmask.long 0x10 0.--31. 1. "CMP1_0,"
line.long 0x14 "PR1_IEP1__SLV__REGS_cmp1_reg1,"
hexmask.long 0x14 0.--31. 1. "CMP1_1,"
line.long 0x18 "PR1_IEP1__SLV__REGS_cmp2_reg0,"
hexmask.long 0x18 0.--31. 1. "CMP2_0,"
line.long 0x1C "PR1_IEP1__SLV__REGS_cmp2_reg1,"
hexmask.long 0x1C 0.--31. 1. "CMP2_1,"
line.long 0x20 "PR1_IEP1__SLV__REGS_cmp3_reg0,"
hexmask.long 0x20 0.--31. 1. "CMP3_0,"
line.long 0x24 "PR1_IEP1__SLV__REGS_cmp3_reg1,"
hexmask.long 0x24 0.--31. 1. "CMP3_1,"
line.long 0x28 "PR1_IEP1__SLV__REGS_cmp4_reg0,"
hexmask.long 0x28 0.--31. 1. "CMP4_0,"
line.long 0x2C "PR1_IEP1__SLV__REGS_cmp4_reg1,"
hexmask.long 0x2C 0.--31. 1. "CMP4_1,"
line.long 0x30 "PR1_IEP1__SLV__REGS_cmp5_reg0,"
hexmask.long 0x30 0.--31. 1. "CMP5_0,"
line.long 0x34 "PR1_IEP1__SLV__REGS_cmp5_reg1,"
hexmask.long 0x34 0.--31. 1. "CMP5_1,"
line.long 0x38 "PR1_IEP1__SLV__REGS_cmp6_reg0,"
hexmask.long 0x38 0.--31. 1. "CMP6_0,"
line.long 0x3C "PR1_IEP1__SLV__REGS_cmp6_reg1,"
hexmask.long 0x3C 0.--31. 1. "CMP6_1,"
line.long 0x40 "PR1_IEP1__SLV__REGS_cmp7_reg0,"
hexmask.long 0x40 0.--31. 1. "CMP7_0,"
line.long 0x44 "PR1_IEP1__SLV__REGS_cmp7_reg1,"
hexmask.long 0x44 0.--31. 1. "CMP7_1,"
line.long 0x48 "PR1_IEP1__SLV__REGS_rxipg0_reg,"
hexmask.long.word 0x48 16.--31. 1. "RX_MIN_IPG0,"
hexmask.long.word 0x48 0.--15. 1. "RX_IPG0,"
line.long 0x4C "PR1_IEP1__SLV__REGS_rxipg1_reg,"
hexmask.long.word 0x4C 16.--31. 1. "RX_MIN_IPG1,"
hexmask.long.word 0x4C 0.--15. 1. "RX_IPG1,"
line.long 0x50 "PR1_IEP1__SLV__REGS_cmp8_reg0,"
hexmask.long 0x50 0.--31. 1. "CMP8_0,"
line.long 0x54 "PR1_IEP1__SLV__REGS_cmp8_reg1,"
hexmask.long 0x54 0.--31. 1. "CMP8_1,"
line.long 0x58 "PR1_IEP1__SLV__REGS_cmp9_reg0,"
hexmask.long 0x58 0.--31. 1. "CMP9_0,"
line.long 0x5C "PR1_IEP1__SLV__REGS_cmp9_reg1,"
hexmask.long 0x5C 0.--31. 1. "CMP9_1,"
line.long 0x60 "PR1_IEP1__SLV__REGS_cmp10_reg0,"
hexmask.long 0x60 0.--31. 1. "CMP10_0,"
line.long 0x64 "PR1_IEP1__SLV__REGS_cmp10_reg1,"
hexmask.long 0x64 0.--31. 1. "CMP10_1,"
line.long 0x68 "PR1_IEP1__SLV__REGS_cmp11_reg0,"
hexmask.long 0x68 0.--31. 1. "CMP11_0,"
line.long 0x6C "PR1_IEP1__SLV__REGS_cmp11_reg1,"
hexmask.long 0x6C 0.--31. 1. "CMP11_1,"
line.long 0x70 "PR1_IEP1__SLV__REGS_cmp12_reg0,"
hexmask.long 0x70 0.--31. 1. "CMP12_0,"
line.long 0x74 "PR1_IEP1__SLV__REGS_cmp12_reg1,"
hexmask.long 0x74 0.--31. 1. "CMP12_1,"
line.long 0x78 "PR1_IEP1__SLV__REGS_cmp13_reg0,"
hexmask.long 0x78 0.--31. 1. "CMP13_0,"
line.long 0x7C "PR1_IEP1__SLV__REGS_cmp13_reg1,"
hexmask.long 0x7C 0.--31. 1. "CMP13_1,"
line.long 0x80 "PR1_IEP1__SLV__REGS_cmp14_reg0,"
hexmask.long 0x80 0.--31. 1. "CMP14_0,"
line.long 0x84 "PR1_IEP1__SLV__REGS_cmp14_reg1,"
hexmask.long 0x84 0.--31. 1. "CMP14_1,"
line.long 0x88 "PR1_IEP1__SLV__REGS_cmp15_reg0,"
hexmask.long 0x88 0.--31. 1. "CMP15_0,"
line.long 0x8C "PR1_IEP1__SLV__REGS_cmp15_reg1,"
hexmask.long 0x8C 0.--31. 1. "CMP15_1,"
line.long 0x90 "PR1_IEP1__SLV__REGS_count_reset_val_reg0,"
hexmask.long 0x90 0.--31. 1. "RESET_VAL_0,"
line.long 0x94 "PR1_IEP1__SLV__REGS_count_reset_val_reg1,"
hexmask.long 0x94 0.--31. 1. "RESET_VAL_1,"
line.long 0x98 "PR1_IEP1__SLV__REGS_pwm_reg,"
bitfld.long 0x98 3. "PWM3_HIT," "0,1"
bitfld.long 0x98 2. "PWM3_RST_CNT_EN," "0,1"
bitfld.long 0x98 1. "PWM0_HIT," "0,1"
bitfld.long 0x98 0. "PWM0_RST_CNT_EN," "0,1"
rgroup.long 0x10C++0x4F
line.long 0x0 "PR1_IEP1__SLV__REGS_capr0_bi_reg0,"
hexmask.long 0x0 0.--31. 1. "CAPR0_0,"
line.long 0x4 "PR1_IEP1__SLV__REGS_capr0_bi_reg1,"
hexmask.long 0x4 0.--31. 1. "CAPR0_1,"
line.long 0x8 "PR1_IEP1__SLV__REGS_capr1_bi_reg0,"
hexmask.long 0x8 0.--31. 1. "CAPR1_0,"
line.long 0xC "PR1_IEP1__SLV__REGS_capr1_bi_reg1,"
hexmask.long 0xC 0.--31. 1. "CAPR1_1,"
line.long 0x10 "PR1_IEP1__SLV__REGS_capr2_bi_reg0,"
hexmask.long 0x10 0.--31. 1. "CAPR2_0,"
line.long 0x14 "PR1_IEP1__SLV__REGS_capr2_bi_reg1,"
hexmask.long 0x14 0.--31. 1. "CAPR2_1,"
line.long 0x18 "PR1_IEP1__SLV__REGS_capr3_bi_reg0,"
hexmask.long 0x18 0.--31. 1. "CAPR3_0,"
line.long 0x1C "PR1_IEP1__SLV__REGS_capr3_bi_reg1,"
hexmask.long 0x1C 0.--31. 1. "CAPR3_1,"
line.long 0x20 "PR1_IEP1__SLV__REGS_capr4_bi_reg0,"
hexmask.long 0x20 0.--31. 1. "CAPR4_0,"
line.long 0x24 "PR1_IEP1__SLV__REGS_capr4_bi_reg1,"
hexmask.long 0x24 0.--31. 1. "CAPR4_1,"
line.long 0x28 "PR1_IEP1__SLV__REGS_capr5_bi_reg0,"
hexmask.long 0x28 0.--31. 1. "CAPR5_0,"
line.long 0x2C "PR1_IEP1__SLV__REGS_capr5_bi_reg1,"
hexmask.long 0x2C 0.--31. 1. "CAPR5_1,"
line.long 0x30 "PR1_IEP1__SLV__REGS_capr6_bi_reg0,"
hexmask.long 0x30 0.--31. 1. "CAPR6_0,"
line.long 0x34 "PR1_IEP1__SLV__REGS_capr6_bi_reg1,"
hexmask.long 0x34 0.--31. 1. "CAPR6_1,"
line.long 0x38 "PR1_IEP1__SLV__REGS_capf6_bi_reg0,"
hexmask.long 0x38 0.--31. 1. "CAPF6_0,"
line.long 0x3C "PR1_IEP1__SLV__REGS_capf6_bi_reg1,"
hexmask.long 0x3C 0.--31. 1. "CAPF6_1,"
line.long 0x40 "PR1_IEP1__SLV__REGS_capr7_bi_reg0,"
hexmask.long 0x40 0.--31. 1. "CAPR7_0,"
line.long 0x44 "PR1_IEP1__SLV__REGS_capr7_bi_reg1,"
hexmask.long 0x44 0.--31. 1. "CAPR7_1,"
line.long 0x48 "PR1_IEP1__SLV__REGS_capf7_bi_reg0,"
hexmask.long 0x48 0.--31. 1. "CAPF7_0,"
line.long 0x4C "PR1_IEP1__SLV__REGS_capf7_bi_reg1,"
hexmask.long 0x4C 0.--31. 1. "CAPF7_1,"
group.long 0x180++0x3
line.long 0x0 "PR1_IEP1__SLV__REGS_sync_ctrl_reg,"
bitfld.long 0x0 10. "SYNC1_OUT_NV_EN," "0,1"
bitfld.long 0x0 9. "SYNC0_OUT_NV_EN," "0,1"
bitfld.long 0x0 8. "SYNC1_IND_EN," "0,1"
bitfld.long 0x0 7. "SYNC1_CYCLIC_EN," "0,1"
newline
bitfld.long 0x0 6. "SYNC1_ACK_EN," "0,1"
bitfld.long 0x0 5. "SYNC0_CYCLIC_EN," "0,1"
bitfld.long 0x0 4. "SYNC0_ACK_EN," "0,1"
bitfld.long 0x0 2. "SYNC1_EN," "0,1"
newline
bitfld.long 0x0 1. "SYNC0_EN," "0,1"
bitfld.long 0x0 0. "SYNC_EN," "0,1"
rgroup.long 0x184++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_sync_first_stat_reg,"
bitfld.long 0x0 1. "FIRST_SYNC1," "0,1"
bitfld.long 0x0 0. "FIRST_SYNC0," "0,1"
line.long 0x4 "PR1_IEP1__SLV__REGS_sync0_stat_reg,"
bitfld.long 0x4 0. "SYNC0_PEND," "0,1"
line.long 0x8 "PR1_IEP1__SLV__REGS_sync1_stat_reg,"
bitfld.long 0x8 0. "SYNC1_PEND," "0,1"
group.long 0x190++0xF
line.long 0x0 "PR1_IEP1__SLV__REGS_sync_pwidth_reg,"
hexmask.long 0x0 0.--31. 1. "SYNC_HPW,"
line.long 0x4 "PR1_IEP1__SLV__REGS_sync0_period_reg,"
hexmask.long 0x4 0.--31. 1. "SYNC0_PERIOD,"
line.long 0x8 "PR1_IEP1__SLV__REGS_sync1_delay_reg,"
hexmask.long 0x8 0.--31. 1. "SYNC1_DELAY,"
line.long 0xC "PR1_IEP1__SLV__REGS_sync_start_reg,"
hexmask.long 0xC 0.--31. 1. "SYNC_START,"
group.long 0x200++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_wd_prediv_reg,"
hexmask.long.word 0x0 0.--15. 1. "PRE_DIV,"
line.long 0x4 "PR1_IEP1__SLV__REGS_pdi_wd_tim_reg,"
hexmask.long.word 0x4 0.--15. 1. "PDI_WD_TIME,"
line.long 0x8 "PR1_IEP1__SLV__REGS_pd_wd_tim_reg,"
hexmask.long.word 0x8 0.--15. 1. "PD_WD_TIME,"
rgroup.long 0x20C++0x3
line.long 0x0 "PR1_IEP1__SLV__REGS_wd_status_reg,"
bitfld.long 0x0 16. "PDI_WD_STAT," "0,1"
bitfld.long 0x0 0. "PD_WD_STAT," "0,1"
group.long 0x210++0x7
line.long 0x0 "PR1_IEP1__SLV__REGS_wd_exp_cnt_reg,"
hexmask.long.byte 0x0 8.--15. 1. "PD_EXP_CNT,"
hexmask.long.byte 0x0 0.--7. 1. "PDI_EXP_CNT,"
line.long 0x4 "PR1_IEP1__SLV__REGS_wd_ctrl_reg,"
bitfld.long 0x4 16. "PDI_WD_EN," "0,1"
bitfld.long 0x4 0. "PD_WD_EN," "0,1"
group.long 0x300++0x3
line.long 0x0 "PR1_IEP1__SLV__REGS_digio_ctrl_reg,"
bitfld.long 0x0 6.--7. "OUT_MODE," "0,1,2,3"
bitfld.long 0x0 4.--5. "IN_MODE," "0,1,2,3"
bitfld.long 0x0 3. "WD_MODE," "0,1"
rbitfld.long 0x0 2. "BIDI_MODE," "0,1"
newline
bitfld.long 0x0 1. "OUTVALID_MODE," "0,1"
rbitfld.long 0x0 0. "OUTVALID_POL," "0,1"
rgroup.long 0x304++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_digio_status_reg,"
hexmask.long 0x0 0.--31. 1. "DIGIO_STAT,"
line.long 0x4 "PR1_IEP1__SLV__REGS_digio_data_in_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_IN,"
line.long 0x8 "PR1_IEP1__SLV__REGS_digio_data_in_raw_reg,"
hexmask.long 0x8 0.--31. 1. "DATA_IN_RAW,"
group.long 0x310++0xB
line.long 0x0 "PR1_IEP1__SLV__REGS_digio_data_out_reg,"
hexmask.long 0x0 0.--31. 1. "DATA_OUT,"
line.long 0x4 "PR1_IEP1__SLV__REGS_digio_data_out_en_reg,"
hexmask.long 0x4 0.--31. 1. "DATA_OUT_EN,"
line.long 0x8 "PR1_IEP1__SLV__REGS_digio_exp_reg,"
bitfld.long 0x8 13. "EOF_SEL," "0,1"
bitfld.long 0x8 12. "SOF_SEL," "0,1"
hexmask.long.byte 0x8 8.--11. 1. "SOF_DLY,"
hexmask.long.byte 0x8 4.--7. 1. "OUTVALID_DLY,"
newline
bitfld.long 0x8 2. "SW_OUTVALID," "0,1"
bitfld.long 0x8 1. "OUTVALID_OVR_EN," "0,1"
bitfld.long 0x8 0. "SW_DATA_OUT_UP," "0,1"
tree.end
base ad:0x0
tree "PRU_ICSSG1_PA_STAT"
tree "PRU_ICSSG1_PA_STAT_WRAP_PA_SLV_CSTAT (PRU_ICSSG1_PA_STAT_WRAP_PA_SLV_CSTAT)"
base ad:0x300AC000
group.long 0x0++0x3
line.long 0x0 "PA_STAT_WRAP__PA_SLV__CSTAT_CRAM,query mode RAM"
hexmask.long 0x0 0.--31. 1. "VALUE,collect statistic"
tree.end
tree "PRU_ICSSG1_PA_STAT_WRAP_PA_SLV_QSTAT (PRU_ICSSG1_PA_STAT_WRAP_PA_SLV_QSTAT)"
base ad:0x300A7000
group.long 0x0++0x3
line.long 0x0 "PA_STAT_WRAP__PA_SLV__QSTAT_QRAM,query mode RAM"
hexmask.long 0x0 0.--31. 1. "VALUE,query statistic"
tree.end
tree.end
tree "PRU_ICSSG1_PR1"
tree "PRU_ICSSG1_PR1_CFG_SLV (PRU_ICSSG1_PR1_CFG_SLV)"
base ad:0x300A6000
rgroup.long 0x0++0x7
line.long 0x0 "PR1_CFG__SLV__REGS_pid_reg,"
hexmask.long 0x0 0.--31. 1. "ICSS_IDVER,Module ID field"
line.long 0x4 "PR1_CFG__SLV__REGS_hwdis_reg,"
hexmask.long.byte 0x4 0.--7. 1. "HWDIS,HW Disable Observation"
group.long 0x8++0x17
line.long 0x0 "PR1_CFG__SLV__REGS_gpcfg0_reg,"
hexmask.long.byte 0x0 26.--29. 1. "PR1_PRU0_GP_MUX_SEL,"
rbitfld.long 0x0 25. "PRU0_GPO_SH1_SEL," "0,1"
newline
hexmask.long.byte 0x0 20.--24. 1. "PRU0_GPO_DIV1,"
hexmask.long.byte 0x0 15.--19. 1. "PRU0_GPO_DIV0,"
newline
bitfld.long 0x0 14. "PRU0_GPO_MODE," "0,1"
bitfld.long 0x0 13. "PRU0_GPI_SB," "0,1"
newline
hexmask.long.byte 0x0 8.--12. 1. "PRU0_GPI_DIV1,"
hexmask.long.byte 0x0 3.--7. 1. "PRU0_GPI_DIV0,"
newline
bitfld.long 0x0 2. "PRU0_GPI_CLK_MODE," "0,1"
bitfld.long 0x0 0.--1. "PRU0_GPI_MODE," "0,1,2,3"
line.long 0x4 "PR1_CFG__SLV__REGS_gpcfg1_reg,"
hexmask.long.byte 0x4 26.--29. 1. "PR1_PRU1_GP_MUX_SEL,"
rbitfld.long 0x4 25. "PRU1_GPO_SH1_SEL," "0,1"
newline
hexmask.long.byte 0x4 20.--24. 1. "PRU1_GPO_DIV1,"
hexmask.long.byte 0x4 15.--19. 1. "PRU1_GPO_DIV0,"
newline
bitfld.long 0x4 14. "PRU1_GPO_MODE," "0,1"
bitfld.long 0x4 13. "PRU1_GPI_SB," "0,1"
newline
hexmask.long.byte 0x4 8.--12. 1. "PRU1_GPI_DIV1,"
hexmask.long.byte 0x4 3.--7. 1. "PRU1_GPI_DIV0,"
newline
bitfld.long 0x4 2. "PRU1_GPI_CLK_MODE," "0,1"
bitfld.long 0x4 0.--1. "PRU1_GPI_MODE," "0,1,2,3"
line.long 0x8 "PR1_CFG__SLV__REGS_cgr_reg,"
bitfld.long 0x8 31. "ICSS_STOP_ACK," "0,1"
rbitfld.long 0x8 30. "ICSS_STOP_REQ," "0,1"
newline
bitfld.long 0x8 29. "ICSS_PWR_IDLE," "0,1"
bitfld.long 0x8 21. "BOTTOM_HALF_CLK_GATE_EN," "0,1"
newline
bitfld.long 0x8 20. "TOP_HALF_CLK_GATE_EN," "0,1"
bitfld.long 0x8 19. "AUTO_SLICE1_CLK_GATE_EN," "0,1"
newline
bitfld.long 0x8 18. "AUTO_SLICE0_CLK_GATE_EN," "0,1"
bitfld.long 0x8 17. "IEP_CLK_EN," "0,1"
newline
rbitfld.long 0x8 16. "IEP_CLK_STOP_ACK," "0,1"
bitfld.long 0x8 15. "IEP_CLK_STOP_REQ," "0,1"
newline
bitfld.long 0x8 14. "ECAP_CLK_EN," "0,1"
rbitfld.long 0x8 13. "ECAP_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x8 12. "ECAP_CLK_STOP_REQ," "0,1"
bitfld.long 0x8 11. "UART_CLK_EN," "0,1"
newline
rbitfld.long 0x8 10. "UART_CLK_STOP_ACK," "0,1"
bitfld.long 0x8 9. "UART_CLK_STOP_REQ," "0,1"
newline
bitfld.long 0x8 8. "INTC_CLK_EN," "0,1"
rbitfld.long 0x8 7. "INTC_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x8 6. "INTC_CLK_STOP_REQ," "0,1"
line.long 0xC "PR1_CFG__SLV__REGS_gpecfg0_reg,"
bitfld.long 0xC 17. "PRU0_GPO_SHIFT_CLK_DONE," "0,1"
bitfld.long 0xC 16. "PRU0_GPO_SHIFT_CLK_HIGH," "0,1"
newline
hexmask.long.byte 0xC 8.--15. 1. "PRU0_GPO_SHIFT_CNT,"
bitfld.long 0xC 6. "PRU0_GPO_SHIFT_GP_EN," "0,1"
newline
bitfld.long 0xC 5. "PRU0_GPO_SHIFT_CLK_FREE," "0,1"
bitfld.long 0xC 4. "PRU0_GPO_SHIFT_SWAP," "0,1"
newline
bitfld.long 0xC 1. "PRU0_GPI_SHIFT_EN," "0,1"
bitfld.long 0xC 0. "PRU0_GPI_SB_P," "0,1"
line.long 0x10 "PR1_CFG__SLV__REGS_gpecfg1_reg,"
bitfld.long 0x10 17. "PRU1_GPO_SHIFT_CLK_DONE," "0,1"
bitfld.long 0x10 16. "PRU1_GPO_SHIFT_CLK_HIGH," "0,1"
newline
hexmask.long.byte 0x10 8.--15. 1. "PRU1_GPO_SHIFT_CNT,"
bitfld.long 0x10 6. "PRU1_GPO_SHIFT_GP_EN," "0,1"
newline
bitfld.long 0x10 5. "PRU1_GPO_SHIFT_CLK_FREE," "0,1"
bitfld.long 0x10 4. "PRU1_GPO_SHIFT_SWAP," "0,1"
newline
bitfld.long 0x10 1. "PRU1_GPI_SHIFT_EN," "0,1"
bitfld.long 0x10 0. "PRU1_GPI_SB_P," "0,1"
line.long 0x14 "PR1_CFG__SLV__REGS_reset_iso_reg,"
bitfld.long 0x14 2. "RESET_ISO_EDGE," "0,1"
bitfld.long 0x14 1. "RESET_ISO_ACK," "0,1"
newline
bitfld.long 0x14 0. "RESET_ISO_REQ," "0,1"
group.long 0x2C++0xB
line.long 0x0 "PR1_CFG__SLV__REGS_mii_rt_reg,"
bitfld.long 0x0 0. "MII_RT_EVENT_EN," "0,1"
line.long 0x4 "PR1_CFG__SLV__REGS_iepclk_reg,"
bitfld.long 0x4 1. "IEP1_SLV_EN," "0,1"
bitfld.long 0x4 0. "IEP_OCP_CLK_EN," "0,1"
line.long 0x8 "PR1_CFG__SLV__REGS_spp_reg,"
bitfld.long 0x8 3. "RTU_XFR_SHIFT_EN," "0,1"
bitfld.long 0x8 2. "XFR_BYTE_SHIFT_EN," "0,1"
newline
bitfld.long 0x8 1. "XFR_SHIFT_EN," "0,1"
bitfld.long 0x8 0. "PRU1_PAD_HP_EN," "0,1"
group.long 0x3C++0x9F
line.long 0x0 "PR1_CFG__SLV__REGS_core_sync_reg,"
bitfld.long 0x0 0. "CORE_VBUSP_SYNC_EN," "0,1"
line.long 0x4 "PR1_CFG__SLV__REGS_sa_mx_reg,"
bitfld.long 0x4 16. "PWM_EFC_EN," "0,1"
bitfld.long 0x4 10.--11. "PWM3_REMAP_EN," "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "PWM0_REMAP_EN," "0,1,2,3"
hexmask.long.byte 0x4 0.--7. 1. "SA_MUX_SEL,"
line.long 0x8 "PR1_CFG__SLV__REGS_pru0_sd_clk_div_reg,"
hexmask.long.byte 0x8 24.--31. 1. "PRU0_SD_MAN_REC_CLK_PERIOD,"
rbitfld.long 0x8 16. "PRU0_SD_MAN_CLK_CAL_DONE," "0,1"
newline
rbitfld.long 0x8 15. "PRU0_SD_MAN_STATUS," "0,1"
hexmask.long.byte 0x8 11.--14. 1. "PRU0_SD_CH_SEL,"
newline
bitfld.long 0x8 10. "PRU0_SD_MAN_NV_DATA_EN," "0,1"
bitfld.long 0x8 9. "PRU0_SD_MAN_EN," "0,1"
newline
bitfld.long 0x8 8. "PRU0_SD_SHARE_EN," "0,1"
line.long 0xC "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg0,"
bitfld.long 0xC 22. "PRU0_FD_ZERO_MAX_0," "0,1"
hexmask.long.byte 0xC 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_0,"
newline
bitfld.long 0xC 16. "PRU0_FD_ZERO_MIN_0," "0,1"
hexmask.long.byte 0xC 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_0,"
newline
bitfld.long 0xC 4.--5. "PRU0_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0xC 2. "PRU0_SD_CLK_INV0," "0,1"
newline
bitfld.long 0xC 0.--1. "PRU0_SD_CLK_SEL0," "0,1,2,3"
line.long 0x10 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg0,"
bitfld.long 0x10 23. "PRU0_FD_EN_0," "0,1"
bitfld.long 0x10 22. "PRU0_FD_ONE_MAX_0," "0,1"
newline
hexmask.long.byte 0x10 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_0,"
bitfld.long 0x10 16. "PRU0_FD_ONE_MIN_0," "0,1"
newline
hexmask.long.byte 0x10 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_0,"
bitfld.long 0x10 8.--10. "PRU0_FD_WINDOW_SIZE_0," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 0.--7. 1. "PRU0_SD_SAMPLE_SIZE0,"
line.long 0x14 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg1,"
bitfld.long 0x14 22. "PRU0_FD_ZERO_MAX_1," "0,1"
hexmask.long.byte 0x14 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_1,"
newline
bitfld.long 0x14 16. "PRU0_FD_ZERO_MIN_1," "0,1"
hexmask.long.byte 0x14 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_1,"
newline
bitfld.long 0x14 4.--5. "PRU0_SD_ACC_SEL1," "0,1,2,3"
bitfld.long 0x14 2. "PRU0_SD_CLK_INV1," "0,1"
newline
bitfld.long 0x14 0.--1. "PRU0_SD_CLK_SEL1," "0,1,2,3"
line.long 0x18 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg1,"
bitfld.long 0x18 23. "PRU0_FD_EN_1," "0,1"
bitfld.long 0x18 22. "PRU0_FD_ONE_MAX_1," "0,1"
newline
hexmask.long.byte 0x18 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_1,"
bitfld.long 0x18 16. "PRU0_FD_ONE_MIN_1," "0,1"
newline
hexmask.long.byte 0x18 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_1,"
bitfld.long 0x18 8.--10. "PRU0_FD_WINDOW_SIZE_1," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x18 0.--7. 1. "PRU0_SD_SAMPLE_SIZE1,"
line.long 0x1C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg2,"
bitfld.long 0x1C 22. "PRU0_FD_ZERO_MAX_2," "0,1"
hexmask.long.byte 0x1C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_2,"
newline
bitfld.long 0x1C 16. "PRU0_FD_ZERO_MIN_2," "0,1"
hexmask.long.byte 0x1C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_2,"
newline
bitfld.long 0x1C 4.--5. "PRU0_SD_ACC_SEL2," "0,1,2,3"
bitfld.long 0x1C 2. "PRU0_SD_CLK_INV2," "0,1"
newline
bitfld.long 0x1C 0.--1. "PRU0_SD_CLK_SEL2," "0,1,2,3"
line.long 0x20 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg2,"
bitfld.long 0x20 23. "PRU0_FD_EN_2," "0,1"
bitfld.long 0x20 22. "PRU0_FD_ONE_MAX_2," "0,1"
newline
hexmask.long.byte 0x20 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_2,"
bitfld.long 0x20 16. "PRU0_FD_ONE_MIN_2," "0,1"
newline
hexmask.long.byte 0x20 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_2,"
bitfld.long 0x20 8.--10. "PRU0_FD_WINDOW_SIZE_2," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x20 0.--7. 1. "PRU0_SD_SAMPLE_SIZE2,"
line.long 0x24 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg3,"
bitfld.long 0x24 22. "PRU0_FD_ZERO_MAX_3," "0,1"
hexmask.long.byte 0x24 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_3,"
newline
bitfld.long 0x24 16. "PRU0_FD_ZERO_MIN_3," "0,1"
hexmask.long.byte 0x24 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_3,"
newline
bitfld.long 0x24 4.--5. "PRU0_SD_ACC_SEL3," "0,1,2,3"
bitfld.long 0x24 2. "PRU0_SD_CLK_INV3," "0,1"
newline
bitfld.long 0x24 0.--1. "PRU0_SD_CLK_SEL3," "0,1,2,3"
line.long 0x28 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg3,"
bitfld.long 0x28 23. "PRU0_FD_EN_3," "0,1"
bitfld.long 0x28 22. "PRU0_FD_ONE_MAX_3," "0,1"
newline
hexmask.long.byte 0x28 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_3,"
bitfld.long 0x28 16. "PRU0_FD_ONE_MIN_3," "0,1"
newline
hexmask.long.byte 0x28 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_3,"
bitfld.long 0x28 8.--10. "PRU0_FD_WINDOW_SIZE_3," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 0.--7. 1. "PRU0_SD_SAMPLE_SIZE3,"
line.long 0x2C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg4,"
bitfld.long 0x2C 22. "PRU0_FD_ZERO_MAX_4," "0,1"
hexmask.long.byte 0x2C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_4,"
newline
bitfld.long 0x2C 16. "PRU0_FD_ZERO_MIN_4," "0,1"
hexmask.long.byte 0x2C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_4,"
newline
bitfld.long 0x2C 4.--5. "PRU0_SD_ACC_SEL4," "0,1,2,3"
bitfld.long 0x2C 2. "PRU0_SD_CLK_INV4," "0,1"
newline
bitfld.long 0x2C 0.--1. "PRU0_SD_CLK_SEL4," "0,1,2,3"
line.long 0x30 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg4,"
bitfld.long 0x30 23. "PRU0_FD_EN_4," "0,1"
bitfld.long 0x30 22. "PRU0_FD_ONE_MAX_4," "0,1"
newline
hexmask.long.byte 0x30 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_4,"
bitfld.long 0x30 16. "PRU0_FD_ONE_MIN_4," "0,1"
newline
hexmask.long.byte 0x30 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_4,"
bitfld.long 0x30 8.--10. "PRU0_FD_WINDOW_SIZE_4," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x30 0.--7. 1. "PRU0_SD_SAMPLE_SIZE4,"
line.long 0x34 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg5,"
bitfld.long 0x34 22. "PRU0_FD_ZERO_MAX_5," "0,1"
hexmask.long.byte 0x34 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_5,"
newline
bitfld.long 0x34 16. "PRU0_FD_ZERO_MIN_5," "0,1"
hexmask.long.byte 0x34 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_5,"
newline
bitfld.long 0x34 4.--5. "PRU0_SD_ACC_SEL5," "0,1,2,3"
bitfld.long 0x34 2. "PRU0_SD_CLK_INV5," "0,1"
newline
bitfld.long 0x34 0.--1. "PRU0_SD_CLK_SEL5," "0,1,2,3"
line.long 0x38 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg5,"
bitfld.long 0x38 23. "PRU0_FD_EN_5," "0,1"
bitfld.long 0x38 22. "PRU0_FD_ONE_MAX_5," "0,1"
newline
hexmask.long.byte 0x38 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_5,"
bitfld.long 0x38 16. "PRU0_FD_ONE_MIN_5," "0,1"
newline
hexmask.long.byte 0x38 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_5,"
bitfld.long 0x38 8.--10. "PRU0_FD_WINDOW_SIZE_5," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x38 0.--7. 1. "PRU0_SD_SAMPLE_SIZE5,"
line.long 0x3C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg6,"
bitfld.long 0x3C 22. "PRU0_FD_ZERO_MAX_6," "0,1"
hexmask.long.byte 0x3C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_6,"
newline
bitfld.long 0x3C 16. "PRU0_FD_ZERO_MIN_6," "0,1"
hexmask.long.byte 0x3C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_6,"
newline
bitfld.long 0x3C 4.--5. "PRU0_SD_ACC_SEL6," "0,1,2,3"
bitfld.long 0x3C 2. "PRU0_SD_CLK_INV6," "0,1"
newline
bitfld.long 0x3C 0.--1. "PRU0_SD_CLK_SEL6," "0,1,2,3"
line.long 0x40 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg6,"
bitfld.long 0x40 23. "PRU0_FD_EN_6," "0,1"
bitfld.long 0x40 22. "PRU0_FD_ONE_MAX_6," "0,1"
newline
hexmask.long.byte 0x40 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_6,"
bitfld.long 0x40 16. "PRU0_FD_ONE_MIN_6," "0,1"
newline
hexmask.long.byte 0x40 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_6,"
bitfld.long 0x40 8.--10. "PRU0_FD_WINDOW_SIZE_6," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x40 0.--7. 1. "PRU0_SD_SAMPLE_SIZE6,"
line.long 0x44 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg7,"
bitfld.long 0x44 22. "PRU0_FD_ZERO_MAX_7," "0,1"
hexmask.long.byte 0x44 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_7,"
newline
bitfld.long 0x44 16. "PRU0_FD_ZERO_MIN_7," "0,1"
hexmask.long.byte 0x44 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_7,"
newline
bitfld.long 0x44 4.--5. "PRU0_SD_ACC_SEL7," "0,1,2,3"
bitfld.long 0x44 2. "PRU0_SD_CLK_INV7," "0,1"
newline
bitfld.long 0x44 0.--1. "PRU0_SD_CLK_SEL7," "0,1,2,3"
line.long 0x48 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg7,"
bitfld.long 0x48 23. "PRU0_FD_EN_7," "0,1"
bitfld.long 0x48 22. "PRU0_FD_ONE_MAX_7," "0,1"
newline
hexmask.long.byte 0x48 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_7,"
bitfld.long 0x48 16. "PRU0_FD_ONE_MIN_7," "0,1"
newline
hexmask.long.byte 0x48 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_7,"
bitfld.long 0x48 8.--10. "PRU0_FD_WINDOW_SIZE_7," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x48 0.--7. 1. "PRU0_SD_SAMPLE_SIZE7,"
line.long 0x4C "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg8,"
bitfld.long 0x4C 22. "PRU0_FD_ZERO_MAX_8," "0,1"
hexmask.long.byte 0x4C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_8,"
newline
bitfld.long 0x4C 16. "PRU0_FD_ZERO_MIN_8," "0,1"
hexmask.long.byte 0x4C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_8,"
newline
bitfld.long 0x4C 4.--5. "PRU0_SD_ACC_SEL8," "0,1,2,3"
bitfld.long 0x4C 2. "PRU0_SD_CLK_INV8," "0,1"
newline
bitfld.long 0x4C 0.--1. "PRU0_SD_CLK_SEL8," "0,1,2,3"
line.long 0x50 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg8,"
bitfld.long 0x50 23. "PRU0_FD_EN_8," "0,1"
bitfld.long 0x50 22. "PRU0_FD_ONE_MAX_8," "0,1"
newline
hexmask.long.byte 0x50 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_8,"
bitfld.long 0x50 16. "PRU0_FD_ONE_MIN_8," "0,1"
newline
hexmask.long.byte 0x50 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_8,"
bitfld.long 0x50 8.--10. "PRU0_FD_WINDOW_SIZE_8," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x50 0.--7. 1. "PRU0_SD_SAMPLE_SIZE8,"
line.long 0x54 "PR1_CFG__SLV__REGS_pru1_sd_clk_div_reg,"
hexmask.long.byte 0x54 24.--31. 1. "PRU1_SD_MAN_REC_CLK_PERIOD,"
rbitfld.long 0x54 16. "PRU1_SD_MAN_CLK_CAL_DONE," "0,1"
newline
rbitfld.long 0x54 15. "PRU1_SD_MAN_STATUS," "0,1"
hexmask.long.byte 0x54 11.--14. 1. "PRU1_SD_CH_SEL,"
newline
bitfld.long 0x54 10. "PRU1_SD_MAN_NV_DATA_EN," "0,1"
bitfld.long 0x54 9. "PRU1_SD_MAN_EN," "0,1"
newline
bitfld.long 0x54 8. "PRU1_SD_SHARE_EN," "0,1"
line.long 0x58 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg0,"
bitfld.long 0x58 22. "PRU1_FD_ZERO_MAX_0," "0,1"
hexmask.long.byte 0x58 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_0,"
newline
bitfld.long 0x58 16. "PRU1_FD_ZERO_MIN_0," "0,1"
hexmask.long.byte 0x58 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_0,"
newline
bitfld.long 0x58 4.--5. "PRU1_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x58 2. "PRU1_SD_CLK_INV0," "0,1"
newline
bitfld.long 0x58 0.--1. "PRU1_SD_CLK_SEL0," "0,1,2,3"
line.long 0x5C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg0,"
bitfld.long 0x5C 23. "PRU1_FD_EN_0," "0,1"
bitfld.long 0x5C 22. "PRU1_FD_ONE_MAX_0," "0,1"
newline
hexmask.long.byte 0x5C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_0,"
bitfld.long 0x5C 16. "PRU1_FD_ONE_MIN_0," "0,1"
newline
hexmask.long.byte 0x5C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_0,"
bitfld.long 0x5C 8.--10. "PRU1_FD_WINDOW_SIZE_0," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x5C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE0,"
line.long 0x60 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg1,"
bitfld.long 0x60 22. "PRU1_FD_ZERO_MAX_1," "0,1"
hexmask.long.byte 0x60 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_1,"
newline
bitfld.long 0x60 16. "PRU1_FD_ZERO_MIN_1," "0,1"
hexmask.long.byte 0x60 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_1,"
newline
bitfld.long 0x60 4.--5. "PRU1_SD_ACC_SEL1," "0,1,2,3"
bitfld.long 0x60 2. "PRU1_SD_CLK_INV1," "0,1"
newline
bitfld.long 0x60 0.--1. "PRU1_SD_CLK_SEL1," "0,1,2,3"
line.long 0x64 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg1,"
bitfld.long 0x64 23. "PRU1_FD_EN_1," "0,1"
bitfld.long 0x64 22. "PRU1_FD_ONE_MAX_1," "0,1"
newline
hexmask.long.byte 0x64 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_1,"
bitfld.long 0x64 16. "PRU1_FD_ONE_MIN_1," "0,1"
newline
hexmask.long.byte 0x64 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_1,"
bitfld.long 0x64 8.--10. "PRU1_FD_WINDOW_SIZE_1," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x64 0.--7. 1. "PRU1_SD_SAMPLE_SIZE1,"
line.long 0x68 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg2,"
bitfld.long 0x68 22. "PRU1_FD_ZERO_MAX_2," "0,1"
hexmask.long.byte 0x68 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_2,"
newline
bitfld.long 0x68 16. "PRU1_FD_ZERO_MIN_2," "0,1"
hexmask.long.byte 0x68 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_2,"
newline
bitfld.long 0x68 4.--5. "PRU1_SD_ACC_SEL2," "0,1,2,3"
bitfld.long 0x68 2. "PRU1_SD_CLK_INV2," "0,1"
newline
bitfld.long 0x68 0.--1. "PRU1_SD_CLK_SEL2," "0,1,2,3"
line.long 0x6C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg2,"
bitfld.long 0x6C 23. "PRU1_FD_EN_2," "0,1"
bitfld.long 0x6C 22. "PRU1_FD_ONE_MAX_2," "0,1"
newline
hexmask.long.byte 0x6C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_2,"
bitfld.long 0x6C 16. "PRU1_FD_ONE_MIN_2," "0,1"
newline
hexmask.long.byte 0x6C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_2,"
bitfld.long 0x6C 8.--10. "PRU1_FD_WINDOW_SIZE_2," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x6C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE2,"
line.long 0x70 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg3,"
bitfld.long 0x70 22. "PRU1_FD_ZERO_MAX_3," "0,1"
hexmask.long.byte 0x70 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_3,"
newline
bitfld.long 0x70 16. "PRU1_FD_ZERO_MIN_3," "0,1"
hexmask.long.byte 0x70 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_3,"
newline
bitfld.long 0x70 4.--5. "PRU1_SD_ACC_SEL3," "0,1,2,3"
bitfld.long 0x70 2. "PRU1_SD_CLK_INV3," "0,1"
newline
bitfld.long 0x70 0.--1. "PRU1_SD_CLK_SEL3," "0,1,2,3"
line.long 0x74 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg3,"
bitfld.long 0x74 23. "PRU1_FD_EN_3," "0,1"
bitfld.long 0x74 22. "PRU1_FD_ONE_MAX_3," "0,1"
newline
hexmask.long.byte 0x74 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_3,"
bitfld.long 0x74 16. "PRU1_FD_ONE_MIN_3," "0,1"
newline
hexmask.long.byte 0x74 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_3,"
bitfld.long 0x74 8.--10. "PRU1_FD_WINDOW_SIZE_3," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x74 0.--7. 1. "PRU1_SD_SAMPLE_SIZE3,"
line.long 0x78 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg4,"
bitfld.long 0x78 22. "PRU1_FD_ZERO_MAX_4," "0,1"
hexmask.long.byte 0x78 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_4,"
newline
bitfld.long 0x78 16. "PRU1_FD_ZERO_MIN_4," "0,1"
hexmask.long.byte 0x78 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_4,"
newline
bitfld.long 0x78 4.--5. "PRU1_SD_ACC_SEL4," "0,1,2,3"
bitfld.long 0x78 2. "PRU1_SD_CLK_INV4," "0,1"
newline
bitfld.long 0x78 0.--1. "PRU1_SD_CLK_SEL4," "0,1,2,3"
line.long 0x7C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg4,"
bitfld.long 0x7C 23. "PRU1_FD_EN_4," "0,1"
bitfld.long 0x7C 22. "PRU1_FD_ONE_MAX_4," "0,1"
newline
hexmask.long.byte 0x7C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_4,"
bitfld.long 0x7C 16. "PRU1_FD_ONE_MIN_4," "0,1"
newline
hexmask.long.byte 0x7C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_4,"
bitfld.long 0x7C 8.--10. "PRU1_FD_WINDOW_SIZE_4," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x7C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE4,"
line.long 0x80 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg5,"
bitfld.long 0x80 22. "PRU1_FD_ZERO_MAX_5," "0,1"
hexmask.long.byte 0x80 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_5,"
newline
bitfld.long 0x80 16. "PRU1_FD_ZERO_MIN_5," "0,1"
hexmask.long.byte 0x80 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_5,"
newline
bitfld.long 0x80 4.--5. "PRU1_SD_ACC_SEL5," "0,1,2,3"
bitfld.long 0x80 2. "PRU1_SD_CLK_INV5," "0,1"
newline
bitfld.long 0x80 0.--1. "PRU1_SD_CLK_SEL5," "0,1,2,3"
line.long 0x84 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg5,"
bitfld.long 0x84 23. "PRU1_FD_EN_5," "0,1"
bitfld.long 0x84 22. "PRU1_FD_ONE_MAX_5," "0,1"
newline
hexmask.long.byte 0x84 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_5,"
bitfld.long 0x84 16. "PRU1_FD_ONE_MIN_5," "0,1"
newline
hexmask.long.byte 0x84 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_5,"
bitfld.long 0x84 8.--10. "PRU1_FD_WINDOW_SIZE_5," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x84 0.--7. 1. "PRU1_SD_SAMPLE_SIZE5,"
line.long 0x88 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg6,"
bitfld.long 0x88 22. "PRU1_FD_ZERO_MAX_6," "0,1"
hexmask.long.byte 0x88 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_6,"
newline
bitfld.long 0x88 16. "PRU1_FD_ZERO_MIN_6," "0,1"
hexmask.long.byte 0x88 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_6,"
newline
bitfld.long 0x88 4.--5. "PRU1_SD_ACC_SEL6," "0,1,2,3"
bitfld.long 0x88 2. "PRU1_SD_CLK_INV6," "0,1"
newline
bitfld.long 0x88 0.--1. "PRU1_SD_CLK_SEL6," "0,1,2,3"
line.long 0x8C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg6,"
bitfld.long 0x8C 23. "PRU1_FD_EN_6," "0,1"
bitfld.long 0x8C 22. "PRU1_FD_ONE_MAX_6," "0,1"
newline
hexmask.long.byte 0x8C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_6,"
bitfld.long 0x8C 16. "PRU1_FD_ONE_MIN_6," "0,1"
newline
hexmask.long.byte 0x8C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_6,"
bitfld.long 0x8C 8.--10. "PRU1_FD_WINDOW_SIZE_6," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE6,"
line.long 0x90 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg7,"
bitfld.long 0x90 22. "PRU1_FD_ZERO_MAX_7," "0,1"
hexmask.long.byte 0x90 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_7,"
newline
bitfld.long 0x90 16. "PRU1_FD_ZERO_MIN_7," "0,1"
hexmask.long.byte 0x90 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_7,"
newline
bitfld.long 0x90 4.--5. "PRU1_SD_ACC_SEL7," "0,1,2,3"
bitfld.long 0x90 2. "PRU1_SD_CLK_INV7," "0,1"
newline
bitfld.long 0x90 0.--1. "PRU1_SD_CLK_SEL7," "0,1,2,3"
line.long 0x94 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg7,"
bitfld.long 0x94 23. "PRU1_FD_EN_7," "0,1"
bitfld.long 0x94 22. "PRU1_FD_ONE_MAX_7," "0,1"
newline
hexmask.long.byte 0x94 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_7,"
bitfld.long 0x94 16. "PRU1_FD_ONE_MIN_7," "0,1"
newline
hexmask.long.byte 0x94 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_7,"
bitfld.long 0x94 8.--10. "PRU1_FD_WINDOW_SIZE_7," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x94 0.--7. 1. "PRU1_SD_SAMPLE_SIZE7,"
line.long 0x98 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg8,"
bitfld.long 0x98 22. "PRU1_FD_ZERO_MAX_8," "0,1"
hexmask.long.byte 0x98 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_8,"
newline
bitfld.long 0x98 16. "PRU1_FD_ZERO_MIN_8," "0,1"
hexmask.long.byte 0x98 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_8,"
newline
bitfld.long 0x98 4.--5. "PRU1_SD_ACC_SEL8," "0,1,2,3"
bitfld.long 0x98 2. "PRU1_SD_CLK_INV8," "0,1"
newline
bitfld.long 0x98 0.--1. "PRU1_SD_CLK_SEL8," "0,1,2,3"
line.long 0x9C "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg8,"
bitfld.long 0x9C 23. "PRU1_FD_EN_8," "0,1"
bitfld.long 0x9C 22. "PRU1_FD_ONE_MAX_8," "0,1"
newline
hexmask.long.byte 0x9C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_8,"
bitfld.long 0x9C 16. "PRU1_FD_ONE_MIN_8," "0,1"
newline
hexmask.long.byte 0x9C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_8,"
bitfld.long 0x9C 8.--10. "PRU1_FD_WINDOW_SIZE_8," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x9C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE8,"
group.long 0xE0++0x3F
line.long 0x0 "PR1_CFG__SLV__REGS_pru0_ed_rx_cfg_reg,"
hexmask.long.word 0x0 16.--31. 1. "PRU0_ED_RX_DIV_FACTOR,"
bitfld.long 0x0 15. "PRU0_ED_RX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x0 4. "PRU0_ED_RX_CLK_SEL," "0,1"
bitfld.long 0x0 3. "PRU0_ED_RX_SB_POL," "0,1"
newline
bitfld.long 0x0 0.--2. "PRU0_ED_RX_SAMPLE_SIZE," "0,1,2,3,4,5,6,7"
line.long 0x4 "PR1_CFG__SLV__REGS_pru0_ed_tx_cfg_reg,"
hexmask.long.word 0x4 16.--31. 1. "PRU0_ED_TX_DIV_FACTOR,"
bitfld.long 0x4 15. "PRU0_ED_TX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x4 11. "PRU0_ENDAT_SHARE_EN," "0,1"
rbitfld.long 0x4 10. "PRU0_ENDAT2_CLK_SYNC," "0,1"
newline
rbitfld.long 0x4 9. "PRU0_ENDAT1_CLK_SYNC," "0,1"
rbitfld.long 0x4 8. "PRU0_ENDAT0_CLK_SYNC," "0,1"
newline
rbitfld.long 0x4 7. "PRU0_ED_BUSY_2," "0,1"
rbitfld.long 0x4 6. "PRU0_ED_BUSY_1," "0,1"
newline
rbitfld.long 0x4 5. "PRU0_ED_BUSY_0," "0,1"
bitfld.long 0x4 4. "PRU0_ED_TX_CLK_SEL," "0,1"
line.long 0x8 "PR1_CFG__SLV__REGS_pru0_ed_ch0_cfg0_reg,"
bitfld.long 0x8 31. "PRU0_ED_TX_FIFO_SWAP_BITS0," "0,1"
bitfld.long 0x8 30. "PRU0_ED_SW_CLK_OUT0," "0,1"
newline
bitfld.long 0x8 29. "PRU0_ED_CLK_OUT_OVR_EN0," "0,1"
rbitfld.long 0x8 28. "PRU0_ED_RX_SNOOP0," "0,1"
newline
hexmask.long.word 0x8 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE0,"
hexmask.long.byte 0x8 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE0,"
newline
hexmask.long.word 0x8 0.--10. 1. "PRU0_ED_TX_WDLY0,"
line.long 0xC "PR1_CFG__SLV__REGS_pru0_ed_ch0_cfg1_reg,"
hexmask.long.word 0xC 16.--31. 1. "PRU0_ED_RX_EN_COUNTER0,"
hexmask.long.word 0xC 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER0,"
line.long 0x10 "PR1_CFG__SLV__REGS_pru0_ed_ch1_cfg0_reg,"
bitfld.long 0x10 31. "PRU0_ED_TX_FIFO_SWAP_BITS1," "0,1"
bitfld.long 0x10 30. "PRU0_ED_SW_CLK_OUT1," "0,1"
newline
bitfld.long 0x10 29. "PRU0_ED_CLK_OUT_OVR_EN1," "0,1"
rbitfld.long 0x10 28. "PRU0_ED_RX_SNOOP1," "0,1"
newline
hexmask.long.word 0x10 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE1,"
hexmask.long.byte 0x10 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE1,"
newline
hexmask.long.word 0x10 0.--10. 1. "PRU0_ED_TX_WDLY1,"
line.long 0x14 "PR1_CFG__SLV__REGS_pru0_ed_ch1_cfg1_reg,"
hexmask.long.word 0x14 16.--31. 1. "PRU0_ED_RX_EN_COUNTER1,"
hexmask.long.word 0x14 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER1,"
line.long 0x18 "PR1_CFG__SLV__REGS_pru0_ed_ch2_cfg0_reg,"
bitfld.long 0x18 31. "PRU0_ED_TX_FIFO_SWAP_BITS2," "0,1"
bitfld.long 0x18 30. "PRU0_ED_SW_CLK_OUT2," "0,1"
newline
bitfld.long 0x18 29. "PRU0_ED_CLK_OUT_OVR_EN2," "0,1"
rbitfld.long 0x18 28. "PRU0_ED_RX_SNOOP2," "0,1"
newline
hexmask.long.word 0x18 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE2,"
hexmask.long.byte 0x18 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE2,"
newline
hexmask.long.word 0x18 0.--10. 1. "PRU0_ED_TX_WDLY2,"
line.long 0x1C "PR1_CFG__SLV__REGS_pru0_ed_ch2_cfg1_reg,"
hexmask.long.word 0x1C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER2,"
hexmask.long.word 0x1C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER2,"
line.long 0x20 "PR1_CFG__SLV__REGS_pru1_ed_rx_cfg_reg,"
hexmask.long.word 0x20 16.--31. 1. "PRU1_ED_RX_DIV_FACTOR,"
bitfld.long 0x20 15. "PRU1_ED_RX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x20 4. "PRU1_ED_RX_CLK_SEL," "0,1"
bitfld.long 0x20 3. "PRU1_ED_RX_SB_POL," "0,1"
newline
bitfld.long 0x20 0.--2. "PRU1_ED_RX_SAMPLE_SIZE," "0,1,2,3,4,5,6,7"
line.long 0x24 "PR1_CFG__SLV__REGS_pru1_ed_tx_cfg_reg,"
hexmask.long.word 0x24 16.--31. 1. "PRU1_ED_TX_DIV_FACTOR,"
bitfld.long 0x24 15. "PRU1_ED_TX_DIV_FACTOR_FRAC," "0,1"
newline
bitfld.long 0x24 11. "PRU1_ENDAT_SHARE_EN," "0,1"
rbitfld.long 0x24 10. "PRU1_ENDAT2_CLK_SYNC," "0,1"
newline
rbitfld.long 0x24 9. "PRU1_ENDAT1_CLK_SYNC," "0,1"
rbitfld.long 0x24 8. "PRU1_ENDAT0_CLK_SYNC," "0,1"
newline
rbitfld.long 0x24 7. "PRU1_ED_BUSY_2," "0,1"
rbitfld.long 0x24 6. "PRU1_ED_BUSY_1," "0,1"
newline
rbitfld.long 0x24 5. "PRU1_ED_BUSY_0," "0,1"
bitfld.long 0x24 4. "PRU1_ED_TX_CLK_SEL," "0,1"
line.long 0x28 "PR1_CFG__SLV__REGS_pru1_ed_ch0_cfg0_reg,"
bitfld.long 0x28 31. "PRU1_ED_TX_FIFO_SWAP_BITS0," "0,1"
bitfld.long 0x28 30. "PRU1_ED_SW_CLK_OUT0," "0,1"
newline
bitfld.long 0x28 29. "PRU1_ED_CLK_OUT_OVR_EN0," "0,1"
rbitfld.long 0x28 28. "PRU1_ED_RX_SNOOP0," "0,1"
newline
hexmask.long.word 0x28 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE0,"
hexmask.long.byte 0x28 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE0,"
newline
hexmask.long.word 0x28 0.--10. 1. "PRU1_ED_TX_WDLY0,"
line.long 0x2C "PR1_CFG__SLV__REGS_pru1_ed_ch0_cfg1_reg,"
hexmask.long.word 0x2C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER0,"
hexmask.long.word 0x2C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER0,"
line.long 0x30 "PR1_CFG__SLV__REGS_pru1_ed_ch1_cfg0_reg,"
bitfld.long 0x30 31. "PRU1_ED_TX_FIFO_SWAP_BITS1," "0,1"
bitfld.long 0x30 30. "PRU1_ED_SW_CLK_OUT1," "0,1"
newline
bitfld.long 0x30 29. "PRU1_ED_CLK_OUT_OVR_EN1," "0,1"
rbitfld.long 0x30 28. "PRU1_ED_RX_SNOOP1," "0,1"
newline
hexmask.long.word 0x30 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE1,"
hexmask.long.byte 0x30 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE1,"
newline
hexmask.long.word 0x30 0.--10. 1. "PRU1_ED_TX_WDLY1,"
line.long 0x34 "PR1_CFG__SLV__REGS_pru1_ed_ch1_cfg1_reg,"
hexmask.long.word 0x34 16.--31. 1. "PRU1_ED_RX_EN_COUNTER1,"
hexmask.long.word 0x34 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER1,"
line.long 0x38 "PR1_CFG__SLV__REGS_pru1_ed_ch2_cfg0_reg,"
bitfld.long 0x38 31. "PRU1_ED_TX_FIFO_SWAP_BITS2," "0,1"
bitfld.long 0x38 30. "PRU1_ED_SW_CLK_OUT2," "0,1"
newline
bitfld.long 0x38 29. "PRU1_ED_CLK_OUT_OVR_EN2," "0,1"
rbitfld.long 0x38 28. "PRU1_ED_RX_SNOOP2," "0,1"
newline
hexmask.long.word 0x38 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE2,"
hexmask.long.byte 0x38 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE2,"
newline
hexmask.long.word 0x38 0.--10. 1. "PRU1_ED_TX_WDLY2,"
line.long 0x3C "PR1_CFG__SLV__REGS_pru1_ed_ch2_cfg1_reg,"
hexmask.long.word 0x3C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER2,"
hexmask.long.word 0x3C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER2,"
group.long 0x124++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_rtu0_poke_en0_reg,"
hexmask.long.byte 0x0 28.--31. 1. "RTU0_POKE_R27_EN,"
hexmask.long.byte 0x0 24.--27. 1. "RTU0_POKE_R26_EN,"
newline
hexmask.long.byte 0x0 20.--23. 1. "RTU0_POKE_R25_EN,"
hexmask.long.byte 0x0 16.--19. 1. "RTU0_POKE_R24_EN,"
newline
hexmask.long.byte 0x0 12.--15. 1. "RTU0_POKE_R23_EN,"
hexmask.long.byte 0x0 8.--11. 1. "RTU0_POKE_R22_EN,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RTU0_POKE_R21_EN,"
hexmask.long.byte 0x0 0.--3. 1. "RTU0_POKE_R20_EN,"
group.long 0x12C++0x4F
line.long 0x0 "PR1_CFG__SLV__REGS_rtu1_poke_en0_reg,"
hexmask.long.byte 0x0 28.--31. 1. "RTU1_POKE_R27_EN,"
hexmask.long.byte 0x0 24.--27. 1. "RTU1_POKE_R26_EN,"
newline
hexmask.long.byte 0x0 20.--23. 1. "RTU1_POKE_R25_EN,"
hexmask.long.byte 0x0 16.--19. 1. "RTU1_POKE_R24_EN,"
newline
hexmask.long.byte 0x0 12.--15. 1. "RTU1_POKE_R23_EN,"
hexmask.long.byte 0x0 8.--11. 1. "RTU1_POKE_R22_EN,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RTU1_POKE_R21_EN,"
hexmask.long.byte 0x0 0.--3. 1. "RTU1_POKE_R20_EN,"
line.long 0x4 "PR1_CFG__SLV__REGS_pwm0,"
bitfld.long 0x4 30. "PWM0_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0x4 21.--29. 1. "PWM0_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0x4 20. "PWM0_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0x4 19. "PWM0_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0x4 18. "PWM0_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0x4 17. "PWM0_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0x4 8.--16. 1. "PWM0_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0x4 0.--7. 1. "PWM0_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0x8 "PR1_CFG__SLV__REGS_pwm1,"
bitfld.long 0x8 30. "PWM1_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0x8 21.--29. 1. "PWM1_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0x8 20. "PWM1_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0x8 19. "PWM1_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0x8 18. "PWM1_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0x8 17. "PWM1_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0x8 8.--16. 1. "PWM1_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0x8 0.--7. 1. "PWM1_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0xC "PR1_CFG__SLV__REGS_pwm2,"
bitfld.long 0xC 30. "PWM2_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0xC 21.--29. 1. "PWM2_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0xC 20. "PWM2_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0xC 19. "PWM2_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0xC 18. "PWM2_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0xC 17. "PWM2_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0xC 8.--16. 1. "PWM2_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0xC 0.--7. 1. "PWM2_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0x10 "PR1_CFG__SLV__REGS_pwm3,"
bitfld.long 0x10 30. "PWM3_TRIP_S,Safety trip status" "0,1"
hexmask.long.word 0x10 21.--29. 1. "PWM3_TRIP_VEC,Safety trip trigger cause vector"
newline
bitfld.long 0x10 20. "PWM3_POS_ERR_TRIP,SW position saftey error trip" "0,1"
bitfld.long 0x10 19. "PWM3_OVER_ERR_TRIP,SW over safety error trip" "0,1"
newline
bitfld.long 0x10 18. "PWM3_TRIP_RESET,SW reset safety flag" "0,1"
bitfld.long 0x10 17. "PWM3_TRIP_CMP0_EN,CMP0 reset safety trip clear enable" "0,1"
newline
hexmask.long.word 0x10 8.--16. 1. "PWM3_TRIP_MASK,SW mask for safety trip  one hot"
hexmask.long.byte 0x10 0.--7. 1. "PWM3_DEBOUNCE_VALUE,debounce counter   defines the number of core_clk required for the pulse not to get rejected"
line.long 0x14 "PR1_CFG__SLV__REGS_pwm0_0,"
bitfld.long 0x14 10.--11. "PWM0_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x14 8.--9. "PWM0_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x14 6.--7. "PWM0_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x14 4.--5. "PWM0_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "PWM0_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x14 0.--1. "PWM0_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x18 "PR1_CFG__SLV__REGS_pwm0_1,"
bitfld.long 0x18 10.--11. "PWM0_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x18 8.--9. "PWM0_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x18 6.--7. "PWM0_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x18 4.--5. "PWM0_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "PWM0_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x18 0.--1. "PWM0_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x1C "PR1_CFG__SLV__REGS_pwm0_2,"
bitfld.long 0x1C 10.--11. "PWM0_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x1C 8.--9. "PWM0_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "PWM0_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x1C 4.--5. "PWM0_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x1C 2.--3. "PWM0_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x1C 0.--1. "PWM0_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x20 "PR1_CFG__SLV__REGS_pwm1_0,"
bitfld.long 0x20 10.--11. "PWM1_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x20 8.--9. "PWM1_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x20 6.--7. "PWM1_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x20 4.--5. "PWM1_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x20 2.--3. "PWM1_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x20 0.--1. "PWM1_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x24 "PR1_CFG__SLV__REGS_pwm1_1,"
bitfld.long 0x24 10.--11. "PWM1_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x24 8.--9. "PWM1_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "PWM1_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x24 4.--5. "PWM1_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x24 2.--3. "PWM1_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x24 0.--1. "PWM1_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x28 "PR1_CFG__SLV__REGS_pwm1_2,"
bitfld.long 0x28 10.--11. "PWM1_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x28 8.--9. "PWM1_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x28 6.--7. "PWM1_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x28 4.--5. "PWM1_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x28 2.--3. "PWM1_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x28 0.--1. "PWM1_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x2C "PR1_CFG__SLV__REGS_pwm2_0,"
bitfld.long 0x2C 10.--11. "PWM2_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x2C 8.--9. "PWM2_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x2C 6.--7. "PWM2_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x2C 4.--5. "PWM2_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x2C 2.--3. "PWM2_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x2C 0.--1. "PWM2_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x30 "PR1_CFG__SLV__REGS_pwm2_1,"
bitfld.long 0x30 10.--11. "PWM2_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x30 8.--9. "PWM2_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x30 6.--7. "PWM2_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x30 4.--5. "PWM2_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x30 2.--3. "PWM2_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x30 0.--1. "PWM2_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x34 "PR1_CFG__SLV__REGS_pwm2_2,"
bitfld.long 0x34 10.--11. "PWM2_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x34 8.--9. "PWM2_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "PWM2_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x34 4.--5. "PWM2_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x34 2.--3. "PWM2_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x34 0.--1. "PWM2_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x38 "PR1_CFG__SLV__REGS_pwm3_0,"
bitfld.long 0x38 10.--11. "PWM3_0_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x38 8.--9. "PWM3_0_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x38 6.--7. "PWM3_0_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x38 4.--5. "PWM3_0_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x38 2.--3. "PWM3_0_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x38 0.--1. "PWM3_0_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x3C "PR1_CFG__SLV__REGS_pwm3_1,"
bitfld.long 0x3C 10.--11. "PWM3_1_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x3C 8.--9. "PWM3_1_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x3C 6.--7. "PWM3_1_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x3C 4.--5. "PWM3_1_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x3C 2.--3. "PWM3_1_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x3C 0.--1. "PWM3_1_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x40 "PR1_CFG__SLV__REGS_pwm3_2,"
bitfld.long 0x40 10.--11. "PWM3_2_NEG_ACT,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x40 8.--9. "PWM3_2_POS_ACT,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x40 6.--7. "PWM3_2_NEG_TRIP,Safety Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x40 4.--5. "PWM3_2_POS_TRIP,Safety Trip pos state 00 z 01 L 10 H" "0,1,2,3"
newline
bitfld.long 0x40 2.--3. "PWM3_2_NEG_INIT,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x40 0.--1. "PWM3_2_POS_INIT,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
line.long 0x44 "PR1_CFG__SLV__REGS_spin_lock0,"
hexmask.long.byte 0x44 8.--13. 1. "MMR_OWN_REQ_VECTOR_0,Spin Lock flag Vector"
eventfld.long 0x44 1. "MMR_OWN_REQ_CLR_0,Spin Lock Status Clear" "0,1"
newline
rbitfld.long 0x44 0. "MMR_OWN_REQ_STATUS_0,Spin Lock Status" "0,1"
line.long 0x48 "PR1_CFG__SLV__REGS_spin_lock1,"
hexmask.long.byte 0x48 8.--13. 1. "MMR_OWN_REQ_VECTOR_1,Spin Lock flag Vector"
eventfld.long 0x48 1. "MMR_OWN_REQ_CLR_1,Spin Lock Status Clear" "0,1"
newline
rbitfld.long 0x48 0. "MMR_OWN_REQ_STATUS_1,Spin Lock Status" "0,1"
line.long 0x4C "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg0,"
bitfld.long 0x4C 31. "PA_PDSP0_INC_TYPE,pa_pdsp0_inc_type" "0,1"
hexmask.long.tbyte 0x4C 14.--30. 1. "PA_PDSP0_INC_VAL,pa_pdsp0_inc_val"
newline
hexmask.long.word 0x4C 0.--13. 1. "PA_PDSP0_INDEX,pa_pdsp0_index"
rgroup.long 0x17C++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat0,"
bitfld.long 0x0 1.--3. "PA_PDSP0_STATUS,pa_pdsp0_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP0_READY,pa_pdsp0_ready" "0,1"
group.long 0x180++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg1,"
bitfld.long 0x0 31. "PA_PDSP1_INC_TYPE,pa_pdsp1_inc_type" "0,1"
hexmask.long.tbyte 0x0 14.--30. 1. "PA_PDSP1_INC_VAL,pa_pdsp1_inc_val"
newline
hexmask.long.word 0x0 0.--13. 1. "PA_PDSP1_INDEX,pa_pdsp1_index"
rgroup.long 0x184++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat1,"
bitfld.long 0x0 1.--3. "PA_PDSP1_STATUS,pa_pdsp1_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP1_READY,pa_pdsp1_ready" "0,1"
group.long 0x188++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg2,"
bitfld.long 0x0 31. "PA_PDSP2_INC_TYPE,pa_pdsp2_inc_type" "0,1"
hexmask.long.tbyte 0x0 14.--30. 1. "PA_PDSP2_INC_VAL,pa_pdsp2_inc_val"
newline
hexmask.long.word 0x0 0.--13. 1. "PA_PDSP2_INDEX,pa_pdsp2_index"
rgroup.long 0x18C++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat2,"
bitfld.long 0x0 1.--3. "PA_PDSP2_STATUS,pa_pdsp2_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP2_READY,pa_pdsp2_ready" "0,1"
group.long 0x190++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg3,"
bitfld.long 0x0 31. "PA_PDSP3_INC_TYPE,pa_pdsp3_inc_type" "0,1"
hexmask.long.tbyte 0x0 14.--30. 1. "PA_PDSP3_INC_VAL,pa_pdsp3_inc_val"
newline
hexmask.long.word 0x0 0.--13. 1. "PA_PDSP3_INDEX,pa_pdsp3_index"
rgroup.long 0x194++0x3
line.long 0x0 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat3,"
bitfld.long 0x0 1.--3. "PA_PDSP3_STATUS,pa_pdsp3_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "PA_PDSP3_READY,pa_pdsp3_ready" "0,1"
tree.end
base ad:0x0
tree "PRU_ICSSG1_PR1_ICSS"
tree "PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV (PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV)"
base ad:0x300B0000
group.long 0x0++0x17
line.long 0x0 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_TSCNT,TIME STAMP COUNTER REGISTER"
hexmask.long 0x0 0.--31. 1. "TSCNT,ACTIVE 32 BIT COUNTER REGISTER WHICH IS USED AS THE CAPTURE TIME-BASE"
line.long 0x4 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CNTPHS,COUNTER PHASE CONTROL REGISTER"
hexmask.long 0x4 0.--31. 1. "CNTPHS,COUNTER PHASE VALUE REGISTER THAT CAN BE PROGRAMMED FOR PHASE LAG/LEAD THIS REGISTER SHADOWS TSCNT AND IS LOADED INTO TSCNT UPON EITHER A SYNCI EVENT OR S/W FORCE VIA A CONTROL BITUSED TO ACHIEVE PHASE CONTROL SYNC WITH RESPECT TO OTHER ECAP AND.."
line.long 0x8 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP1,CAPTURE-1 REGISTER"
hexmask.long 0x8 0.--31. 1. "CAP1,THIS REGISTER CAN BE LOADED [WRITTEN] BY :TIME-STAMP [IE COUNTER VALUE] DURING A CAPTURE EVENTS/W MAY BE USEFUL FOR TEST PURPOSES / INITIALISATIONAPRD SHADOW REGISTER [IE CAP3] WHEN USED IN APWM MODE"
line.long 0xC "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP2,CAPTURE-2 REGISTER"
hexmask.long 0xC 0.--31. 1. "CAP2,THIS REGISTER CAN BE LOADED [WRITTEN] BY :TIME-STAMP [IE COUNTER VALUE] DURING A CAPTURE EVENTS/W MAY BE USEFUL FOR TEST PURPOSESACMP SHADOW REGISTER [IE CAP4] WHEN USED IN APWM MODE"
line.long 0x10 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP3,CAPTURE-3 REGISTER"
hexmask.long 0x10 0.--31. 1. "CAP3,IN CMP MODE THIS IS A TIME-STAMP CAPTURE REGISTERIN APMW MODE THIS IS THE PERIOD SHADOW [APER] REGISTER USER UPDATES THE PWM PERIOD VALUE VIA THIS REGISTER IN THIS MODE CAP3 [APRD] SHADOWS CAP1"
line.long 0x14 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP4,CAPTURE-4 REGISTER"
hexmask.long 0x14 0.--31. 1. "CAP4,IN CMP MODE THIS IS A TIME-STAMP CAPTURE REGISTERIN APMW MODE THIS IS THE COMPARE SHADOW [ACMP] REGISTER USER UPDATES THE PWM COMPARE VALUE VIA THIS REGISTER IN THIS MODE CAP4 [ACMP] SHADOWS CAP2"
group.long 0x28++0x7
line.long 0x0 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECCTL2_ECCTL1,ECAP CONTROL REGISTER 1"
hexmask.long.byte 0x0 27.--31. 1. "FILTER,"
bitfld.long 0x0 26. "APWMPOL,APWM OUTPUT POLARITY SELECT:0OUTPUT IS ACTIVE HIGH [IE COMPARE VALUE DEFINES HIGH TIME]1OUTPUT IS ACTIVE LOW [IE COMPARE VALUE DEFINES LOW TIME]NOTE: THIS IS APPLICABLE ONLY IN APWM OPERATING MODE" "0,1"
bitfld.long 0x0 25. "CAP_APWM,CAP/APWM OPERATING MODE SELECT:0ECAP MODULE OPERATES IN CAPTURE MODETHIS MODE FORCES THE FOLLOWING CONFIGURATION:1] INHIBITS TSCNT RESETS VIA PRD_EQ EVENT2] INHIBITS SHADOW LOADS ON CAP1 &AMP" "0,1"
newline
bitfld.long 0x0 24. "SWSYNC,SOFTWARE FORCED COUNTER [TSCNT] SYNCING:0WRITING A ZERO HAS NO EFFECT WILL ALWAYS RETURN A ZERO1WRITING A ONE WILL FORCE A TSCNT SHADOW LOAD OF CURRENT ECAP MODULE AND ANY ECAP MODULES DOWN-STREAM PROVIDING THE SYNCO_SEL BITS ARE 0 0 AFTER WRITING.." "0,1"
bitfld.long 0x0 22.--23. "SYNCO_SEL,SYNC-OUT SELECT:0 0SELECT SYNC-IN EVENT TO BE THE SYNC-OUT SIGNAL [PASS THROUGH]0 1SELECT PRD_EQ EVENT TO BE THE SYNC-OUT SIGNAL1 0DISABLE SYNC OUT SIGNAL1 1DISABLE SYNC OUT SIGNALNOTE: SELECTION PRD_EQ IS MEANINGFUL ONLY IN APWM MODE  HOWEVER.." "0,1,2,3"
bitfld.long 0x0 21. "SYNCI_EN,COUNTER [TSCNT] SYNC-IN SELECT MODE:0DISABLE SYNC-IN OPTION1ENABLE COUNTER [TSCNT] TO BE LOADED FROM CNTPHS REGISTER UPON EITHER A SYNCI SIGNAL OR A S/W FORCE EVENT" "0,1"
newline
bitfld.long 0x0 20. "TSCNTSTP,COUNTER STOP [FREEZE] CONTROL:0COUNTER STOPPED1COUNTER FREE RUNNING" "0,1"
bitfld.long 0x0 19. "REARM_RESET,ONE-SHOT RE-ARMING  IE WAIT FOR STOP TRIGGER:WRITING A ONE ARMS THE ONE-SHOT SEQUENCE  IE:1] RESETS THE MOD4 COUNTER TO ZERO2] UN-FREEZES THE MOD4 COUNTER3] ENABLES CAPTURE REGISTER LOADSWRITING A ZERO HAS NO EFFECT ALWAYS RETURNS A 0NOTE:.." "0,1"
bitfld.long 0x0 17.--18. "STOPVALUE,STOP VALUE FOR ONE-SHOT MODE:THIS IS THE NUMBER [BETWEEN 1-4] OF CAPTURES ALLOWED TO OCCUR BEFORE THE CAP[1-4] REGISTERS ARE FROZEN  IECAPTURE SEQUENCE IS STOPPED0 0STOP AFTER CAPTURE EVENT 10 1STOP AFTER CAPTURE EVENT 21 0STOP AFTER CAPTURE.." "0,1,2,3"
newline
bitfld.long 0x0 16. "CONT_ONESHT,CONTINUOUS OR ONESHOT MODE CONTROL:[APPLICABLE ONLY IN CAPTURE MODE]0OPERATE IN CONTINUOUS MODE1OPERATE IN ONE-SHOT MODE" "0,1"
bitfld.long 0x0 15. "FREE,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1"
bitfld.long 0x0 14. "SOFT,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1"
newline
hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,EVENT FILTER PRESCALE SELECT:0 0 0 0 0DIVIDE BY 1 [IE NO PRESCALE  BY-PASS THE PRESCALER]0 0 0 0 1DIVIDE BY 20 0 0 1 0DIVIDE BY 40 0 0 1 1DIVIDE BY 60 0 1 0 0DIVIDE BY 80 0 1 0 1DIVIDE BY 10 1 1 1 1 0DIVIDE BY 601 1 1 1 1DIVIDE BY 62"
bitfld.long 0x0 8. "CAPLDEN,ENABLE LOADING OF CAP1-4 REGISTERS ON A CAPTURE EVENT:0DISABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME1ENABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME" "0,1"
bitfld.long 0x0 7. "CTRRST4,COUNTER RESET ON CAPTURE EVENT 4:0DO NOT RESET COUNTER ON CAPTURE EVENT 4 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 4 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,?"
newline
bitfld.long 0x0 6. "CAP4POL,CAPTURE EVENT 4 POLARITY SELECT:0CAPTURE EVENT 4 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 4 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
bitfld.long 0x0 5. "CTRRST3,COUNTER RESET ON CAPTURE EVENT 3:0DO NOT RESET COUNTER ON CAPTURE EVENT 3 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 3 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,?"
bitfld.long 0x0 4. "CAP3POL,CAPTURE EVENT 3 POLARITY SELECT:0CAPTURE EVENT 3 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 3 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
newline
bitfld.long 0x0 3. "CTRRST2,COUNTER RESET ON CAPTURE EVENT 2:0DO NOT RESET COUNTER ON CAPTURE EVENT 2 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 2 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,?"
bitfld.long 0x0 2. "CAP2POL,CAPTURE EVENT 2 POLARITY SELECT:0CAPTURE EVENT 2 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 2 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
bitfld.long 0x0 1. "CTRRST1,COUNTER RESET ON CAPTURE EVENT 1:0DO NOT RESET COUNTER ON CAPTURE EVENT 1 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 1 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,1: 0DO NOT RESET COUNTER ON CAPTURE EVENT 1.."
newline
bitfld.long 0x0 0. "CAP1POL,CAPTURE EVENT 1 POLARITY SELECT:0CAPTURE EVENT 1 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 1 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
line.long 0x4 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECFLG_ECEINT,ECAP INTERRUPT ENABLE REGISTER"
hexmask.long.byte 0x4 24.--31. 1. "FLAG_RESV0,"
rbitfld.long 0x4 23. "FLAG_CMPEQ,COMPARE EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE COMPARE REGISTER VALUE [ACMP]READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1"
rbitfld.long 0x4 22. "FLAG_PRDEQ,PERIOD EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE PERIOD REGISTER VALUE [APER] AND WAS RESETREADING A 0 INDICATES NO EVENT OCCURREDNOTES: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1"
newline
rbitfld.long 0x4 21. "FLAG_CNTOVF,COUNTER OVERFLOW STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] HAS MADE THE TRANSITION FROM FFFFFFFF 00000000READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ACTIVE IN CAP &AMP" "0,1"
rbitfld.long 0x4 20. "FLAG_CEVT4,CAPTURE EVENT 4 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FOURTH EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x4 19. "FLAG_CEVT3,CAPTURE EVENT 3 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE THIRD EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
newline
rbitfld.long 0x4 18. "FLAG_CEVT2,CAPTURE EVENT 2 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE SECOND EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x4 17. "FLAG_CEVT1,CAPTURE EVENT 1 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FIRST EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x4 16. "FLAG_INT,GLOBAL INTERRUPT STATUS FLAG: READING A 1 ON THIS BIT INDICATES THAT AN INTERRUPT WAS GENERATED FROM ONE OF THE FOLLOWING EVENTSREADING A 0 INDICATES NO INTERRUPT GENERATED" "0,1"
newline
hexmask.long.byte 0x4 8.--15. 1. "EN__RESV1,"
bitfld.long 0x4 7. "EN_CMPEQ,COMPARE EQUAL INTERRUPT ENABLE: 0DISABLED COMPARE EQUAL AS AN INTERRUPT SOURCE1ENABLE COMPARE EQUAL AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 6. "EN_PRDEQ,PERIOD EQUAL INTERRUPT ENABLE: 0DISABLED PERIOD EQUAL AS AN INTERRUPT SOURCE1ENABLE PERIOD EQUAL AS AN INTERRUPT SOURCE" "0,1"
newline
bitfld.long 0x4 5. "EN_CNTOVF,COUNTER OVERFLOW INTERRUPT ENABLE: 0DISABLED COUNTER OVERFLOW AS AN INTERRUPT SOURCE1ENABLE COUNTER OVERFLOW AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 4. "EN_CEVT4,CAPTURE EVENT 4 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 3. "EN_CEVT3,CAPTURE EVENT 3 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
newline
bitfld.long 0x4 2. "EN_CEVT2,CAPTURE EVENT 2 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x4 1. "EN_CEVT1,CAPTURE EVENT 1 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
rbitfld.long 0x4 0. "EN_RESV0," "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_PID,ECAP PERIPHERAL ID REGISTER"
hexmask.long 0x0 0.--31. 1. "REVID,"
tree.end
tree "PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV (PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV)"
base ad:0x300A0000
rgroup.long 0x0++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_REVISION_REG,"
bitfld.long 0x0 30.--31. "REV_SCHEME,Scheme" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "REV_MODULE,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REV_RTL,RTL revisions"
newline
bitfld.long 0x0 8.--10. "REV_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "REV_CUSTOM,Custom revision" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REV_MINOR,Minor revision"
group.long 0x4++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_CONTROL_REG,"
bitfld.long 0x0 4. "PRIORITY_HOLD_MODE,Priority Holding Mode" "0,1"
bitfld.long 0x0 2.--3. "NEST_MODE,Nesting Mode" "0,1,2,3"
bitfld.long 0x0 1. "WAKEUP_MODE,Wakeup mode enable" "0,1"
group.long 0x10++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_GLOBAL_ENABLE_HINT_REG,"
bitfld.long 0x0 0. "ENABLE_HINT_ANY,Global Enable for all Host Ints" "0,1"
group.long 0x1C++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_GLB_NEST_LEVEL_REG,"
bitfld.long 0x0 31. "GLB_NEST_AUTO_OVR,Global Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x0 0.--8. 1. "GLB_NEST_LEVEL,Global Nesting Level"
wgroup.long 0x20++0x7
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_STATUS_SET_INDEX_REG,"
hexmask.long.word 0x0 0.--9. 1. "STATUS_SET_INDEX,Status Set Index Register (write index to set status of)"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_STATUS_CLR_INDEX_REG,"
hexmask.long.word 0x4 0.--9. 1. "STATUS_CLR_INDEX,Status Clear Index Register (write index to clear status of)"
group.long 0x28++0x7
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_SET_INDEX_REG,"
hexmask.long.word 0x0 0.--9. 1. "ENABLE_SET_INDEX,Enable Set Index Register (write index to set enable of)"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_INDEX_REG,"
hexmask.long.word 0x4 0.--9. 1. "ENABLE_CLR_INDEX,Enable Clear Index Register (write index to clear enable of)"
group.long 0x34++0x7
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_ENABLE_SET_INDEX_REG,"
hexmask.long.word 0x0 0.--9. 1. "HINT_ENABLE_SET_INDEX,Enable set for Host Interrupts"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_ENABLE_CLR_INDEX_REG,"
hexmask.long.word 0x4 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Enable clear for Host Interrupts"
rgroup.long 0x80++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_GLB_PRI_INTR_REG,"
bitfld.long 0x0 31. "GLB_NONE,No interrupt pending flag" "0,1"
hexmask.long.word 0x0 0.--9. 1. "GLB_PRI_INTR,Prioritized Interrupt"
group.long 0x200++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG0,"
bitfld.long 0x0 31. "RAW_STATUS_31,Raw Status (write 1 to set) for intr_in[31]" "0,1"
bitfld.long 0x0 30. "RAW_STATUS_30,Raw Status (write 1 to set) for intr_in[30]" "0,1"
bitfld.long 0x0 29. "RAW_STATUS_29,Raw Status (write 1 to set) for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "RAW_STATUS_28,Raw Status (write 1 to set) for intr_in[28]" "0,1"
bitfld.long 0x0 27. "RAW_STATUS_27,Raw Status (write 1 to set) for intr_in[27]" "0,1"
bitfld.long 0x0 26. "RAW_STATUS_26,Raw Status (write 1 to set) for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "RAW_STATUS_25,Raw Status (write 1 to set) for intr_in[25]" "0,1"
bitfld.long 0x0 24. "RAW_STATUS_24,Raw Status (write 1 to set) for intr_in[24]" "0,1"
bitfld.long 0x0 23. "RAW_STATUS_23,Raw Status (write 1 to set) for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "RAW_STATUS_22,Raw Status (write 1 to set) for intr_in[22]" "0,1"
bitfld.long 0x0 21. "RAW_STATUS_21,Raw Status (write 1 to set) for intr_in[21]" "0,1"
bitfld.long 0x0 20. "RAW_STATUS_20,Raw Status (write 1 to set) for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "RAW_STATUS_19,Raw Status (write 1 to set) for intr_in[19]" "0,1"
bitfld.long 0x0 18. "RAW_STATUS_18,Raw Status (write 1 to set) for intr_in[18]" "0,1"
bitfld.long 0x0 17. "RAW_STATUS_17,Raw Status (write 1 to set) for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "RAW_STATUS_16,Raw Status (write 1 to set) for intr_in[16]" "0,1"
bitfld.long 0x0 15. "RAW_STATUS_15,Raw Status (write 1 to set) for intr_in[15]" "0,1"
bitfld.long 0x0 14. "RAW_STATUS_14,Raw Status (write 1 to set) for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "RAW_STATUS_13,Raw Status (write 1 to set) for intr_in[13]" "0,1"
bitfld.long 0x0 12. "RAW_STATUS_12,Raw Status (write 1 to set) for intr_in[12]" "0,1"
bitfld.long 0x0 11. "RAW_STATUS_11,Raw Status (write 1 to set) for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "RAW_STATUS_10,Raw Status (write 1 to set) for intr_in[10]" "0,1"
bitfld.long 0x0 9. "RAW_STATUS_9,Raw Status (write 1 to set) for intr_in[9]" "0,1"
bitfld.long 0x0 8. "RAW_STATUS_8,Raw Status (write 1 to set) for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "RAW_STATUS_7,Raw Status (write 1 to set) for intr_in[7]" "0,1"
bitfld.long 0x0 6. "RAW_STATUS_6,Raw Status (write 1 to set) for intr_in[6]" "0,1"
bitfld.long 0x0 5. "RAW_STATUS_5,Raw Status (write 1 to set) for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "RAW_STATUS_4,Raw Status (write 1 to set) for intr_in[4]" "0,1"
bitfld.long 0x0 3. "RAW_STATUS_3,Raw Status (write 1 to set) for intr_in[3]" "0,1"
bitfld.long 0x0 2. "RAW_STATUS_2,Raw Status (write 1 to set) for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "RAW_STATUS_1,Raw Status (write 1 to set) for intr_in[1]" "0,1"
bitfld.long 0x0 0. "RAW_STATUS_0,Raw Status (write 1 to set) for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG1,"
bitfld.long 0x4 31. "RAW_STATUS_63,Raw Status (write 1 to set) for intr_in[63]" "0,1"
bitfld.long 0x4 30. "RAW_STATUS_62,Raw Status (write 1 to set) for intr_in[62]" "0,1"
bitfld.long 0x4 29. "RAW_STATUS_61,Raw Status (write 1 to set) for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "RAW_STATUS_60,Raw Status (write 1 to set) for intr_in[60]" "0,1"
bitfld.long 0x4 27. "RAW_STATUS_59,Raw Status (write 1 to set) for intr_in[59]" "0,1"
bitfld.long 0x4 26. "RAW_STATUS_58,Raw Status (write 1 to set) for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "RAW_STATUS_57,Raw Status (write 1 to set) for intr_in[57]" "0,1"
bitfld.long 0x4 24. "RAW_STATUS_56,Raw Status (write 1 to set) for intr_in[56]" "0,1"
bitfld.long 0x4 23. "RAW_STATUS_55,Raw Status (write 1 to set) for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "RAW_STATUS_54,Raw Status (write 1 to set) for intr_in[54]" "0,1"
bitfld.long 0x4 21. "RAW_STATUS_53,Raw Status (write 1 to set) for intr_in[53]" "0,1"
bitfld.long 0x4 20. "RAW_STATUS_52,Raw Status (write 1 to set) for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "RAW_STATUS_51,Raw Status (write 1 to set) for intr_in[51]" "0,1"
bitfld.long 0x4 18. "RAW_STATUS_50,Raw Status (write 1 to set) for intr_in[50]" "0,1"
bitfld.long 0x4 17. "RAW_STATUS_49,Raw Status (write 1 to set) for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "RAW_STATUS_48,Raw Status (write 1 to set) for intr_in[48]" "0,1"
bitfld.long 0x4 15. "RAW_STATUS_47,Raw Status (write 1 to set) for intr_in[47]" "0,1"
bitfld.long 0x4 14. "RAW_STATUS_46,Raw Status (write 1 to set) for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "RAW_STATUS_45,Raw Status (write 1 to set) for intr_in[45]" "0,1"
bitfld.long 0x4 12. "RAW_STATUS_44,Raw Status (write 1 to set) for intr_in[44]" "0,1"
bitfld.long 0x4 11. "RAW_STATUS_43,Raw Status (write 1 to set) for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "RAW_STATUS_42,Raw Status (write 1 to set) for intr_in[42]" "0,1"
bitfld.long 0x4 9. "RAW_STATUS_41,Raw Status (write 1 to set) for intr_in[41]" "0,1"
bitfld.long 0x4 8. "RAW_STATUS_40,Raw Status (write 1 to set) for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "RAW_STATUS_39,Raw Status (write 1 to set) for intr_in[39]" "0,1"
bitfld.long 0x4 6. "RAW_STATUS_38,Raw Status (write 1 to set) for intr_in[38]" "0,1"
bitfld.long 0x4 5. "RAW_STATUS_37,Raw Status (write 1 to set) for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "RAW_STATUS_36,Raw Status (write 1 to set) for intr_in[36]" "0,1"
bitfld.long 0x4 3. "RAW_STATUS_35,Raw Status (write 1 to set) for intr_in[35]" "0,1"
bitfld.long 0x4 2. "RAW_STATUS_34,Raw Status (write 1 to set) for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "RAW_STATUS_33,Raw Status (write 1 to set) for intr_in[33]" "0,1"
bitfld.long 0x4 0. "RAW_STATUS_32,Raw Status (write 1 to set) for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG2,"
bitfld.long 0x8 31. "RAW_STATUS_95,Raw Status (write 1 to set) for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "RAW_STATUS_94,Raw Status (write 1 to set) for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "RAW_STATUS_93,Raw Status (write 1 to set) for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "RAW_STATUS_92,Raw Status (write 1 to set) for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "RAW_STATUS_91,Raw Status (write 1 to set) for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "RAW_STATUS_90,Raw Status (write 1 to set) for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "RAW_STATUS_89,Raw Status (write 1 to set) for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "RAW_STATUS_88,Raw Status (write 1 to set) for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "RAW_STATUS_87,Raw Status (write 1 to set) for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "RAW_STATUS_86,Raw Status (write 1 to set) for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "RAW_STATUS_85,Raw Status (write 1 to set) for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "RAW_STATUS_84,Raw Status (write 1 to set) for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "RAW_STATUS_83,Raw Status (write 1 to set) for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "RAW_STATUS_82,Raw Status (write 1 to set) for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "RAW_STATUS_81,Raw Status (write 1 to set) for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "RAW_STATUS_80,Raw Status (write 1 to set) for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "RAW_STATUS_79,Raw Status (write 1 to set) for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "RAW_STATUS_78,Raw Status (write 1 to set) for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "RAW_STATUS_77,Raw Status (write 1 to set) for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "RAW_STATUS_76,Raw Status (write 1 to set) for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "RAW_STATUS_75,Raw Status (write 1 to set) for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "RAW_STATUS_74,Raw Status (write 1 to set) for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "RAW_STATUS_73,Raw Status (write 1 to set) for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "RAW_STATUS_72,Raw Status (write 1 to set) for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "RAW_STATUS_71,Raw Status (write 1 to set) for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "RAW_STATUS_70,Raw Status (write 1 to set) for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "RAW_STATUS_69,Raw Status (write 1 to set) for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "RAW_STATUS_68,Raw Status (write 1 to set) for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "RAW_STATUS_67,Raw Status (write 1 to set) for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "RAW_STATUS_66,Raw Status (write 1 to set) for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "RAW_STATUS_65,Raw Status (write 1 to set) for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "RAW_STATUS_64,Raw Status (write 1 to set) for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG3,"
bitfld.long 0xC 31. "RAW_STATUS_127,Raw Status (write 1 to set) for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "RAW_STATUS_126,Raw Status (write 1 to set) for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "RAW_STATUS_125,Raw Status (write 1 to set) for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "RAW_STATUS_124,Raw Status (write 1 to set) for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "RAW_STATUS_123,Raw Status (write 1 to set) for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "RAW_STATUS_122,Raw Status (write 1 to set) for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "RAW_STATUS_121,Raw Status (write 1 to set) for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "RAW_STATUS_120,Raw Status (write 1 to set) for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "RAW_STATUS_119,Raw Status (write 1 to set) for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "RAW_STATUS_118,Raw Status (write 1 to set) for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "RAW_STATUS_117,Raw Status (write 1 to set) for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "RAW_STATUS_116,Raw Status (write 1 to set) for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "RAW_STATUS_115,Raw Status (write 1 to set) for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "RAW_STATUS_114,Raw Status (write 1 to set) for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "RAW_STATUS_113,Raw Status (write 1 to set) for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "RAW_STATUS_112,Raw Status (write 1 to set) for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "RAW_STATUS_111,Raw Status (write 1 to set) for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "RAW_STATUS_110,Raw Status (write 1 to set) for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "RAW_STATUS_109,Raw Status (write 1 to set) for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "RAW_STATUS_108,Raw Status (write 1 to set) for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "RAW_STATUS_107,Raw Status (write 1 to set) for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "RAW_STATUS_106,Raw Status (write 1 to set) for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "RAW_STATUS_105,Raw Status (write 1 to set) for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "RAW_STATUS_104,Raw Status (write 1 to set) for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "RAW_STATUS_103,Raw Status (write 1 to set) for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "RAW_STATUS_102,Raw Status (write 1 to set) for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "RAW_STATUS_101,Raw Status (write 1 to set) for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "RAW_STATUS_100,Raw Status (write 1 to set) for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "RAW_STATUS_99,Raw Status (write 1 to set) for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "RAW_STATUS_98,Raw Status (write 1 to set) for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "RAW_STATUS_97,Raw Status (write 1 to set) for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "RAW_STATUS_96,Raw Status (write 1 to set) for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG4,"
bitfld.long 0x10 31. "RAW_STATUS_159,Raw Status (write 1 to set) for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "RAW_STATUS_158,Raw Status (write 1 to set) for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "RAW_STATUS_157,Raw Status (write 1 to set) for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "RAW_STATUS_156,Raw Status (write 1 to set) for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "RAW_STATUS_155,Raw Status (write 1 to set) for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "RAW_STATUS_154,Raw Status (write 1 to set) for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "RAW_STATUS_153,Raw Status (write 1 to set) for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "RAW_STATUS_152,Raw Status (write 1 to set) for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "RAW_STATUS_151,Raw Status (write 1 to set) for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "RAW_STATUS_150,Raw Status (write 1 to set) for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "RAW_STATUS_149,Raw Status (write 1 to set) for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "RAW_STATUS_148,Raw Status (write 1 to set) for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "RAW_STATUS_147,Raw Status (write 1 to set) for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "RAW_STATUS_146,Raw Status (write 1 to set) for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "RAW_STATUS_145,Raw Status (write 1 to set) for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "RAW_STATUS_144,Raw Status (write 1 to set) for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "RAW_STATUS_143,Raw Status (write 1 to set) for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "RAW_STATUS_142,Raw Status (write 1 to set) for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "RAW_STATUS_141,Raw Status (write 1 to set) for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "RAW_STATUS_140,Raw Status (write 1 to set) for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "RAW_STATUS_139,Raw Status (write 1 to set) for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "RAW_STATUS_138,Raw Status (write 1 to set) for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "RAW_STATUS_137,Raw Status (write 1 to set) for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "RAW_STATUS_136,Raw Status (write 1 to set) for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "RAW_STATUS_135,Raw Status (write 1 to set) for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "RAW_STATUS_134,Raw Status (write 1 to set) for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "RAW_STATUS_133,Raw Status (write 1 to set) for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "RAW_STATUS_132,Raw Status (write 1 to set) for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "RAW_STATUS_131,Raw Status (write 1 to set) for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "RAW_STATUS_130,Raw Status (write 1 to set) for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "RAW_STATUS_129,Raw Status (write 1 to set) for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "RAW_STATUS_128,Raw Status (write 1 to set) for slv_events_in[64]" "0,1"
group.long 0x280++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG0,"
bitfld.long 0x0 31. "ENA_STATUS_31,Enabled Status for intr_in[31]" "0,1"
bitfld.long 0x0 30. "ENA_STATUS_30,Enabled Status for intr_in[30]" "0,1"
bitfld.long 0x0 29. "ENA_STATUS_29,Enabled Status for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "ENA_STATUS_28,Enabled Status for intr_in[28]" "0,1"
bitfld.long 0x0 27. "ENA_STATUS_27,Enabled Status for intr_in[27]" "0,1"
bitfld.long 0x0 26. "ENA_STATUS_26,Enabled Status for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "ENA_STATUS_25,Enabled Status for intr_in[25]" "0,1"
bitfld.long 0x0 24. "ENA_STATUS_24,Enabled Status for intr_in[24]" "0,1"
bitfld.long 0x0 23. "ENA_STATUS_23,Enabled Status for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "ENA_STATUS_22,Enabled Status for intr_in[22]" "0,1"
bitfld.long 0x0 21. "ENA_STATUS_21,Enabled Status for intr_in[21]" "0,1"
bitfld.long 0x0 20. "ENA_STATUS_20,Enabled Status for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "ENA_STATUS_19,Enabled Status for intr_in[19]" "0,1"
bitfld.long 0x0 18. "ENA_STATUS_18,Enabled Status for intr_in[18]" "0,1"
bitfld.long 0x0 17. "ENA_STATUS_17,Enabled Status for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "ENA_STATUS_16,Enabled Status for intr_in[16]" "0,1"
bitfld.long 0x0 15. "ENA_STATUS_15,Enabled Status for intr_in[15]" "0,1"
bitfld.long 0x0 14. "ENA_STATUS_14,Enabled Status for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "ENA_STATUS_13,Enabled Status for intr_in[13]" "0,1"
bitfld.long 0x0 12. "ENA_STATUS_12,Enabled Status for intr_in[12]" "0,1"
bitfld.long 0x0 11. "ENA_STATUS_11,Enabled Status for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "ENA_STATUS_10,Enabled Status for intr_in[10]" "0,1"
bitfld.long 0x0 9. "ENA_STATUS_9,Enabled Status for intr_in[9]" "0,1"
bitfld.long 0x0 8. "ENA_STATUS_8,Enabled Status for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "ENA_STATUS_7,Enabled Status for intr_in[7]" "0,1"
bitfld.long 0x0 6. "ENA_STATUS_6,Enabled Status for intr_in[6]" "0,1"
bitfld.long 0x0 5. "ENA_STATUS_5,Enabled Status for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "ENA_STATUS_4,Enabled Status for intr_in[4]" "0,1"
bitfld.long 0x0 3. "ENA_STATUS_3,Enabled Status for intr_in[3]" "0,1"
bitfld.long 0x0 2. "ENA_STATUS_2,Enabled Status for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "ENA_STATUS_1,Enabled Status for intr_in[1]" "0,1"
bitfld.long 0x0 0. "ENA_STATUS_0,Enabled Status for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG1,"
bitfld.long 0x4 31. "ENA_STATUS_63,Enabled Status for intr_in[63]" "0,1"
bitfld.long 0x4 30. "ENA_STATUS_62,Enabled Status for intr_in[62]" "0,1"
bitfld.long 0x4 29. "ENA_STATUS_61,Enabled Status for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "ENA_STATUS_60,Enabled Status for intr_in[60]" "0,1"
bitfld.long 0x4 27. "ENA_STATUS_59,Enabled Status for intr_in[59]" "0,1"
bitfld.long 0x4 26. "ENA_STATUS_58,Enabled Status for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "ENA_STATUS_57,Enabled Status for intr_in[57]" "0,1"
bitfld.long 0x4 24. "ENA_STATUS_56,Enabled Status for intr_in[56]" "0,1"
bitfld.long 0x4 23. "ENA_STATUS_55,Enabled Status for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "ENA_STATUS_54,Enabled Status for intr_in[54]" "0,1"
bitfld.long 0x4 21. "ENA_STATUS_53,Enabled Status for intr_in[53]" "0,1"
bitfld.long 0x4 20. "ENA_STATUS_52,Enabled Status for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "ENA_STATUS_51,Enabled Status for intr_in[51]" "0,1"
bitfld.long 0x4 18. "ENA_STATUS_50,Enabled Status for intr_in[50]" "0,1"
bitfld.long 0x4 17. "ENA_STATUS_49,Enabled Status for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "ENA_STATUS_48,Enabled Status for intr_in[48]" "0,1"
bitfld.long 0x4 15. "ENA_STATUS_47,Enabled Status for intr_in[47]" "0,1"
bitfld.long 0x4 14. "ENA_STATUS_46,Enabled Status for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "ENA_STATUS_45,Enabled Status for intr_in[45]" "0,1"
bitfld.long 0x4 12. "ENA_STATUS_44,Enabled Status for intr_in[44]" "0,1"
bitfld.long 0x4 11. "ENA_STATUS_43,Enabled Status for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "ENA_STATUS_42,Enabled Status for intr_in[42]" "0,1"
bitfld.long 0x4 9. "ENA_STATUS_41,Enabled Status for intr_in[41]" "0,1"
bitfld.long 0x4 8. "ENA_STATUS_40,Enabled Status for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "ENA_STATUS_39,Enabled Status for intr_in[39]" "0,1"
bitfld.long 0x4 6. "ENA_STATUS_38,Enabled Status for intr_in[38]" "0,1"
bitfld.long 0x4 5. "ENA_STATUS_37,Enabled Status for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "ENA_STATUS_36,Enabled Status for intr_in[36]" "0,1"
bitfld.long 0x4 3. "ENA_STATUS_35,Enabled Status for intr_in[35]" "0,1"
bitfld.long 0x4 2. "ENA_STATUS_34,Enabled Status for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "ENA_STATUS_33,Enabled Status for intr_in[33]" "0,1"
bitfld.long 0x4 0. "ENA_STATUS_32,Enabled Status for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG2,"
bitfld.long 0x8 31. "ENA_STATUS_95,Enabled Status for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "ENA_STATUS_94,Enabled Status for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "ENA_STATUS_93,Enabled Status for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "ENA_STATUS_92,Enabled Status for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "ENA_STATUS_91,Enabled Status for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "ENA_STATUS_90,Enabled Status for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "ENA_STATUS_89,Enabled Status for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "ENA_STATUS_88,Enabled Status for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "ENA_STATUS_87,Enabled Status for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "ENA_STATUS_86,Enabled Status for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "ENA_STATUS_85,Enabled Status for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "ENA_STATUS_84,Enabled Status for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "ENA_STATUS_83,Enabled Status for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "ENA_STATUS_82,Enabled Status for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "ENA_STATUS_81,Enabled Status for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "ENA_STATUS_80,Enabled Status for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "ENA_STATUS_79,Enabled Status for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "ENA_STATUS_78,Enabled Status for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "ENA_STATUS_77,Enabled Status for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "ENA_STATUS_76,Enabled Status for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "ENA_STATUS_75,Enabled Status for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "ENA_STATUS_74,Enabled Status for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "ENA_STATUS_73,Enabled Status for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "ENA_STATUS_72,Enabled Status for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "ENA_STATUS_71,Enabled Status for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "ENA_STATUS_70,Enabled Status for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "ENA_STATUS_69,Enabled Status for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "ENA_STATUS_68,Enabled Status for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "ENA_STATUS_67,Enabled Status for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "ENA_STATUS_66,Enabled Status for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "ENA_STATUS_65,Enabled Status for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "ENA_STATUS_64,Enabled Status for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG3,"
bitfld.long 0xC 31. "ENA_STATUS_127,Enabled Status for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "ENA_STATUS_126,Enabled Status for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "ENA_STATUS_125,Enabled Status for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "ENA_STATUS_124,Enabled Status for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "ENA_STATUS_123,Enabled Status for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "ENA_STATUS_122,Enabled Status for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "ENA_STATUS_121,Enabled Status for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "ENA_STATUS_120,Enabled Status for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "ENA_STATUS_119,Enabled Status for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "ENA_STATUS_118,Enabled Status for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "ENA_STATUS_117,Enabled Status for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "ENA_STATUS_116,Enabled Status for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "ENA_STATUS_115,Enabled Status for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "ENA_STATUS_114,Enabled Status for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "ENA_STATUS_113,Enabled Status for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "ENA_STATUS_112,Enabled Status for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "ENA_STATUS_111,Enabled Status for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "ENA_STATUS_110,Enabled Status for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "ENA_STATUS_109,Enabled Status for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "ENA_STATUS_108,Enabled Status for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "ENA_STATUS_107,Enabled Status for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "ENA_STATUS_106,Enabled Status for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "ENA_STATUS_105,Enabled Status for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "ENA_STATUS_104,Enabled Status for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "ENA_STATUS_103,Enabled Status for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "ENA_STATUS_102,Enabled Status for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "ENA_STATUS_101,Enabled Status for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "ENA_STATUS_100,Enabled Status for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "ENA_STATUS_99,Enabled Status for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "ENA_STATUS_98,Enabled Status for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "ENA_STATUS_97,Enabled Status for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "ENA_STATUS_96,Enabled Status for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG4,"
bitfld.long 0x10 31. "ENA_STATUS_159,Enabled Status for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENA_STATUS_158,Enabled Status for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENA_STATUS_157,Enabled Status for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "ENA_STATUS_156,Enabled Status for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "ENA_STATUS_155,Enabled Status for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENA_STATUS_154,Enabled Status for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "ENA_STATUS_153,Enabled Status for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENA_STATUS_152,Enabled Status for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "ENA_STATUS_151,Enabled Status for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "ENA_STATUS_150,Enabled Status for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENA_STATUS_149,Enabled Status for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENA_STATUS_148,Enabled Status for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENA_STATUS_147,Enabled Status for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENA_STATUS_146,Enabled Status for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENA_STATUS_145,Enabled Status for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "ENA_STATUS_144,Enabled Status for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "ENA_STATUS_143,Enabled Status for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENA_STATUS_142,Enabled Status for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "ENA_STATUS_141,Enabled Status for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENA_STATUS_140,Enabled Status for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "ENA_STATUS_139,Enabled Status for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "ENA_STATUS_138,Enabled Status for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENA_STATUS_137,Enabled Status for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENA_STATUS_136,Enabled Status for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENA_STATUS_135,Enabled Status for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENA_STATUS_134,Enabled Status for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENA_STATUS_133,Enabled Status for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "ENA_STATUS_132,Enabled Status for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "ENA_STATUS_131,Enabled Status for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENA_STATUS_130,Enabled Status for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "ENA_STATUS_129,Enabled Status for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENA_STATUS_128,Enabled Status for slv_events_in[64]" "0,1"
group.long 0x300++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG0,"
bitfld.long 0x0 31. "ENABLE_31,Enable (set) for intr_in[31]" "0,1"
bitfld.long 0x0 30. "ENABLE_30,Enable (set) for intr_in[30]" "0,1"
bitfld.long 0x0 29. "ENABLE_29,Enable (set) for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "ENABLE_28,Enable (set) for intr_in[28]" "0,1"
bitfld.long 0x0 27. "ENABLE_27,Enable (set) for intr_in[27]" "0,1"
bitfld.long 0x0 26. "ENABLE_26,Enable (set) for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "ENABLE_25,Enable (set) for intr_in[25]" "0,1"
bitfld.long 0x0 24. "ENABLE_24,Enable (set) for intr_in[24]" "0,1"
bitfld.long 0x0 23. "ENABLE_23,Enable (set) for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "ENABLE_22,Enable (set) for intr_in[22]" "0,1"
bitfld.long 0x0 21. "ENABLE_21,Enable (set) for intr_in[21]" "0,1"
bitfld.long 0x0 20. "ENABLE_20,Enable (set) for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "ENABLE_19,Enable (set) for intr_in[19]" "0,1"
bitfld.long 0x0 18. "ENABLE_18,Enable (set) for intr_in[18]" "0,1"
bitfld.long 0x0 17. "ENABLE_17,Enable (set) for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "ENABLE_16,Enable (set) for intr_in[16]" "0,1"
bitfld.long 0x0 15. "ENABLE_15,Enable (set) for intr_in[15]" "0,1"
bitfld.long 0x0 14. "ENABLE_14,Enable (set) for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "ENABLE_13,Enable (set) for intr_in[13]" "0,1"
bitfld.long 0x0 12. "ENABLE_12,Enable (set) for intr_in[12]" "0,1"
bitfld.long 0x0 11. "ENABLE_11,Enable (set) for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "ENABLE_10,Enable (set) for intr_in[10]" "0,1"
bitfld.long 0x0 9. "ENABLE_9,Enable (set) for intr_in[9]" "0,1"
bitfld.long 0x0 8. "ENABLE_8,Enable (set) for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "ENABLE_7,Enable (set) for intr_in[7]" "0,1"
bitfld.long 0x0 6. "ENABLE_6,Enable (set) for intr_in[6]" "0,1"
bitfld.long 0x0 5. "ENABLE_5,Enable (set) for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "ENABLE_4,Enable (set) for intr_in[4]" "0,1"
bitfld.long 0x0 3. "ENABLE_3,Enable (set) for intr_in[3]" "0,1"
bitfld.long 0x0 2. "ENABLE_2,Enable (set) for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_1,Enable (set) for intr_in[1]" "0,1"
bitfld.long 0x0 0. "ENABLE_0,Enable (set) for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG1,"
bitfld.long 0x4 31. "ENABLE_63,Enable (set) for intr_in[63]" "0,1"
bitfld.long 0x4 30. "ENABLE_62,Enable (set) for intr_in[62]" "0,1"
bitfld.long 0x4 29. "ENABLE_61,Enable (set) for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "ENABLE_60,Enable (set) for intr_in[60]" "0,1"
bitfld.long 0x4 27. "ENABLE_59,Enable (set) for intr_in[59]" "0,1"
bitfld.long 0x4 26. "ENABLE_58,Enable (set) for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "ENABLE_57,Enable (set) for intr_in[57]" "0,1"
bitfld.long 0x4 24. "ENABLE_56,Enable (set) for intr_in[56]" "0,1"
bitfld.long 0x4 23. "ENABLE_55,Enable (set) for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "ENABLE_54,Enable (set) for intr_in[54]" "0,1"
bitfld.long 0x4 21. "ENABLE_53,Enable (set) for intr_in[53]" "0,1"
bitfld.long 0x4 20. "ENABLE_52,Enable (set) for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "ENABLE_51,Enable (set) for intr_in[51]" "0,1"
bitfld.long 0x4 18. "ENABLE_50,Enable (set) for intr_in[50]" "0,1"
bitfld.long 0x4 17. "ENABLE_49,Enable (set) for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "ENABLE_48,Enable (set) for intr_in[48]" "0,1"
bitfld.long 0x4 15. "ENABLE_47,Enable (set) for intr_in[47]" "0,1"
bitfld.long 0x4 14. "ENABLE_46,Enable (set) for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "ENABLE_45,Enable (set) for intr_in[45]" "0,1"
bitfld.long 0x4 12. "ENABLE_44,Enable (set) for intr_in[44]" "0,1"
bitfld.long 0x4 11. "ENABLE_43,Enable (set) for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "ENABLE_42,Enable (set) for intr_in[42]" "0,1"
bitfld.long 0x4 9. "ENABLE_41,Enable (set) for intr_in[41]" "0,1"
bitfld.long 0x4 8. "ENABLE_40,Enable (set) for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "ENABLE_39,Enable (set) for intr_in[39]" "0,1"
bitfld.long 0x4 6. "ENABLE_38,Enable (set) for intr_in[38]" "0,1"
bitfld.long 0x4 5. "ENABLE_37,Enable (set) for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "ENABLE_36,Enable (set) for intr_in[36]" "0,1"
bitfld.long 0x4 3. "ENABLE_35,Enable (set) for intr_in[35]" "0,1"
bitfld.long 0x4 2. "ENABLE_34,Enable (set) for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "ENABLE_33,Enable (set) for intr_in[33]" "0,1"
bitfld.long 0x4 0. "ENABLE_32,Enable (set) for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG2,"
bitfld.long 0x8 31. "ENABLE_95,Enable (set) for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "ENABLE_94,Enable (set) for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "ENABLE_93,Enable (set) for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "ENABLE_92,Enable (set) for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "ENABLE_91,Enable (set) for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "ENABLE_90,Enable (set) for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "ENABLE_89,Enable (set) for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "ENABLE_88,Enable (set) for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "ENABLE_87,Enable (set) for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "ENABLE_86,Enable (set) for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "ENABLE_85,Enable (set) for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "ENABLE_84,Enable (set) for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "ENABLE_83,Enable (set) for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "ENABLE_82,Enable (set) for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "ENABLE_81,Enable (set) for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "ENABLE_80,Enable (set) for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "ENABLE_79,Enable (set) for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "ENABLE_78,Enable (set) for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "ENABLE_77,Enable (set) for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "ENABLE_76,Enable (set) for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "ENABLE_75,Enable (set) for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "ENABLE_74,Enable (set) for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "ENABLE_73,Enable (set) for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "ENABLE_72,Enable (set) for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "ENABLE_71,Enable (set) for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "ENABLE_70,Enable (set) for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "ENABLE_69,Enable (set) for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "ENABLE_68,Enable (set) for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "ENABLE_67,Enable (set) for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "ENABLE_66,Enable (set) for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "ENABLE_65,Enable (set) for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "ENABLE_64,Enable (set) for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG3,"
bitfld.long 0xC 31. "ENABLE_127,Enable (set) for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "ENABLE_126,Enable (set) for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "ENABLE_125,Enable (set) for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "ENABLE_124,Enable (set) for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "ENABLE_123,Enable (set) for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "ENABLE_122,Enable (set) for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "ENABLE_121,Enable (set) for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "ENABLE_120,Enable (set) for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "ENABLE_119,Enable (set) for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "ENABLE_118,Enable (set) for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "ENABLE_117,Enable (set) for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "ENABLE_116,Enable (set) for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "ENABLE_115,Enable (set) for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "ENABLE_114,Enable (set) for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "ENABLE_113,Enable (set) for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "ENABLE_112,Enable (set) for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "ENABLE_111,Enable (set) for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "ENABLE_110,Enable (set) for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "ENABLE_109,Enable (set) for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "ENABLE_108,Enable (set) for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "ENABLE_107,Enable (set) for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "ENABLE_106,Enable (set) for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "ENABLE_105,Enable (set) for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "ENABLE_104,Enable (set) for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "ENABLE_103,Enable (set) for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "ENABLE_102,Enable (set) for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "ENABLE_101,Enable (set) for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "ENABLE_100,Enable (set) for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "ENABLE_99,Enable (set) for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "ENABLE_98,Enable (set) for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "ENABLE_97,Enable (set) for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "ENABLE_96,Enable (set) for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG4,"
bitfld.long 0x10 31. "ENABLE_159,Enable (set) for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENABLE_158,Enable (set) for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENABLE_157,Enable (set) for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_156,Enable (set) for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "ENABLE_155,Enable (set) for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENABLE_154,Enable (set) for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_153,Enable (set) for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENABLE_152,Enable (set) for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "ENABLE_151,Enable (set) for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_150,Enable (set) for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENABLE_149,Enable (set) for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENABLE_148,Enable (set) for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_147,Enable (set) for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENABLE_146,Enable (set) for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENABLE_145,Enable (set) for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_144,Enable (set) for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "ENABLE_143,Enable (set) for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENABLE_142,Enable (set) for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_141,Enable (set) for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENABLE_140,Enable (set) for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "ENABLE_139,Enable (set) for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_138,Enable (set) for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENABLE_137,Enable (set) for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENABLE_136,Enable (set) for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_135,Enable (set) for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENABLE_134,Enable (set) for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENABLE_133,Enable (set) for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_132,Enable (set) for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "ENABLE_131,Enable (set) for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENABLE_130,Enable (set) for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_129,Enable (set) for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENABLE_128,Enable (set) for slv_events_in[64]" "0,1"
group.long 0x380++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG0,"
bitfld.long 0x0 31. "ENABLE_31_CLR,Enable clear for intr_in[31]" "0,1"
bitfld.long 0x0 30. "ENABLE_30_CLR,Enable clear for intr_in[30]" "0,1"
bitfld.long 0x0 29. "ENABLE_29_CLR,Enable clear for intr_in[29]" "0,1"
newline
bitfld.long 0x0 28. "ENABLE_28_CLR,Enable clear for intr_in[28]" "0,1"
bitfld.long 0x0 27. "ENABLE_27_CLR,Enable clear for intr_in[27]" "0,1"
bitfld.long 0x0 26. "ENABLE_26_CLR,Enable clear for intr_in[26]" "0,1"
newline
bitfld.long 0x0 25. "ENABLE_25_CLR,Enable clear for intr_in[25]" "0,1"
bitfld.long 0x0 24. "ENABLE_24_CLR,Enable clear for intr_in[24]" "0,1"
bitfld.long 0x0 23. "ENABLE_23_CLR,Enable clear for intr_in[23]" "0,1"
newline
bitfld.long 0x0 22. "ENABLE_22_CLR,Enable clear for intr_in[22]" "0,1"
bitfld.long 0x0 21. "ENABLE_21_CLR,Enable clear for intr_in[21]" "0,1"
bitfld.long 0x0 20. "ENABLE_20_CLR,Enable clear for intr_in[20]" "0,1"
newline
bitfld.long 0x0 19. "ENABLE_19_CLR,Enable clear for intr_in[19]" "0,1"
bitfld.long 0x0 18. "ENABLE_18_CLR,Enable clear for intr_in[18]" "0,1"
bitfld.long 0x0 17. "ENABLE_17_CLR,Enable clear for intr_in[17]" "0,1"
newline
bitfld.long 0x0 16. "ENABLE_16_CLR,Enable clear for intr_in[16]" "0,1"
bitfld.long 0x0 15. "ENABLE_15_CLR,Enable clear for intr_in[15]" "0,1"
bitfld.long 0x0 14. "ENABLE_14_CLR,Enable clear for intr_in[14]" "0,1"
newline
bitfld.long 0x0 13. "ENABLE_13_CLR,Enable clear for intr_in[13]" "0,1"
bitfld.long 0x0 12. "ENABLE_12_CLR,Enable clear for intr_in[12]" "0,1"
bitfld.long 0x0 11. "ENABLE_11_CLR,Enable clear for intr_in[11]" "0,1"
newline
bitfld.long 0x0 10. "ENABLE_10_CLR,Enable clear for intr_in[10]" "0,1"
bitfld.long 0x0 9. "ENABLE_9_CLR,Enable clear for intr_in[9]" "0,1"
bitfld.long 0x0 8. "ENABLE_8_CLR,Enable clear for intr_in[8]" "0,1"
newline
bitfld.long 0x0 7. "ENABLE_7_CLR,Enable clear for intr_in[7]" "0,1"
bitfld.long 0x0 6. "ENABLE_6_CLR,Enable clear for intr_in[6]" "0,1"
bitfld.long 0x0 5. "ENABLE_5_CLR,Enable clear for intr_in[5]" "0,1"
newline
bitfld.long 0x0 4. "ENABLE_4_CLR,Enable clear for intr_in[4]" "0,1"
bitfld.long 0x0 3. "ENABLE_3_CLR,Enable clear for intr_in[3]" "0,1"
bitfld.long 0x0 2. "ENABLE_2_CLR,Enable clear for intr_in[2]" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_1_CLR,Enable clear for intr_in[1]" "0,1"
bitfld.long 0x0 0. "ENABLE_0_CLR,Enable clear for intr_in[0]" "0,1"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG1,"
bitfld.long 0x4 31. "ENABLE_63_CLR,Enable clear for intr_in[63]" "0,1"
bitfld.long 0x4 30. "ENABLE_62_CLR,Enable clear for intr_in[62]" "0,1"
bitfld.long 0x4 29. "ENABLE_61_CLR,Enable clear for intr_in[61]" "0,1"
newline
bitfld.long 0x4 28. "ENABLE_60_CLR,Enable clear for intr_in[60]" "0,1"
bitfld.long 0x4 27. "ENABLE_59_CLR,Enable clear for intr_in[59]" "0,1"
bitfld.long 0x4 26. "ENABLE_58_CLR,Enable clear for intr_in[58]" "0,1"
newline
bitfld.long 0x4 25. "ENABLE_57_CLR,Enable clear for intr_in[57]" "0,1"
bitfld.long 0x4 24. "ENABLE_56_CLR,Enable clear for intr_in[56]" "0,1"
bitfld.long 0x4 23. "ENABLE_55_CLR,Enable clear for intr_in[55]" "0,1"
newline
bitfld.long 0x4 22. "ENABLE_54_CLR,Enable clear for intr_in[54]" "0,1"
bitfld.long 0x4 21. "ENABLE_53_CLR,Enable clear for intr_in[53]" "0,1"
bitfld.long 0x4 20. "ENABLE_52_CLR,Enable clear for intr_in[52]" "0,1"
newline
bitfld.long 0x4 19. "ENABLE_51_CLR,Enable clear for intr_in[51]" "0,1"
bitfld.long 0x4 18. "ENABLE_50_CLR,Enable clear for intr_in[50]" "0,1"
bitfld.long 0x4 17. "ENABLE_49_CLR,Enable clear for intr_in[49]" "0,1"
newline
bitfld.long 0x4 16. "ENABLE_48_CLR,Enable clear for intr_in[48]" "0,1"
bitfld.long 0x4 15. "ENABLE_47_CLR,Enable clear for intr_in[47]" "0,1"
bitfld.long 0x4 14. "ENABLE_46_CLR,Enable clear for intr_in[46]" "0,1"
newline
bitfld.long 0x4 13. "ENABLE_45_CLR,Enable clear for intr_in[45]" "0,1"
bitfld.long 0x4 12. "ENABLE_44_CLR,Enable clear for intr_in[44]" "0,1"
bitfld.long 0x4 11. "ENABLE_43_CLR,Enable clear for intr_in[43]" "0,1"
newline
bitfld.long 0x4 10. "ENABLE_42_CLR,Enable clear for intr_in[42]" "0,1"
bitfld.long 0x4 9. "ENABLE_41_CLR,Enable clear for intr_in[41]" "0,1"
bitfld.long 0x4 8. "ENABLE_40_CLR,Enable clear for intr_in[40]" "0,1"
newline
bitfld.long 0x4 7. "ENABLE_39_CLR,Enable clear for intr_in[39]" "0,1"
bitfld.long 0x4 6. "ENABLE_38_CLR,Enable clear for intr_in[38]" "0,1"
bitfld.long 0x4 5. "ENABLE_37_CLR,Enable clear for intr_in[37]" "0,1"
newline
bitfld.long 0x4 4. "ENABLE_36_CLR,Enable clear for intr_in[36]" "0,1"
bitfld.long 0x4 3. "ENABLE_35_CLR,Enable clear for intr_in[35]" "0,1"
bitfld.long 0x4 2. "ENABLE_34_CLR,Enable clear for intr_in[34]" "0,1"
newline
bitfld.long 0x4 1. "ENABLE_33_CLR,Enable clear for intr_in[33]" "0,1"
bitfld.long 0x4 0. "ENABLE_32_CLR,Enable clear for intr_in[32]" "0,1"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG2,"
bitfld.long 0x8 31. "ENABLE_95_CLR,Enable clear for slv_events_in[31]" "0,1"
bitfld.long 0x8 30. "ENABLE_94_CLR,Enable clear for slv_events_in[30]" "0,1"
bitfld.long 0x8 29. "ENABLE_93_CLR,Enable clear for slv_events_in[29]" "0,1"
newline
bitfld.long 0x8 28. "ENABLE_92_CLR,Enable clear for slv_events_in[28]" "0,1"
bitfld.long 0x8 27. "ENABLE_91_CLR,Enable clear for slv_events_in[27]" "0,1"
bitfld.long 0x8 26. "ENABLE_90_CLR,Enable clear for slv_events_in[26]" "0,1"
newline
bitfld.long 0x8 25. "ENABLE_89_CLR,Enable clear for slv_events_in[25]" "0,1"
bitfld.long 0x8 24. "ENABLE_88_CLR,Enable clear for slv_events_in[24]" "0,1"
bitfld.long 0x8 23. "ENABLE_87_CLR,Enable clear for slv_events_in[23]" "0,1"
newline
bitfld.long 0x8 22. "ENABLE_86_CLR,Enable clear for slv_events_in[22]" "0,1"
bitfld.long 0x8 21. "ENABLE_85_CLR,Enable clear for slv_events_in[21]" "0,1"
bitfld.long 0x8 20. "ENABLE_84_CLR,Enable clear for slv_events_in[20]" "0,1"
newline
bitfld.long 0x8 19. "ENABLE_83_CLR,Enable clear for slv_events_in[19]" "0,1"
bitfld.long 0x8 18. "ENABLE_82_CLR,Enable clear for slv_events_in[18]" "0,1"
bitfld.long 0x8 17. "ENABLE_81_CLR,Enable clear for slv_events_in[17]" "0,1"
newline
bitfld.long 0x8 16. "ENABLE_80_CLR,Enable clear for slv_events_in[16]" "0,1"
bitfld.long 0x8 15. "ENABLE_79_CLR,Enable clear for slv_events_in[15]" "0,1"
bitfld.long 0x8 14. "ENABLE_78_CLR,Enable clear for slv_events_in[14]" "0,1"
newline
bitfld.long 0x8 13. "ENABLE_77_CLR,Enable clear for slv_events_in[13]" "0,1"
bitfld.long 0x8 12. "ENABLE_76_CLR,Enable clear for slv_events_in[12]" "0,1"
bitfld.long 0x8 11. "ENABLE_75_CLR,Enable clear for slv_events_in[11]" "0,1"
newline
bitfld.long 0x8 10. "ENABLE_74_CLR,Enable clear for slv_events_in[10]" "0,1"
bitfld.long 0x8 9. "ENABLE_73_CLR,Enable clear for slv_events_in[9]" "0,1"
bitfld.long 0x8 8. "ENABLE_72_CLR,Enable clear for slv_events_in[8]" "0,1"
newline
bitfld.long 0x8 7. "ENABLE_71_CLR,Enable clear for slv_events_in[7]" "0,1"
bitfld.long 0x8 6. "ENABLE_70_CLR,Enable clear for slv_events_in[6]" "0,1"
bitfld.long 0x8 5. "ENABLE_69_CLR,Enable clear for slv_events_in[5]" "0,1"
newline
bitfld.long 0x8 4. "ENABLE_68_CLR,Enable clear for slv_events_in[4]" "0,1"
bitfld.long 0x8 3. "ENABLE_67_CLR,Enable clear for slv_events_in[3]" "0,1"
bitfld.long 0x8 2. "ENABLE_66_CLR,Enable clear for slv_events_in[2]" "0,1"
newline
bitfld.long 0x8 1. "ENABLE_65_CLR,Enable clear for slv_events_in[1]" "0,1"
bitfld.long 0x8 0. "ENABLE_64_CLR,Enable clear for slv_events_in[0]" "0,1"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG3,"
bitfld.long 0xC 31. "ENABLE_127_CLR,Enable clear for slv_events_in[63]" "0,1"
bitfld.long 0xC 30. "ENABLE_126_CLR,Enable clear for slv_events_in[62]" "0,1"
bitfld.long 0xC 29. "ENABLE_125_CLR,Enable clear for slv_events_in[61]" "0,1"
newline
bitfld.long 0xC 28. "ENABLE_124_CLR,Enable clear for slv_events_in[60]" "0,1"
bitfld.long 0xC 27. "ENABLE_123_CLR,Enable clear for slv_events_in[59]" "0,1"
bitfld.long 0xC 26. "ENABLE_122_CLR,Enable clear for slv_events_in[58]" "0,1"
newline
bitfld.long 0xC 25. "ENABLE_121_CLR,Enable clear for slv_events_in[57]" "0,1"
bitfld.long 0xC 24. "ENABLE_120_CLR,Enable clear for slv_events_in[56]" "0,1"
bitfld.long 0xC 23. "ENABLE_119_CLR,Enable clear for slv_events_in[55]" "0,1"
newline
bitfld.long 0xC 22. "ENABLE_118_CLR,Enable clear for slv_events_in[54]" "0,1"
bitfld.long 0xC 21. "ENABLE_117_CLR,Enable clear for slv_events_in[53]" "0,1"
bitfld.long 0xC 20. "ENABLE_116_CLR,Enable clear for slv_events_in[52]" "0,1"
newline
bitfld.long 0xC 19. "ENABLE_115_CLR,Enable clear for slv_events_in[51]" "0,1"
bitfld.long 0xC 18. "ENABLE_114_CLR,Enable clear for slv_events_in[50]" "0,1"
bitfld.long 0xC 17. "ENABLE_113_CLR,Enable clear for slv_events_in[49]" "0,1"
newline
bitfld.long 0xC 16. "ENABLE_112_CLR,Enable clear for slv_events_in[48]" "0,1"
bitfld.long 0xC 15. "ENABLE_111_CLR,Enable clear for slv_events_in[47]" "0,1"
bitfld.long 0xC 14. "ENABLE_110_CLR,Enable clear for slv_events_in[46]" "0,1"
newline
bitfld.long 0xC 13. "ENABLE_109_CLR,Enable clear for slv_events_in[45]" "0,1"
bitfld.long 0xC 12. "ENABLE_108_CLR,Enable clear for slv_events_in[44]" "0,1"
bitfld.long 0xC 11. "ENABLE_107_CLR,Enable clear for slv_events_in[43]" "0,1"
newline
bitfld.long 0xC 10. "ENABLE_106_CLR,Enable clear for slv_events_in[42]" "0,1"
bitfld.long 0xC 9. "ENABLE_105_CLR,Enable clear for slv_events_in[41]" "0,1"
bitfld.long 0xC 8. "ENABLE_104_CLR,Enable clear for slv_events_in[40]" "0,1"
newline
bitfld.long 0xC 7. "ENABLE_103_CLR,Enable clear for slv_events_in[39]" "0,1"
bitfld.long 0xC 6. "ENABLE_102_CLR,Enable clear for slv_events_in[38]" "0,1"
bitfld.long 0xC 5. "ENABLE_101_CLR,Enable clear for slv_events_in[37]" "0,1"
newline
bitfld.long 0xC 4. "ENABLE_100_CLR,Enable clear for slv_events_in[36]" "0,1"
bitfld.long 0xC 3. "ENABLE_99_CLR,Enable clear for slv_events_in[35]" "0,1"
bitfld.long 0xC 2. "ENABLE_98_CLR,Enable clear for slv_events_in[34]" "0,1"
newline
bitfld.long 0xC 1. "ENABLE_97_CLR,Enable clear for slv_events_in[33]" "0,1"
bitfld.long 0xC 0. "ENABLE_96_CLR,Enable clear for slv_events_in[32]" "0,1"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG4,"
bitfld.long 0x10 31. "ENABLE_159_CLR,Enable clear for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENABLE_158_CLR,Enable clear for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENABLE_157_CLR,Enable clear for slv_events_in[93]" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_156_CLR,Enable clear for slv_events_in[92]" "0,1"
bitfld.long 0x10 27. "ENABLE_155_CLR,Enable clear for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENABLE_154_CLR,Enable clear for slv_events_in[90]" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_153_CLR,Enable clear for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENABLE_152_CLR,Enable clear for slv_events_in[88]" "0,1"
bitfld.long 0x10 23. "ENABLE_151_CLR,Enable clear for slv_events_in[87]" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_150_CLR,Enable clear for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENABLE_149_CLR,Enable clear for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENABLE_148_CLR,Enable clear for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_147_CLR,Enable clear for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENABLE_146_CLR,Enable clear for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENABLE_145_CLR,Enable clear for slv_events_in[81]" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_144_CLR,Enable clear for slv_events_in[80]" "0,1"
bitfld.long 0x10 15. "ENABLE_143_CLR,Enable clear for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENABLE_142_CLR,Enable clear for slv_events_in[78]" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_141_CLR,Enable clear for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENABLE_140_CLR,Enable clear for slv_events_in[76]" "0,1"
bitfld.long 0x10 11. "ENABLE_139_CLR,Enable clear for slv_events_in[75]" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_138_CLR,Enable clear for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENABLE_137_CLR,Enable clear for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENABLE_136_CLR,Enable clear for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_135_CLR,Enable clear for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENABLE_134_CLR,Enable clear for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENABLE_133_CLR,Enable clear for slv_events_in[69]" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_132_CLR,Enable clear for slv_events_in[68]" "0,1"
bitfld.long 0x10 3. "ENABLE_131_CLR,Enable clear for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENABLE_130_CLR,Enable clear for slv_events_in[66]" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_129_CLR,Enable clear for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENABLE_128_CLR,Enable clear for slv_events_in[64]" "0,1"
group.long 0x400++0x9F
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG0,"
hexmask.long.byte 0x0 24.--28. 1. "CH_MAP_3,Interrupt Channel Map for intr_in[3]"
hexmask.long.byte 0x0 16.--20. 1. "CH_MAP_2,Interrupt Channel Map for intr_in[2]"
hexmask.long.byte 0x0 8.--12. 1. "CH_MAP_1,Interrupt Channel Map for intr_in[1]"
newline
hexmask.long.byte 0x0 0.--4. 1. "CH_MAP_0,Interrupt Channel Map for intr_in[0]"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG1,"
hexmask.long.byte 0x4 24.--28. 1. "CH_MAP_7,Interrupt Channel Map for intr_in[7]"
hexmask.long.byte 0x4 16.--20. 1. "CH_MAP_6,Interrupt Channel Map for intr_in[6]"
hexmask.long.byte 0x4 8.--12. 1. "CH_MAP_5,Interrupt Channel Map for intr_in[5]"
newline
hexmask.long.byte 0x4 0.--4. 1. "CH_MAP_4,Interrupt Channel Map for intr_in[4]"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG2,"
hexmask.long.byte 0x8 24.--28. 1. "CH_MAP_11,Interrupt Channel Map for intr_in[11]"
hexmask.long.byte 0x8 16.--20. 1. "CH_MAP_10,Interrupt Channel Map for intr_in[10]"
hexmask.long.byte 0x8 8.--12. 1. "CH_MAP_9,Interrupt Channel Map for intr_in[9]"
newline
hexmask.long.byte 0x8 0.--4. 1. "CH_MAP_8,Interrupt Channel Map for intr_in[8]"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG3,"
hexmask.long.byte 0xC 24.--28. 1. "CH_MAP_15,Interrupt Channel Map for intr_in[15]"
hexmask.long.byte 0xC 16.--20. 1. "CH_MAP_14,Interrupt Channel Map for intr_in[14]"
hexmask.long.byte 0xC 8.--12. 1. "CH_MAP_13,Interrupt Channel Map for intr_in[13]"
newline
hexmask.long.byte 0xC 0.--4. 1. "CH_MAP_12,Interrupt Channel Map for intr_in[12]"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG4,"
hexmask.long.byte 0x10 24.--28. 1. "CH_MAP_19,Interrupt Channel Map for intr_in[19]"
hexmask.long.byte 0x10 16.--20. 1. "CH_MAP_18,Interrupt Channel Map for intr_in[18]"
hexmask.long.byte 0x10 8.--12. 1. "CH_MAP_17,Interrupt Channel Map for intr_in[17]"
newline
hexmask.long.byte 0x10 0.--4. 1. "CH_MAP_16,Interrupt Channel Map for intr_in[16]"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG5,"
hexmask.long.byte 0x14 24.--28. 1. "CH_MAP_23,Interrupt Channel Map for intr_in[23]"
hexmask.long.byte 0x14 16.--20. 1. "CH_MAP_22,Interrupt Channel Map for intr_in[22]"
hexmask.long.byte 0x14 8.--12. 1. "CH_MAP_21,Interrupt Channel Map for intr_in[21]"
newline
hexmask.long.byte 0x14 0.--4. 1. "CH_MAP_20,Interrupt Channel Map for intr_in[20]"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG6,"
hexmask.long.byte 0x18 24.--28. 1. "CH_MAP_27,Interrupt Channel Map for intr_in[27]"
hexmask.long.byte 0x18 16.--20. 1. "CH_MAP_26,Interrupt Channel Map for intr_in[26]"
hexmask.long.byte 0x18 8.--12. 1. "CH_MAP_25,Interrupt Channel Map for intr_in[25]"
newline
hexmask.long.byte 0x18 0.--4. 1. "CH_MAP_24,Interrupt Channel Map for intr_in[24]"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG7,"
hexmask.long.byte 0x1C 24.--28. 1. "CH_MAP_31,Interrupt Channel Map for intr_in[31]"
hexmask.long.byte 0x1C 16.--20. 1. "CH_MAP_30,Interrupt Channel Map for intr_in[30]"
hexmask.long.byte 0x1C 8.--12. 1. "CH_MAP_29,Interrupt Channel Map for intr_in[29]"
newline
hexmask.long.byte 0x1C 0.--4. 1. "CH_MAP_28,Interrupt Channel Map for intr_in[28]"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG8,"
hexmask.long.byte 0x20 24.--28. 1. "CH_MAP_35,Interrupt Channel Map for intr_in[35]"
hexmask.long.byte 0x20 16.--20. 1. "CH_MAP_34,Interrupt Channel Map for intr_in[34]"
hexmask.long.byte 0x20 8.--12. 1. "CH_MAP_33,Interrupt Channel Map for intr_in[33]"
newline
hexmask.long.byte 0x20 0.--4. 1. "CH_MAP_32,Interrupt Channel Map for intr_in[32]"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG9,"
hexmask.long.byte 0x24 24.--28. 1. "CH_MAP_39,Interrupt Channel Map for intr_in[39]"
hexmask.long.byte 0x24 16.--20. 1. "CH_MAP_38,Interrupt Channel Map for intr_in[38]"
hexmask.long.byte 0x24 8.--12. 1. "CH_MAP_37,Interrupt Channel Map for intr_in[37]"
newline
hexmask.long.byte 0x24 0.--4. 1. "CH_MAP_36,Interrupt Channel Map for intr_in[36]"
line.long 0x28 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG10,"
hexmask.long.byte 0x28 24.--28. 1. "CH_MAP_43,Interrupt Channel Map for intr_in[43]"
hexmask.long.byte 0x28 16.--20. 1. "CH_MAP_42,Interrupt Channel Map for intr_in[42]"
hexmask.long.byte 0x28 8.--12. 1. "CH_MAP_41,Interrupt Channel Map for intr_in[41]"
newline
hexmask.long.byte 0x28 0.--4. 1. "CH_MAP_40,Interrupt Channel Map for intr_in[40]"
line.long 0x2C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG11,"
hexmask.long.byte 0x2C 24.--28. 1. "CH_MAP_47,Interrupt Channel Map for intr_in[47]"
hexmask.long.byte 0x2C 16.--20. 1. "CH_MAP_46,Interrupt Channel Map for intr_in[46]"
hexmask.long.byte 0x2C 8.--12. 1. "CH_MAP_45,Interrupt Channel Map for intr_in[45]"
newline
hexmask.long.byte 0x2C 0.--4. 1. "CH_MAP_44,Interrupt Channel Map for intr_in[44]"
line.long 0x30 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG12,"
hexmask.long.byte 0x30 24.--28. 1. "CH_MAP_51,Interrupt Channel Map for intr_in[51]"
hexmask.long.byte 0x30 16.--20. 1. "CH_MAP_50,Interrupt Channel Map for intr_in[50]"
hexmask.long.byte 0x30 8.--12. 1. "CH_MAP_49,Interrupt Channel Map for intr_in[49]"
newline
hexmask.long.byte 0x30 0.--4. 1. "CH_MAP_48,Interrupt Channel Map for intr_in[48]"
line.long 0x34 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG13,"
hexmask.long.byte 0x34 24.--28. 1. "CH_MAP_55,Interrupt Channel Map for intr_in[55]"
hexmask.long.byte 0x34 16.--20. 1. "CH_MAP_54,Interrupt Channel Map for intr_in[54]"
hexmask.long.byte 0x34 8.--12. 1. "CH_MAP_53,Interrupt Channel Map for intr_in[53]"
newline
hexmask.long.byte 0x34 0.--4. 1. "CH_MAP_52,Interrupt Channel Map for intr_in[52]"
line.long 0x38 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG14,"
hexmask.long.byte 0x38 24.--28. 1. "CH_MAP_59,Interrupt Channel Map for intr_in[59]"
hexmask.long.byte 0x38 16.--20. 1. "CH_MAP_58,Interrupt Channel Map for intr_in[58]"
hexmask.long.byte 0x38 8.--12. 1. "CH_MAP_57,Interrupt Channel Map for intr_in[57]"
newline
hexmask.long.byte 0x38 0.--4. 1. "CH_MAP_56,Interrupt Channel Map for intr_in[56]"
line.long 0x3C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG15,"
hexmask.long.byte 0x3C 24.--28. 1. "CH_MAP_63,Interrupt Channel Map for intr_in[63]"
hexmask.long.byte 0x3C 16.--20. 1. "CH_MAP_62,Interrupt Channel Map for intr_in[62]"
hexmask.long.byte 0x3C 8.--12. 1. "CH_MAP_61,Interrupt Channel Map for intr_in[61]"
newline
hexmask.long.byte 0x3C 0.--4. 1. "CH_MAP_60,Interrupt Channel Map for intr_in[60]"
line.long 0x40 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG16,"
hexmask.long.byte 0x40 24.--28. 1. "CH_MAP_67,Interrupt Channel Map for slv_events_in[3]"
hexmask.long.byte 0x40 16.--20. 1. "CH_MAP_66,Interrupt Channel Map for slv_events_in[2]"
hexmask.long.byte 0x40 8.--12. 1. "CH_MAP_65,Interrupt Channel Map for slv_events_in[1]"
newline
hexmask.long.byte 0x40 0.--4. 1. "CH_MAP_64,Interrupt Channel Map for slv_events_in[0]"
line.long 0x44 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG17,"
hexmask.long.byte 0x44 24.--28. 1. "CH_MAP_71,Interrupt Channel Map for slv_events_in[7]"
hexmask.long.byte 0x44 16.--20. 1. "CH_MAP_70,Interrupt Channel Map for slv_events_in[6]"
hexmask.long.byte 0x44 8.--12. 1. "CH_MAP_69,Interrupt Channel Map for slv_events_in[5]"
newline
hexmask.long.byte 0x44 0.--4. 1. "CH_MAP_68,Interrupt Channel Map for slv_events_in[4]"
line.long 0x48 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG18,"
hexmask.long.byte 0x48 24.--28. 1. "CH_MAP_75,Interrupt Channel Map for slv_events_in[11]"
hexmask.long.byte 0x48 16.--20. 1. "CH_MAP_74,Interrupt Channel Map for slv_events_in[10]"
hexmask.long.byte 0x48 8.--12. 1. "CH_MAP_73,Interrupt Channel Map for slv_events_in[9]"
newline
hexmask.long.byte 0x48 0.--4. 1. "CH_MAP_72,Interrupt Channel Map for slv_events_in[8]"
line.long 0x4C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG19,"
hexmask.long.byte 0x4C 24.--28. 1. "CH_MAP_79,Interrupt Channel Map for slv_events_in[15]"
hexmask.long.byte 0x4C 16.--20. 1. "CH_MAP_78,Interrupt Channel Map for slv_events_in[14]"
hexmask.long.byte 0x4C 8.--12. 1. "CH_MAP_77,Interrupt Channel Map for slv_events_in[13]"
newline
hexmask.long.byte 0x4C 0.--4. 1. "CH_MAP_76,Interrupt Channel Map for slv_events_in[12]"
line.long 0x50 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG20,"
hexmask.long.byte 0x50 24.--28. 1. "CH_MAP_83,Interrupt Channel Map for slv_events_in[19]"
hexmask.long.byte 0x50 16.--20. 1. "CH_MAP_82,Interrupt Channel Map for slv_events_in[18]"
hexmask.long.byte 0x50 8.--12. 1. "CH_MAP_81,Interrupt Channel Map for slv_events_in[17]"
newline
hexmask.long.byte 0x50 0.--4. 1. "CH_MAP_80,Interrupt Channel Map for slv_events_in[16]"
line.long 0x54 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG21,"
hexmask.long.byte 0x54 24.--28. 1. "CH_MAP_87,Interrupt Channel Map for slv_events_in[23]"
hexmask.long.byte 0x54 16.--20. 1. "CH_MAP_86,Interrupt Channel Map for slv_events_in[22]"
hexmask.long.byte 0x54 8.--12. 1. "CH_MAP_85,Interrupt Channel Map for slv_events_in[21]"
newline
hexmask.long.byte 0x54 0.--4. 1. "CH_MAP_84,Interrupt Channel Map for slv_events_in[20]"
line.long 0x58 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG22,"
hexmask.long.byte 0x58 24.--28. 1. "CH_MAP_91,Interrupt Channel Map for slv_events_in[27]"
hexmask.long.byte 0x58 16.--20. 1. "CH_MAP_90,Interrupt Channel Map for slv_events_in[26]"
hexmask.long.byte 0x58 8.--12. 1. "CH_MAP_89,Interrupt Channel Map for slv_events_in[25]"
newline
hexmask.long.byte 0x58 0.--4. 1. "CH_MAP_88,Interrupt Channel Map for slv_events_in[24]"
line.long 0x5C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG23,"
hexmask.long.byte 0x5C 24.--28. 1. "CH_MAP_95,Interrupt Channel Map for slv_events_in[31]"
hexmask.long.byte 0x5C 16.--20. 1. "CH_MAP_94,Interrupt Channel Map for slv_events_in[30]"
hexmask.long.byte 0x5C 8.--12. 1. "CH_MAP_93,Interrupt Channel Map for slv_events_in[29]"
newline
hexmask.long.byte 0x5C 0.--4. 1. "CH_MAP_92,Interrupt Channel Map for slv_events_in[28]"
line.long 0x60 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG24,"
hexmask.long.byte 0x60 24.--28. 1. "CH_MAP_99,Interrupt Channel Map for slv_events_in[35]"
hexmask.long.byte 0x60 16.--20. 1. "CH_MAP_98,Interrupt Channel Map for slv_events_in[34]"
hexmask.long.byte 0x60 8.--12. 1. "CH_MAP_97,Interrupt Channel Map for slv_events_in[33]"
newline
hexmask.long.byte 0x60 0.--4. 1. "CH_MAP_96,Interrupt Channel Map for slv_events_in[32]"
line.long 0x64 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG25,"
hexmask.long.byte 0x64 24.--28. 1. "CH_MAP_103,Interrupt Channel Map for slv_events_in[39]"
hexmask.long.byte 0x64 16.--20. 1. "CH_MAP_102,Interrupt Channel Map for slv_events_in[38]"
hexmask.long.byte 0x64 8.--12. 1. "CH_MAP_101,Interrupt Channel Map for slv_events_in[37]"
newline
hexmask.long.byte 0x64 0.--4. 1. "CH_MAP_100,Interrupt Channel Map for slv_events_in[36]"
line.long 0x68 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG26,"
hexmask.long.byte 0x68 24.--28. 1. "CH_MAP_107,Interrupt Channel Map for slv_events_in[43]"
hexmask.long.byte 0x68 16.--20. 1. "CH_MAP_106,Interrupt Channel Map for slv_events_in[42]"
hexmask.long.byte 0x68 8.--12. 1. "CH_MAP_105,Interrupt Channel Map for slv_events_in[41]"
newline
hexmask.long.byte 0x68 0.--4. 1. "CH_MAP_104,Interrupt Channel Map for slv_events_in[40]"
line.long 0x6C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG27,"
hexmask.long.byte 0x6C 24.--28. 1. "CH_MAP_111,Interrupt Channel Map for slv_events_in[47]"
hexmask.long.byte 0x6C 16.--20. 1. "CH_MAP_110,Interrupt Channel Map for slv_events_in[46]"
hexmask.long.byte 0x6C 8.--12. 1. "CH_MAP_109,Interrupt Channel Map for slv_events_in[45]"
newline
hexmask.long.byte 0x6C 0.--4. 1. "CH_MAP_108,Interrupt Channel Map for slv_events_in[44]"
line.long 0x70 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG28,"
hexmask.long.byte 0x70 24.--28. 1. "CH_MAP_115,Interrupt Channel Map for slv_events_in[51]"
hexmask.long.byte 0x70 16.--20. 1. "CH_MAP_114,Interrupt Channel Map for slv_events_in[50]"
hexmask.long.byte 0x70 8.--12. 1. "CH_MAP_113,Interrupt Channel Map for slv_events_in[49]"
newline
hexmask.long.byte 0x70 0.--4. 1. "CH_MAP_112,Interrupt Channel Map for slv_events_in[48]"
line.long 0x74 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG29,"
hexmask.long.byte 0x74 24.--28. 1. "CH_MAP_119,Interrupt Channel Map for slv_events_in[55]"
hexmask.long.byte 0x74 16.--20. 1. "CH_MAP_118,Interrupt Channel Map for slv_events_in[54]"
hexmask.long.byte 0x74 8.--12. 1. "CH_MAP_117,Interrupt Channel Map for slv_events_in[53]"
newline
hexmask.long.byte 0x74 0.--4. 1. "CH_MAP_116,Interrupt Channel Map for slv_events_in[52]"
line.long 0x78 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG30,"
hexmask.long.byte 0x78 24.--28. 1. "CH_MAP_123,Interrupt Channel Map for slv_events_in[59]"
hexmask.long.byte 0x78 16.--20. 1. "CH_MAP_122,Interrupt Channel Map for slv_events_in[58]"
hexmask.long.byte 0x78 8.--12. 1. "CH_MAP_121,Interrupt Channel Map for slv_events_in[57]"
newline
hexmask.long.byte 0x78 0.--4. 1. "CH_MAP_120,Interrupt Channel Map for slv_events_in[56]"
line.long 0x7C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG31,"
hexmask.long.byte 0x7C 24.--28. 1. "CH_MAP_127,Interrupt Channel Map for slv_events_in[63]"
hexmask.long.byte 0x7C 16.--20. 1. "CH_MAP_126,Interrupt Channel Map for slv_events_in[62]"
hexmask.long.byte 0x7C 8.--12. 1. "CH_MAP_125,Interrupt Channel Map for slv_events_in[61]"
newline
hexmask.long.byte 0x7C 0.--4. 1. "CH_MAP_124,Interrupt Channel Map for slv_events_in[60]"
line.long 0x80 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG32,"
hexmask.long.byte 0x80 24.--28. 1. "CH_MAP_131,Interrupt Channel Map for slv_events_in[67]"
hexmask.long.byte 0x80 16.--20. 1. "CH_MAP_130,Interrupt Channel Map for slv_events_in[66]"
hexmask.long.byte 0x80 8.--12. 1. "CH_MAP_129,Interrupt Channel Map for slv_events_in[65]"
newline
hexmask.long.byte 0x80 0.--4. 1. "CH_MAP_128,Interrupt Channel Map for slv_events_in[64]"
line.long 0x84 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG33,"
hexmask.long.byte 0x84 24.--28. 1. "CH_MAP_135,Interrupt Channel Map for slv_events_in[71]"
hexmask.long.byte 0x84 16.--20. 1. "CH_MAP_134,Interrupt Channel Map for slv_events_in[70]"
hexmask.long.byte 0x84 8.--12. 1. "CH_MAP_133,Interrupt Channel Map for slv_events_in[69]"
newline
hexmask.long.byte 0x84 0.--4. 1. "CH_MAP_132,Interrupt Channel Map for slv_events_in[68]"
line.long 0x88 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG34,"
hexmask.long.byte 0x88 24.--28. 1. "CH_MAP_139,Interrupt Channel Map for slv_events_in[75]"
hexmask.long.byte 0x88 16.--20. 1. "CH_MAP_138,Interrupt Channel Map for slv_events_in[74]"
hexmask.long.byte 0x88 8.--12. 1. "CH_MAP_137,Interrupt Channel Map for slv_events_in[73]"
newline
hexmask.long.byte 0x88 0.--4. 1. "CH_MAP_136,Interrupt Channel Map for slv_events_in[72]"
line.long 0x8C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG35,"
hexmask.long.byte 0x8C 24.--28. 1. "CH_MAP_143,Interrupt Channel Map for slv_events_in[79]"
hexmask.long.byte 0x8C 16.--20. 1. "CH_MAP_142,Interrupt Channel Map for slv_events_in[78]"
hexmask.long.byte 0x8C 8.--12. 1. "CH_MAP_141,Interrupt Channel Map for slv_events_in[77]"
newline
hexmask.long.byte 0x8C 0.--4. 1. "CH_MAP_140,Interrupt Channel Map for slv_events_in[76]"
line.long 0x90 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG36,"
hexmask.long.byte 0x90 24.--28. 1. "CH_MAP_147,Interrupt Channel Map for slv_events_in[83]"
hexmask.long.byte 0x90 16.--20. 1. "CH_MAP_146,Interrupt Channel Map for slv_events_in[82]"
hexmask.long.byte 0x90 8.--12. 1. "CH_MAP_145,Interrupt Channel Map for slv_events_in[81]"
newline
hexmask.long.byte 0x90 0.--4. 1. "CH_MAP_144,Interrupt Channel Map for slv_events_in[80]"
line.long 0x94 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG37,"
hexmask.long.byte 0x94 24.--28. 1. "CH_MAP_151,Interrupt Channel Map for slv_events_in[87]"
hexmask.long.byte 0x94 16.--20. 1. "CH_MAP_150,Interrupt Channel Map for slv_events_in[86]"
hexmask.long.byte 0x94 8.--12. 1. "CH_MAP_149,Interrupt Channel Map for slv_events_in[85]"
newline
hexmask.long.byte 0x94 0.--4. 1. "CH_MAP_148,Interrupt Channel Map for slv_events_in[84]"
line.long 0x98 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG38,"
hexmask.long.byte 0x98 24.--28. 1. "CH_MAP_155,Interrupt Channel Map for slv_events_in[91]"
hexmask.long.byte 0x98 16.--20. 1. "CH_MAP_154,Interrupt Channel Map for slv_events_in[90]"
hexmask.long.byte 0x98 8.--12. 1. "CH_MAP_153,Interrupt Channel Map for slv_events_in[89]"
newline
hexmask.long.byte 0x98 0.--4. 1. "CH_MAP_152,Interrupt Channel Map for slv_events_in[88]"
line.long 0x9C "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG39,"
hexmask.long.byte 0x9C 24.--28. 1. "CH_MAP_159,Interrupt Channel Map for slv_events_in[95]"
hexmask.long.byte 0x9C 16.--20. 1. "CH_MAP_158,Interrupt Channel Map for slv_events_in[94]"
hexmask.long.byte 0x9C 8.--12. 1. "CH_MAP_157,Interrupt Channel Map for slv_events_in[93]"
newline
hexmask.long.byte 0x9C 0.--4. 1. "CH_MAP_156,Interrupt Channel Map for slv_events_in[92]"
group.long 0x800++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG0,"
hexmask.long.byte 0x0 24.--28. 1. "HINT_MAP_3,Host Interrupt Map for Channel 3"
hexmask.long.byte 0x0 16.--20. 1. "HINT_MAP_2,Host Interrupt Map for Channel 2"
hexmask.long.byte 0x0 8.--12. 1. "HINT_MAP_1,Host Interrupt Map for Channel 1"
newline
hexmask.long.byte 0x0 0.--4. 1. "HINT_MAP_0,Host Interrupt Map for Channel 0"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG1,"
hexmask.long.byte 0x4 24.--28. 1. "HINT_MAP_7,Host Interrupt Map for Channel 7"
hexmask.long.byte 0x4 16.--20. 1. "HINT_MAP_6,Host Interrupt Map for Channel 6"
hexmask.long.byte 0x4 8.--12. 1. "HINT_MAP_5,Host Interrupt Map for Channel 5"
newline
hexmask.long.byte 0x4 0.--4. 1. "HINT_MAP_4,Host Interrupt Map for Channel 4"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG2,"
hexmask.long.byte 0x8 24.--28. 1. "HINT_MAP_11,Host Interrupt Map for Channel 11"
hexmask.long.byte 0x8 16.--20. 1. "HINT_MAP_10,Host Interrupt Map for Channel 10"
hexmask.long.byte 0x8 8.--12. 1. "HINT_MAP_9,Host Interrupt Map for Channel 9"
newline
hexmask.long.byte 0x8 0.--4. 1. "HINT_MAP_8,Host Interrupt Map for Channel 8"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG3,"
hexmask.long.byte 0xC 24.--28. 1. "HINT_MAP_15,Host Interrupt Map for Channel 15"
hexmask.long.byte 0xC 16.--20. 1. "HINT_MAP_14,Host Interrupt Map for Channel 14"
hexmask.long.byte 0xC 8.--12. 1. "HINT_MAP_13,Host Interrupt Map for Channel 13"
newline
hexmask.long.byte 0xC 0.--4. 1. "HINT_MAP_12,Host Interrupt Map for Channel 12"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG4,"
hexmask.long.byte 0x10 24.--28. 1. "HINT_MAP_19,Host Interrupt Map for Channel 19"
hexmask.long.byte 0x10 16.--20. 1. "HINT_MAP_18,Host Interrupt Map for Channel 18"
hexmask.long.byte 0x10 8.--12. 1. "HINT_MAP_17,Host Interrupt Map for Channel 17"
newline
hexmask.long.byte 0x10 0.--4. 1. "HINT_MAP_16,Host Interrupt Map for Channel 16"
rgroup.long 0x900++0x4F
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG0,"
bitfld.long 0x0 31. "NONE_HINT_0,No interrupt pending flag" "0,1"
hexmask.long.word 0x0 0.--9. 1. "PRI_HINT_0,Host Int 0 Prioritized Interrupt"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG1,"
bitfld.long 0x4 31. "NONE_HINT_1,No interrupt pending flag" "0,1"
hexmask.long.word 0x4 0.--9. 1. "PRI_HINT_1,Host Int 1 Prioritized Interrupt"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG2,"
bitfld.long 0x8 31. "NONE_HINT_2,No interrupt pending flag" "0,1"
hexmask.long.word 0x8 0.--9. 1. "PRI_HINT_2,Host Int 2 Prioritized Interrupt"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG3,"
bitfld.long 0xC 31. "NONE_HINT_3,No interrupt pending flag" "0,1"
hexmask.long.word 0xC 0.--9. 1. "PRI_HINT_3,Host Int 3 Prioritized Interrupt"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG4,"
bitfld.long 0x10 31. "NONE_HINT_4,No interrupt pending flag" "0,1"
hexmask.long.word 0x10 0.--9. 1. "PRI_HINT_4,Host Int 4 Prioritized Interrupt"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG5,"
bitfld.long 0x14 31. "NONE_HINT_5,No interrupt pending flag" "0,1"
hexmask.long.word 0x14 0.--9. 1. "PRI_HINT_5,Host Int 5 Prioritized Interrupt"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG6,"
bitfld.long 0x18 31. "NONE_HINT_6,No interrupt pending flag" "0,1"
hexmask.long.word 0x18 0.--9. 1. "PRI_HINT_6,Host Int 6 Prioritized Interrupt"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG7,"
bitfld.long 0x1C 31. "NONE_HINT_7,No interrupt pending flag" "0,1"
hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT_7,Host Int 7 Prioritized Interrupt"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG8,"
bitfld.long 0x20 31. "NONE_HINT_8,No interrupt pending flag" "0,1"
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT_8,Host Int 8 Prioritized Interrupt"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG9,"
bitfld.long 0x24 31. "NONE_HINT_9,No interrupt pending flag" "0,1"
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT_9,Host Int 9 Prioritized Interrupt"
line.long 0x28 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG10,"
bitfld.long 0x28 31. "NONE_HINT_10,No interrupt pending flag" "0,1"
hexmask.long.word 0x28 0.--9. 1. "PRI_HINT_10,Host Int 10 Prioritized Interrupt"
line.long 0x2C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG11,"
bitfld.long 0x2C 31. "NONE_HINT_11,No interrupt pending flag" "0,1"
hexmask.long.word 0x2C 0.--9. 1. "PRI_HINT_11,Host Int 11 Prioritized Interrupt"
line.long 0x30 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG12,"
bitfld.long 0x30 31. "NONE_HINT_12,No interrupt pending flag" "0,1"
hexmask.long.word 0x30 0.--9. 1. "PRI_HINT_12,Host Int 12 Prioritized Interrupt"
line.long 0x34 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG13,"
bitfld.long 0x34 31. "NONE_HINT_13,No interrupt pending flag" "0,1"
hexmask.long.word 0x34 0.--9. 1. "PRI_HINT_13,Host Int 13 Prioritized Interrupt"
line.long 0x38 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG14,"
bitfld.long 0x38 31. "NONE_HINT_14,No interrupt pending flag" "0,1"
hexmask.long.word 0x38 0.--9. 1. "PRI_HINT_14,Host Int 14 Prioritized Interrupt"
line.long 0x3C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG15,"
bitfld.long 0x3C 31. "NONE_HINT_15,No interrupt pending flag" "0,1"
hexmask.long.word 0x3C 0.--9. 1. "PRI_HINT_15,Host Int 15 Prioritized Interrupt"
line.long 0x40 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG16,"
bitfld.long 0x40 31. "NONE_HINT_16,No interrupt pending flag" "0,1"
hexmask.long.word 0x40 0.--9. 1. "PRI_HINT_16,Host Int 16 Prioritized Interrupt"
line.long 0x44 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG17,"
bitfld.long 0x44 31. "NONE_HINT_17,No interrupt pending flag" "0,1"
hexmask.long.word 0x44 0.--9. 1. "PRI_HINT_17,Host Int 17 Prioritized Interrupt"
line.long 0x48 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG18,"
bitfld.long 0x48 31. "NONE_HINT_18,No interrupt pending flag" "0,1"
hexmask.long.word 0x48 0.--9. 1. "PRI_HINT_18,Host Int 18 Prioritized Interrupt"
line.long 0x4C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG19,"
bitfld.long 0x4C 31. "NONE_HINT_19,No interrupt pending flag" "0,1"
hexmask.long.word 0x4C 0.--9. 1. "PRI_HINT_19,Host Int 19 Prioritized Interrupt"
group.long 0xD00++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG0,"
bitfld.long 0x0 31. "POLARITY_31,Polarity for intr_in[31] 0=low" "0: low,?"
bitfld.long 0x0 30. "POLARITY_30,Polarity for intr_in[30] 0=low" "0: low,?"
bitfld.long 0x0 29. "POLARITY_29,Polarity for intr_in[29] 0=low" "0: low,?"
newline
bitfld.long 0x0 28. "POLARITY_28,Polarity for intr_in[28] 0=low" "0: low,?"
bitfld.long 0x0 27. "POLARITY_27,Polarity for intr_in[27] 0=low" "0: low,?"
bitfld.long 0x0 26. "POLARITY_26,Polarity for intr_in[26] 0=low" "0: low,?"
newline
bitfld.long 0x0 25. "POLARITY_25,Polarity for intr_in[25] 0=low" "0: low,?"
bitfld.long 0x0 24. "POLARITY_24,Polarity for intr_in[24] 0=low" "0: low,?"
bitfld.long 0x0 23. "POLARITY_23,Polarity for intr_in[23] 0=low" "0: low,?"
newline
bitfld.long 0x0 22. "POLARITY_22,Polarity for intr_in[22] 0=low" "0: low,?"
bitfld.long 0x0 21. "POLARITY_21,Polarity for intr_in[21] 0=low" "0: low,?"
bitfld.long 0x0 20. "POLARITY_20,Polarity for intr_in[20] 0=low" "0: low,?"
newline
bitfld.long 0x0 19. "POLARITY_19,Polarity for intr_in[19] 0=low" "0: low,?"
bitfld.long 0x0 18. "POLARITY_18,Polarity for intr_in[18] 0=low" "0: low,?"
bitfld.long 0x0 17. "POLARITY_17,Polarity for intr_in[17] 0=low" "0: low,?"
newline
bitfld.long 0x0 16. "POLARITY_16,Polarity for intr_in[16] 0=low" "0: low,?"
bitfld.long 0x0 15. "POLARITY_15,Polarity for intr_in[15] 0=low" "0: low,?"
bitfld.long 0x0 14. "POLARITY_14,Polarity for intr_in[14] 0=low" "0: low,?"
newline
bitfld.long 0x0 13. "POLARITY_13,Polarity for intr_in[13] 0=low" "0: low,?"
bitfld.long 0x0 12. "POLARITY_12,Polarity for intr_in[12] 0=low" "0: low,?"
bitfld.long 0x0 11. "POLARITY_11,Polarity for intr_in[11] 0=low" "0: low,?"
newline
bitfld.long 0x0 10. "POLARITY_10,Polarity for intr_in[10] 0=low" "0: low,?"
bitfld.long 0x0 9. "POLARITY_9,Polarity for intr_in[9] 0=low" "0: low,?"
bitfld.long 0x0 8. "POLARITY_8,Polarity for intr_in[8] 0=low" "0: low,?"
newline
bitfld.long 0x0 7. "POLARITY_7,Polarity for intr_in[7] 0=low" "0: low,?"
bitfld.long 0x0 6. "POLARITY_6,Polarity for intr_in[6] 0=low" "0: low,?"
bitfld.long 0x0 5. "POLARITY_5,Polarity for intr_in[5] 0=low" "0: low,?"
newline
bitfld.long 0x0 4. "POLARITY_4,Polarity for intr_in[4] 0=low" "0: low,?"
bitfld.long 0x0 3. "POLARITY_3,Polarity for intr_in[3] 0=low" "0: low,?"
bitfld.long 0x0 2. "POLARITY_2,Polarity for intr_in[2] 0=low" "0: low,?"
newline
bitfld.long 0x0 1. "POLARITY_1,Polarity for intr_in[1] 0=low" "0: low,?"
bitfld.long 0x0 0. "POLARITY_0,Polarity for intr_in[0] 0=low" "0: low,?"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG1,"
bitfld.long 0x4 31. "POLARITY_63,Polarity for intr_in[63] 0=low" "0: low,?"
bitfld.long 0x4 30. "POLARITY_62,Polarity for intr_in[62] 0=low" "0: low,?"
bitfld.long 0x4 29. "POLARITY_61,Polarity for intr_in[61] 0=low" "0: low,?"
newline
bitfld.long 0x4 28. "POLARITY_60,Polarity for intr_in[60] 0=low" "0: low,?"
bitfld.long 0x4 27. "POLARITY_59,Polarity for intr_in[59] 0=low" "0: low,?"
bitfld.long 0x4 26. "POLARITY_58,Polarity for intr_in[58] 0=low" "0: low,?"
newline
bitfld.long 0x4 25. "POLARITY_57,Polarity for intr_in[57] 0=low" "0: low,?"
bitfld.long 0x4 24. "POLARITY_56,Polarity for intr_in[56] 0=low" "0: low,?"
bitfld.long 0x4 23. "POLARITY_55,Polarity for intr_in[55] 0=low" "0: low,?"
newline
bitfld.long 0x4 22. "POLARITY_54,Polarity for intr_in[54] 0=low" "0: low,?"
bitfld.long 0x4 21. "POLARITY_53,Polarity for intr_in[53] 0=low" "0: low,?"
bitfld.long 0x4 20. "POLARITY_52,Polarity for intr_in[52] 0=low" "0: low,?"
newline
bitfld.long 0x4 19. "POLARITY_51,Polarity for intr_in[51] 0=low" "0: low,?"
bitfld.long 0x4 18. "POLARITY_50,Polarity for intr_in[50] 0=low" "0: low,?"
bitfld.long 0x4 17. "POLARITY_49,Polarity for intr_in[49] 0=low" "0: low,?"
newline
bitfld.long 0x4 16. "POLARITY_48,Polarity for intr_in[48] 0=low" "0: low,?"
bitfld.long 0x4 15. "POLARITY_47,Polarity for intr_in[47] 0=low" "0: low,?"
bitfld.long 0x4 14. "POLARITY_46,Polarity for intr_in[46] 0=low" "0: low,?"
newline
bitfld.long 0x4 13. "POLARITY_45,Polarity for intr_in[45] 0=low" "0: low,?"
bitfld.long 0x4 12. "POLARITY_44,Polarity for intr_in[44] 0=low" "0: low,?"
bitfld.long 0x4 11. "POLARITY_43,Polarity for intr_in[43] 0=low" "0: low,?"
newline
bitfld.long 0x4 10. "POLARITY_42,Polarity for intr_in[42] 0=low" "0: low,?"
bitfld.long 0x4 9. "POLARITY_41,Polarity for intr_in[41] 0=low" "0: low,?"
bitfld.long 0x4 8. "POLARITY_40,Polarity for intr_in[40] 0=low" "0: low,?"
newline
bitfld.long 0x4 7. "POLARITY_39,Polarity for intr_in[39] 0=low" "0: low,?"
bitfld.long 0x4 6. "POLARITY_38,Polarity for intr_in[38] 0=low" "0: low,?"
bitfld.long 0x4 5. "POLARITY_37,Polarity for intr_in[37] 0=low" "0: low,?"
newline
bitfld.long 0x4 4. "POLARITY_36,Polarity for intr_in[36] 0=low" "0: low,?"
bitfld.long 0x4 3. "POLARITY_35,Polarity for intr_in[35] 0=low" "0: low,?"
bitfld.long 0x4 2. "POLARITY_34,Polarity for intr_in[34] 0=low" "0: low,?"
newline
bitfld.long 0x4 1. "POLARITY_33,Polarity for intr_in[33] 0=low" "0: low,?"
bitfld.long 0x4 0. "POLARITY_32,Polarity for intr_in[32] 0=low" "0: low,?"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG2,"
bitfld.long 0x8 31. "POLARITY_95,Polarity for slv_events_in[31] 0=low" "0: low,?"
bitfld.long 0x8 30. "POLARITY_94,Polarity for slv_events_in[30] 0=low" "0: low,?"
bitfld.long 0x8 29. "POLARITY_93,Polarity for slv_events_in[29] 0=low" "0: low,?"
newline
bitfld.long 0x8 28. "POLARITY_92,Polarity for slv_events_in[28] 0=low" "0: low,?"
bitfld.long 0x8 27. "POLARITY_91,Polarity for slv_events_in[27] 0=low" "0: low,?"
bitfld.long 0x8 26. "POLARITY_90,Polarity for slv_events_in[26] 0=low" "0: low,?"
newline
bitfld.long 0x8 25. "POLARITY_89,Polarity for slv_events_in[25] 0=low" "0: low,?"
bitfld.long 0x8 24. "POLARITY_88,Polarity for slv_events_in[24] 0=low" "0: low,?"
bitfld.long 0x8 23. "POLARITY_87,Polarity for slv_events_in[23] 0=low" "0: low,?"
newline
bitfld.long 0x8 22. "POLARITY_86,Polarity for slv_events_in[22] 0=low" "0: low,?"
bitfld.long 0x8 21. "POLARITY_85,Polarity for slv_events_in[21] 0=low" "0: low,?"
bitfld.long 0x8 20. "POLARITY_84,Polarity for slv_events_in[20] 0=low" "0: low,?"
newline
bitfld.long 0x8 19. "POLARITY_83,Polarity for slv_events_in[19] 0=low" "0: low,?"
bitfld.long 0x8 18. "POLARITY_82,Polarity for slv_events_in[18] 0=low" "0: low,?"
bitfld.long 0x8 17. "POLARITY_81,Polarity for slv_events_in[17] 0=low" "0: low,?"
newline
bitfld.long 0x8 16. "POLARITY_80,Polarity for slv_events_in[16] 0=low" "0: low,?"
bitfld.long 0x8 15. "POLARITY_79,Polarity for slv_events_in[15] 0=low" "0: low,?"
bitfld.long 0x8 14. "POLARITY_78,Polarity for slv_events_in[14] 0=low" "0: low,?"
newline
bitfld.long 0x8 13. "POLARITY_77,Polarity for slv_events_in[13] 0=low" "0: low,?"
bitfld.long 0x8 12. "POLARITY_76,Polarity for slv_events_in[12] 0=low" "0: low,?"
bitfld.long 0x8 11. "POLARITY_75,Polarity for slv_events_in[11] 0=low" "0: low,?"
newline
bitfld.long 0x8 10. "POLARITY_74,Polarity for slv_events_in[10] 0=low" "0: low,?"
bitfld.long 0x8 9. "POLARITY_73,Polarity for slv_events_in[9] 0=low" "0: low,?"
bitfld.long 0x8 8. "POLARITY_72,Polarity for slv_events_in[8] 0=low" "0: low,?"
newline
bitfld.long 0x8 7. "POLARITY_71,Polarity for slv_events_in[7] 0=low" "0: low,?"
bitfld.long 0x8 6. "POLARITY_70,Polarity for slv_events_in[6] 0=low" "0: low,?"
bitfld.long 0x8 5. "POLARITY_69,Polarity for slv_events_in[5] 0=low" "0: low,?"
newline
bitfld.long 0x8 4. "POLARITY_68,Polarity for slv_events_in[4] 0=low" "0: low,?"
bitfld.long 0x8 3. "POLARITY_67,Polarity for slv_events_in[3] 0=low" "0: low,?"
bitfld.long 0x8 2. "POLARITY_66,Polarity for slv_events_in[2] 0=low" "0: low,?"
newline
bitfld.long 0x8 1. "POLARITY_65,Polarity for slv_events_in[1] 0=low" "0: low,?"
bitfld.long 0x8 0. "POLARITY_64,Polarity for slv_events_in[0] 0=low" "0: low,?"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG3,"
bitfld.long 0xC 31. "POLARITY_127,Polarity for slv_events_in[63] 0=low" "0: low,?"
bitfld.long 0xC 30. "POLARITY_126,Polarity for slv_events_in[62] 0=low" "0: low,?"
bitfld.long 0xC 29. "POLARITY_125,Polarity for slv_events_in[61] 0=low" "0: low,?"
newline
bitfld.long 0xC 28. "POLARITY_124,Polarity for slv_events_in[60] 0=low" "0: low,?"
bitfld.long 0xC 27. "POLARITY_123,Polarity for slv_events_in[59] 0=low" "0: low,?"
bitfld.long 0xC 26. "POLARITY_122,Polarity for slv_events_in[58] 0=low" "0: low,?"
newline
bitfld.long 0xC 25. "POLARITY_121,Polarity for slv_events_in[57] 0=low" "0: low,?"
bitfld.long 0xC 24. "POLARITY_120,Polarity for slv_events_in[56] 0=low" "0: low,?"
bitfld.long 0xC 23. "POLARITY_119,Polarity for slv_events_in[55] 0=low" "0: low,?"
newline
bitfld.long 0xC 22. "POLARITY_118,Polarity for slv_events_in[54] 0=low" "0: low,?"
bitfld.long 0xC 21. "POLARITY_117,Polarity for slv_events_in[53] 0=low" "0: low,?"
bitfld.long 0xC 20. "POLARITY_116,Polarity for slv_events_in[52] 0=low" "0: low,?"
newline
bitfld.long 0xC 19. "POLARITY_115,Polarity for slv_events_in[51] 0=low" "0: low,?"
bitfld.long 0xC 18. "POLARITY_114,Polarity for slv_events_in[50] 0=low" "0: low,?"
bitfld.long 0xC 17. "POLARITY_113,Polarity for slv_events_in[49] 0=low" "0: low,?"
newline
bitfld.long 0xC 16. "POLARITY_112,Polarity for slv_events_in[48] 0=low" "0: low,?"
bitfld.long 0xC 15. "POLARITY_111,Polarity for slv_events_in[47] 0=low" "0: low,?"
bitfld.long 0xC 14. "POLARITY_110,Polarity for slv_events_in[46] 0=low" "0: low,?"
newline
bitfld.long 0xC 13. "POLARITY_109,Polarity for slv_events_in[45] 0=low" "0: low,?"
bitfld.long 0xC 12. "POLARITY_108,Polarity for slv_events_in[44] 0=low" "0: low,?"
bitfld.long 0xC 11. "POLARITY_107,Polarity for slv_events_in[43] 0=low" "0: low,?"
newline
bitfld.long 0xC 10. "POLARITY_106,Polarity for slv_events_in[42] 0=low" "0: low,?"
bitfld.long 0xC 9. "POLARITY_105,Polarity for slv_events_in[41] 0=low" "0: low,?"
bitfld.long 0xC 8. "POLARITY_104,Polarity for slv_events_in[40] 0=low" "0: low,?"
newline
bitfld.long 0xC 7. "POLARITY_103,Polarity for slv_events_in[39] 0=low" "0: low,?"
bitfld.long 0xC 6. "POLARITY_102,Polarity for slv_events_in[38] 0=low" "0: low,?"
bitfld.long 0xC 5. "POLARITY_101,Polarity for slv_events_in[37] 0=low" "0: low,?"
newline
bitfld.long 0xC 4. "POLARITY_100,Polarity for slv_events_in[36] 0=low" "0: low,?"
bitfld.long 0xC 3. "POLARITY_99,Polarity for slv_events_in[35] 0=low" "0: low,?"
bitfld.long 0xC 2. "POLARITY_98,Polarity for slv_events_in[34] 0=low" "0: low,?"
newline
bitfld.long 0xC 1. "POLARITY_97,Polarity for slv_events_in[33] 0=low" "0: low,?"
bitfld.long 0xC 0. "POLARITY_96,Polarity for slv_events_in[32] 0=low" "0: low,?"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG4,"
bitfld.long 0x10 31. "POLARITY_159,Polarity for slv_events_in[95] 0=low" "0: low,?"
bitfld.long 0x10 30. "POLARITY_158,Polarity for slv_events_in[94] 0=low" "0: low,?"
bitfld.long 0x10 29. "POLARITY_157,Polarity for slv_events_in[93] 0=low" "0: low,?"
newline
bitfld.long 0x10 28. "POLARITY_156,Polarity for slv_events_in[92] 0=low" "0: low,?"
bitfld.long 0x10 27. "POLARITY_155,Polarity for slv_events_in[91] 0=low" "0: low,?"
bitfld.long 0x10 26. "POLARITY_154,Polarity for slv_events_in[90] 0=low" "0: low,?"
newline
bitfld.long 0x10 25. "POLARITY_153,Polarity for slv_events_in[89] 0=low" "0: low,?"
bitfld.long 0x10 24. "POLARITY_152,Polarity for slv_events_in[88] 0=low" "0: low,?"
bitfld.long 0x10 23. "POLARITY_151,Polarity for slv_events_in[87] 0=low" "0: low,?"
newline
bitfld.long 0x10 22. "POLARITY_150,Polarity for slv_events_in[86] 0=low" "0: low,?"
bitfld.long 0x10 21. "POLARITY_149,Polarity for slv_events_in[85] 0=low" "0: low,?"
bitfld.long 0x10 20. "POLARITY_148,Polarity for slv_events_in[84] 0=low" "0: low,?"
newline
bitfld.long 0x10 19. "POLARITY_147,Polarity for slv_events_in[83] 0=low" "0: low,?"
bitfld.long 0x10 18. "POLARITY_146,Polarity for slv_events_in[82] 0=low" "0: low,?"
bitfld.long 0x10 17. "POLARITY_145,Polarity for slv_events_in[81] 0=low" "0: low,?"
newline
bitfld.long 0x10 16. "POLARITY_144,Polarity for slv_events_in[80] 0=low" "0: low,?"
bitfld.long 0x10 15. "POLARITY_143,Polarity for slv_events_in[79] 0=low" "0: low,?"
bitfld.long 0x10 14. "POLARITY_142,Polarity for slv_events_in[78] 0=low" "0: low,?"
newline
bitfld.long 0x10 13. "POLARITY_141,Polarity for slv_events_in[77] 0=low" "0: low,?"
bitfld.long 0x10 12. "POLARITY_140,Polarity for slv_events_in[76] 0=low" "0: low,?"
bitfld.long 0x10 11. "POLARITY_139,Polarity for slv_events_in[75] 0=low" "0: low,?"
newline
bitfld.long 0x10 10. "POLARITY_138,Polarity for slv_events_in[74] 0=low" "0: low,?"
bitfld.long 0x10 9. "POLARITY_137,Polarity for slv_events_in[73] 0=low" "0: low,?"
bitfld.long 0x10 8. "POLARITY_136,Polarity for slv_events_in[72] 0=low" "0: low,?"
newline
bitfld.long 0x10 7. "POLARITY_135,Polarity for slv_events_in[71] 0=low" "0: low,?"
bitfld.long 0x10 6. "POLARITY_134,Polarity for slv_events_in[70] 0=low" "0: low,?"
bitfld.long 0x10 5. "POLARITY_133,Polarity for slv_events_in[69] 0=low" "0: low,?"
newline
bitfld.long 0x10 4. "POLARITY_132,Polarity for slv_events_in[68] 0=low" "0: low,?"
bitfld.long 0x10 3. "POLARITY_131,Polarity for slv_events_in[67] 0=low" "0: low,?"
bitfld.long 0x10 2. "POLARITY_130,Polarity for slv_events_in[66] 0=low" "0: low,?"
newline
bitfld.long 0x10 1. "POLARITY_129,Polarity for slv_events_in[65] 0=low" "0: low,?"
bitfld.long 0x10 0. "POLARITY_128,Polarity for slv_events_in[64] 0=low" "0: low,?"
group.long 0xD80++0x13
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG0,"
bitfld.long 0x0 31. "TYPE_31,Type for intr_in[31] 0=level" "0: level,?"
bitfld.long 0x0 30. "TYPE_30,Type for intr_in[30] 0=level" "0: level,?"
bitfld.long 0x0 29. "TYPE_29,Type for intr_in[29] 0=level" "0: level,?"
newline
bitfld.long 0x0 28. "TYPE_28,Type for intr_in[28] 0=level" "0: level,?"
bitfld.long 0x0 27. "TYPE_27,Type for intr_in[27] 0=level" "0: level,?"
bitfld.long 0x0 26. "TYPE_26,Type for intr_in[26] 0=level" "0: level,?"
newline
bitfld.long 0x0 25. "TYPE_25,Type for intr_in[25] 0=level" "0: level,?"
bitfld.long 0x0 24. "TYPE_24,Type for intr_in[24] 0=level" "0: level,?"
bitfld.long 0x0 23. "TYPE_23,Type for intr_in[23] 0=level" "0: level,?"
newline
bitfld.long 0x0 22. "TYPE_22,Type for intr_in[22] 0=level" "0: level,?"
bitfld.long 0x0 21. "TYPE_21,Type for intr_in[21] 0=level" "0: level,?"
bitfld.long 0x0 20. "TYPE_20,Type for intr_in[20] 0=level" "0: level,?"
newline
bitfld.long 0x0 19. "TYPE_19,Type for intr_in[19] 0=level" "0: level,?"
bitfld.long 0x0 18. "TYPE_18,Type for intr_in[18] 0=level" "0: level,?"
bitfld.long 0x0 17. "TYPE_17,Type for intr_in[17] 0=level" "0: level,?"
newline
bitfld.long 0x0 16. "TYPE_16,Type for intr_in[16] 0=level" "0: level,?"
bitfld.long 0x0 15. "TYPE_15,Type for intr_in[15] 0=level" "0: level,?"
bitfld.long 0x0 14. "TYPE_14,Type for intr_in[14] 0=level" "0: level,?"
newline
bitfld.long 0x0 13. "TYPE_13,Type for intr_in[13] 0=level" "0: level,?"
bitfld.long 0x0 12. "TYPE_12,Type for intr_in[12] 0=level" "0: level,?"
bitfld.long 0x0 11. "TYPE_11,Type for intr_in[11] 0=level" "0: level,?"
newline
bitfld.long 0x0 10. "TYPE_10,Type for intr_in[10] 0=level" "0: level,?"
bitfld.long 0x0 9. "TYPE_9,Type for intr_in[9] 0=level" "0: level,?"
bitfld.long 0x0 8. "TYPE_8,Type for intr_in[8] 0=level" "0: level,?"
newline
bitfld.long 0x0 7. "TYPE_7,Type for intr_in[7] 0=level" "0: level,?"
bitfld.long 0x0 6. "TYPE_6,Type for intr_in[6] 0=level" "0: level,?"
bitfld.long 0x0 5. "TYPE_5,Type for intr_in[5] 0=level" "0: level,?"
newline
bitfld.long 0x0 4. "TYPE_4,Type for intr_in[4] 0=level" "0: level,?"
bitfld.long 0x0 3. "TYPE_3,Type for intr_in[3] 0=level" "0: level,?"
bitfld.long 0x0 2. "TYPE_2,Type for intr_in[2] 0=level" "0: level,?"
newline
bitfld.long 0x0 1. "TYPE_1,Type for intr_in[1] 0=level" "0: level,?"
bitfld.long 0x0 0. "TYPE_0,Type for intr_in[0] 0=level" "0: level,?"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG1,"
bitfld.long 0x4 31. "TYPE_63,Type for intr_in[63] 0=level" "0: level,?"
bitfld.long 0x4 30. "TYPE_62,Type for intr_in[62] 0=level" "0: level,?"
bitfld.long 0x4 29. "TYPE_61,Type for intr_in[61] 0=level" "0: level,?"
newline
bitfld.long 0x4 28. "TYPE_60,Type for intr_in[60] 0=level" "0: level,?"
bitfld.long 0x4 27. "TYPE_59,Type for intr_in[59] 0=level" "0: level,?"
bitfld.long 0x4 26. "TYPE_58,Type for intr_in[58] 0=level" "0: level,?"
newline
bitfld.long 0x4 25. "TYPE_57,Type for intr_in[57] 0=level" "0: level,?"
bitfld.long 0x4 24. "TYPE_56,Type for intr_in[56] 0=level" "0: level,?"
bitfld.long 0x4 23. "TYPE_55,Type for intr_in[55] 0=level" "0: level,?"
newline
bitfld.long 0x4 22. "TYPE_54,Type for intr_in[54] 0=level" "0: level,?"
bitfld.long 0x4 21. "TYPE_53,Type for intr_in[53] 0=level" "0: level,?"
bitfld.long 0x4 20. "TYPE_52,Type for intr_in[52] 0=level" "0: level,?"
newline
bitfld.long 0x4 19. "TYPE_51,Type for intr_in[51] 0=level" "0: level,?"
bitfld.long 0x4 18. "TYPE_50,Type for intr_in[50] 0=level" "0: level,?"
bitfld.long 0x4 17. "TYPE_49,Type for intr_in[49] 0=level" "0: level,?"
newline
bitfld.long 0x4 16. "TYPE_48,Type for intr_in[48] 0=level" "0: level,?"
bitfld.long 0x4 15. "TYPE_47,Type for intr_in[47] 0=level" "0: level,?"
bitfld.long 0x4 14. "TYPE_46,Type for intr_in[46] 0=level" "0: level,?"
newline
bitfld.long 0x4 13. "TYPE_45,Type for intr_in[45] 0=level" "0: level,?"
bitfld.long 0x4 12. "TYPE_44,Type for intr_in[44] 0=level" "0: level,?"
bitfld.long 0x4 11. "TYPE_43,Type for intr_in[43] 0=level" "0: level,?"
newline
bitfld.long 0x4 10. "TYPE_42,Type for intr_in[42] 0=level" "0: level,?"
bitfld.long 0x4 9. "TYPE_41,Type for intr_in[41] 0=level" "0: level,?"
bitfld.long 0x4 8. "TYPE_40,Type for intr_in[40] 0=level" "0: level,?"
newline
bitfld.long 0x4 7. "TYPE_39,Type for intr_in[39] 0=level" "0: level,?"
bitfld.long 0x4 6. "TYPE_38,Type for intr_in[38] 0=level" "0: level,?"
bitfld.long 0x4 5. "TYPE_37,Type for intr_in[37] 0=level" "0: level,?"
newline
bitfld.long 0x4 4. "TYPE_36,Type for intr_in[36] 0=level" "0: level,?"
bitfld.long 0x4 3. "TYPE_35,Type for intr_in[35] 0=level" "0: level,?"
bitfld.long 0x4 2. "TYPE_34,Type for intr_in[34] 0=level" "0: level,?"
newline
bitfld.long 0x4 1. "TYPE_33,Type for intr_in[33] 0=level" "0: level,?"
bitfld.long 0x4 0. "TYPE_32,Type for intr_in[32] 0=level" "0: level,?"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG2,"
bitfld.long 0x8 31. "TYPE_95,Type for slv_events_in[31] 0=level" "0: level,?"
bitfld.long 0x8 30. "TYPE_94,Type for slv_events_in[30] 0=level" "0: level,?"
bitfld.long 0x8 29. "TYPE_93,Type for slv_events_in[29] 0=level" "0: level,?"
newline
bitfld.long 0x8 28. "TYPE_92,Type for slv_events_in[28] 0=level" "0: level,?"
bitfld.long 0x8 27. "TYPE_91,Type for slv_events_in[27] 0=level" "0: level,?"
bitfld.long 0x8 26. "TYPE_90,Type for slv_events_in[26] 0=level" "0: level,?"
newline
bitfld.long 0x8 25. "TYPE_89,Type for slv_events_in[25] 0=level" "0: level,?"
bitfld.long 0x8 24. "TYPE_88,Type for slv_events_in[24] 0=level" "0: level,?"
bitfld.long 0x8 23. "TYPE_87,Type for slv_events_in[23] 0=level" "0: level,?"
newline
bitfld.long 0x8 22. "TYPE_86,Type for slv_events_in[22] 0=level" "0: level,?"
bitfld.long 0x8 21. "TYPE_85,Type for slv_events_in[21] 0=level" "0: level,?"
bitfld.long 0x8 20. "TYPE_84,Type for slv_events_in[20] 0=level" "0: level,?"
newline
bitfld.long 0x8 19. "TYPE_83,Type for slv_events_in[19] 0=level" "0: level,?"
bitfld.long 0x8 18. "TYPE_82,Type for slv_events_in[18] 0=level" "0: level,?"
bitfld.long 0x8 17. "TYPE_81,Type for slv_events_in[17] 0=level" "0: level,?"
newline
bitfld.long 0x8 16. "TYPE_80,Type for slv_events_in[16] 0=level" "0: level,?"
bitfld.long 0x8 15. "TYPE_79,Type for slv_events_in[15] 0=level" "0: level,?"
bitfld.long 0x8 14. "TYPE_78,Type for slv_events_in[14] 0=level" "0: level,?"
newline
bitfld.long 0x8 13. "TYPE_77,Type for slv_events_in[13] 0=level" "0: level,?"
bitfld.long 0x8 12. "TYPE_76,Type for slv_events_in[12] 0=level" "0: level,?"
bitfld.long 0x8 11. "TYPE_75,Type for slv_events_in[11] 0=level" "0: level,?"
newline
bitfld.long 0x8 10. "TYPE_74,Type for slv_events_in[10] 0=level" "0: level,?"
bitfld.long 0x8 9. "TYPE_73,Type for slv_events_in[9] 0=level" "0: level,?"
bitfld.long 0x8 8. "TYPE_72,Type for slv_events_in[8] 0=level" "0: level,?"
newline
bitfld.long 0x8 7. "TYPE_71,Type for slv_events_in[7] 0=level" "0: level,?"
bitfld.long 0x8 6. "TYPE_70,Type for slv_events_in[6] 0=level" "0: level,?"
bitfld.long 0x8 5. "TYPE_69,Type for slv_events_in[5] 0=level" "0: level,?"
newline
bitfld.long 0x8 4. "TYPE_68,Type for slv_events_in[4] 0=level" "0: level,?"
bitfld.long 0x8 3. "TYPE_67,Type for slv_events_in[3] 0=level" "0: level,?"
bitfld.long 0x8 2. "TYPE_66,Type for slv_events_in[2] 0=level" "0: level,?"
newline
bitfld.long 0x8 1. "TYPE_65,Type for slv_events_in[1] 0=level" "0: level,?"
bitfld.long 0x8 0. "TYPE_64,Type for slv_events_in[0] 0=level" "0: level,?"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG3,"
bitfld.long 0xC 31. "TYPE_127,Type for slv_events_in[63] 0=level" "0: level,?"
bitfld.long 0xC 30. "TYPE_126,Type for slv_events_in[62] 0=level" "0: level,?"
bitfld.long 0xC 29. "TYPE_125,Type for slv_events_in[61] 0=level" "0: level,?"
newline
bitfld.long 0xC 28. "TYPE_124,Type for slv_events_in[60] 0=level" "0: level,?"
bitfld.long 0xC 27. "TYPE_123,Type for slv_events_in[59] 0=level" "0: level,?"
bitfld.long 0xC 26. "TYPE_122,Type for slv_events_in[58] 0=level" "0: level,?"
newline
bitfld.long 0xC 25. "TYPE_121,Type for slv_events_in[57] 0=level" "0: level,?"
bitfld.long 0xC 24. "TYPE_120,Type for slv_events_in[56] 0=level" "0: level,?"
bitfld.long 0xC 23. "TYPE_119,Type for slv_events_in[55] 0=level" "0: level,?"
newline
bitfld.long 0xC 22. "TYPE_118,Type for slv_events_in[54] 0=level" "0: level,?"
bitfld.long 0xC 21. "TYPE_117,Type for slv_events_in[53] 0=level" "0: level,?"
bitfld.long 0xC 20. "TYPE_116,Type for slv_events_in[52] 0=level" "0: level,?"
newline
bitfld.long 0xC 19. "TYPE_115,Type for slv_events_in[51] 0=level" "0: level,?"
bitfld.long 0xC 18. "TYPE_114,Type for slv_events_in[50] 0=level" "0: level,?"
bitfld.long 0xC 17. "TYPE_113,Type for slv_events_in[49] 0=level" "0: level,?"
newline
bitfld.long 0xC 16. "TYPE_112,Type for slv_events_in[48] 0=level" "0: level,?"
bitfld.long 0xC 15. "TYPE_111,Type for slv_events_in[47] 0=level" "0: level,?"
bitfld.long 0xC 14. "TYPE_110,Type for slv_events_in[46] 0=level" "0: level,?"
newline
bitfld.long 0xC 13. "TYPE_109,Type for slv_events_in[45] 0=level" "0: level,?"
bitfld.long 0xC 12. "TYPE_108,Type for slv_events_in[44] 0=level" "0: level,?"
bitfld.long 0xC 11. "TYPE_107,Type for slv_events_in[43] 0=level" "0: level,?"
newline
bitfld.long 0xC 10. "TYPE_106,Type for slv_events_in[42] 0=level" "0: level,?"
bitfld.long 0xC 9. "TYPE_105,Type for slv_events_in[41] 0=level" "0: level,?"
bitfld.long 0xC 8. "TYPE_104,Type for slv_events_in[40] 0=level" "0: level,?"
newline
bitfld.long 0xC 7. "TYPE_103,Type for slv_events_in[39] 0=level" "0: level,?"
bitfld.long 0xC 6. "TYPE_102,Type for slv_events_in[38] 0=level" "0: level,?"
bitfld.long 0xC 5. "TYPE_101,Type for slv_events_in[37] 0=level" "0: level,?"
newline
bitfld.long 0xC 4. "TYPE_100,Type for slv_events_in[36] 0=level" "0: level,?"
bitfld.long 0xC 3. "TYPE_99,Type for slv_events_in[35] 0=level" "0: level,?"
bitfld.long 0xC 2. "TYPE_98,Type for slv_events_in[34] 0=level" "0: level,?"
newline
bitfld.long 0xC 1. "TYPE_97,Type for slv_events_in[33] 0=level" "0: level,?"
bitfld.long 0xC 0. "TYPE_96,Type for slv_events_in[32] 0=level" "0: level,?"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG4,"
bitfld.long 0x10 31. "TYPE_159,Type for slv_events_in[95] 0=level" "0: level,?"
bitfld.long 0x10 30. "TYPE_158,Type for slv_events_in[94] 0=level" "0: level,?"
bitfld.long 0x10 29. "TYPE_157,Type for slv_events_in[93] 0=level" "0: level,?"
newline
bitfld.long 0x10 28. "TYPE_156,Type for slv_events_in[92] 0=level" "0: level,?"
bitfld.long 0x10 27. "TYPE_155,Type for slv_events_in[91] 0=level" "0: level,?"
bitfld.long 0x10 26. "TYPE_154,Type for slv_events_in[90] 0=level" "0: level,?"
newline
bitfld.long 0x10 25. "TYPE_153,Type for slv_events_in[89] 0=level" "0: level,?"
bitfld.long 0x10 24. "TYPE_152,Type for slv_events_in[88] 0=level" "0: level,?"
bitfld.long 0x10 23. "TYPE_151,Type for slv_events_in[87] 0=level" "0: level,?"
newline
bitfld.long 0x10 22. "TYPE_150,Type for slv_events_in[86] 0=level" "0: level,?"
bitfld.long 0x10 21. "TYPE_149,Type for slv_events_in[85] 0=level" "0: level,?"
bitfld.long 0x10 20. "TYPE_148,Type for slv_events_in[84] 0=level" "0: level,?"
newline
bitfld.long 0x10 19. "TYPE_147,Type for slv_events_in[83] 0=level" "0: level,?"
bitfld.long 0x10 18. "TYPE_146,Type for slv_events_in[82] 0=level" "0: level,?"
bitfld.long 0x10 17. "TYPE_145,Type for slv_events_in[81] 0=level" "0: level,?"
newline
bitfld.long 0x10 16. "TYPE_144,Type for slv_events_in[80] 0=level" "0: level,?"
bitfld.long 0x10 15. "TYPE_143,Type for slv_events_in[79] 0=level" "0: level,?"
bitfld.long 0x10 14. "TYPE_142,Type for slv_events_in[78] 0=level" "0: level,?"
newline
bitfld.long 0x10 13. "TYPE_141,Type for slv_events_in[77] 0=level" "0: level,?"
bitfld.long 0x10 12. "TYPE_140,Type for slv_events_in[76] 0=level" "0: level,?"
bitfld.long 0x10 11. "TYPE_139,Type for slv_events_in[75] 0=level" "0: level,?"
newline
bitfld.long 0x10 10. "TYPE_138,Type for slv_events_in[74] 0=level" "0: level,?"
bitfld.long 0x10 9. "TYPE_137,Type for slv_events_in[73] 0=level" "0: level,?"
bitfld.long 0x10 8. "TYPE_136,Type for slv_events_in[72] 0=level" "0: level,?"
newline
bitfld.long 0x10 7. "TYPE_135,Type for slv_events_in[71] 0=level" "0: level,?"
bitfld.long 0x10 6. "TYPE_134,Type for slv_events_in[70] 0=level" "0: level,?"
bitfld.long 0x10 5. "TYPE_133,Type for slv_events_in[69] 0=level" "0: level,?"
newline
bitfld.long 0x10 4. "TYPE_132,Type for slv_events_in[68] 0=level" "0: level,?"
bitfld.long 0x10 3. "TYPE_131,Type for slv_events_in[67] 0=level" "0: level,?"
bitfld.long 0x10 2. "TYPE_130,Type for slv_events_in[66] 0=level" "0: level,?"
newline
bitfld.long 0x10 1. "TYPE_129,Type for slv_events_in[65] 0=level" "0: level,?"
bitfld.long 0x10 0. "TYPE_128,Type for slv_events_in[64] 0=level" "0: level,?"
group.long 0x1100++0x4F
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG0,"
bitfld.long 0x0 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x0 0.--8. 1. "NEST_HINT_0,Host Int 0 Nesting Level"
line.long 0x4 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG1,"
bitfld.long 0x4 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x4 0.--8. 1. "NEST_HINT_1,Host Int 1 Nesting Level"
line.long 0x8 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG2,"
bitfld.long 0x8 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x8 0.--8. 1. "NEST_HINT_2,Host Int 2 Nesting Level"
line.long 0xC "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG3,"
bitfld.long 0xC 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0xC 0.--8. 1. "NEST_HINT_3,Host Int 3 Nesting Level"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG4,"
bitfld.long 0x10 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT_4,Host Int 4 Nesting Level"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG5,"
bitfld.long 0x14 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT_5,Host Int 5 Nesting Level"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG6,"
bitfld.long 0x18 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT_6,Host Int 6 Nesting Level"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG7,"
bitfld.long 0x1C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT_7,Host Int 7 Nesting Level"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG8,"
bitfld.long 0x20 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT_8,Host Int 8 Nesting Level"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG9,"
bitfld.long 0x24 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT_9,Host Int 9 Nesting Level"
line.long 0x28 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG10,"
bitfld.long 0x28 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x28 0.--8. 1. "NEST_HINT_10,Host Int 10 Nesting Level"
line.long 0x2C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG11,"
bitfld.long 0x2C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x2C 0.--8. 1. "NEST_HINT_11,Host Int 11 Nesting Level"
line.long 0x30 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG12,"
bitfld.long 0x30 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x30 0.--8. 1. "NEST_HINT_12,Host Int 12 Nesting Level"
line.long 0x34 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG13,"
bitfld.long 0x34 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x34 0.--8. 1. "NEST_HINT_13,Host Int 13 Nesting Level"
line.long 0x38 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG14,"
bitfld.long 0x38 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x38 0.--8. 1. "NEST_HINT_14,Host Int 14 Nesting Level"
line.long 0x3C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG15,"
bitfld.long 0x3C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x3C 0.--8. 1. "NEST_HINT_15,Host Int 15 Nesting Level"
line.long 0x40 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG16,"
bitfld.long 0x40 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x40 0.--8. 1. "NEST_HINT_16,Host Int 16 Nesting Level"
line.long 0x44 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG17,"
bitfld.long 0x44 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x44 0.--8. 1. "NEST_HINT_17,Host Int 17 Nesting Level"
line.long 0x48 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG18,"
bitfld.long 0x48 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x48 0.--8. 1. "NEST_HINT_18,Host Int 18 Nesting Level"
line.long 0x4C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG19,"
bitfld.long 0x4C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x4C 0.--8. 1. "NEST_HINT_19,Host Int 19 Nesting Level"
group.long 0x1500++0x3
line.long 0x0 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_HINT_REG0,"
bitfld.long 0x0 19. "ENABLE_HINT_19,Enable for Host Int 19" "0,1"
bitfld.long 0x0 18. "ENABLE_HINT_18,Enable for Host Int 18" "0,1"
bitfld.long 0x0 17. "ENABLE_HINT_17,Enable for Host Int 17" "0,1"
newline
bitfld.long 0x0 16. "ENABLE_HINT_16,Enable for Host Int 16" "0,1"
bitfld.long 0x0 15. "ENABLE_HINT_15,Enable for Host Int 15" "0,1"
bitfld.long 0x0 14. "ENABLE_HINT_14,Enable for Host Int 14" "0,1"
newline
bitfld.long 0x0 13. "ENABLE_HINT_13,Enable for Host Int 13" "0,1"
bitfld.long 0x0 12. "ENABLE_HINT_12,Enable for Host Int 12" "0,1"
bitfld.long 0x0 11. "ENABLE_HINT_11,Enable for Host Int 11" "0,1"
newline
bitfld.long 0x0 10. "ENABLE_HINT_10,Enable for Host Int 10" "0,1"
bitfld.long 0x0 9. "ENABLE_HINT_9,Enable for Host Int 9" "0,1"
bitfld.long 0x0 8. "ENABLE_HINT_8,Enable for Host Int 8" "0,1"
newline
bitfld.long 0x0 7. "ENABLE_HINT_7,Enable for Host Int 7" "0,1"
bitfld.long 0x0 6. "ENABLE_HINT_6,Enable for Host Int 6" "0,1"
bitfld.long 0x0 5. "ENABLE_HINT_5,Enable for Host Int 5" "0,1"
newline
bitfld.long 0x0 4. "ENABLE_HINT_4,Enable for Host Int 4" "0,1"
bitfld.long 0x0 3. "ENABLE_HINT_3,Enable for Host Int 3" "0,1"
bitfld.long 0x0 2. "ENABLE_HINT_2,Enable for Host Int 2" "0,1"
newline
bitfld.long 0x0 1. "ENABLE_HINT_1,Enable for Host Int 1" "0,1"
bitfld.long 0x0 0. "ENABLE_HINT_0,Enable for Host Int 0" "0,1"
tree.end
tree "PRU_ICSSG1_PR1_ICSS_UART_UART_SLV (PRU_ICSSG1_PR1_ICSS_UART_UART_SLV)"
base ad:0x300A8000
group.long 0x0++0x13
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_RBR_TBR,RBR_TBR Registers"
hexmask.long.word 0x0 8.--17. 1. "TBR_DATA,Transmit Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR_DATA,Receive Buffer Register"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_INT_EN,UART Interrupt Enable Register"
bitfld.long 0x4 3. "EDSSI,Enable for Modem Status Interrupt" "0,1"
bitfld.long 0x4 2. "ELSI,Enable for Receiver Line Status Interrupt" "0,1"
bitfld.long 0x4 1. "ETBEI,Enable for Transmitter Holding Register Empty Interrupt" "0,1"
bitfld.long 0x4 0. "ERBI,Enable for Receiver Data Available Interrupt" "0,1"
line.long 0x8 "PR1_ICSS_UART__UART_SLV__REGS_INT_FIFO,Interrupt Identification Register / FIFO Control Register"
bitfld.long 0x8 14.--15. "FCR_RXFIFTL,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x8 11. "FCR_DMAMODE1,DMA Mode Select" "0,1"
bitfld.long 0x8 10. "FCR_TXCLR,Transmitter FIFO Reset" "0,1"
bitfld.long 0x8 9. "FCR_RXCLR,Receiver FIFO Reset" "0,1"
bitfld.long 0x8 8. "FCR_FIFOEN,FIFO Enable Register" "0,1"
rbitfld.long 0x8 6.--7. "IIR_FIFOEN,FIFOs enabled" "0,1,2,3"
newline
rbitfld.long 0x8 1.--3. "IIR_INTID,Interrupt Type" "0,1,2,3,4,5,6,7"
rbitfld.long 0x8 0. "IIR_IPEND,Receiver Data Available Interrupt Pending" "0,1"
line.long 0xC "PR1_ICSS_UART__UART_SLV__REGS_LCTR,Line Control Register"
bitfld.long 0xC 7. "DLAB,Divisor Latch Access Bit" "0,1"
bitfld.long 0xC 6. "BC,Break Control" "0,1"
bitfld.long 0xC 5. "SP,Stick Parity" "0,1"
bitfld.long 0xC 4. "EPS,Even Parity Select" "0,1"
bitfld.long 0xC 3. "PEN,Parity Enable" "0,1"
bitfld.long 0xC 2. "STB,Number of Stop Bits" "0,1"
newline
bitfld.long 0xC 1. "WLS1,Word Length Select Bit 1" "0,1"
bitfld.long 0xC 0. "WLS0,Word Length Select Bit 0" "0,1"
line.long 0x10 "PR1_ICSS_UART__UART_SLV__REGS_MCTR,Modem Control Register"
bitfld.long 0x10 5. "AFE,Autoflow Control Enable" "0,1"
bitfld.long 0x10 4. "LOOP,LOOP Bit" "0,1"
bitfld.long 0x10 3. "OUT2,Out2 Bit" "0,1"
bitfld.long 0x10 2. "OUT1,Out1 Bit" "0,1"
bitfld.long 0x10 1. "RTS,Ready to Send" "0,1"
bitfld.long 0x10 0. "DTR,Data Terminal Ready" "0,1"
rgroup.long 0x14++0x7
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_LSR1,Line Status Register1"
bitfld.long 0x0 7. "RXFIFOE,Receiver FIFO Error" "0,1"
bitfld.long 0x0 6. "TEMT,Transmitter Empty" "0,1"
bitfld.long 0x0 5. "THRE,Transmitter Holding Register" "0,1"
bitfld.long 0x0 4. "BI,Break Interrupt" "0,1"
bitfld.long 0x0 3. "FE,Framing Error" "0,1"
bitfld.long 0x0 2. "PE,Parity Error" "0,1"
newline
bitfld.long 0x0 1. "OE,Overrun Error" "0,1"
bitfld.long 0x0 0. "DR,Data Ready" "0,1"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_MSR,Modem Status Register"
bitfld.long 0x4 7. "CD,Carrier Detect" "0,1"
bitfld.long 0x4 6. "RI,Ring Indicator" "0,1"
bitfld.long 0x4 5. "DSR,Data Set Ready" "0,1"
bitfld.long 0x4 4. "CTS,Clear To Send" "0,1"
bitfld.long 0x4 3. "DCD,Delta Carrier Detect" "0,1"
bitfld.long 0x4 2. "TERI,Trailing Edge Ring Indicator" "0,1"
newline
bitfld.long 0x4 1. "DDSR,Delta Set Ready" "0,1"
bitfld.long 0x4 0. "DCTS,Delta Clear To Send" "0,1"
group.long 0x1C++0xB
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_SCRATCH,UART Scratch Register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,Scratch Register Bits"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_DIVLSB,UART Divisor Register"
hexmask.long.byte 0x4 0.--7. 1. "DLL,Divisor Latch [LSB]"
line.long 0x8 "PR1_ICSS_UART__UART_SLV__REGS_DIVMSB,UART Divisor Register"
hexmask.long.byte 0x8 0.--7. 1. "DLH,Divisor Latch [MSB]"
rgroup.long 0x28++0x3
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_PID,Peripheral ID Register"
hexmask.long 0x0 0.--31. 1. "PID,"
group.long 0x30++0x7
line.long 0x0 "PR1_ICSS_UART__UART_SLV__REGS_PWR,UART PowerManagement and Emulation Register"
bitfld.long 0x0 15. "URST,UART Reset Bit" "0,1"
bitfld.long 0x0 14. "UTRST,UART Transmitter Reset Bit" "0,1"
bitfld.long 0x0 13. "URRST,UART Receiver Reset Bit" "0,1"
rbitfld.long 0x0 1. "RES,Free Bit" "0,1"
bitfld.long 0x0 0. "FREE,Free Bit" "0,1"
line.long 0x4 "PR1_ICSS_UART__UART_SLV__REGS_MODE,UART Mode Definition Register"
bitfld.long 0x4 0. "OSM_SEL,Oversampling Mode Select" "0,1"
tree.end
tree.end
tree "PRU_ICSSG1_PR1_MDIO_V1P7_MDIO (PRU_ICSSG1_PR1_MDIO_V1P7_MDIO)"
base ad:0x300B2400
rgroup.long 0x0++0x3
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_MDIO_VERSION_REG,version_reg"
hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID"
hexmask.long.byte 0x0 8.--15. 1. "REVMAJ,Major revision value"
hexmask.long.byte 0x0 0.--7. 1. "REVMINOR,Minor revision value"
group.long 0x4++0x7
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_CONTROL_REG,control_reg"
rbitfld.long 0x0 31. "IDLE,MDIO state machine idle" "0,1"
bitfld.long 0x0 30. "ENABLE,Enable control" "0,1"
hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel"
newline
bitfld.long 0x0 20. "PREAMBLE,Preamble disable" "0,1"
bitfld.long 0x0 19. "FAULT,Fault indicator" "0,1"
bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
newline
bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock divider"
line.long 0x4 "PR1_MDIO_V1P7__MDIO__REGS_ALIVE_REG,alive_reg"
hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO alive"
rgroup.long 0xC++0x3
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_LINK_REG,link_reg"
hexmask.long 0x0 0.--31. 1. "LINK,MDIO link state"
group.long 0x10++0x37
line.long 0x0 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_RAW_REG,link_int_raw_reg"
bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x4 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASKED_REG,link_int_masked_reg"
bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x8 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASK_SET_REG,link_int_mask_set_reg"
bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0xC "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASK_CLEAR_REG,link_int_mask_clear_reg"
bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x10 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_RAW_REG,user_int_raw_reg"
bitfld.long 0x10 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
line.long 0x14 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASKED_REG,user_int_masked_reg"
bitfld.long 0x14 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
line.long 0x18 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASK_SET_REG,user_int_mask_set_reg"
bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
line.long 0x1C "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASK_CLEAR_REG,user_int_mask_clear_reg"
bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
line.long 0x20 "PR1_MDIO_V1P7__MDIO__REGS_MANUAL_IF_REG,manual_if_reg"
bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable" "0,1"
bitfld.long 0x20 0. "MDIO_PIN,MDIO Pin" "0,1"
line.long 0x24 "PR1_MDIO_V1P7__MDIO__REGS_POLL_REG,poll_reg"
bitfld.long 0x24 31. "MANUALMODE,MDIO Manual Mode" "0,1"
bitfld.long 0x24 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
hexmask.long.byte 0x24 0.--7. 1. "IPG,MDIO IPG"
line.long 0x28 "PR1_MDIO_V1P7__MDIO__REGS_POLL_EN_REG,poll_en_reg"
hexmask.long 0x28 0.--31. 1. "POLL_EN,MDIO Poll Enable"
line.long 0x2C "PR1_MDIO_V1P7__MDIO__REGS_CLAUS45_REG,"
hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO Clause 45"
line.long 0x30 "PR1_MDIO_V1P7__MDIO__REGS_USER_ADDR0_REG,MDIO USER Address 0"
hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
line.long 0x34 "PR1_MDIO_V1P7__MDIO__REGS_USER_ADDR1_REG,MDIO USER Address 1"
hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
tree.end
base ad:0x0
tree "PRU_ICSSG1_PR1_MII"
tree "PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG (PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG)"
base ad:0x300B2000
group.long 0x0++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rxcfg0,MIIRXCFG0Register"
bitfld.long 0x0 9. "RX_EOF_SCLR_DIS0," "0,1"
bitfld.long 0x0 8. "RX_ERR_RAW0," "0,1"
bitfld.long 0x0 7. "RX_SFD_RAW0," "0,1"
newline
bitfld.long 0x0 6. "RX_AUTO_FWD_PRE0," "0,1"
bitfld.long 0x0 5. "RX_BYTE_SWAP0," "0,1"
bitfld.long 0x0 4. "RX_L2_EN0," "0,1"
newline
bitfld.long 0x0 3. "RX_MUX_SEL0," "0,1"
bitfld.long 0x0 2. "RX_CUT_PREAMBLE0," "0,1"
bitfld.long 0x0 1. "RX_DATA_RDY_MODE_DIS0," "0,1"
newline
bitfld.long 0x0 0. "RX_ENABLE0," "0,1"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rxcfg1,MIIRXCFG1Register"
bitfld.long 0x4 9. "RX_EOF_SCLR_DIS1," "0,1"
bitfld.long 0x4 8. "RX_ERR_RAW1," "0,1"
bitfld.long 0x4 7. "RX_SFD_RAW1," "0,1"
newline
bitfld.long 0x4 6. "RX_AUTO_FWD_PRE1," "0,1"
bitfld.long 0x4 5. "RX_BYTE_SWAP1," "0,1"
bitfld.long 0x4 4. "RX_L2_EN1," "0,1"
newline
bitfld.long 0x4 3. "RX_MUX_SEL1," "0,1"
bitfld.long 0x4 2. "RX_CUT_PREAMBLE1," "0,1"
bitfld.long 0x4 1. "RX_DATA_RDY_MODE_DIS1," "0,1"
newline
bitfld.long 0x4 0. "RX_ENABLE1," "0,1"
group.long 0x10++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_txcfg0,MIITXCFG0Register"
bitfld.long 0x0 28.--30. "TX_CLK_DELAY0," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 16.--25. 1. "TX_START_DELAY0,"
bitfld.long 0x0 12. "TX_IPG_WIRE_CLK_EN0," "0,1"
newline
bitfld.long 0x0 11. "TX_32_MODE_EN0," "0,1"
bitfld.long 0x0 10. "PRE_TX_AUTO_ESC_ERR0," "0,1"
bitfld.long 0x0 9. "PRE_TX_AUTO_SEQUENCE0," "0,1"
newline
bitfld.long 0x0 8. "TX_MUX_SEL0," "0,1"
bitfld.long 0x0 3. "TX_BYTE_SWAP0," "0,1"
bitfld.long 0x0 2. "TX_EN_MODE0," "0,1"
newline
bitfld.long 0x0 1. "TX_AUTO_PREAMBLE0," "0,1"
bitfld.long 0x0 0. "TX_ENABLE0," "0,1"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_txcfg1,MIITXCFG1Register"
bitfld.long 0x4 28.--30. "TX_CLK_DELAY1," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 16.--25. 1. "TX_START_DELAY1,"
bitfld.long 0x4 12. "TX_IPG_WIRE_CLK_EN1," "0,1"
newline
bitfld.long 0x4 11. "TX_32_MODE_EN1," "0,1"
bitfld.long 0x4 10. "PRE_TX_AUTO_ESC_ERR1," "0,1"
bitfld.long 0x4 9. "PRE_TX_AUTO_SEQUENCE1," "0,1"
newline
bitfld.long 0x4 8. "TX_MUX_SEL1," "0,1"
bitfld.long 0x4 3. "TX_BYTE_SWAP1," "0,1"
bitfld.long 0x4 2. "TX_EN_MODE1," "0,1"
newline
bitfld.long 0x4 1. "TX_AUTO_PREAMBLE1," "0,1"
bitfld.long 0x4 0. "TX_ENABLE1," "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_crc0,MIITXCRC0Register"
hexmask.long 0x0 0.--31. 1. "TX_CRC0,Transmit CRC for last packet"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_crc1,MIITXCRC1Register"
hexmask.long 0x4 0.--31. 1. "TX_CRC1,Transmit CRC for last packet"
group.long 0x30++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_ipg0,MIITXIPG0Register"
hexmask.long.word 0x0 0.--15. 1. "TX_IPG0,Transmit IPG"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_ipg1,MIITXIPG1Register"
hexmask.long.word 0x4 0.--15. 1. "TX_IPG1,Transmit IPG"
rgroup.long 0x38++0x7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_prs0,MIIPortStatus0Register"
bitfld.long 0x0 1. "SYNC_PORT0_CRS,sync_port0_crs" "0,1"
bitfld.long 0x0 0. "SYNC_PORT0_COL,sync_port0_col" "0,1"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_prs1,MIIPortStatus1Register"
bitfld.long 0x4 1. "SYNC_PORT1_CRS,sync_port1_crs" "0,1"
bitfld.long 0x4 0. "SYNC_PORT1_COL,sync_port1_col" "0,1"
group.long 0x40++0x17
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_frms0,MIIRXFRMS0Register"
hexmask.long.word 0x0 16.--31. 1. "RX_MAX_FRM0,rx_max_frm0"
hexmask.long.word 0x0 0.--15. 1. "RX_MIN_FRM0,rx_min_frm0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_frms1,MIIRXFRMS1Register"
hexmask.long.word 0x4 16.--31. 1. "RX_MAX_FRM1,rx_max_frm1"
hexmask.long.word 0x4 0.--15. 1. "RX_MIN_FRM1,rx_min_frm1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_pcnt0,MIIRXPCNT0Register"
hexmask.long.byte 0x8 4.--8. 1. "RX_MAX_PCNT0,rx_max_pcnt0"
hexmask.long.byte 0x8 0.--3. 1. "RX_MIN_PCNT0,rx_min_pcnt0"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_pcnt1,MIIRXPCNT1Register"
hexmask.long.byte 0xC 4.--8. 1. "RX_MAX_PCNT1,rx_max_pcnt1"
hexmask.long.byte 0xC 0.--3. 1. "RX_MIN_PCNT1,rx_min_pcnt1"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_err0,MIIRXERR0Register"
bitfld.long 0x10 3. "RX_MAX_FRM_ERR0,rx_max_frm_err0" "0,1"
bitfld.long 0x10 2. "RX_MIN_FRM_ERR0,rx_min_frm_err0" "0,1"
bitfld.long 0x10 1. "RX_MAX_PCNT_ERR0,rx_max_pcnt_err0" "0,1"
newline
bitfld.long 0x10 0. "RX_MIN_PCNT_ERR0,rx_min_pcnt_err0" "0,1"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_err1,MIIRXERR1Register"
bitfld.long 0x14 3. "RX_MAX_FRM_ERR1,rx_max_frm_err1" "0,1"
bitfld.long 0x14 2. "RX_MIN_FRM_ERR1,rx_min_frm_err1" "0,1"
bitfld.long 0x14 1. "RX_MAX_PCNT_ERR1,rx_max_pcnt_err1" "0,1"
newline
bitfld.long 0x14 0. "RX_MIN_PCNT_ERR1,rx_min_pcnt_err1" "0,1"
rgroup.long 0x60++0xF
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_fifo_level0,MIIRXFIFOLEVEL0Register"
hexmask.long.byte 0x0 0.--7. 1. "RX_FIFO_LEVEL0,rx_fifo_level0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_fifo_level1,MIIRXFIFOLEVEL1Register"
hexmask.long.byte 0x4 0.--7. 1. "RX_FIFO_LEVEL1,rx_fifo_level1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_fifo_level0,MIIRXFIFOLEVEL0Register"
hexmask.long.byte 0x8 0.--7. 1. "TX_FIFO_LEVEL0,tx_fifo_level0"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_fifo_level1,MIIRXFIFOLEVEL1Register"
hexmask.long.byte 0xC 0.--7. 1. "TX_FIFO_LEVEL1,tx_fifo_level1"
tree.end
tree "PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G (PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G)"
base ad:0x300B3000
group.long 0x8++0x23
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru0_0,"
hexmask.long 0x0 0.--31. 1. "MAC_PRU0_0,MAC pru0 DA3:DA0 Used for SAV and DA match"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru0_1,"
hexmask.long.word 0x4 0.--15. 1. "MAC_PRU0_1,MAC pru0 DA5:DA4 Used for SAV and DA match"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru1_0,"
hexmask.long 0x8 0.--31. 1. "MAC_PRU1_0,MAC pru1 DA3:DA0 Used for SAV and DA match"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_pru1_1,"
hexmask.long.word 0xC 0.--15. 1. "MAC_PRU1_1,MAC pru1 DA5:DA4 Used for SAV and DA match"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_interface_0,"
hexmask.long 0x10 0.--31. 1. "MAC_INF_0,MAC Host interface DA3:DA0 Used for SAV and DA match"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_mac_interface_1,"
hexmask.long.word 0x14 0.--15. 1. "MAC_INF_1,MAC Host interface DA5:DA4 Used for SAV and DA match"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_preempt_cfg,"
hexmask.long.byte 0x18 24.--31. 1. "SMD_R,Response frame TAG"
hexmask.long.byte 0x18 16.--23. 1. "SMD_V,Verification frame TAG"
newline
hexmask.long.byte 0x18 8.--15. 1. "EXP_SMD,None preemptable frame start  or express frame"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_smdt1s_cfg,"
hexmask.long.byte 0x1C 24.--31. 1. "SMDT1S_3,SMDT1S3 pattern"
hexmask.long.byte 0x1C 16.--23. 1. "SMDT1S_2,SMDT1S2 pattern"
newline
hexmask.long.byte 0x1C 8.--15. 1. "SMDT1S_1,SMDT1S1 pattern"
hexmask.long.byte 0x1C 0.--7. 1. "SMDT1S_0,SMDT1S0 pattern"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_smdt1c_cfg,"
hexmask.long.byte 0x20 24.--31. 1. "SMDT1C_3,SMDT1C3 pattern"
hexmask.long.byte 0x20 16.--23. 1. "SMDT1C_2,SMDT1C2 pattern"
newline
hexmask.long.byte 0x20 8.--15. 1. "SMDT1C_1,SMDT1C1 pattern"
hexmask.long.byte 0x20 0.--7. 1. "SMDT1C_0,SMDT1C0 pattern"
group.long 0x34++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_frag_cnt_cfg,"
hexmask.long.byte 0x0 24.--31. 1. "FRAG_CNT_3,FRAG Cnt3 pattern"
hexmask.long.byte 0x0 16.--23. 1. "FRAG_CNT_2,FRAG Cnt2 pattern"
newline
hexmask.long.byte 0x0 8.--15. 1. "FRAG_CNT_1,FRAG Cnt1 pattern"
hexmask.long.byte 0x0 0.--7. 1. "FRAG_CNT_0,FRAG Cnt0 pattern"
group.long 0x40++0xF
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push0,"
hexmask.long.byte 0x0 24.--31. 1. "PA_STAT_PUSH3_0,pa stat push3"
hexmask.long.byte 0x0 16.--23. 1. "PA_STAT_PUSH2_0,pa stat push2"
newline
hexmask.long.byte 0x0 8.--15. 1. "PA_STAT_PUSH1_0,pa stat push1"
hexmask.long.byte 0x0 0.--7. 1. "PA_STAT_PUSH0_0,pa stat push0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push1,"
hexmask.long.byte 0x4 24.--31. 1. "PA_STAT_PUSH3_1,pa stat push3"
hexmask.long.byte 0x4 16.--23. 1. "PA_STAT_PUSH2_1,pa stat push2"
newline
hexmask.long.byte 0x4 8.--15. 1. "PA_STAT_PUSH1_1,pa stat push1"
hexmask.long.byte 0x4 0.--7. 1. "PA_STAT_PUSH0_1,pa stat push0"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push2,"
hexmask.long.byte 0x8 24.--31. 1. "PA_STAT_PUSH3_2,pa stat push3"
hexmask.long.byte 0x8 16.--23. 1. "PA_STAT_PUSH2_2,pa stat push2"
newline
hexmask.long.byte 0x8 8.--15. 1. "PA_STAT_PUSH1_2,pa stat push1"
hexmask.long.byte 0x8 0.--7. 1. "PA_STAT_PUSH0_2,pa stat push0"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pa_stat_push3,"
hexmask.long.byte 0xC 24.--31. 1. "PA_STAT_PUSH3_3,pa stat push3"
hexmask.long.byte 0xC 16.--23. 1. "PA_STAT_PUSH2_3,pa stat push2"
newline
hexmask.long.byte 0xC 8.--15. 1. "PA_STAT_PUSH1_3,pa stat push1"
hexmask.long.byte 0xC 0.--7. 1. "PA_STAT_PUSH0_3,pa stat push0"
group.long 0x60++0xAB
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_gen_cfg1,"
hexmask.long.tbyte 0x0 8.--25. 1. "SMEM_VLAN_OFFSET,SMEM VLAN FID table base address"
hexmask.long.byte 0x0 3.--6. 1. "FDB_HASH_SIZE,FDB hash size 0:64 1:128 2:256 3:512 4:1024 5:2048"
newline
bitfld.long 0x0 0.--1. "FDB_BUCKET_SIZE,FDB buket size 0:1 1:2 2:4 3:8" "0: 1,1: 2,2: 4,3: 8"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_gen_cfg2,"
hexmask.long.byte 0x4 9.--12. 1. "FDB_GEN_MODE_BYTE_EN,FDB General Mode Byte compare size 0 = 1 Byte  15 = 16 Bytes"
bitfld.long 0x4 8. "FDB_GEN_MODE_EN_BK1,FDB General Mode Enable Bank1 if set PRU0/PRU1/HOST will get disabled" "0,1"
newline
bitfld.long 0x4 7. "FDB_GEN_MODE_EN_BK0,FDB General Mode Enable Bank0 if set PRU0/PRU1/HOST will get disabled" "0,1"
bitfld.long 0x4 6. "FDB_VLAN_EN,FDB Global VLAN Enable" "0,1"
newline
bitfld.long 0x4 5. "FDB_HSR_EN,FDB Global HSR Enable note VLAN most be disabled" "0,1"
bitfld.long 0x4 2. "FDB_HOST_EN,FDB HOST Enable" "0,1"
newline
bitfld.long 0x4 1. "FDB_PRU1_EN,FDB PRU1 Enable" "0,1"
bitfld.long 0x4 0. "FDB_PRU0_EN,FDB PRU0 Enable" "0,1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_gen_status,"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_df_vlan,"
hexmask.long.word 0xC 16.--27. 1. "FDB_PRU1_DF_VLAN,FDB Default VLAN for PRU1"
hexmask.long.word 0xC 0.--11. 1. "FDB_PRU0_DF_VLAN,FDB Default VLAN for PRU0"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_da0,"
hexmask.long 0x10 0.--31. 1. "FDB_HOST_DA0,FDB HOST DA3:0"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_da1,"
hexmask.long.word 0x14 0.--15. 1. "FDB_HOST_DA1,FDB HOST DA5:4"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_sa0,"
hexmask.long 0x18 0.--31. 1. "FDB_HOST_SA0,FDB HOST SA3:0"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_fdb_host_vlan_sa1,"
hexmask.long.word 0x1C 16.--31. 1. "FDB_HOST_VLAN_HSR,FDB HOST VLAN[11:0] OR HSR[15:0]"
hexmask.long.word 0x1C 0.--15. 1. "FDB_HOST_SA1,FDB HOST SA5:4"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_start_len_pru0,"
hexmask.long.byte 0x20 16.--19. 1. "FT1_LEN,Defines the total number of Bytes Filter1 will check before Valid bit is set"
hexmask.long.word 0x20 0.--14. 1. "FT1_START,Byte count start for Filter1. Any wrt will clear all Filter1 Status Bits"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_cfg_pru0,"
bitfld.long 0x24 14.--15. "FT1_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 12.--13. "FT1_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x24 10.--11. "FT1_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 8.--9. "FT1_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x24 6.--7. "FT1_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 4.--5. "FT1_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x24 2.--3. "FT1_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x24 0.--1. "FT1_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da0_pru0,"
hexmask.long 0x28 0.--31. 1. "FT1_0_DA0,Filter1 DA4:DA1"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da1_pru0,"
hexmask.long.word 0x2C 0.--15. 1. "FT1_0_DA1,Filter1 DA6:DA5"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask0_pru0,"
hexmask.long 0x30 0.--31. 1. "FT1_0_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask1_pru0,"
hexmask.long.word 0x34 0.--15. 1. "FT1_0_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da0_pru0,"
hexmask.long 0x38 0.--31. 1. "FT1_1_DA0,Filter1 DA4:DA1"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da1_pru0,"
hexmask.long.word 0x3C 0.--15. 1. "FT1_1_DA1,Filter1 DA6:DA5"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask0_pru0,"
hexmask.long 0x40 0.--31. 1. "FT1_1_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask1_pru0,"
hexmask.long.word 0x44 0.--15. 1. "FT1_1_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da0_pru0,"
hexmask.long 0x48 0.--31. 1. "FT1_2_DA0,Filter1 DA4:DA1"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da1_pru0,"
hexmask.long.word 0x4C 0.--15. 1. "FT1_2_DA1,Filter1 DA6:DA5"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask0_pru0,"
hexmask.long 0x50 0.--31. 1. "FT1_2_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask1_pru0,"
hexmask.long.word 0x54 0.--15. 1. "FT1_2_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da0_pru0,"
hexmask.long 0x58 0.--31. 1. "FT1_3_DA0,Filter1 DA4:DA1"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da1_pru0,"
hexmask.long.word 0x5C 0.--15. 1. "FT1_3_DA1,Filter1 DA6:DA5"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask0_pru0,"
hexmask.long 0x60 0.--31. 1. "FT1_3_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask1_pru0,"
hexmask.long.word 0x64 0.--15. 1. "FT1_3_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da0_pru0,"
hexmask.long 0x68 0.--31. 1. "FT1_4_DA0,Filter1 DA4:DA1"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da1_pru0,"
hexmask.long.word 0x6C 0.--15. 1. "FT1_4_DA1,Filter1 DA6:DA5"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask0_pru0,"
hexmask.long 0x70 0.--31. 1. "FT1_4_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask1_pru0,"
hexmask.long.word 0x74 0.--15. 1. "FT1_4_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da0_pru0,"
hexmask.long 0x78 0.--31. 1. "FT1_5_DA0,Filter1 DA4:DA1"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da1_pru0,"
hexmask.long.word 0x7C 0.--15. 1. "FT1_5_DA1,Filter1 DA6:DA5"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask0_pru0,"
hexmask.long 0x80 0.--31. 1. "FT1_5_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask1_pru0,"
hexmask.long.word 0x84 0.--15. 1. "FT1_5_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da0_pru0,"
hexmask.long 0x88 0.--31. 1. "FT1_6_DA0,Filter1 DA4:DA1"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da1_pru0,"
hexmask.long.word 0x8C 0.--15. 1. "FT1_6_DA1,Filter1 DA6:DA5"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask0_pru0,"
hexmask.long 0x90 0.--31. 1. "FT1_6_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask1_pru0,"
hexmask.long.word 0x94 0.--15. 1. "FT1_6_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da0_pru0,"
hexmask.long 0x98 0.--31. 1. "FT1_7_DA0,Filter1 DA4:DA1"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da1_pru0,"
hexmask.long.word 0x9C 0.--15. 1. "FT1_7_DA1,Filter1 DA6:DA5"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask0_pru0,"
hexmask.long 0xA0 0.--31. 1. "FT1_7_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask1_pru0,"
hexmask.long.word 0xA4 0.--15. 1. "FT1_7_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_pru0,"
hexmask.long.word 0xA8 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x10C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x110++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_0_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_0_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_len_pru0,"
bitfld.long 0x8 24. "FT3_0_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_0_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_0_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_0_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_0_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_0_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_0_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x12C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x130++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_1_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_1_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_len_pru0,"
bitfld.long 0x8 24. "FT3_1_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_1_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_1_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_1_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_1_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_1_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_1_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x14C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x150++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_2_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_2_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_len_pru0,"
bitfld.long 0x8 24. "FT3_2_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_2_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_2_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_2_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_2_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_2_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_2_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x16C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x170++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_3_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_3_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_len_pru0,"
bitfld.long 0x8 24. "FT3_3_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_3_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_3_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_3_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_3_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_3_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_3_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x18C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x190++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_4_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_4_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_len_pru0,"
bitfld.long 0x8 24. "FT3_4_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_4_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_4_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_4_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_4_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_4_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_4_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1AC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x1B0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_5_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_5_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_len_pru0,"
bitfld.long 0x8 24. "FT3_5_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_5_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_5_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_5_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_5_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_5_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_5_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1CC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x1D0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_6_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_6_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_len_pru0,"
bitfld.long 0x8 24. "FT3_6_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_6_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_6_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_6_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_6_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_6_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_6_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1EC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x1F0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_7_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_7_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_len_pru0,"
bitfld.long 0x8 24. "FT3_7_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_7_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_7_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_7_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_7_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_7_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_7_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x20C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x210++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_8_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_8_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_len_pru0,"
bitfld.long 0x8 24. "FT3_8_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_8_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_8_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_8_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_8_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_8CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_8_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_8_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x22C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x230++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_9_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_9_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_len_pru0,"
bitfld.long 0x8 24. "FT3_9_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_9_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_9_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_9_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_9_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_9CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_9_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_9_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x24C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x250++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_10_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_10_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_len_pru0,"
bitfld.long 0x8 24. "FT3_10_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_10_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_10_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_10_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_10_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_10CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_10_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_10_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x26C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x270++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_11_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_11_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_len_pru0,"
bitfld.long 0x8 24. "FT3_11_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_11_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_11_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_11_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_11_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_11CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_11_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_11_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x28C++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x290++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_12_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_12_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_len_pru0,"
bitfld.long 0x8 24. "FT3_12_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_12_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_12_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_12_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_12_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_12CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_12_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_12_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2AC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x2B0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_13_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_13_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_len_pru0,"
bitfld.long 0x8 24. "FT3_13_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_13_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_13_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_13_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_13_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_13CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_13_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_13_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2CC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x2D0++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_14_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_14_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_len_pru0,"
bitfld.long 0x8 24. "FT3_14_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_14_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_14_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_14_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_14_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_14CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_14_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_14_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_pru0,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2EC++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_auto_pru0,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x2F0++0x3E7
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_len_pru0,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_jmp_offset_pru0,"
hexmask.long.word 0x4 16.--30. 1. "FT3_15_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_15_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_len_pru0,"
bitfld.long 0x8 24. "FT3_15_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_15_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_15_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_cfg_pru0,"
hexmask.long.word 0xC 16.--31. 1. "FT3_15_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_15_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_15CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_pru0,"
hexmask.long 0x10 0.--31. 1. "FT3_15_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_mask_pru0,"
hexmask.long 0x14 0.--31. 1. "FT3_15_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p0_pru0,"
hexmask.long 0x18 0.--31. 1. "FT3_0_P0,Filter3 P4:P1"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p1_pru0,"
hexmask.long 0x1C 0.--31. 1. "FT3_0_P1,Filter3 P8:P5"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask0_pru0,"
hexmask.long 0x20 0.--31. 1. "FT3_0_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask1_pru0,"
hexmask.long 0x24 0.--31. 1. "FT3_0_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p0_pru0,"
hexmask.long 0x28 0.--31. 1. "FT3_1_P0,Filter3 P4:P1"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p1_pru0,"
hexmask.long 0x2C 0.--31. 1. "FT3_1_P1,Filter3 P8:P5"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask0_pru0,"
hexmask.long 0x30 0.--31. 1. "FT3_1_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask1_pru0,"
hexmask.long 0x34 0.--31. 1. "FT3_1_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p0_pru0,"
hexmask.long 0x38 0.--31. 1. "FT3_2_P0,Filter3 P4:P1"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p1_pru0,"
hexmask.long 0x3C 0.--31. 1. "FT3_2_P1,Filter3 P8:P5"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask0_pru0,"
hexmask.long 0x40 0.--31. 1. "FT3_2_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask1_pru0,"
hexmask.long 0x44 0.--31. 1. "FT3_2_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p0_pru0,"
hexmask.long 0x48 0.--31. 1. "FT3_3_P0,Filter3 P4:P1"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p1_pru0,"
hexmask.long 0x4C 0.--31. 1. "FT3_3_P1,Filter3 P8:P5"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask0_pru0,"
hexmask.long 0x50 0.--31. 1. "FT3_3_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask1_pru0,"
hexmask.long 0x54 0.--31. 1. "FT3_3_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p0_pru0,"
hexmask.long 0x58 0.--31. 1. "FT3_4_P0,Filter3 P4:P1"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p1_pru0,"
hexmask.long 0x5C 0.--31. 1. "FT3_4_P1,Filter3 P8:P5"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask0_pru0,"
hexmask.long 0x60 0.--31. 1. "FT3_4_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask1_pru0,"
hexmask.long 0x64 0.--31. 1. "FT3_4_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p0_pru0,"
hexmask.long 0x68 0.--31. 1. "FT3_5_P0,Filter3 P4:P1"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p1_pru0,"
hexmask.long 0x6C 0.--31. 1. "FT3_5_P1,Filter3 P8:P5"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask0_pru0,"
hexmask.long 0x70 0.--31. 1. "FT3_5_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask1_pru0,"
hexmask.long 0x74 0.--31. 1. "FT3_5_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p0_pru0,"
hexmask.long 0x78 0.--31. 1. "FT3_6_P0,Filter3 P4:P1"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p1_pru0,"
hexmask.long 0x7C 0.--31. 1. "FT3_6_P1,Filter3 P8:P5"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask0_pru0,"
hexmask.long 0x80 0.--31. 1. "FT3_6_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask1_pru0,"
hexmask.long 0x84 0.--31. 1. "FT3_6_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p0_pru0,"
hexmask.long 0x88 0.--31. 1. "FT3_7_P0,Filter3 P4:P1"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p1_pru0,"
hexmask.long 0x8C 0.--31. 1. "FT3_7_P1,Filter3 P8:P5"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask0_pru0,"
hexmask.long 0x90 0.--31. 1. "FT3_7_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask1_pru0,"
hexmask.long 0x94 0.--31. 1. "FT3_7_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p0_pru0,"
hexmask.long 0x98 0.--31. 1. "FT3_8_P0,Filter3 P4:P1"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p1_pru0,"
hexmask.long 0x9C 0.--31. 1. "FT3_8_P1,Filter3 P8:P5"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask0_pru0,"
hexmask.long 0xA0 0.--31. 1. "FT3_8_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask1_pru0,"
hexmask.long 0xA4 0.--31. 1. "FT3_8_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p0_pru0,"
hexmask.long 0xA8 0.--31. 1. "FT3_9_P0,Filter3 P4:P1"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p1_pru0,"
hexmask.long 0xAC 0.--31. 1. "FT3_9_P1,Filter3 P8:P5"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask0_pru0,"
hexmask.long 0xB0 0.--31. 1. "FT3_9_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask1_pru0,"
hexmask.long 0xB4 0.--31. 1. "FT3_9_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p0_pru0,"
hexmask.long 0xB8 0.--31. 1. "FT3_10_P0,Filter3 P4:P1"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p1_pru0,"
hexmask.long 0xBC 0.--31. 1. "FT3_10_P1,Filter3 P8:P5"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask0_pru0,"
hexmask.long 0xC0 0.--31. 1. "FT3_10_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask1_pru0,"
hexmask.long 0xC4 0.--31. 1. "FT3_10_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p0_pru0,"
hexmask.long 0xC8 0.--31. 1. "FT3_11_P0,Filter3 P4:P1"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p1_pru0,"
hexmask.long 0xCC 0.--31. 1. "FT3_11_P1,Filter3 P8:P5"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask0_pru0,"
hexmask.long 0xD0 0.--31. 1. "FT3_11_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask1_pru0,"
hexmask.long 0xD4 0.--31. 1. "FT3_11_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p0_pru0,"
hexmask.long 0xD8 0.--31. 1. "FT3_12_P0,Filter3 P4:P1"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p1_pru0,"
hexmask.long 0xDC 0.--31. 1. "FT3_12_P1,Filter3 P8:P5"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask0_pru0,"
hexmask.long 0xE0 0.--31. 1. "FT3_12_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask1_pru0,"
hexmask.long 0xE4 0.--31. 1. "FT3_12_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p0_pru0,"
hexmask.long 0xE8 0.--31. 1. "FT3_13_P0,Filter3 P4:P1"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p1_pru0,"
hexmask.long 0xEC 0.--31. 1. "FT3_13_P1,Filter3 P8:P5"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask0_pru0,"
hexmask.long 0xF0 0.--31. 1. "FT3_13_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask1_pru0,"
hexmask.long 0xF4 0.--31. 1. "FT3_13_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p0_pru0,"
hexmask.long 0xF8 0.--31. 1. "FT3_14_P0,Filter3 P4:P1"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p1_pru0,"
hexmask.long 0xFC 0.--31. 1. "FT3_14_P1,Filter3 P8:P5"
line.long 0x100 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask0_pru0,"
hexmask.long 0x100 0.--31. 1. "FT3_14_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x104 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask1_pru0,"
hexmask.long 0x104 0.--31. 1. "FT3_14_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x108 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p0_pru0,"
hexmask.long 0x108 0.--31. 1. "FT3_15_P0,Filter3 P4:P1"
line.long 0x10C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p1_pru0,"
hexmask.long 0x10C 0.--31. 1. "FT3_15_P1,Filter3 P8:P5"
line.long 0x110 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask0_pru0,"
hexmask.long 0x110 0.--31. 1. "FT3_15_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x114 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask1_pru0,"
hexmask.long 0x114 0.--31. 1. "FT3_15_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x118 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft_rx_ptr_pru0,"
hexmask.long 0x118 0.--31. 1. "FT_RX_PTR_PRU0,RX current filter Byte Count"
line.long 0x11C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_and_en_pru0,"
hexmask.long 0x11C 0.--31. 1. "RX_CLASS0_AND_EN,rx class and enabels"
line.long 0x120 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_or_en_pru0,"
hexmask.long 0x120 0.--31. 1. "RX_CLASS0_OR_EN,rx class or enabels"
line.long 0x124 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_and_en_pru0,"
hexmask.long 0x124 0.--31. 1. "RX_CLASS1_AND_EN,rx class and enabels"
line.long 0x128 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_or_en_pru0,"
hexmask.long 0x128 0.--31. 1. "RX_CLASS1_OR_EN,rx class or enabels"
line.long 0x12C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_and_en_pru0,"
hexmask.long 0x12C 0.--31. 1. "RX_CLASS2_AND_EN,rx class and enabels"
line.long 0x130 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_or_en_pru0,"
hexmask.long 0x130 0.--31. 1. "RX_CLASS2_OR_EN,rx class or enabels"
line.long 0x134 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_and_en_pru0,"
hexmask.long 0x134 0.--31. 1. "RX_CLASS3_AND_EN,rx class and enabels"
line.long 0x138 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_or_en_pru0,"
hexmask.long 0x138 0.--31. 1. "RX_CLASS3_OR_EN,rx class or enabels"
line.long 0x13C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_and_en_pru0,"
hexmask.long 0x13C 0.--31. 1. "RX_CLASS4_AND_EN,rx class and enabels"
line.long 0x140 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_or_en_pru0,"
hexmask.long 0x140 0.--31. 1. "RX_CLASS4_OR_EN,rx class or enabels"
line.long 0x144 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_and_en_pru0,"
hexmask.long 0x144 0.--31. 1. "RX_CLASS5_AND_EN,rx class and enabels"
line.long 0x148 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_or_en_pru0,"
hexmask.long 0x148 0.--31. 1. "RX_CLASS5_OR_EN,rx class or enabels"
line.long 0x14C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_and_en_pru0,"
hexmask.long 0x14C 0.--31. 1. "RX_CLASS6_AND_EN,rx class and enabels"
line.long 0x150 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_or_en_pru0,"
hexmask.long 0x150 0.--31. 1. "RX_CLASS6_OR_EN,rx class or enabels"
line.long 0x154 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_and_en_pru0,"
hexmask.long 0x154 0.--31. 1. "RX_CLASS7_AND_EN,rx class and enabels"
line.long 0x158 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_or_en_pru0,"
hexmask.long 0x158 0.--31. 1. "RX_CLASS7_OR_EN,rx class or enabels"
line.long 0x15C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_and_en_pru0,"
hexmask.long 0x15C 0.--31. 1. "RX_CLASS8_AND_EN,rx class and enabels"
line.long 0x160 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_or_en_pru0,"
hexmask.long 0x160 0.--31. 1. "RX_CLASS8_OR_EN,rx class or enabels"
line.long 0x164 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_and_en_pru0,"
hexmask.long 0x164 0.--31. 1. "RX_CLASS9_AND_EN,rx class and enabels"
line.long 0x168 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_or_en_pru0,"
hexmask.long 0x168 0.--31. 1. "RX_CLASS9_OR_EN,rx class or enabels"
line.long 0x16C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_and_en_pru0,"
hexmask.long 0x16C 0.--31. 1. "RX_CLASS10_AND_EN,rx class and enabels"
line.long 0x170 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_or_en_pru0,"
hexmask.long 0x170 0.--31. 1. "RX_CLASS10_OR_EN,rx class or enabels"
line.long 0x174 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_and_en_pru0,"
hexmask.long 0x174 0.--31. 1. "RX_CLASS11_AND_EN,rx class and enabels"
line.long 0x178 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_or_en_pru0,"
hexmask.long 0x178 0.--31. 1. "RX_CLASS11_OR_EN,rx class or enabels"
line.long 0x17C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_and_en_pru0,"
hexmask.long 0x17C 0.--31. 1. "RX_CLASS12_AND_EN,rx class and enabels"
line.long 0x180 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_or_en_pru0,"
hexmask.long 0x180 0.--31. 1. "RX_CLASS12_OR_EN,rx class or enabels"
line.long 0x184 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_and_en_pru0,"
hexmask.long 0x184 0.--31. 1. "RX_CLASS13_AND_EN,rx class and enabels"
line.long 0x188 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_or_en_pru0,"
hexmask.long 0x188 0.--31. 1. "RX_CLASS13_OR_EN,rx class or enabels"
line.long 0x18C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_and_en_pru0,"
hexmask.long 0x18C 0.--31. 1. "RX_CLASS14_AND_EN,rx class and enabels"
line.long 0x190 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_or_en_pru0,"
hexmask.long 0x190 0.--31. 1. "RX_CLASS14_OR_EN,rx class or enabels"
line.long 0x194 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_and_en_pru0,"
hexmask.long 0x194 0.--31. 1. "RX_CLASS15_AND_EN,rx class and enabels"
line.long 0x198 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_or_en_pru0,"
hexmask.long 0x198 0.--31. 1. "RX_CLASS15_OR_EN,rx class or enabels"
line.long 0x19C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg1_pru0,"
bitfld.long 0x19C 30.--31. "RX_CLASS15_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 28.--29. "RX_CLASS14_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 26.--27. "RX_CLASS13_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 24.--25. "RX_CLASS12_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 22.--23. "RX_CLASS11_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 20.--21. "RX_CLASS10_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 18.--19. "RX_CLASS9_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 16.--17. "RX_CLASS8_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 14.--15. "RX_CLASS7_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 12.--13. "RX_CLASS6_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 10.--11. "RX_CLASS5_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 8.--9. "RX_CLASS4_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 6.--7. "RX_CLASS3_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 4.--5. "RX_CLASS2_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 2.--3. "RX_CLASS1_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 0.--1. "RX_CLASS0_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
line.long 0x1A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg2_pru0,"
hexmask.long.word 0x1A0 16.--31. 1. "RX_CLASS_OR_NV,rx class or nv enable"
hexmask.long.word 0x1A0 0.--15. 1. "RX_CLASS_AND_NV,rx class and nv enable"
line.long 0x1A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates0_pru0,"
bitfld.long 0x1A4 8. "RX_RED_PHASE_EN0,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A4 6. "RX_ALLOW_MASK0,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A4 5. "RX_CLASS_RAW_MASK0,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A4 4. "RX_PHASE_MASK0,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A4 0.--2. "RX_RATE_GATE_SEL0,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates1_pru0,"
bitfld.long 0x1A8 8. "RX_RED_PHASE_EN1,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A8 6. "RX_ALLOW_MASK1,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A8 5. "RX_CLASS_RAW_MASK1,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A8 4. "RX_PHASE_MASK1,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A8 0.--2. "RX_RATE_GATE_SEL1,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates2_pru0,"
bitfld.long 0x1AC 8. "RX_RED_PHASE_EN2,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1AC 6. "RX_ALLOW_MASK2,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1AC 5. "RX_CLASS_RAW_MASK2,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1AC 4. "RX_PHASE_MASK2,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1AC 0.--2. "RX_RATE_GATE_SEL2,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates3_pru0,"
bitfld.long 0x1B0 8. "RX_RED_PHASE_EN3,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B0 6. "RX_ALLOW_MASK3,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B0 5. "RX_CLASS_RAW_MASK3,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B0 4. "RX_PHASE_MASK3,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B0 0.--2. "RX_RATE_GATE_SEL3,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates4_pru0,"
bitfld.long 0x1B4 8. "RX_RED_PHASE_EN4,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B4 6. "RX_ALLOW_MASK4,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B4 5. "RX_CLASS_RAW_MASK4,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B4 4. "RX_PHASE_MASK4,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B4 0.--2. "RX_RATE_GATE_SEL4,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates5_pru0,"
bitfld.long 0x1B8 8. "RX_RED_PHASE_EN5,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B8 6. "RX_ALLOW_MASK5,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B8 5. "RX_CLASS_RAW_MASK5,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B8 4. "RX_PHASE_MASK5,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B8 0.--2. "RX_RATE_GATE_SEL5,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates6_pru0,"
bitfld.long 0x1BC 8. "RX_RED_PHASE_EN6,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1BC 6. "RX_ALLOW_MASK6,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1BC 5. "RX_CLASS_RAW_MASK6,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1BC 4. "RX_PHASE_MASK6,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1BC 0.--2. "RX_RATE_GATE_SEL6,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates7_pru0,"
bitfld.long 0x1C0 8. "RX_RED_PHASE_EN7,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C0 6. "RX_ALLOW_MASK7,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C0 5. "RX_CLASS_RAW_MASK7,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C0 4. "RX_PHASE_MASK7,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C0 0.--2. "RX_RATE_GATE_SEL7,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates8_pru0,"
bitfld.long 0x1C4 8. "RX_RED_PHASE_EN8,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C4 6. "RX_ALLOW_MASK8,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C4 5. "RX_CLASS_RAW_MASK8,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C4 4. "RX_PHASE_MASK8,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C4 0.--2. "RX_RATE_GATE_SEL8,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates9_pru0,"
bitfld.long 0x1C8 8. "RX_RED_PHASE_EN9,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C8 6. "RX_ALLOW_MASK9,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C8 5. "RX_CLASS_RAW_MASK9,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C8 4. "RX_PHASE_MASK9,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C8 0.--2. "RX_RATE_GATE_SEL9,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates10_pru0,"
bitfld.long 0x1CC 8. "RX_RED_PHASE_EN10,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1CC 6. "RX_ALLOW_MASK10,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1CC 5. "RX_CLASS_RAW_MASK10,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1CC 4. "RX_PHASE_MASK10,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1CC 0.--2. "RX_RATE_GATE_SEL10,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates11_pru0,"
bitfld.long 0x1D0 8. "RX_RED_PHASE_EN11,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D0 6. "RX_ALLOW_MASK11,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 5. "RX_CLASS_RAW_MASK11,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D0 4. "RX_PHASE_MASK11,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 0.--2. "RX_RATE_GATE_SEL11,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates12_pru0,"
bitfld.long 0x1D4 8. "RX_RED_PHASE_EN12,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D4 6. "RX_ALLOW_MASK12,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D4 5. "RX_CLASS_RAW_MASK12,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D4 4. "RX_PHASE_MASK12,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D4 0.--2. "RX_RATE_GATE_SEL12,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates13_pru0,"
bitfld.long 0x1D8 8. "RX_RED_PHASE_EN13,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D8 6. "RX_ALLOW_MASK13,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D8 5. "RX_CLASS_RAW_MASK13,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D8 4. "RX_PHASE_MASK13,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D8 0.--2. "RX_RATE_GATE_SEL13,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates14_pru0,"
bitfld.long 0x1DC 8. "RX_RED_PHASE_EN14,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1DC 6. "RX_ALLOW_MASK14,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1DC 5. "RX_CLASS_RAW_MASK14,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1DC 4. "RX_PHASE_MASK14,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1DC 0.--2. "RX_RATE_GATE_SEL14,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates15_pru0,"
bitfld.long 0x1E0 8. "RX_RED_PHASE_EN15,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1E0 6. "RX_ALLOW_MASK15,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 5. "RX_CLASS_RAW_MASK15,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1E0 4. "RX_PHASE_MASK15,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 0.--2. "RX_RATE_GATE_SEL15,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_green_pru0,"
rbitfld.long 0x1E4 4. "RX_GREEN_VAL,0 RED 1 GREEN status" "0,1"
hexmask.long.byte 0x1E4 0.--3. 1. "RX_GREEN_CMP_SEL,define which IEP CMP start green"
line.long 0x1E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_sa_hash_pru0,"
hexmask.long.word 0x1E8 0.--9. 1. "SA_HASH_SEED,SA Hash Seed"
line.long 0x1EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_pru0,"
hexmask.long.word 0x1EC 0.--9. 1. "CONN_HASH_SEED,Connection Hash Seed"
line.long 0x1F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_start_pru0,"
hexmask.long.word 0x1F0 0.--14. 1. "CONN_HASH_START,Connection Hash Start which 4 Bytes to hash"
line.long 0x1F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg0_pru0,"
hexmask.long 0x1F4 0.--31. 1. "RX_RATE_CIR_IDLE0,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg1_pru0,"
hexmask.long 0x1F8 0.--31. 1. "RX_RATE_CIR_IDLE1,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg2_pru0,"
hexmask.long 0x1FC 0.--31. 1. "RX_RATE_CIR_IDLE2,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x200 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg3_pru0,"
hexmask.long 0x200 0.--31. 1. "RX_RATE_CIR_IDLE3,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x204 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg4_pru0,"
hexmask.long 0x204 0.--31. 1. "RX_RATE_CIR_IDLE4,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x208 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg5_pru0,"
hexmask.long 0x208 0.--31. 1. "RX_RATE_CIR_IDLE5,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x20C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg6_pru0,"
hexmask.long 0x20C 0.--31. 1. "RX_RATE_CIR_IDLE6,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x210 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg7_pru0,"
hexmask.long 0x210 0.--31. 1. "RX_RATE_CIR_IDLE7,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x214 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel0_pru0,"
hexmask.long.byte 0x214 24.--29. 1. "RX_RATE_SRC_SEL3,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 16.--21. 1. "RX_RATE_SRC_SEL2,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x214 8.--13. 1. "RX_RATE_SRC_SEL1,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 0.--5. 1. "RX_RATE_SRC_SEL0,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x218 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel1_pru0,"
hexmask.long.byte 0x218 24.--29. 1. "RX_RATE_SRC_SEL7,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 16.--21. 1. "RX_RATE_SRC_SEL6,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x218 8.--13. 1. "RX_RATE_SRC_SEL5,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 0.--5. 1. "RX_RATE_SRC_SEL4,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x21C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_0_pru0,"
hexmask.long 0x21C 0.--31. 1. "TX_RATE_CIR_IDLE0,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x220 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_0_pru0,"
rbitfld.long 0x220 17. "TX_RATE_ALLOW0,TX Rate Pkt Enable" "0,1"
bitfld.long 0x220 16. "TX_RATE_EN0,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x220 0.--15. 1. "TX_RATE_LEN0,TX Rate Pkt Length"
line.long 0x224 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_1_pru0,"
hexmask.long 0x224 0.--31. 1. "TX_RATE_CIR_IDLE1,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x228 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_1_pru0,"
rbitfld.long 0x228 17. "TX_RATE_ALLOW1,TX Rate Pkt Enable" "0,1"
bitfld.long 0x228 16. "TX_RATE_EN1,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x228 0.--15. 1. "TX_RATE_LEN1,TX Rate Pkt Length"
line.long 0x22C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_2_pru0,"
hexmask.long 0x22C 0.--31. 1. "TX_RATE_CIR_IDLE2,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x230 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_2_pru0,"
rbitfld.long 0x230 17. "TX_RATE_ALLOW2,TX Rate Pkt Enable" "0,1"
bitfld.long 0x230 16. "TX_RATE_EN2,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x230 0.--15. 1. "TX_RATE_LEN2,TX Rate Pkt Length"
line.long 0x234 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_3_pru0,"
hexmask.long 0x234 0.--31. 1. "TX_RATE_CIR_IDLE3,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x238 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_3_pru0,"
rbitfld.long 0x238 17. "TX_RATE_ALLOW3,TX Rate Pkt Enable" "0,1"
bitfld.long 0x238 16. "TX_RATE_EN3,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x238 0.--15. 1. "TX_RATE_LEN3,TX Rate Pkt Length"
line.long 0x23C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_4_pru0,"
hexmask.long 0x23C 0.--31. 1. "TX_RATE_CIR_IDLE4,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x240 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_4_pru0,"
rbitfld.long 0x240 17. "TX_RATE_ALLOW4,TX Rate Pkt Enable" "0,1"
bitfld.long 0x240 16. "TX_RATE_EN4,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x240 0.--15. 1. "TX_RATE_LEN4,TX Rate Pkt Length"
line.long 0x244 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_5_pru0,"
hexmask.long 0x244 0.--31. 1. "TX_RATE_CIR_IDLE5,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x248 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_5_pru0,"
rbitfld.long 0x248 17. "TX_RATE_ALLOW5,TX Rate Pkt Enable" "0,1"
bitfld.long 0x248 16. "TX_RATE_EN5,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x248 0.--15. 1. "TX_RATE_LEN5,TX Rate Pkt Length"
line.long 0x24C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_6_pru0,"
hexmask.long 0x24C 0.--31. 1. "TX_RATE_CIR_IDLE6,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x250 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_6_pru0,"
rbitfld.long 0x250 17. "TX_RATE_ALLOW6,TX Rate Pkt Enable" "0,1"
bitfld.long 0x250 16. "TX_RATE_EN6,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x250 0.--15. 1. "TX_RATE_LEN6,TX Rate Pkt Length"
line.long 0x254 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_7_pru0,"
hexmask.long 0x254 0.--31. 1. "TX_RATE_CIR_IDLE7,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x258 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_7_pru0,"
rbitfld.long 0x258 17. "TX_RATE_ALLOW7,TX Rate Pkt Enable" "0,1"
bitfld.long 0x258 16. "TX_RATE_EN7,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x258 0.--15. 1. "TX_RATE_LEN7,TX Rate Pkt Length"
line.long 0x25C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_good_pru0,"
hexmask.long 0x25C 0.--31. 1. "RX_GOOD_FRM_CNT,RX Good Frame Count Inc on none min err max err crc err odd err  Wrt subtracts"
line.long 0x260 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bc_pru0,"
hexmask.long.word 0x260 0.--15. 1. "RX_BC_FRM_CNT,RX BC Frame Count Inc on BC type  Wrt subtracts"
line.long 0x264 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mc_pru0,"
hexmask.long.word 0x264 0.--15. 1. "RX_MC_FRM_CNT,RX MC Frame Count Inc on MC type  Wrt subtracts"
line.long 0x268 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_crc_err_pru0,"
hexmask.long.word 0x268 0.--15. 1. "RX_CRC_ERR_FRM_CNT,RX CRC Err Frame Count Inc on crc err  Wrt subtracts"
line.long 0x26C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mii_err_pru0,"
hexmask.long.word 0x26C 0.--15. 1. "RX_MII_ERR_FRM_CNT,RX MII Err Frame Count Inc on mii sgmii rgmii err  Wrt subtracts"
line.long 0x270 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_odd_err_pru0,"
hexmask.long.word 0x270 0.--15. 1. "RX_ODD_ERR_FRM_CNT,RX Odd Nibble Frame Count Inc on odd nibble mii  Wrt subtracts"
line.long 0x274 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_size_pru0,"
hexmask.long.word 0x274 0.--15. 1. "RX_MAX_SIZE_FRM,RX MAX Size Frame Count Limit"
line.long 0x278 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_err_pru0,"
hexmask.long.word 0x278 0.--15. 1. "RX_MAX_ERR_FRM_CNT,RX MAX Size Err Frame Count Inc if > than Limit  Wrt subtracts"
line.long 0x27C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_size_pru0,"
hexmask.long.word 0x27C 0.--15. 1. "RX_MIN_SIZE_FRM,RX MIN Size Frame Limit"
line.long 0x280 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_err_pru0,"
hexmask.long.word 0x280 0.--15. 1. "RX_MIN_ERR_FRM_CNT,RX MIN Size Frame Count Inc if < than limit  Wrt subtracts"
line.long 0x284 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_overrun_err_pru0,"
hexmask.long.word 0x284 0.--15. 1. "RX_OVERRUN_ERR_FRM_CNT,RX L1 FIFO overflow Frame Count Inc on overflow event  Wrt subtracts"
line.long 0x288 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class0_hit_pru0,"
hexmask.long 0x288 0.--31. 1. "RX_STAT_CLASS0_PRU0,RX Class0 Hit Count  Wrt subtracts"
line.long 0x28C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class1_hit_pru0,"
hexmask.long 0x28C 0.--31. 1. "RX_STAT_CLASS1_PRU0,RX Class1 Hit Count  Wrt subtracts"
line.long 0x290 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class2_hit_pru0,"
hexmask.long 0x290 0.--31. 1. "RX_STAT_CLASS2_PRU0,RX Class2 Hit Count  Wrt subtracts"
line.long 0x294 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class3_hit_pru0,"
hexmask.long 0x294 0.--31. 1. "RX_STAT_CLASS3_PRU0,RX Class3 Hit Count  Wrt subtracts"
line.long 0x298 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class4_hit_pru0,"
hexmask.long 0x298 0.--31. 1. "RX_STAT_CLASS4_PRU0,RX Class4 Hit Count  Wrt subtracts"
line.long 0x29C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class5_hit_pru0,"
hexmask.long 0x29C 0.--31. 1. "RX_STAT_CLASS5_PRU0,RX Class5 Hit Count  Wrt subtracts"
line.long 0x2A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class6_hit_pru0,"
hexmask.long 0x2A0 0.--31. 1. "RX_STAT_CLASS6_PRU0,RX Class6 Hit Count  Wrt subtracts"
line.long 0x2A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class7_hit_pru0,"
hexmask.long 0x2A4 0.--31. 1. "RX_STAT_CLASS7_PRU0,RX Class7 Hit Count  Wrt subtracts"
line.long 0x2A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class8_hit_pru0,"
hexmask.long 0x2A8 0.--31. 1. "RX_STAT_CLASS8_PRU0,RX Class8 Hit Count  Wrt subtracts"
line.long 0x2AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class9_hit_pru0,"
hexmask.long 0x2AC 0.--31. 1. "RX_STAT_CLASS9_PRU0,RX Class9 Hit Count  Wrt subtracts"
line.long 0x2B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class10_hit_pru0,"
hexmask.long 0x2B0 0.--31. 1. "RX_STAT_CLASS10_PRU0,RX Class10 Hit Count  Wrt subtracts"
line.long 0x2B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class11_hit_pru0,"
hexmask.long 0x2B4 0.--31. 1. "RX_STAT_CLASS11_PRU0,RX Class11 Hit Count  Wrt subtracts"
line.long 0x2B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class12_hit_pru0,"
hexmask.long 0x2B8 0.--31. 1. "RX_STAT_CLASS12_PRU0,RX Class12 Hit Count  Wrt subtracts"
line.long 0x2BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class13_hit_pru0,"
hexmask.long 0x2BC 0.--31. 1. "RX_STAT_CLASS13_PRU0,RX Class13 Hit Count  Wrt subtracts"
line.long 0x2C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class14_hit_pru0,"
hexmask.long 0x2C0 0.--31. 1. "RX_STAT_CLASS14_PRU0,RX Class14 Hit Count  Wrt subtracts"
line.long 0x2C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class15_hit_pru0,"
hexmask.long 0x2C4 0.--31. 1. "RX_STAT_CLASS15_PRU0,RX Class15 Hit Count  Wrt subtracts"
line.long 0x2C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_smd_frag_err_pru0,"
hexmask.long.byte 0x2C8 24.--31. 1. "RX_STAT_SMD_ERR_PRU0,RX SMDS Error Count  Inc when first none 0x55 does not match any valid SMD  Wrt subtracts"
hexmask.long.byte 0x2C8 16.--23. 1. "RX_STAT_FRAG_ERR_PRU0,RX Frag_Cnt Seq Error Count  Wrt subtracts"
newline
hexmask.long.byte 0x2C8 8.--15. 1. "RX_STAT_SMDC_ERR_PRU0,RX SMDCx Seq Error Count  Wrt subtracts"
hexmask.long.byte 0x2C8 0.--7. 1. "RX_STAT_SMDS_ERR_PRU0,RX SMDSx Seq Error Count  Wrt subtracts"
line.long 0x2CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_size_pru0,"
hexmask.long.word 0x2CC 0.--13. 1. "RX_STAT_BKT1_SIZE,RX Bucket1 Byte Size"
line.long 0x2D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_size_pru0,"
hexmask.long.word 0x2D0 0.--13. 1. "RX_STAT_BKT2_SIZE,RX Bucket2 Byte Size"
line.long 0x2D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_size_pru0,"
hexmask.long.word 0x2D4 0.--13. 1. "RX_STAT_BKT3_SIZE,RX Bucket3 Byte Size"
line.long 0x2D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_size_pru0,"
hexmask.long.word 0x2D8 0.--13. 1. "RX_STAT_BKT4_SIZE,RX Bucket4 Byte Size"
line.long 0x2DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_64_pru0,"
hexmask.long.word 0x2DC 0.--15. 1. "RX_64_FRM_CNT,RX 64Byte Frame Count Inc if 64B size"
line.long 0x2E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_pru0,"
hexmask.long.word 0x2E0 0.--15. 1. "RX_STAT_BKT1,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
line.long 0x2E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_pru0,"
hexmask.long.word 0x2E4 0.--15. 1. "RX_STAT_BKT2,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x2E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_pru0,"
hexmask.long.word 0x2E8 0.--15. 1. "RX_STAT_BKT3,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x2EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_pru0,"
hexmask.long.word 0x2EC 0.--15. 1. "RX_STAT_BKT4,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x2F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt5_pru0,"
hexmask.long.word 0x2F0 0.--15. 1. "RX_STAT_BKT5,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
line.long 0x2F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_total_bytes_pru0,"
hexmask.long 0x2F4 0.--31. 1. "RX_STAT_TOTAL_BYTES_PRU,RX Total Byte Count"
line.long 0x2F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rxtx_stat_total_bytes_pru0,"
hexmask.long 0x2F8 0.--31. 1. "RXTX_STAT_TOTAL_BYTES_PRU,RX and TX Total Byte Count"
line.long 0x2FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_good_port0,"
hexmask.long 0x2FC 0.--31. 1. "TX_GOOD_FRM_CNT,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
line.long 0x300 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bc_port0,"
hexmask.long.word 0x300 0.--15. 1. "TX_BC_FRM_CNT,TX BC Frame Count Inc if BC"
line.long 0x304 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_mc_port0,"
hexmask.long.word 0x304 0.--15. 1. "TX_MC_FRM_CNT,TX MC Frame Count Inc if MC"
line.long 0x308 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_odd_err_port0,"
hexmask.long.word 0x308 0.--15. 1. "TX_ODD_ERR_FRM_CNT,TX Odd Nibble Frame Count Inc if mii odd nibble"
line.long 0x30C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_underflow_err_port0,"
hexmask.long.word 0x30C 0.--15. 1. "TX_UNDERFLOW_CNT,TX MAX Underflow Error Cnt"
line.long 0x310 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_size_port0,"
hexmask.long.word 0x310 0.--15. 1. "TX_MAX_SIZE_FRM,TX MAX Size Frame Count Limit"
line.long 0x314 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_err_port0,"
hexmask.long.word 0x314 0.--15. 1. "TX_MAX_ERR_FRM_CNT,TX MAX Size Err Frame Count Inc if > max Limit"
line.long 0x318 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_size_port0,"
hexmask.long.word 0x318 0.--15. 1. "TX_MIN_SIZE_FRM,TX MIN Size Frame Count Limit"
line.long 0x31C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_err_port0,"
hexmask.long.word 0x31C 0.--15. 1. "TX_MIN_ERR_FRM_CNT,TX MIN Size Err Frame Count Inc if < min Limit"
line.long 0x320 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_size_port0,"
hexmask.long.word 0x320 0.--13. 1. "TX_STAT_BKT1_SIZE,TX Bucket1 Byte Size"
line.long 0x324 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_size_port0,"
hexmask.long.word 0x324 0.--13. 1. "TX_STAT_BKT2_SIZE,TX Bucket2 Byte Size"
line.long 0x328 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_size_port0,"
hexmask.long.word 0x328 0.--13. 1. "TX_STAT_BKT3_SIZE,TX Bucket3 Byte Size"
line.long 0x32C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_size_port0,"
hexmask.long.word 0x32C 0.--13. 1. "TX_STAT_BKT4_SIZE,TX Bucket4 Byte Size"
line.long 0x330 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_64_port0,"
hexmask.long.word 0x330 0.--15. 1. "TX_64_FRM_CNT,TX 64Byte Frame Count Inc if 64B"
line.long 0x334 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_port0,"
hexmask.long.word 0x334 0.--15. 1. "TX_STAT_BKT1,TX Bucket1 Inc if <= than Bucket1"
line.long 0x338 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_port0,"
hexmask.long.word 0x338 0.--15. 1. "TX_STAT_BKT2,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x33C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_port0,"
hexmask.long.word 0x33C 0.--15. 1. "TX_STAT_BKT3,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x340 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_port0,"
hexmask.long.word 0x340 0.--15. 1. "TX_STAT_BKT4,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x344 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt5_port0,"
hexmask.long.word 0x344 0.--15. 1. "TX_STAT_BKT5,TX Bucket5 Inc if > than Bucket4 Byte Size"
line.long 0x348 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_total_bytes_port0,"
hexmask.long 0x348 0.--31. 1. "TX_TOTAL_STAT_BYTES_PORT,TX Total Byte Count of all Frames"
line.long 0x34C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_tag_port0,"
hexmask.long 0x34C 0.--31. 1. "TX_HSR_TAG,HSR TAG"
line.long 0x350 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_seq_port0,"
hexmask.long.word 0x350 0.--15. 1. "TX_HSR_SEQ,HSR Seq count. It will incr for every HSR type"
line.long 0x354 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_type_tag_port0,"
hexmask.long.word 0x354 0.--15. 1. "TX_VLAN_TYPE_TAG,TX VLAN Type Tag  match to enable VLAN removal"
line.long 0x358 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_ins_tag_port0,"
hexmask.long 0x358 0.--31. 1. "TX_VLAN_INS_TAG,TX VLAN Insertion"
line.long 0x35C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_start_len_pru1,"
hexmask.long.byte 0x35C 16.--19. 1. "FT1_LEN,Defines the total number of Bytes Filter1 will check before Valid bit is set"
hexmask.long.word 0x35C 0.--14. 1. "FT1_START,Byte count start for Filter1. Any wrt will clear all Filter1 Status Bits"
line.long 0x360 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_cfg_pru1,"
bitfld.long 0x360 14.--15. "FT1_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 12.--13. "FT1_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x360 10.--11. "FT1_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 8.--9. "FT1_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x360 6.--7. "FT1_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 4.--5. "FT1_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
newline
bitfld.long 0x360 2.--3. "FT1_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
bitfld.long 0x360 0.--1. "FT1_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x364 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da0_pru1,"
hexmask.long 0x364 0.--31. 1. "FT1_0_DA0,Filter1 DA4:DA1"
line.long 0x368 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da1_pru1,"
hexmask.long.word 0x368 0.--15. 1. "FT1_0_DA1,Filter1 DA6:DA5"
line.long 0x36C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask0_pru1,"
hexmask.long 0x36C 0.--31. 1. "FT1_0_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x370 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_0_da_mask1_pru1,"
hexmask.long.word 0x370 0.--15. 1. "FT1_0_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x374 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da0_pru1,"
hexmask.long 0x374 0.--31. 1. "FT1_1_DA0,Filter1 DA4:DA1"
line.long 0x378 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da1_pru1,"
hexmask.long.word 0x378 0.--15. 1. "FT1_1_DA1,Filter1 DA6:DA5"
line.long 0x37C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask0_pru1,"
hexmask.long 0x37C 0.--31. 1. "FT1_1_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x380 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_1_da_mask1_pru1,"
hexmask.long.word 0x380 0.--15. 1. "FT1_1_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x384 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da0_pru1,"
hexmask.long 0x384 0.--31. 1. "FT1_2_DA0,Filter1 DA4:DA1"
line.long 0x388 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da1_pru1,"
hexmask.long.word 0x388 0.--15. 1. "FT1_2_DA1,Filter1 DA6:DA5"
line.long 0x38C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask0_pru1,"
hexmask.long 0x38C 0.--31. 1. "FT1_2_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x390 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_2_da_mask1_pru1,"
hexmask.long.word 0x390 0.--15. 1. "FT1_2_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x394 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da0_pru1,"
hexmask.long 0x394 0.--31. 1. "FT1_3_DA0,Filter1 DA4:DA1"
line.long 0x398 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da1_pru1,"
hexmask.long.word 0x398 0.--15. 1. "FT1_3_DA1,Filter1 DA6:DA5"
line.long 0x39C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask0_pru1,"
hexmask.long 0x39C 0.--31. 1. "FT1_3_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_3_da_mask1_pru1,"
hexmask.long.word 0x3A0 0.--15. 1. "FT1_3_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da0_pru1,"
hexmask.long 0x3A4 0.--31. 1. "FT1_4_DA0,Filter1 DA4:DA1"
line.long 0x3A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da1_pru1,"
hexmask.long.word 0x3A8 0.--15. 1. "FT1_4_DA1,Filter1 DA6:DA5"
line.long 0x3AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask0_pru1,"
hexmask.long 0x3AC 0.--31. 1. "FT1_4_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_4_da_mask1_pru1,"
hexmask.long.word 0x3B0 0.--15. 1. "FT1_4_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da0_pru1,"
hexmask.long 0x3B4 0.--31. 1. "FT1_5_DA0,Filter1 DA4:DA1"
line.long 0x3B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da1_pru1,"
hexmask.long.word 0x3B8 0.--15. 1. "FT1_5_DA1,Filter1 DA6:DA5"
line.long 0x3BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask0_pru1,"
hexmask.long 0x3BC 0.--31. 1. "FT1_5_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_5_da_mask1_pru1,"
hexmask.long.word 0x3C0 0.--15. 1. "FT1_5_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da0_pru1,"
hexmask.long 0x3C4 0.--31. 1. "FT1_6_DA0,Filter1 DA4:DA1"
line.long 0x3C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da1_pru1,"
hexmask.long.word 0x3C8 0.--15. 1. "FT1_6_DA1,Filter1 DA6:DA5"
line.long 0x3CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask0_pru1,"
hexmask.long 0x3CC 0.--31. 1. "FT1_6_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_6_da_mask1_pru1,"
hexmask.long.word 0x3D0 0.--15. 1. "FT1_6_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da0_pru1,"
hexmask.long 0x3D4 0.--31. 1. "FT1_7_DA0,Filter1 DA4:DA1"
line.long 0x3D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da1_pru1,"
hexmask.long.word 0x3D8 0.--15. 1. "FT1_7_DA1,Filter1 DA6:DA5"
line.long 0x3DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask0_pru1,"
hexmask.long 0x3DC 0.--31. 1. "FT1_7_DA_MASK0,Filter1 MDA4:MDA1 set to 1 to mask that bit"
line.long 0x3E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft1_7_da_mask1_pru1,"
hexmask.long.word 0x3E0 0.--15. 1. "FT1_7_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
line.long 0x3E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_pru1,"
hexmask.long.word 0x3E4 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6D8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x6DC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_0_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_0_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_len_pru1,"
bitfld.long 0x8 24. "FT3_0_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_0_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_0_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_0_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_0_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_0CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_0_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_0_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6F8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x6FC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_1_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_1_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_len_pru1,"
bitfld.long 0x8 24. "FT3_1_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_1_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_1_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_1_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_1_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_1CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_1_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_1_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x718++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x71C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_2_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_2_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_len_pru1,"
bitfld.long 0x8 24. "FT3_2_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_2_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_2_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_2_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_2_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_2CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_2_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_2_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x738++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x73C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_3_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_3_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_len_pru1,"
bitfld.long 0x8 24. "FT3_3_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_3_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_3_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_3_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_3_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_3CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_3_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_3_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x758++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x75C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_4_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_4_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_len_pru1,"
bitfld.long 0x8 24. "FT3_4_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_4_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_4_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_4_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_4_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_4CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_4_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_4_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x778++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x77C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_5_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_5_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_len_pru1,"
bitfld.long 0x8 24. "FT3_5_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_5_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_5_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_5_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_5_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_5CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_5_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_5_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x798++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x79C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_6_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_6_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_len_pru1,"
bitfld.long 0x8 24. "FT3_6_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_6_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_6_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_6_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_6_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_6CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_6_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_6_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7B8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x7BC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_7_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_7_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_len_pru1,"
bitfld.long 0x8 24. "FT3_7_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_7_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_7_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_7_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_7_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_7CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_7_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_7_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7D8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x7DC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_8_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_8_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_len_pru1,"
bitfld.long 0x8 24. "FT3_8_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_8_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_8_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_8_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_8_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_8CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_8_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_8_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7F8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x7FC++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_9_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_9_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_len_pru1,"
bitfld.long 0x8 24. "FT3_9_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_9_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_9_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_9_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_9_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_9CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_9_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_9_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x818++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x81C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_10_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_10_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_len_pru1,"
bitfld.long 0x8 24. "FT3_10_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_10_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_10_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_10_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_10_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_10CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_10_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_10_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x838++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x83C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_11_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_11_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_len_pru1,"
bitfld.long 0x8 24. "FT3_11_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_11_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_11_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_11_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_11_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_11CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_11_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_11_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x858++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x85C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_12_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_12_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_len_pru1,"
bitfld.long 0x8 24. "FT3_12_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_12_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_12_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_12_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_12_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_12CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_12_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_12_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x878++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x87C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_13_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_13_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_len_pru1,"
bitfld.long 0x8 24. "FT3_13_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_13_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_13_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_13_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_13_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_13CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_13_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_13_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x898++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x89C++0x1B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_14_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_14_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_len_pru1,"
bitfld.long 0x8 24. "FT3_14_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_14_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_14_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_14_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_14_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_14CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_14_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_14_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_pru1,"
hexmask.long.word 0x18 0.--14. 1. "FT3_START,Byte count start for Filter3. Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x8B8++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_auto_pru1,"
hexmask.long.word 0x0 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
group.long 0x8BC++0x35B
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_start_len_pru1,"
bitfld.long 0x0 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag  rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_jmp_offset_pru1,"
hexmask.long.word 0x4 16.--30. 1. "FT3_15_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x4 0.--14. 1. "FT3_15_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_len_pru1,"
bitfld.long 0x8 24. "FT3_15_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "FT3_15_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function"
newline
hexmask.long.word 0x8 0.--8. 1. "FT3_15_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_cfg_pru1,"
hexmask.long.word 0xC 16.--31. 1. "FT3_15_TRIG_OR_EN,Trigger ft3 select for auto skip enable  if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0xC 2. "FT3_15_VLAN_SKIP_EN,0: Disabled 1: Enable" "0: Disabled,1: Enable"
newline
bitfld.long 0xC 0.--1. "FT3_15CFG,0: Disabled 1: EQ 2: GT 3: LT" "0: Disabled,1: EQ,2: GT,3: LT"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_pru1,"
hexmask.long 0x10 0.--31. 1. "FT3_15_T,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_t_mask_pru1,"
hexmask.long 0x14 0.--31. 1. "FT3_15_T_MASK,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p0_pru1,"
hexmask.long 0x18 0.--31. 1. "FT3_0_P0,Filter3 P4:P1"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p1_pru1,"
hexmask.long 0x1C 0.--31. 1. "FT3_0_P1,Filter3 P8:P5"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask0_pru1,"
hexmask.long 0x20 0.--31. 1. "FT3_0_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_0_p_mask1_pru1,"
hexmask.long 0x24 0.--31. 1. "FT3_0_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p0_pru1,"
hexmask.long 0x28 0.--31. 1. "FT3_1_P0,Filter3 P4:P1"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p1_pru1,"
hexmask.long 0x2C 0.--31. 1. "FT3_1_P1,Filter3 P8:P5"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask0_pru1,"
hexmask.long 0x30 0.--31. 1. "FT3_1_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_1_p_mask1_pru1,"
hexmask.long 0x34 0.--31. 1. "FT3_1_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p0_pru1,"
hexmask.long 0x38 0.--31. 1. "FT3_2_P0,Filter3 P4:P1"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p1_pru1,"
hexmask.long 0x3C 0.--31. 1. "FT3_2_P1,Filter3 P8:P5"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask0_pru1,"
hexmask.long 0x40 0.--31. 1. "FT3_2_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_2_p_mask1_pru1,"
hexmask.long 0x44 0.--31. 1. "FT3_2_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p0_pru1,"
hexmask.long 0x48 0.--31. 1. "FT3_3_P0,Filter3 P4:P1"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p1_pru1,"
hexmask.long 0x4C 0.--31. 1. "FT3_3_P1,Filter3 P8:P5"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask0_pru1,"
hexmask.long 0x50 0.--31. 1. "FT3_3_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_3_p_mask1_pru1,"
hexmask.long 0x54 0.--31. 1. "FT3_3_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p0_pru1,"
hexmask.long 0x58 0.--31. 1. "FT3_4_P0,Filter3 P4:P1"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p1_pru1,"
hexmask.long 0x5C 0.--31. 1. "FT3_4_P1,Filter3 P8:P5"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask0_pru1,"
hexmask.long 0x60 0.--31. 1. "FT3_4_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_4_p_mask1_pru1,"
hexmask.long 0x64 0.--31. 1. "FT3_4_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p0_pru1,"
hexmask.long 0x68 0.--31. 1. "FT3_5_P0,Filter3 P4:P1"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p1_pru1,"
hexmask.long 0x6C 0.--31. 1. "FT3_5_P1,Filter3 P8:P5"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask0_pru1,"
hexmask.long 0x70 0.--31. 1. "FT3_5_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_5_p_mask1_pru1,"
hexmask.long 0x74 0.--31. 1. "FT3_5_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p0_pru1,"
hexmask.long 0x78 0.--31. 1. "FT3_6_P0,Filter3 P4:P1"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p1_pru1,"
hexmask.long 0x7C 0.--31. 1. "FT3_6_P1,Filter3 P8:P5"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask0_pru1,"
hexmask.long 0x80 0.--31. 1. "FT3_6_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_6_p_mask1_pru1,"
hexmask.long 0x84 0.--31. 1. "FT3_6_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p0_pru1,"
hexmask.long 0x88 0.--31. 1. "FT3_7_P0,Filter3 P4:P1"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p1_pru1,"
hexmask.long 0x8C 0.--31. 1. "FT3_7_P1,Filter3 P8:P5"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask0_pru1,"
hexmask.long 0x90 0.--31. 1. "FT3_7_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_7_p_mask1_pru1,"
hexmask.long 0x94 0.--31. 1. "FT3_7_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p0_pru1,"
hexmask.long 0x98 0.--31. 1. "FT3_8_P0,Filter3 P4:P1"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p1_pru1,"
hexmask.long 0x9C 0.--31. 1. "FT3_8_P1,Filter3 P8:P5"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask0_pru1,"
hexmask.long 0xA0 0.--31. 1. "FT3_8_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_8_p_mask1_pru1,"
hexmask.long 0xA4 0.--31. 1. "FT3_8_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p0_pru1,"
hexmask.long 0xA8 0.--31. 1. "FT3_9_P0,Filter3 P4:P1"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p1_pru1,"
hexmask.long 0xAC 0.--31. 1. "FT3_9_P1,Filter3 P8:P5"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask0_pru1,"
hexmask.long 0xB0 0.--31. 1. "FT3_9_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_9_p_mask1_pru1,"
hexmask.long 0xB4 0.--31. 1. "FT3_9_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p0_pru1,"
hexmask.long 0xB8 0.--31. 1. "FT3_10_P0,Filter3 P4:P1"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p1_pru1,"
hexmask.long 0xBC 0.--31. 1. "FT3_10_P1,Filter3 P8:P5"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask0_pru1,"
hexmask.long 0xC0 0.--31. 1. "FT3_10_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_10_p_mask1_pru1,"
hexmask.long 0xC4 0.--31. 1. "FT3_10_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p0_pru1,"
hexmask.long 0xC8 0.--31. 1. "FT3_11_P0,Filter3 P4:P1"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p1_pru1,"
hexmask.long 0xCC 0.--31. 1. "FT3_11_P1,Filter3 P8:P5"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask0_pru1,"
hexmask.long 0xD0 0.--31. 1. "FT3_11_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_11_p_mask1_pru1,"
hexmask.long 0xD4 0.--31. 1. "FT3_11_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p0_pru1,"
hexmask.long 0xD8 0.--31. 1. "FT3_12_P0,Filter3 P4:P1"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p1_pru1,"
hexmask.long 0xDC 0.--31. 1. "FT3_12_P1,Filter3 P8:P5"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask0_pru1,"
hexmask.long 0xE0 0.--31. 1. "FT3_12_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_12_p_mask1_pru1,"
hexmask.long 0xE4 0.--31. 1. "FT3_12_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p0_pru1,"
hexmask.long 0xE8 0.--31. 1. "FT3_13_P0,Filter3 P4:P1"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p1_pru1,"
hexmask.long 0xEC 0.--31. 1. "FT3_13_P1,Filter3 P8:P5"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask0_pru1,"
hexmask.long 0xF0 0.--31. 1. "FT3_13_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_13_p_mask1_pru1,"
hexmask.long 0xF4 0.--31. 1. "FT3_13_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p0_pru1,"
hexmask.long 0xF8 0.--31. 1. "FT3_14_P0,Filter3 P4:P1"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p1_pru1,"
hexmask.long 0xFC 0.--31. 1. "FT3_14_P1,Filter3 P8:P5"
line.long 0x100 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask0_pru1,"
hexmask.long 0x100 0.--31. 1. "FT3_14_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x104 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_14_p_mask1_pru1,"
hexmask.long 0x104 0.--31. 1. "FT3_14_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x108 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p0_pru1,"
hexmask.long 0x108 0.--31. 1. "FT3_15_P0,Filter3 P4:P1"
line.long 0x10C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p1_pru1,"
hexmask.long 0x10C 0.--31. 1. "FT3_15_P1,Filter3 P8:P5"
line.long 0x110 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask0_pru1,"
hexmask.long 0x110 0.--31. 1. "FT3_15_P_MASK0,Filter3 MP4:MP1 set to 1 to mask that bit"
line.long 0x114 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft3_15_p_mask1_pru1,"
hexmask.long 0x114 0.--31. 1. "FT3_15_P_MASK1,Filter3 MP8:MP5 set to 1 to mask that bit"
line.long 0x118 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_ft_rx_ptr_pru1,"
hexmask.long 0x118 0.--31. 1. "FT_RX_PTR_PRU1,RX current filter Byte Count"
line.long 0x11C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_and_en_pru1,"
hexmask.long 0x11C 0.--31. 1. "RX_CLASS0_AND_EN,rx class and enabels"
line.long 0x120 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class0_or_en_pru1,"
hexmask.long 0x120 0.--31. 1. "RX_CLASS0_OR_EN,rx class or enabels"
line.long 0x124 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_and_en_pru1,"
hexmask.long 0x124 0.--31. 1. "RX_CLASS1_AND_EN,rx class and enabels"
line.long 0x128 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class1_or_en_pru1,"
hexmask.long 0x128 0.--31. 1. "RX_CLASS1_OR_EN,rx class or enabels"
line.long 0x12C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_and_en_pru1,"
hexmask.long 0x12C 0.--31. 1. "RX_CLASS2_AND_EN,rx class and enabels"
line.long 0x130 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class2_or_en_pru1,"
hexmask.long 0x130 0.--31. 1. "RX_CLASS2_OR_EN,rx class or enabels"
line.long 0x134 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_and_en_pru1,"
hexmask.long 0x134 0.--31. 1. "RX_CLASS3_AND_EN,rx class and enabels"
line.long 0x138 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class3_or_en_pru1,"
hexmask.long 0x138 0.--31. 1. "RX_CLASS3_OR_EN,rx class or enabels"
line.long 0x13C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_and_en_pru1,"
hexmask.long 0x13C 0.--31. 1. "RX_CLASS4_AND_EN,rx class and enabels"
line.long 0x140 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class4_or_en_pru1,"
hexmask.long 0x140 0.--31. 1. "RX_CLASS4_OR_EN,rx class or enabels"
line.long 0x144 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_and_en_pru1,"
hexmask.long 0x144 0.--31. 1. "RX_CLASS5_AND_EN,rx class and enabels"
line.long 0x148 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class5_or_en_pru1,"
hexmask.long 0x148 0.--31. 1. "RX_CLASS5_OR_EN,rx class or enabels"
line.long 0x14C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_and_en_pru1,"
hexmask.long 0x14C 0.--31. 1. "RX_CLASS6_AND_EN,rx class and enabels"
line.long 0x150 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class6_or_en_pru1,"
hexmask.long 0x150 0.--31. 1. "RX_CLASS6_OR_EN,rx class or enabels"
line.long 0x154 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_and_en_pru1,"
hexmask.long 0x154 0.--31. 1. "RX_CLASS7_AND_EN,rx class and enabels"
line.long 0x158 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class7_or_en_pru1,"
hexmask.long 0x158 0.--31. 1. "RX_CLASS7_OR_EN,rx class or enabels"
line.long 0x15C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_and_en_pru1,"
hexmask.long 0x15C 0.--31. 1. "RX_CLASS8_AND_EN,rx class and enabels"
line.long 0x160 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class8_or_en_pru1,"
hexmask.long 0x160 0.--31. 1. "RX_CLASS8_OR_EN,rx class or enabels"
line.long 0x164 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_and_en_pru1,"
hexmask.long 0x164 0.--31. 1. "RX_CLASS9_AND_EN,rx class and enabels"
line.long 0x168 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class9_or_en_pru1,"
hexmask.long 0x168 0.--31. 1. "RX_CLASS9_OR_EN,rx class or enabels"
line.long 0x16C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_and_en_pru1,"
hexmask.long 0x16C 0.--31. 1. "RX_CLASS10_AND_EN,rx class and enabels"
line.long 0x170 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class10_or_en_pru1,"
hexmask.long 0x170 0.--31. 1. "RX_CLASS10_OR_EN,rx class or enabels"
line.long 0x174 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_and_en_pru1,"
hexmask.long 0x174 0.--31. 1. "RX_CLASS11_AND_EN,rx class and enabels"
line.long 0x178 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class11_or_en_pru1,"
hexmask.long 0x178 0.--31. 1. "RX_CLASS11_OR_EN,rx class or enabels"
line.long 0x17C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_and_en_pru1,"
hexmask.long 0x17C 0.--31. 1. "RX_CLASS12_AND_EN,rx class and enabels"
line.long 0x180 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class12_or_en_pru1,"
hexmask.long 0x180 0.--31. 1. "RX_CLASS12_OR_EN,rx class or enabels"
line.long 0x184 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_and_en_pru1,"
hexmask.long 0x184 0.--31. 1. "RX_CLASS13_AND_EN,rx class and enabels"
line.long 0x188 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class13_or_en_pru1,"
hexmask.long 0x188 0.--31. 1. "RX_CLASS13_OR_EN,rx class or enabels"
line.long 0x18C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_and_en_pru1,"
hexmask.long 0x18C 0.--31. 1. "RX_CLASS14_AND_EN,rx class and enabels"
line.long 0x190 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class14_or_en_pru1,"
hexmask.long 0x190 0.--31. 1. "RX_CLASS14_OR_EN,rx class or enabels"
line.long 0x194 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_and_en_pru1,"
hexmask.long 0x194 0.--31. 1. "RX_CLASS15_AND_EN,rx class and enabels"
line.long 0x198 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class15_or_en_pru1,"
hexmask.long 0x198 0.--31. 1. "RX_CLASS15_OR_EN,rx class or enabels"
line.long 0x19C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg1_pru1,"
bitfld.long 0x19C 30.--31. "RX_CLASS15_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 28.--29. "RX_CLASS14_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 26.--27. "RX_CLASS13_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 24.--25. "RX_CLASS12_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 22.--23. "RX_CLASS11_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 20.--21. "RX_CLASS10_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 18.--19. "RX_CLASS9_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 16.--17. "RX_CLASS8_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 14.--15. "RX_CLASS7_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 12.--13. "RX_CLASS6_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 10.--11. "RX_CLASS5_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 8.--9. "RX_CLASS4_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 6.--7. "RX_CLASS3_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 4.--5. "RX_CLASS2_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
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bitfld.long 0x19C 2.--3. "RX_CLASS1_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
bitfld.long 0x19C 0.--1. "RX_CLASS0_SEL,rx class final term selection 00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0: OR,1: AND,?,?"
line.long 0x1A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_cfg2_pru1,"
hexmask.long.word 0x1A0 16.--31. 1. "RX_CLASS_OR_NV,rx class or nv enable"
hexmask.long.word 0x1A0 0.--15. 1. "RX_CLASS_AND_NV,rx class and nv enable"
line.long 0x1A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates0_pru1,"
bitfld.long 0x1A4 8. "RX_RED_PHASE_EN0,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A4 6. "RX_ALLOW_MASK0,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A4 5. "RX_CLASS_RAW_MASK0,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A4 4. "RX_PHASE_MASK0,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A4 0.--2. "RX_RATE_GATE_SEL0,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates1_pru1,"
bitfld.long 0x1A8 8. "RX_RED_PHASE_EN1,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1A8 6. "RX_ALLOW_MASK1,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A8 5. "RX_CLASS_RAW_MASK1,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1A8 4. "RX_PHASE_MASK1,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1A8 0.--2. "RX_RATE_GATE_SEL1,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates2_pru1,"
bitfld.long 0x1AC 8. "RX_RED_PHASE_EN2,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1AC 6. "RX_ALLOW_MASK2,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1AC 5. "RX_CLASS_RAW_MASK2,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1AC 4. "RX_PHASE_MASK2,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1AC 0.--2. "RX_RATE_GATE_SEL2,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates3_pru1,"
bitfld.long 0x1B0 8. "RX_RED_PHASE_EN3,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B0 6. "RX_ALLOW_MASK3,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B0 5. "RX_CLASS_RAW_MASK3,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B0 4. "RX_PHASE_MASK3,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B0 0.--2. "RX_RATE_GATE_SEL3,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates4_pru1,"
bitfld.long 0x1B4 8. "RX_RED_PHASE_EN4,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B4 6. "RX_ALLOW_MASK4,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B4 5. "RX_CLASS_RAW_MASK4,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B4 4. "RX_PHASE_MASK4,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B4 0.--2. "RX_RATE_GATE_SEL4,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates5_pru1,"
bitfld.long 0x1B8 8. "RX_RED_PHASE_EN5,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1B8 6. "RX_ALLOW_MASK5,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B8 5. "RX_CLASS_RAW_MASK5,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1B8 4. "RX_PHASE_MASK5,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1B8 0.--2. "RX_RATE_GATE_SEL5,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates6_pru1,"
bitfld.long 0x1BC 8. "RX_RED_PHASE_EN6,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1BC 6. "RX_ALLOW_MASK6,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1BC 5. "RX_CLASS_RAW_MASK6,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1BC 4. "RX_PHASE_MASK6,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1BC 0.--2. "RX_RATE_GATE_SEL6,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates7_pru1,"
bitfld.long 0x1C0 8. "RX_RED_PHASE_EN7,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C0 6. "RX_ALLOW_MASK7,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C0 5. "RX_CLASS_RAW_MASK7,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C0 4. "RX_PHASE_MASK7,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C0 0.--2. "RX_RATE_GATE_SEL7,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates8_pru1,"
bitfld.long 0x1C4 8. "RX_RED_PHASE_EN8,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C4 6. "RX_ALLOW_MASK8,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C4 5. "RX_CLASS_RAW_MASK8,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C4 4. "RX_PHASE_MASK8,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C4 0.--2. "RX_RATE_GATE_SEL8,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates9_pru1,"
bitfld.long 0x1C8 8. "RX_RED_PHASE_EN9,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1C8 6. "RX_ALLOW_MASK9,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1C8 5. "RX_CLASS_RAW_MASK9,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1C8 4. "RX_PHASE_MASK9,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1C8 0.--2. "RX_RATE_GATE_SEL9,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates10_pru1,"
bitfld.long 0x1CC 8. "RX_RED_PHASE_EN10,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1CC 6. "RX_ALLOW_MASK10,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1CC 5. "RX_CLASS_RAW_MASK10,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1CC 4. "RX_PHASE_MASK10,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1CC 0.--2. "RX_RATE_GATE_SEL10,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates11_pru1,"
bitfld.long 0x1D0 8. "RX_RED_PHASE_EN11,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D0 6. "RX_ALLOW_MASK11,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 5. "RX_CLASS_RAW_MASK11,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D0 4. "RX_PHASE_MASK11,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D0 0.--2. "RX_RATE_GATE_SEL11,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates12_pru1,"
bitfld.long 0x1D4 8. "RX_RED_PHASE_EN12,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D4 6. "RX_ALLOW_MASK12,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D4 5. "RX_CLASS_RAW_MASK12,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D4 4. "RX_PHASE_MASK12,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D4 0.--2. "RX_RATE_GATE_SEL12,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates13_pru1,"
bitfld.long 0x1D8 8. "RX_RED_PHASE_EN13,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1D8 6. "RX_ALLOW_MASK13,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
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bitfld.long 0x1D8 5. "RX_CLASS_RAW_MASK13,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1D8 4. "RX_PHASE_MASK13,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1D8 0.--2. "RX_RATE_GATE_SEL13,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates14_pru1,"
bitfld.long 0x1DC 8. "RX_RED_PHASE_EN14,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1DC 6. "RX_ALLOW_MASK14,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1DC 5. "RX_CLASS_RAW_MASK14,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1DC 4. "RX_PHASE_MASK14,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1DC 0.--2. "RX_RATE_GATE_SEL14,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_class_gates15_pru1,"
bitfld.long 0x1E0 8. "RX_RED_PHASE_EN15,red phase neable 0: disable 1: enable" "0: disable,1: enable"
bitfld.long 0x1E0 6. "RX_ALLOW_MASK15,allow mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 5. "RX_CLASS_RAW_MASK15,class raw mask 0: unmask 1: mask" "0: unmask,1: mask"
bitfld.long 0x1E0 4. "RX_PHASE_MASK15,time phase mask 0: unmask 1: mask" "0: unmask,1: mask"
newline
bitfld.long 0x1E0 0.--2. "RX_RATE_GATE_SEL15,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
line.long 0x1E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_green_pru1,"
rbitfld.long 0x1E4 4. "RX_GREEN_VAL,0 RED 1 GREEN status" "0,1"
hexmask.long.byte 0x1E4 0.--3. 1. "RX_GREEN_CMP_SEL,define which IEP CMP start green"
line.long 0x1E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_sa_hash_pru1,"
hexmask.long.word 0x1E8 0.--9. 1. "SA_HASH_SEED,SA Hash Seed"
line.long 0x1EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_pru1,"
hexmask.long.word 0x1EC 0.--9. 1. "CONN_HASH_SEED,Connection Hash Seed"
line.long 0x1F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_conn_hash_start_pru1,"
hexmask.long.word 0x1F0 0.--14. 1. "CONN_HASH_START,Connection Hash Start which 4 Bytes to hash"
line.long 0x1F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg0_pru1,"
hexmask.long 0x1F4 0.--31. 1. "RX_RATE_CIR_IDLE0,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg1_pru1,"
hexmask.long 0x1F8 0.--31. 1. "RX_RATE_CIR_IDLE1,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x1FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg2_pru1,"
hexmask.long 0x1FC 0.--31. 1. "RX_RATE_CIR_IDLE2,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x200 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg3_pru1,"
hexmask.long 0x200 0.--31. 1. "RX_RATE_CIR_IDLE3,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x204 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg4_pru1,"
hexmask.long 0x204 0.--31. 1. "RX_RATE_CIR_IDLE4,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x208 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg5_pru1,"
hexmask.long 0x208 0.--31. 1. "RX_RATE_CIR_IDLE5,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x20C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg6_pru1,"
hexmask.long 0x20C 0.--31. 1. "RX_RATE_CIR_IDLE6,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x210 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_cfg7_pru1,"
hexmask.long 0x210 0.--31. 1. "RX_RATE_CIR_IDLE7,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x214 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel0_pru1,"
hexmask.long.byte 0x214 24.--29. 1. "RX_RATE_SRC_SEL3,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 16.--21. 1. "RX_RATE_SRC_SEL2,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x214 8.--13. 1. "RX_RATE_SRC_SEL1,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x214 0.--5. 1. "RX_RATE_SRC_SEL0,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x218 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_rate_src_sel1_pru1,"
hexmask.long.byte 0x218 24.--29. 1. "RX_RATE_SRC_SEL7,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 16.--21. 1. "RX_RATE_SRC_SEL6,Map which filter/flag/class hit that rate logic uses  see table for mapping"
newline
hexmask.long.byte 0x218 8.--13. 1. "RX_RATE_SRC_SEL5,Map which filter/flag/class hit that rate logic uses  see table for mapping"
hexmask.long.byte 0x218 0.--5. 1. "RX_RATE_SRC_SEL4,Map which filter/flag/class hit that rate logic uses  see table for mapping"
line.long 0x21C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_0_pru1,"
hexmask.long 0x21C 0.--31. 1. "TX_RATE_CIR_IDLE0,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x220 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_0_pru1,"
rbitfld.long 0x220 17. "TX_RATE_ALLOW0,TX Rate Pkt Enable" "0,1"
bitfld.long 0x220 16. "TX_RATE_EN0,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x220 0.--15. 1. "TX_RATE_LEN0,TX Rate Pkt Length"
line.long 0x224 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_1_pru1,"
hexmask.long 0x224 0.--31. 1. "TX_RATE_CIR_IDLE1,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x228 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_1_pru1,"
rbitfld.long 0x228 17. "TX_RATE_ALLOW1,TX Rate Pkt Enable" "0,1"
bitfld.long 0x228 16. "TX_RATE_EN1,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x228 0.--15. 1. "TX_RATE_LEN1,TX Rate Pkt Length"
line.long 0x22C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_2_pru1,"
hexmask.long 0x22C 0.--31. 1. "TX_RATE_CIR_IDLE2,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x230 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_2_pru1,"
rbitfld.long 0x230 17. "TX_RATE_ALLOW2,TX Rate Pkt Enable" "0,1"
bitfld.long 0x230 16. "TX_RATE_EN2,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x230 0.--15. 1. "TX_RATE_LEN2,TX Rate Pkt Length"
line.long 0x234 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_3_pru1,"
hexmask.long 0x234 0.--31. 1. "TX_RATE_CIR_IDLE3,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x238 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_3_pru1,"
rbitfld.long 0x238 17. "TX_RATE_ALLOW3,TX Rate Pkt Enable" "0,1"
bitfld.long 0x238 16. "TX_RATE_EN3,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x238 0.--15. 1. "TX_RATE_LEN3,TX Rate Pkt Length"
line.long 0x23C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_4_pru1,"
hexmask.long 0x23C 0.--31. 1. "TX_RATE_CIR_IDLE4,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x240 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_4_pru1,"
rbitfld.long 0x240 17. "TX_RATE_ALLOW4,TX Rate Pkt Enable" "0,1"
bitfld.long 0x240 16. "TX_RATE_EN4,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x240 0.--15. 1. "TX_RATE_LEN4,TX Rate Pkt Length"
line.long 0x244 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_5_pru1,"
hexmask.long 0x244 0.--31. 1. "TX_RATE_CIR_IDLE5,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x248 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_5_pru1,"
rbitfld.long 0x248 17. "TX_RATE_ALLOW5,TX Rate Pkt Enable" "0,1"
bitfld.long 0x248 16. "TX_RATE_EN5,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x248 0.--15. 1. "TX_RATE_LEN5,TX Rate Pkt Length"
line.long 0x24C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_6_pru1,"
hexmask.long 0x24C 0.--31. 1. "TX_RATE_CIR_IDLE6,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x250 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_6_pru1,"
rbitfld.long 0x250 17. "TX_RATE_ALLOW6,TX Rate Pkt Enable" "0,1"
bitfld.long 0x250 16. "TX_RATE_EN6,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x250 0.--15. 1. "TX_RATE_LEN6,TX Rate Pkt Length"
line.long 0x254 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg1_7_pru1,"
hexmask.long 0x254 0.--31. 1. "TX_RATE_CIR_IDLE7,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED"
line.long 0x258 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_rate_cfg2_7_pru1,"
rbitfld.long 0x258 17. "TX_RATE_ALLOW7,TX Rate Pkt Enable" "0,1"
bitfld.long 0x258 16. "TX_RATE_EN7,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x258 0.--15. 1. "TX_RATE_LEN7,TX Rate Pkt Length"
line.long 0x25C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_good_pru1,"
hexmask.long 0x25C 0.--31. 1. "RX_GOOD_FRM_CNT,RX Good Frame Count Inc on none min err max err crc err odd err  Wrt subtracts"
line.long 0x260 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bc_pru1,"
hexmask.long.word 0x260 0.--15. 1. "RX_BC_FRM_CNT,RX BC Frame Count Inc on BC type  Wrt subtracts"
line.long 0x264 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mc_pru1,"
hexmask.long.word 0x264 0.--15. 1. "RX_MC_FRM_CNT,RX MC Frame Count Inc on MC type  Wrt subtracts"
line.long 0x268 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_crc_err_pru1,"
hexmask.long.word 0x268 0.--15. 1. "RX_CRC_ERR_FRM_CNT,RX CRC Err Frame Count Inc on crc err  Wrt subtracts"
line.long 0x26C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_mii_err_pru1,"
hexmask.long.word 0x26C 0.--15. 1. "RX_MII_ERR_FRM_CNT,RX MII Err Frame Count Inc on mii sgmii rgmii err  Wrt subtracts"
line.long 0x270 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_odd_err_pru1,"
hexmask.long.word 0x270 0.--15. 1. "RX_ODD_ERR_FRM_CNT,RX Odd Nibble Frame Count Inc on odd nibble mii  Wrt subtracts"
line.long 0x274 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_size_pru1,"
hexmask.long.word 0x274 0.--15. 1. "RX_MAX_SIZE_FRM,RX MAX Size Frame Count Limit"
line.long 0x278 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_max_err_pru1,"
hexmask.long.word 0x278 0.--15. 1. "RX_MAX_ERR_FRM_CNT,RX MAX Size Err Frame Count Inc if > than Limit  Wrt subtracts"
line.long 0x27C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_size_pru1,"
hexmask.long.word 0x27C 0.--15. 1. "RX_MIN_SIZE_FRM,RX MIN Size Frame Limit"
line.long 0x280 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_min_err_pru1,"
hexmask.long.word 0x280 0.--15. 1. "RX_MIN_ERR_FRM_CNT,RX MIN Size Frame Count Inc if < than limit  Wrt subtracts"
line.long 0x284 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_overrun_err_pru1,"
hexmask.long.word 0x284 0.--15. 1. "RX_OVERRUN_ERR_FRM_CNT,RX L1 FIFO overflow Frame Count Inc on overflow event  Wrt subtracts"
line.long 0x288 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class0_hit_pru1,"
hexmask.long 0x288 0.--31. 1. "RX_STAT_CLASS0_PRU1,RX Class0 Hit Count  Wrt subtracts"
line.long 0x28C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class1_hit_pru1,"
hexmask.long 0x28C 0.--31. 1. "RX_STAT_CLASS1_PRU1,RX Class1 Hit Count  Wrt subtracts"
line.long 0x290 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class2_hit_pru1,"
hexmask.long 0x290 0.--31. 1. "RX_STAT_CLASS2_PRU1,RX Class2 Hit Count  Wrt subtracts"
line.long 0x294 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class3_hit_pru1,"
hexmask.long 0x294 0.--31. 1. "RX_STAT_CLASS3_PRU1,RX Class3 Hit Count  Wrt subtracts"
line.long 0x298 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class4_hit_pru1,"
hexmask.long 0x298 0.--31. 1. "RX_STAT_CLASS4_PRU1,RX Class4 Hit Count  Wrt subtracts"
line.long 0x29C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class5_hit_pru1,"
hexmask.long 0x29C 0.--31. 1. "RX_STAT_CLASS5_PRU1,RX Class5 Hit Count  Wrt subtracts"
line.long 0x2A0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class6_hit_pru1,"
hexmask.long 0x2A0 0.--31. 1. "RX_STAT_CLASS6_PRU1,RX Class6 Hit Count  Wrt subtracts"
line.long 0x2A4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class7_hit_pru1,"
hexmask.long 0x2A4 0.--31. 1. "RX_STAT_CLASS7_PRU1,RX Class7 Hit Count  Wrt subtracts"
line.long 0x2A8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class8_hit_pru1,"
hexmask.long 0x2A8 0.--31. 1. "RX_STAT_CLASS8_PRU1,RX Class8 Hit Count  Wrt subtracts"
line.long 0x2AC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class9_hit_pru1,"
hexmask.long 0x2AC 0.--31. 1. "RX_STAT_CLASS9_PRU1,RX Class9 Hit Count  Wrt subtracts"
line.long 0x2B0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class10_hit_pru1,"
hexmask.long 0x2B0 0.--31. 1. "RX_STAT_CLASS10_PRU1,RX Class10 Hit Count  Wrt subtracts"
line.long 0x2B4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class11_hit_pru1,"
hexmask.long 0x2B4 0.--31. 1. "RX_STAT_CLASS11_PRU1,RX Class11 Hit Count  Wrt subtracts"
line.long 0x2B8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class12_hit_pru1,"
hexmask.long 0x2B8 0.--31. 1. "RX_STAT_CLASS12_PRU1,RX Class12 Hit Count  Wrt subtracts"
line.long 0x2BC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class13_hit_pru1,"
hexmask.long 0x2BC 0.--31. 1. "RX_STAT_CLASS13_PRU1,RX Class13 Hit Count  Wrt subtracts"
line.long 0x2C0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class14_hit_pru1,"
hexmask.long 0x2C0 0.--31. 1. "RX_STAT_CLASS14_PRU1,RX Class14 Hit Count  Wrt subtracts"
line.long 0x2C4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_class15_hit_pru1,"
hexmask.long 0x2C4 0.--31. 1. "RX_STAT_CLASS15_PRU1,RX Class15 Hit Count  Wrt subtracts"
line.long 0x2C8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_smd_frag_err_pru1,"
hexmask.long.byte 0x2C8 24.--31. 1. "RX_STAT_SMD_ERR_PRU1,RX SMDS Error Count  Inc when first none 0x55 does not match any valid SMD  Wrt subtracts"
hexmask.long.byte 0x2C8 16.--23. 1. "RX_STAT_FRAG_ERR_PRU1,RX Frag_Cnt Seq Error Count  Wrt subtracts"
newline
hexmask.long.byte 0x2C8 8.--15. 1. "RX_STAT_SMDC_ERR_PRU1,RX SMDCx Seq Error Count  Wrt subtracts"
hexmask.long.byte 0x2C8 0.--7. 1. "RX_STAT_SMDS_ERR_PRU1,RX SMDSx Seq Error Count  Wrt subtracts"
line.long 0x2CC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_size_pru1,"
hexmask.long.word 0x2CC 0.--13. 1. "RX_STAT_BKT1_SIZE,RX Bucket1 Byte Size"
line.long 0x2D0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_size_pru1,"
hexmask.long.word 0x2D0 0.--13. 1. "RX_STAT_BKT2_SIZE,RX Bucket2 Byte Size"
line.long 0x2D4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_size_pru1,"
hexmask.long.word 0x2D4 0.--13. 1. "RX_STAT_BKT3_SIZE,RX Bucket3 Byte Size"
line.long 0x2D8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_size_pru1,"
hexmask.long.word 0x2D8 0.--13. 1. "RX_STAT_BKT4_SIZE,RX Bucket4 Byte Size"
line.long 0x2DC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_64_pru1,"
hexmask.long.word 0x2DC 0.--15. 1. "RX_64_FRM_CNT,RX 64Byte Frame Count Inc if 64B size"
line.long 0x2E0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt1_pru1,"
hexmask.long.word 0x2E0 0.--15. 1. "RX_STAT_BKT1,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
line.long 0x2E4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt2_pru1,"
hexmask.long.word 0x2E4 0.--15. 1. "RX_STAT_BKT2,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x2E8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt3_pru1,"
hexmask.long.word 0x2E8 0.--15. 1. "RX_STAT_BKT3,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x2EC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt4_pru1,"
hexmask.long.word 0x2EC 0.--15. 1. "RX_STAT_BKT4,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x2F0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_bkt5_pru1,"
hexmask.long.word 0x2F0 0.--15. 1. "RX_STAT_BKT5,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
line.long 0x2F4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rx_stat_total_bytes_pru1,"
hexmask.long 0x2F4 0.--31. 1. "RX_STAT_TOTAL_BYTES_PRU,RX Total Byte Count"
line.long 0x2F8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_rxtx_stat_total_bytes_pru1,"
hexmask.long 0x2F8 0.--31. 1. "RXTX_STAT_TOTAL_BYTES_PRU,RX and TX Total Byte Count"
line.long 0x2FC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_good_port1,"
hexmask.long 0x2FC 0.--31. 1. "TX_GOOD_FRM_CNT,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
line.long 0x300 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bc_port1,"
hexmask.long.word 0x300 0.--15. 1. "TX_BC_FRM_CNT,TX BC Frame Count Inc if BC"
line.long 0x304 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_mc_port1,"
hexmask.long.word 0x304 0.--15. 1. "TX_MC_FRM_CNT,TX MC Frame Count Inc if MC"
line.long 0x308 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_odd_err_port1,"
hexmask.long.word 0x308 0.--15. 1. "TX_ODD_ERR_FRM_CNT,TX Odd Nibble Frame Count Inc if mii odd nibble"
line.long 0x30C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_underflow_err_port1,"
hexmask.long.word 0x30C 0.--15. 1. "TX_UNDERFLOW_CNT,TX MAX Underflow Error Cnt"
line.long 0x310 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_size_port1,"
hexmask.long.word 0x310 0.--15. 1. "TX_MAX_SIZE_FRM,TX MAX Size Frame Count Limit"
line.long 0x314 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_max_err_port1,"
hexmask.long.word 0x314 0.--15. 1. "TX_MAX_ERR_FRM_CNT,TX MAX Size Err Frame Count Inc if > max Limit"
line.long 0x318 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_size_port1,"
hexmask.long.word 0x318 0.--15. 1. "TX_MIN_SIZE_FRM,TX MIN Size Frame Count Limit"
line.long 0x31C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_min_err_port1,"
hexmask.long.word 0x31C 0.--15. 1. "TX_MIN_ERR_FRM_CNT,TX MIN Size Err Frame Count Inc if < min Limit"
line.long 0x320 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_size_port1,"
hexmask.long.word 0x320 0.--13. 1. "TX_STAT_BKT1_SIZE,TX Bucket1 Byte Size"
line.long 0x324 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_size_port1,"
hexmask.long.word 0x324 0.--13. 1. "TX_STAT_BKT2_SIZE,TX Bucket2 Byte Size"
line.long 0x328 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_size_port1,"
hexmask.long.word 0x328 0.--13. 1. "TX_STAT_BKT3_SIZE,TX Bucket3 Byte Size"
line.long 0x32C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_size_port1,"
hexmask.long.word 0x32C 0.--13. 1. "TX_STAT_BKT4_SIZE,TX Bucket4 Byte Size"
line.long 0x330 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_64_port1,"
hexmask.long.word 0x330 0.--15. 1. "TX_64_FRM_CNT,TX 64Byte Frame Count Inc if 64B"
line.long 0x334 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt1_port1,"
hexmask.long.word 0x334 0.--15. 1. "TX_STAT_BKT1,TX Bucket1 Inc if <= than Bucket1"
line.long 0x338 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt2_port1,"
hexmask.long.word 0x338 0.--15. 1. "TX_STAT_BKT2,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x33C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt3_port1,"
hexmask.long.word 0x33C 0.--15. 1. "TX_STAT_BKT3,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x340 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt4_port1,"
hexmask.long.word 0x340 0.--15. 1. "TX_STAT_BKT4,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x344 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_bkt5_port1,"
hexmask.long.word 0x344 0.--15. 1. "TX_STAT_BKT5,TX Bucket5 Inc if > than Bucket4 Byte Size"
line.long 0x348 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_stat_total_bytes_port1,"
hexmask.long 0x348 0.--31. 1. "TX_TOTAL_STAT_BYTES_PORT,TX Total Byte Count of all Frames"
line.long 0x34C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_tag_port1,"
hexmask.long 0x34C 0.--31. 1. "TX_HSR_TAG,HSR TAG"
line.long 0x350 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_hsr_seq_port1,"
hexmask.long.word 0x350 0.--15. 1. "TX_HSR_SEQ,HSR Seq count. It will incr for every HSR type"
line.long 0x354 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_type_tag_port1,"
hexmask.long.word 0x354 0.--15. 1. "TX_VLAN_TYPE_TAG,TX VLAN Type Tag  match to enable VLAN removal"
line.long 0x358 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_vlan_ins_tag_port1,"
hexmask.long 0x358 0.--31. 1. "TX_VLAN_INS_TAG,TX VLAN Insertion"
group.long 0xD00++0xFF
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue0,"
hexmask.long.word 0x0 0.--15. 1. "QUEUE_H_PTR0,Queue 0"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue1,"
hexmask.long.word 0x4 0.--15. 1. "QUEUE_H_PTR1,Queue 1"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue2,"
hexmask.long.word 0x8 0.--15. 1. "QUEUE_H_PTR2,Queue 2"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue3,"
hexmask.long.word 0xC 0.--15. 1. "QUEUE_H_PTR3,Queue 3"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue4,"
hexmask.long.word 0x10 0.--15. 1. "QUEUE_H_PTR4,Queue 4"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue5,"
hexmask.long.word 0x14 0.--15. 1. "QUEUE_H_PTR5,Queue 5"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue6,"
hexmask.long.word 0x18 0.--15. 1. "QUEUE_H_PTR6,Queue 6"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue7,"
hexmask.long.word 0x1C 0.--15. 1. "QUEUE_H_PTR7,Queue 7"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue8,"
hexmask.long.word 0x20 0.--15. 1. "QUEUE_H_PTR8,Queue 8"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue9,"
hexmask.long.word 0x24 0.--15. 1. "QUEUE_H_PTR9,Queue 9"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue10,"
hexmask.long.word 0x28 0.--15. 1. "QUEUE_H_PTR10,Queue 10"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue11,"
hexmask.long.word 0x2C 0.--15. 1. "QUEUE_H_PTR11,Queue 11"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue12,"
hexmask.long.word 0x30 0.--15. 1. "QUEUE_H_PTR12,Queue 12"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue13,"
hexmask.long.word 0x34 0.--15. 1. "QUEUE_H_PTR13,Queue 13"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue14,"
hexmask.long.word 0x38 0.--15. 1. "QUEUE_H_PTR14,Queue 14"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue15,"
hexmask.long.word 0x3C 0.--15. 1. "QUEUE_H_PTR15,Queue 15"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue16,"
hexmask.long.word 0x40 0.--15. 1. "QUEUE_H_PTR16,Queue 16"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue17,"
hexmask.long.word 0x44 0.--15. 1. "QUEUE_H_PTR17,Queue 17"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue18,"
hexmask.long.word 0x48 0.--15. 1. "QUEUE_H_PTR18,Queue 18"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue19,"
hexmask.long.word 0x4C 0.--15. 1. "QUEUE_H_PTR19,Queue 19"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue20,"
hexmask.long.word 0x50 0.--15. 1. "QUEUE_H_PTR20,Queue 20"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue21,"
hexmask.long.word 0x54 0.--15. 1. "QUEUE_H_PTR21,Queue 21"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue22,"
hexmask.long.word 0x58 0.--15. 1. "QUEUE_H_PTR22,Queue 22"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue23,"
hexmask.long.word 0x5C 0.--15. 1. "QUEUE_H_PTR23,Queue 23"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue24,"
hexmask.long.word 0x60 0.--15. 1. "QUEUE_H_PTR24,Queue 24"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue25,"
hexmask.long.word 0x64 0.--15. 1. "QUEUE_H_PTR25,Queue 25"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue26,"
hexmask.long.word 0x68 0.--15. 1. "QUEUE_H_PTR26,Queue 26"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue27,"
hexmask.long.word 0x6C 0.--15. 1. "QUEUE_H_PTR27,Queue 27"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue28,"
hexmask.long.word 0x70 0.--15. 1. "QUEUE_H_PTR28,Queue 28"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue29,"
hexmask.long.word 0x74 0.--15. 1. "QUEUE_H_PTR29,Queue 29"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue30,"
hexmask.long.word 0x78 0.--15. 1. "QUEUE_H_PTR30,Queue 30"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue31,"
hexmask.long.word 0x7C 0.--15. 1. "QUEUE_H_PTR31,Queue 31"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue32,"
hexmask.long.word 0x80 0.--15. 1. "QUEUE_H_PTR32,Queue 32"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue33,"
hexmask.long.word 0x84 0.--15. 1. "QUEUE_H_PTR33,Queue 33"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue34,"
hexmask.long.word 0x88 0.--15. 1. "QUEUE_H_PTR34,Queue 34"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue35,"
hexmask.long.word 0x8C 0.--15. 1. "QUEUE_H_PTR35,Queue 35"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue36,"
hexmask.long.word 0x90 0.--15. 1. "QUEUE_H_PTR36,Queue 36"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue37,"
hexmask.long.word 0x94 0.--15. 1. "QUEUE_H_PTR37,Queue 37"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue38,"
hexmask.long.word 0x98 0.--15. 1. "QUEUE_H_PTR38,Queue 38"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue39,"
hexmask.long.word 0x9C 0.--15. 1. "QUEUE_H_PTR39,Queue 39"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue40,"
hexmask.long.word 0xA0 0.--15. 1. "QUEUE_H_PTR40,Queue 40"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue41,"
hexmask.long.word 0xA4 0.--15. 1. "QUEUE_H_PTR41,Queue 41"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue42,"
hexmask.long.word 0xA8 0.--15. 1. "QUEUE_H_PTR42,Queue 42"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue43,"
hexmask.long.word 0xAC 0.--15. 1. "QUEUE_H_PTR43,Queue 43"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue44,"
hexmask.long.word 0xB0 0.--15. 1. "QUEUE_H_PTR44,Queue 44"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue45,"
hexmask.long.word 0xB4 0.--15. 1. "QUEUE_H_PTR45,Queue 45"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue46,"
hexmask.long.word 0xB8 0.--15. 1. "QUEUE_H_PTR46,Queue 46"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue47,"
hexmask.long.word 0xBC 0.--15. 1. "QUEUE_H_PTR47,Queue 47"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue48,"
hexmask.long.word 0xC0 0.--15. 1. "QUEUE_H_PTR48,Queue 48"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue49,"
hexmask.long.word 0xC4 0.--15. 1. "QUEUE_H_PTR49,Queue 49"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue50,"
hexmask.long.word 0xC8 0.--15. 1. "QUEUE_H_PTR50,Queue 50"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue51,"
hexmask.long.word 0xCC 0.--15. 1. "QUEUE_H_PTR51,Queue 51"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue52,"
hexmask.long.word 0xD0 0.--15. 1. "QUEUE_H_PTR52,Queue 52"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue53,"
hexmask.long.word 0xD4 0.--15. 1. "QUEUE_H_PTR53,Queue 53"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue54,"
hexmask.long.word 0xD8 0.--15. 1. "QUEUE_H_PTR54,Queue 54"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue55,"
hexmask.long.word 0xDC 0.--15. 1. "QUEUE_H_PTR55,Queue 55"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue56,"
hexmask.long.word 0xE0 0.--15. 1. "QUEUE_H_PTR56,Queue 56"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue57,"
hexmask.long.word 0xE4 0.--15. 1. "QUEUE_H_PTR57,Queue 57"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue58,"
hexmask.long.word 0xE8 0.--15. 1. "QUEUE_H_PTR58,Queue 58"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue59,"
hexmask.long.word 0xEC 0.--15. 1. "QUEUE_H_PTR59,Queue 59"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue60,"
hexmask.long.word 0xF0 0.--15. 1. "QUEUE_H_PTR60,Queue 60"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue61,"
hexmask.long.word 0xF4 0.--15. 1. "QUEUE_H_PTR61,Queue 61"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue62,"
hexmask.long.word 0xF8 0.--15. 1. "QUEUE_H_PTR62,Queue 62"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue63,"
hexmask.long.word 0xFC 0.--15. 1. "QUEUE_H_PTR63,Queue 63"
rgroup.long 0xE00++0x13F
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek0,"
hexmask.long.word 0x0 0.--15. 1. "QUEUE_H_PEEK_PTR0,Queue 0 Peek portal"
line.long 0x4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek1,"
hexmask.long.word 0x4 0.--15. 1. "QUEUE_H_PEEK_PTR1,Queue 1 Peek portal"
line.long 0x8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek2,"
hexmask.long.word 0x8 0.--15. 1. "QUEUE_H_PEEK_PTR2,Queue 2 Peek portal"
line.long 0xC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek3,"
hexmask.long.word 0xC 0.--15. 1. "QUEUE_H_PEEK_PTR3,Queue 3 Peek portal"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek4,"
hexmask.long.word 0x10 0.--15. 1. "QUEUE_H_PEEK_PTR4,Queue 4 Peek portal"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek5,"
hexmask.long.word 0x14 0.--15. 1. "QUEUE_H_PEEK_PTR5,Queue 5 Peek portal"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek6,"
hexmask.long.word 0x18 0.--15. 1. "QUEUE_H_PEEK_PTR6,Queue 6 Peek portal"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek7,"
hexmask.long.word 0x1C 0.--15. 1. "QUEUE_H_PEEK_PTR7,Queue 7 Peek portal"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek8,"
hexmask.long.word 0x20 0.--15. 1. "QUEUE_H_PEEK_PTR8,Queue 8 Peek portal"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek9,"
hexmask.long.word 0x24 0.--15. 1. "QUEUE_H_PEEK_PTR9,Queue 9 Peek portal"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek10,"
hexmask.long.word 0x28 0.--15. 1. "QUEUE_H_PEEK_PTR10,Queue 10 Peek portal"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek11,"
hexmask.long.word 0x2C 0.--15. 1. "QUEUE_H_PEEK_PTR11,Queue 11 Peek portal"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek12,"
hexmask.long.word 0x30 0.--15. 1. "QUEUE_H_PEEK_PTR12,Queue 12 Peek portal"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek13,"
hexmask.long.word 0x34 0.--15. 1. "QUEUE_H_PEEK_PTR13,Queue 13 Peek portal"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek14,"
hexmask.long.word 0x38 0.--15. 1. "QUEUE_H_PEEK_PTR14,Queue 14 Peek portal"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek15,"
hexmask.long.word 0x3C 0.--15. 1. "QUEUE_H_PEEK_PTR15,Queue 15 Peek portal"
line.long 0x40 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt0,"
hexmask.long.word 0x40 0.--15. 1. "QUEUE_CNT_ENTRIES_0,Queue Entry Count0"
line.long 0x44 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt1,"
hexmask.long.word 0x44 0.--15. 1. "QUEUE_CNT_ENTRIES_1,Queue Entry Count1"
line.long 0x48 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt2,"
hexmask.long.word 0x48 0.--15. 1. "QUEUE_CNT_ENTRIES_2,Queue Entry Count2"
line.long 0x4C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt3,"
hexmask.long.word 0x4C 0.--15. 1. "QUEUE_CNT_ENTRIES_3,Queue Entry Count3"
line.long 0x50 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt4,"
hexmask.long.word 0x50 0.--15. 1. "QUEUE_CNT_ENTRIES_4,Queue Entry Count4"
line.long 0x54 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt5,"
hexmask.long.word 0x54 0.--15. 1. "QUEUE_CNT_ENTRIES_5,Queue Entry Count5"
line.long 0x58 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt6,"
hexmask.long.word 0x58 0.--15. 1. "QUEUE_CNT_ENTRIES_6,Queue Entry Count6"
line.long 0x5C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt7,"
hexmask.long.word 0x5C 0.--15. 1. "QUEUE_CNT_ENTRIES_7,Queue Entry Count7"
line.long 0x60 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt8,"
hexmask.long.word 0x60 0.--15. 1. "QUEUE_CNT_ENTRIES_8,Queue Entry Count8"
line.long 0x64 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt9,"
hexmask.long.word 0x64 0.--15. 1. "QUEUE_CNT_ENTRIES_9,Queue Entry Count9"
line.long 0x68 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt10,"
hexmask.long.word 0x68 0.--15. 1. "QUEUE_CNT_ENTRIES_10,Queue Entry Count10"
line.long 0x6C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt11,"
hexmask.long.word 0x6C 0.--15. 1. "QUEUE_CNT_ENTRIES_11,Queue Entry Count11"
line.long 0x70 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt12,"
hexmask.long.word 0x70 0.--15. 1. "QUEUE_CNT_ENTRIES_12,Queue Entry Count12"
line.long 0x74 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt13,"
hexmask.long.word 0x74 0.--15. 1. "QUEUE_CNT_ENTRIES_13,Queue Entry Count13"
line.long 0x78 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt14,"
hexmask.long.word 0x78 0.--15. 1. "QUEUE_CNT_ENTRIES_14,Queue Entry Count14"
line.long 0x7C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt15,"
hexmask.long.word 0x7C 0.--15. 1. "QUEUE_CNT_ENTRIES_15,Queue Entry Count15"
line.long 0x80 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt16,"
hexmask.long.word 0x80 0.--15. 1. "QUEUE_CNT_ENTRIES_16,Queue Entry Count16"
line.long 0x84 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt17,"
hexmask.long.word 0x84 0.--15. 1. "QUEUE_CNT_ENTRIES_17,Queue Entry Count17"
line.long 0x88 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt18,"
hexmask.long.word 0x88 0.--15. 1. "QUEUE_CNT_ENTRIES_18,Queue Entry Count18"
line.long 0x8C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt19,"
hexmask.long.word 0x8C 0.--15. 1. "QUEUE_CNT_ENTRIES_19,Queue Entry Count19"
line.long 0x90 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt20,"
hexmask.long.word 0x90 0.--15. 1. "QUEUE_CNT_ENTRIES_20,Queue Entry Count20"
line.long 0x94 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt21,"
hexmask.long.word 0x94 0.--15. 1. "QUEUE_CNT_ENTRIES_21,Queue Entry Count21"
line.long 0x98 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt22,"
hexmask.long.word 0x98 0.--15. 1. "QUEUE_CNT_ENTRIES_22,Queue Entry Count22"
line.long 0x9C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt23,"
hexmask.long.word 0x9C 0.--15. 1. "QUEUE_CNT_ENTRIES_23,Queue Entry Count23"
line.long 0xA0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt24,"
hexmask.long.word 0xA0 0.--15. 1. "QUEUE_CNT_ENTRIES_24,Queue Entry Count24"
line.long 0xA4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt25,"
hexmask.long.word 0xA4 0.--15. 1. "QUEUE_CNT_ENTRIES_25,Queue Entry Count25"
line.long 0xA8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt26,"
hexmask.long.word 0xA8 0.--15. 1. "QUEUE_CNT_ENTRIES_26,Queue Entry Count26"
line.long 0xAC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt27,"
hexmask.long.word 0xAC 0.--15. 1. "QUEUE_CNT_ENTRIES_27,Queue Entry Count27"
line.long 0xB0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt28,"
hexmask.long.word 0xB0 0.--15. 1. "QUEUE_CNT_ENTRIES_28,Queue Entry Count28"
line.long 0xB4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt29,"
hexmask.long.word 0xB4 0.--15. 1. "QUEUE_CNT_ENTRIES_29,Queue Entry Count29"
line.long 0xB8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt30,"
hexmask.long.word 0xB8 0.--15. 1. "QUEUE_CNT_ENTRIES_30,Queue Entry Count30"
line.long 0xBC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt31,"
hexmask.long.word 0xBC 0.--15. 1. "QUEUE_CNT_ENTRIES_31,Queue Entry Count31"
line.long 0xC0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt32,"
hexmask.long.word 0xC0 0.--15. 1. "QUEUE_CNT_ENTRIES_32,Queue Entry Count32"
line.long 0xC4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt33,"
hexmask.long.word 0xC4 0.--15. 1. "QUEUE_CNT_ENTRIES_33,Queue Entry Count33"
line.long 0xC8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt34,"
hexmask.long.word 0xC8 0.--15. 1. "QUEUE_CNT_ENTRIES_34,Queue Entry Count34"
line.long 0xCC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt35,"
hexmask.long.word 0xCC 0.--15. 1. "QUEUE_CNT_ENTRIES_35,Queue Entry Count35"
line.long 0xD0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt36,"
hexmask.long.word 0xD0 0.--15. 1. "QUEUE_CNT_ENTRIES_36,Queue Entry Count36"
line.long 0xD4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt37,"
hexmask.long.word 0xD4 0.--15. 1. "QUEUE_CNT_ENTRIES_37,Queue Entry Count37"
line.long 0xD8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt38,"
hexmask.long.word 0xD8 0.--15. 1. "QUEUE_CNT_ENTRIES_38,Queue Entry Count38"
line.long 0xDC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt39,"
hexmask.long.word 0xDC 0.--15. 1. "QUEUE_CNT_ENTRIES_39,Queue Entry Count39"
line.long 0xE0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt40,"
hexmask.long.word 0xE0 0.--15. 1. "QUEUE_CNT_ENTRIES_40,Queue Entry Count40"
line.long 0xE4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt41,"
hexmask.long.word 0xE4 0.--15. 1. "QUEUE_CNT_ENTRIES_41,Queue Entry Count41"
line.long 0xE8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt42,"
hexmask.long.word 0xE8 0.--15. 1. "QUEUE_CNT_ENTRIES_42,Queue Entry Count42"
line.long 0xEC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt43,"
hexmask.long.word 0xEC 0.--15. 1. "QUEUE_CNT_ENTRIES_43,Queue Entry Count43"
line.long 0xF0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt44,"
hexmask.long.word 0xF0 0.--15. 1. "QUEUE_CNT_ENTRIES_44,Queue Entry Count44"
line.long 0xF4 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt45,"
hexmask.long.word 0xF4 0.--15. 1. "QUEUE_CNT_ENTRIES_45,Queue Entry Count45"
line.long 0xF8 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt46,"
hexmask.long.word 0xF8 0.--15. 1. "QUEUE_CNT_ENTRIES_46,Queue Entry Count46"
line.long 0xFC "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt47,"
hexmask.long.word 0xFC 0.--15. 1. "QUEUE_CNT_ENTRIES_47,Queue Entry Count47"
line.long 0x100 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt48,"
hexmask.long.word 0x100 0.--15. 1. "QUEUE_CNT_ENTRIES_48,Queue Entry Count48"
line.long 0x104 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt49,"
hexmask.long.word 0x104 0.--15. 1. "QUEUE_CNT_ENTRIES_49,Queue Entry Count49"
line.long 0x108 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt50,"
hexmask.long.word 0x108 0.--15. 1. "QUEUE_CNT_ENTRIES_50,Queue Entry Count50"
line.long 0x10C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt51,"
hexmask.long.word 0x10C 0.--15. 1. "QUEUE_CNT_ENTRIES_51,Queue Entry Count51"
line.long 0x110 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt52,"
hexmask.long.word 0x110 0.--15. 1. "QUEUE_CNT_ENTRIES_52,Queue Entry Count52"
line.long 0x114 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt53,"
hexmask.long.word 0x114 0.--15. 1. "QUEUE_CNT_ENTRIES_53,Queue Entry Count53"
line.long 0x118 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt54,"
hexmask.long.word 0x118 0.--15. 1. "QUEUE_CNT_ENTRIES_54,Queue Entry Count54"
line.long 0x11C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt55,"
hexmask.long.word 0x11C 0.--15. 1. "QUEUE_CNT_ENTRIES_55,Queue Entry Count55"
line.long 0x120 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt56,"
hexmask.long.word 0x120 0.--15. 1. "QUEUE_CNT_ENTRIES_56,Queue Entry Count56"
line.long 0x124 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt57,"
hexmask.long.word 0x124 0.--15. 1. "QUEUE_CNT_ENTRIES_57,Queue Entry Count57"
line.long 0x128 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt58,"
hexmask.long.word 0x128 0.--15. 1. "QUEUE_CNT_ENTRIES_58,Queue Entry Count58"
line.long 0x12C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt59,"
hexmask.long.word 0x12C 0.--15. 1. "QUEUE_CNT_ENTRIES_59,Queue Entry Count59"
line.long 0x130 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt60,"
hexmask.long.word 0x130 0.--15. 1. "QUEUE_CNT_ENTRIES_60,Queue Entry Count60"
line.long 0x134 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt61,"
hexmask.long.word 0x134 0.--15. 1. "QUEUE_CNT_ENTRIES_61,Queue Entry Count61"
line.long 0x138 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt62,"
hexmask.long.word 0x138 0.--15. 1. "QUEUE_CNT_ENTRIES_62,Queue Entry Count62"
line.long 0x13C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt63,"
hexmask.long.word 0x13C 0.--15. 1. "QUEUE_CNT_ENTRIES_63,Queue Entry Count63"
group.long 0xF40++0x3
line.long 0x0 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_reset,"
hexmask.long.byte 0x0 0.--5. 1. "RESET_QUEUE_ID,Reset Queue ID"
tree.end
tree.end
tree "PRU_ICSSG1_PR1_PROT_SLV (PRU_ICSSG1_PR1_PROT_SLV)"
base ad:0x300A4C00
group.long 0x0++0x7
line.long 0x0 "PR1_PROTECT__SLV__REGS_unlock_key,"
hexmask.long 0x0 0.--31. 1. "UNLOCK_KEY,UnLock Key Pattern 0x83E7_0B13 to UnLock 0x0000_0000 to Lock Must unlock to update MMRs"
line.long 0x4 "PR1_PROTECT__SLV__REGS_cfg,Config"
bitfld.long 0x4 6. "PRU1_DMEM1_LOCK_EN,Write Protect DMEM1 0: disable 1: enable When enabled only PRU1 can write to DMEM1" "0: disable,1: enable When enabled only PRU1 can write to DMEM1"
newline
bitfld.long 0x4 5. "PRU0_DMEM0_LOCK_EN,Write Protect DMEM0 0: disable 1: enable When enabled only PRU0 can write to DMEM0" "0: disable,1: enable When enabled only PRU0 can write to DMEM0"
newline
bitfld.long 0x4 4. "ICSS_CFG_WP_EN,Write Protect ICSS_CFG 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 3. "RTU1_PRU_WP_EN,Write Protect RTU1_PRU access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 2. "RTU0_PRU_WP_EN,Write Protect RTU0_PRU access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 1. "PRU1_WP_EN,Write Protect PRU1 access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
newline
bitfld.long 0x4 0. "PRU0_WP_EN,Write Protect PRU0 access Debug IMEM 0: disable 1: enable" "0: disable,1: enable"
tree.end
base ad:0x0
tree "PRU_ICSSG1_PR1_TASKS"
tree "PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR (PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR)"
base ad:0x300AA000
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU0__PR1_TASKS_MGR_PRU0_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
tree "PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR (PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR)"
base ad:0x300AA200
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU1__PR1_TASKS_MGR_PRU1_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
tree "PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR (PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX0_PR1_TASKS_MGR_PRU_TX0_MMR)"
base ad:0x300AA400
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU_TX0__PR1_TASKS_MGR_PRU_TX0_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
tree "PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR (PRU_ICSSG1_PR1_TASKS_MGR_PRU_TX1_PR1_TASKS_MGR_PRU_TX1_MMR)"
base ad:0x300AA500
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_PRU_TX1__PR1_TASKS_MGR_PRU_TX1_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
tree "PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR (PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR)"
base ad:0x300AA100
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_RTU0__PR1_TASKS_MGR_RTU0_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
tree "PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR (PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR)"
base ad:0x300AA300
group.long 0x0++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_global_cfg,Global Configuration"
bitfld.long 0x0 11. "TS2_EN_S4,TS2 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "TS2_EN_S3,TS2 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 9. "TS2_EN_S2,TS2 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "TS2_EN_S1,TS2 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 7. "TS2_EN_S0,TS2 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "TS1_EN_S4,TS1 Sub4 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "TS1_EN_S3,TS1 Sub3 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "TS1_EN_S2,TS1 Sub2 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 3. "TS1_EN_S1,TS1 Sub1 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TS1_EN_S0,TS1 Sub0 0: Disabled 1: Enabled" "0: Disabled,1: Enabled"
bitfld.long 0x0 0.--1. "TASKS_MGR_MODE,TaskSwap Mode 0: Disabled 1: RXTX 2: General_HW" "0: Disabled,1: RXTX,2: General_HW,?"
rgroup.long 0x4++0x3
line.long 0x0 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_global_status,Global Status"
bitfld.long 0x0 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x0 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x0 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
newline
bitfld.long 0x0 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
bitfld.long 0x0 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x0 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
newline
bitfld.long 0x0 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x0 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
bitfld.long 0x0 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
newline
bitfld.long 0x0 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "TS2_STATE,Task2 State"
hexmask.long.byte 0x0 0.--3. 1. "TS1_STATE,Task1 State"
group.long 0x8++0x43
line.long 0x0 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s0,TS1 Sub0 PC"
hexmask.long.word 0x0 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x4 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s1,TS1 Sub1 PC"
hexmask.long.word 0x4 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x8 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s2,TS1 Sub2 PC"
hexmask.long.word 0x8 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0xC "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s3,TS1 Sub3 PC"
hexmask.long.word 0xC 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x10 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_pc_s4,TS1 Sub4 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x14 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s0,TS2 Sub0 PC"
hexmask.long.word 0x14 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x18 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s1,TS2 Sub1 PC"
hexmask.long.word 0x18 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x1C "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s2,TS2 Sub2 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x20 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s3,TS2 Sub3 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x24 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_pc_s4,TS2 Sub4 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x28 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_rx_cfg,RX Configuration"
hexmask.long.byte 0x28 10.--14. 1. "BKN_SIZE,RX BKN Size  After BK1 and BK@  then after another 1 to 32 Bytes"
hexmask.long.byte 0x28 5.--9. 1. "BK2_SIZE,RX BK2 Size  The Second 1 to 32 Bytes trigger"
hexmask.long.byte 0x28 0.--4. 1. "BK1_SIZE,RX BK1 Size   The first 1 to 32 Bytes trigger"
line.long 0x2C "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_tx_cfg,TX Configuration"
hexmask.long.byte 0x2C 0.--5. 1. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes"
line.long 0x30 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_gen_cfg1,Generic TS1 Configuration1"
hexmask.long.byte 0x30 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x30 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x30 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x30 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x34 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts1_gen_cfg2,Generic TS1 Configuration2"
hexmask.long.byte 0x34 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x38 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_gen_cfg1,Generic TS2 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
newline
hexmask.long.byte 0x38 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x3C "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_ts2_gen_cfg2,Generic TS2 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x40 "PR1_TASKS_MGR_RTU1__PR1_TASKS_MGR_RTU1_MMR__REGS_cap_en_cfg,Enable capture new event cfg"
hexmask.long.word 0x40 0.--9. 1. "NEW_CAP_EN,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
tree.end
tree.end
tree.end
tree "PRU_ICSSG1_RAM_SLV_RAM (PRU_ICSSG1_RAM_SLV_RAM)"
base ad:0x30090000
group.long 0x0++0x3
line.long 0x0 "RAM__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
base ad:0x0
tree "PRU_ICSSG1_RAT"
tree "PRU_ICSSG1_RAT_SLICE0_CFG (PRU_ICSSG1_RAT_SLICE0_CFG)"
base ad:0x30088000
rgroup.long 0x0++0x7
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_config,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x3
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
group.long 0x820++0x3
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1"
bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1"
rgroup.long 0x824++0x17
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 4 = RAT."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 1 = Boundary crossing error."
line.long 0x8 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits."
line.long 0x10 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x840++0x13
line.long 0x0 "PR1_RAT_SLICE0__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1"
line.long 0x4 "PR1_RAT_SLICE0__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1"
line.long 0x8 "PR1_RAT_SLICE0__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1"
line.long 0xC "PR1_RAT_SLICE0__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1"
line.long 0x10 "PR1_RAT_SLICE0__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "PRU_ICSSG1_RAT_SLICE1_CFG (PRU_ICSSG1_RAT_SLICE1_CFG)"
base ad:0x30089000
rgroup.long 0x0++0x7
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "?,?,?,?"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_config,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x3
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID."
group.long 0x820++0x3
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1"
bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1"
rgroup.long 0x824++0x17
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 4 = RAT."
hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID."
hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID."
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group."
hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 1 = Boundary crossing error."
line.long 0x8 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits."
line.long 0xC "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits."
line.long 0x10 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID."
bitfld.long 0x10 13. "WRITE,Write." "0,1"
bitfld.long 0x10 12. "READ,Read." "0,1"
bitfld.long 0x10 11. "DEBUG,Debug." "0,1"
newline
bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1"
bitfld.long 0x10 9. "PRIV,Priv." "0,1"
bitfld.long 0x10 8. "SECURE,Secure." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID."
line.long 0x14 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count."
group.long 0x840++0x13
line.long 0x0 "PR1_RAT_SLICE1__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1"
line.long 0x4 "PR1_RAT_SLICE1__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1"
line.long 0x8 "PR1_RAT_SLICE1__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1"
line.long 0xC "PR1_RAT_SLICE1__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1"
line.long 0x10 "PR1_RAT_SLICE1__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree.end
tree.end
endif
tree.end
sif (cpuis("AM243?-CR5-MAIN0")||cpuis("AM243?-CR5-MAIN1"))
tree "PSC0 (PSC0)"
base ad:0x400000
rgroup.long 0x0++0x3
line.long 0x0 "VBUS_PID,The peripheral identification register is a constant register that contains the ID and ID revision number for that module. The PID stores version information used to identify the module. All bits within this register are read-only (writes have.."
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release"
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
rgroup.long 0x10++0x7
line.long 0x0 "VBUS_GBLCTL,This register contains global control to PSC."
hexmask.long.byte 0x0 8.--15. 1. "IO_ANA_CTL,General purpose IO/Analog PowerDown control. Directly drives io_ana_pdctl_po[7:0] outputs."
line.long 0x4 "VBUS_GBLSTAT,This register shows the PSC global status."
hexmask.long.word 0x4 16.--27. 1. "EF_SMRFLEX,Smart reflex class0 bits"
bitfld.long 0x4 0. "OVRIDE,PSC Override Status" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "VBUS_INTEVAL,This register has no storage. Read from this register returns 0."
bitfld.long 0x0 19. "GOSET,GOSTAT Interrupt Set" "0,1"
bitfld.long 0x0 18. "EPCSET,External Power Control Interrupt Set" "0,1"
bitfld.long 0x0 17. "ERRSET,Combined Interrupt Set" "0,1"
newline
bitfld.long 0x0 2. "EPCEV,External Power Control Interrupt Set" "0,1"
bitfld.long 0x0 1. "ERREV,Re_evaluate Error Interrupt" "0,1"
bitfld.long 0x0 0. "ALLEV,Re_evaluate combined PSC interrupt" "0,1"
rgroup.long 0x40++0x3
line.long 0x0 "VBUS_MERRPR,This register records pending error conditions for all modules. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "M,Records pending error conditions. Each bit n represents a module."
group.long 0x50++0x3
line.long 0x0 "VBUS_MERRCR,This register has no storage. Read from this register returns 0. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "M,Write of 1 clears the corresponding MERRPR bit."
rgroup.long 0x60++0x3
line.long 0x0 "VBUS_PERRPR,This register records pending error conditions for each power domain. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "P,Power Domain n Error Condition. Each bit n represents a power domain."
group.long 0x68++0x3
line.long 0x0 "VBUS_PERRCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "P,Write of 1 clears the corresponding PERRPR bit."
rgroup.long 0x70++0x3
line.long 0x0 "VBUS_EPCPR,This register records pending external power control conditions. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "EPC,External Power Control Intervention Request for Power Domain n"
group.long 0x78++0x3
line.long 0x0 "VBUS_EPCCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "EPC,Write of 1 clears the corresponding EPCPR bit"
rgroup.long 0x100++0x3
line.long 0x0 "VBUS_RAILSTAT,This register is a read-only and shows the current rail requestor whose request is being granted and the current value of the counter associated with this requestor."
hexmask.long.byte 0x0 24.--28. 1. "RAILNUM,Indicates Current Rail Requestor being processed by GPSC"
hexmask.long.byte 0x0 0.--7. 1. "RAILCNT,Indicates the current rail counter value"
group.long 0x104++0x7
line.long 0x0 "VBUS_RAILCTL,This register is user programmable. It holds the counter values for rail counter. User can select one of the two counter values to be used for each power domain (see RAILSEL register)."
hexmask.long.byte 0x0 8.--15. 1. "RAILCTR1,Rail Counter Value 1"
hexmask.long.byte 0x0 0.--7. 1. "RAILCTR0,Rail Counter Value 0"
line.long 0x4 "VBUS_RAILSEL,User can use this register to select the counter value (RAILCTL) for each power domain."
hexmask.long 0x4 0.--31. 1. "P,Rail Counter Select for Power Domain"
group.long 0x120++0x3
line.long 0x0 "VBUS_PTCMD,This is a pseudo-command register with no actual storage. Reads return 0. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "GO,Power Domain n GO Transition"
rgroup.long 0x128++0x3
line.long 0x0 "VBUS_PTSTAT,This is a status register. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)."
hexmask.long 0x0 0.--31. 1. "GOSTAT,Power Domain n Transition Command Status"
rgroup.long 0x200++0x3
line.long 0x0 "VBUS_PDSTAT,This is a status register. One register per power domain. Each register contains the status for the given power domain."
bitfld.long 0x0 11. "EMUIHB,Emulation Alters Domain State" "0,1"
bitfld.long 0x0 10. "PWRBAD,Power Bad error" "0,1"
bitfld.long 0x0 9. "PORDONE,POR Done Input Status" "0,1"
newline
bitfld.long 0x0 8. "PORZ,PORz output actual status" "0,1"
hexmask.long.byte 0x0 0.--4. 1. "STATE,Current Power Domain State"
group.long 0x300++0x3
line.long 0x0 "VBUS_PDCTL,This is a control register. One register per power domain."
bitfld.long 0x0 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x0 29. "PWRSW,Power shorting Switch Control" "0,1"
bitfld.long 0x0 28. "ISO,Isolation Cell control" "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "WAKECNT,RAM wake count delay value"
bitfld.long 0x0 12.--14. "PDMODE,Power Down mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 9. "EMUIHBIE,Emulation alters domain state" "0,1"
newline
bitfld.long 0x0 8. "EPCGOOD,External Power Control Power Good Indication" "0,1"
bitfld.long 0x0 0. "NEXT,User_Desired Next Power Domain State" "0,1"
rgroup.long 0x400++0x3
line.long 0x0 "VBUS_PDCFG,This is a status register. It shows PSC settings for easy debug."
bitfld.long 0x0 3. "ICEPICK,Icepick support" "0,1"
bitfld.long 0x0 1. "MEMSLPKWK,Memory sleep-wake domain" "0,1"
bitfld.long 0x0 0. "ALWAYSON,Always on power domain" "0,1"
rgroup.long 0x600++0x3
line.long 0x0 "VBUS_MDCFG,This is a constant register showing some PSC settings for easy debug. This register is read only."
hexmask.long.byte 0x0 16.--20. 1. "PWRDOM,Indicates which power domain this module belongs to"
bitfld.long 0x0 15. "AUTOONLY,0: This LPSC supports all modes  1: This LPSC supports Enable  AutoSleep or AutoWake only" "0: This LPSC supports all modes,1: This LPSC supports Enable"
bitfld.long 0x0 14. "RESETISO,0: This LPSC does not support Reset Isolation  1: This LPSC supports Reset Isolation" "0: This LPSC does not support Reset Isolation,1: This LPSC supports Reset Isolation"
newline
bitfld.long 0x0 13. "NEXTLOCK,0: MDCTL.NEXT field is writable  1: MDCTL.NEXT field is locked" "0: MDCTL,1: MDCTL"
bitfld.long 0x0 12. "ASYNC,Async Lpsc" "0,1"
bitfld.long 0x0 11. "ICEPICK,IcePick support" "0,1"
newline
bitfld.long 0x0 10. "PERMDIS,Permanently disable" "0,1"
bitfld.long 0x0 9. "PLLHANDSHAKE,RTL parameter PLL_HANDSHAKE" "0,1"
bitfld.long 0x0 6.--8. "NUMSCRDISBALE,Number of PWR_SCR_DISABLE interfaces required on LPSC" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--5. "NUMCLKEN,Number of PWR_CLK_EN interfaces required on LPSC" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "NUMCLK,Number of PWR_CLKSTOP interfaces required on LPSC" "0,1,2,3,4,5,6,7"
rgroup.long 0x800++0x3
line.long 0x0 "VBUS_MDSTAT,This register shows the status of each module. Requires one register per module on the device."
bitfld.long 0x0 17. "EMUIHB,Emulation Alters Module State. Inhibits Module Inactive or Force Module Active." "0,1"
bitfld.long 0x0 16. "EMURST,Emulation Alters Reset" "0,1"
bitfld.long 0x0 12. "MCKOUT,Actual modclk output to module" "0,1"
newline
bitfld.long 0x0 11. "MRSTDONE,Module reset initialization done status" "0,1"
bitfld.long 0x0 10. "MRSTZ,Module reset actual status" "0,1"
bitfld.long 0x0 9. "LRSTDONE,Module local reset initialization done status" "0,1"
newline
bitfld.long 0x0 8. "LRSTZ,Module local reset actual status" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "STATE,These bits indicate the current module state"
group.long 0xA00++0x3
line.long 0x0 "VBUS_MDCTL,This register provides specific control for the individual module. One register per module on the device."
bitfld.long 0x0 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x0 12. "RESETISO,Reset Isolation" "0,1"
bitfld.long 0x0 11. "BLKCHIP1RST,Block Chip_1_Reset" "0,1"
newline
bitfld.long 0x0 10. "EMUIHBIE,Emulation Alters Module State. Inhibits Module Inactive or Force Module Active." "0,1"
bitfld.long 0x0 9. "EMURSTIE,Emulation Alter Reset Interrupt Enable" "0,1"
bitfld.long 0x0 8. "LRSTZ,Module local reset control" "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "NEXT,Module Next State"
tree.end
tree "PSRAMECC0"
base ad:0x0
tree "PSRAMECC0_ECC_AGGR (PSRAMECC0_ECC_AGGR)"
base ad:0x700000
rgroup.long 0x0++0x3
line.long 0x0 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
base ad:0x0
tree "PSRAMECC0_RAM (PSRAMECC0_RAM)"
group.long 0x0++0x3
line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree "ROM0 (ROM0)"
base ad:0x41800000
rgroup.long 0x0++0x3
line.long 0x0 "ROM_ROM_REG,The ROM memory words provide memory mapped random access data storage."
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "RTI"
base ad:0x0
tree "RTI0_CFG (RTI0_CFG)"
base ad:0xE000000
group.long 0x0++0x1B
line.long 0x0 "CFG_GCTRL,"
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.."
bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode"
newline
bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
line.long 0x4 "CFG_TBCTRL,"
bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0  Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
line.long 0x8 "CFG_CAPCTRL,"
bitfld.long 0x8 1. "CAPCNTR1,This bit determines  which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
bitfld.long 0x8 0. "CAPCNTR0,This bit determines  which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
line.long 0xC "CFG_COMPCTRL,"
bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
newline
bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register."
line.long 0x14 "CFG_UC0,"
hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x18 "CFG_CPUC0,"
hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value  which is compared with the Up Counter 0. When the compare matches  Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
rgroup.long 0x20++0x7
line.long 0x0 "CFG_CAFRC0,"
hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
line.long 0x4 "CFG_CAUC0,"
hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.."
group.long 0x30++0xB
line.long 0x0 "CFG_FRC1,"
hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register."
line.long 0x4 "CFG_UC1,"
hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x8 "CFG_CPUC1,"
hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value  which is compared with the Up Counter 1. When the compare matches  Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
rgroup.long 0x40++0x7
line.long 0x0 "CFG_CAFRC1,"
hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
line.long 0x4 "CFG_CAUC1,"
hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.."
group.long 0x50++0x27
line.long 0x0 "CFG_COMP0,"
hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x4 "CFG_UDCP0,"
hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value  which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x8 "CFG_COMP1,"
hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0xC "CFG_UDCP1,"
hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value  which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x10 "CFG_COMP2,"
hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x14 "CFG_UDCP2,"
hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value  which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x18 "CFG_COMP3,"
hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x1C "CFG_UDCP3,"
hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value  which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x20 "CFG_TBLCOMP,"
hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.."
line.long 0x24 "CFG_TBHCOMP,"
hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0  since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.."
group.long 0x80++0xB
line.long 0x0 "CFG_SETINT,"
bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
line.long 0x4 "CFG_CLEARINT,"
bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
line.long 0x8 "CFG_INTFLAG,"
bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
group.long 0x90++0xF
line.long 0x0 "CFG_DWDCTRL,"
hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.."
line.long 0x4 "CFG_DWDPRLD,"
hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.."
line.long 0x8 "CFG_WDSTATUS,"
bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated  or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
line.long 0xC "CFG_WDKEY,"
hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.."
rgroup.long 0xA0++0x3
line.long 0x0 "CFG_DWDCNTR,"
hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz  a watchdog reset will be generated in 1 second. User and.."
group.long 0xA4++0x1B
line.long 0x0 "CFG_WWDRXNCTRL,"
hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read)  privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration  or if the watchdog is not.."
line.long 0x4 "CFG_WWDSIZECTRL,"
hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read)  privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).."
line.long 0x8 "CFG_INTCLRENABLE,"
hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.."
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hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.."
line.long 0xC "CFG_COMP0CLR,"
hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 0 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x10 "CFG_COMP1CLR,"
hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 1 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x14 "CFG_COMP2CLR,"
hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 2 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x18 "CFG_COMP3CLR,"
hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 3 interrupt or DMA request line is cleared. User and privilege.."
tree.end
tree "RTI1_CFG (RTI1_CFG)"
base ad:0xE010000
group.long 0x0++0x1B
line.long 0x0 "CFG_GCTRL,"
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.."
bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode"
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bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
line.long 0x4 "CFG_TBCTRL,"
bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0  Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
line.long 0x8 "CFG_CAPCTRL,"
bitfld.long 0x8 1. "CAPCNTR1,This bit determines  which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
bitfld.long 0x8 0. "CAPCNTR0,This bit determines  which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
line.long 0xC "CFG_COMPCTRL,"
bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
newline
bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register."
line.long 0x14 "CFG_UC0,"
hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x18 "CFG_CPUC0,"
hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value  which is compared with the Up Counter 0. When the compare matches  Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
rgroup.long 0x20++0x7
line.long 0x0 "CFG_CAFRC0,"
hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
line.long 0x4 "CFG_CAUC0,"
hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.."
group.long 0x30++0xB
line.long 0x0 "CFG_FRC1,"
hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register."
line.long 0x4 "CFG_UC1,"
hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x8 "CFG_CPUC1,"
hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value  which is compared with the Up Counter 1. When the compare matches  Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
rgroup.long 0x40++0x7
line.long 0x0 "CFG_CAFRC1,"
hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
line.long 0x4 "CFG_CAUC1,"
hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.."
group.long 0x50++0x27
line.long 0x0 "CFG_COMP0,"
hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x4 "CFG_UDCP0,"
hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value  which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x8 "CFG_COMP1,"
hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0xC "CFG_UDCP1,"
hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value  which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x10 "CFG_COMP2,"
hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x14 "CFG_UDCP2,"
hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value  which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x18 "CFG_COMP3,"
hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x1C "CFG_UDCP3,"
hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value  which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x20 "CFG_TBLCOMP,"
hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.."
line.long 0x24 "CFG_TBHCOMP,"
hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0  since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.."
group.long 0x80++0xB
line.long 0x0 "CFG_SETINT,"
bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
line.long 0x4 "CFG_CLEARINT,"
bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
line.long 0x8 "CFG_INTFLAG,"
bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
group.long 0x90++0xF
line.long 0x0 "CFG_DWDCTRL,"
hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.."
line.long 0x4 "CFG_DWDPRLD,"
hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.."
line.long 0x8 "CFG_WDSTATUS,"
bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated  or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
line.long 0xC "CFG_WDKEY,"
hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.."
rgroup.long 0xA0++0x3
line.long 0x0 "CFG_DWDCNTR,"
hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz  a watchdog reset will be generated in 1 second. User and.."
group.long 0xA4++0x1B
line.long 0x0 "CFG_WWDRXNCTRL,"
hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read)  privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration  or if the watchdog is not.."
line.long 0x4 "CFG_WWDSIZECTRL,"
hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read)  privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).."
line.long 0x8 "CFG_INTCLRENABLE,"
hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.."
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hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.."
line.long 0xC "CFG_COMP0CLR,"
hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 0 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x10 "CFG_COMP1CLR,"
hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 1 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x14 "CFG_COMP2CLR,"
hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 2 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x18 "CFG_COMP3CLR,"
hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 3 interrupt or DMA request line is cleared. User and privilege.."
tree.end
tree "RTI8_CFG (RTI8_CFG)"
base ad:0xE080000
group.long 0x0++0x1B
line.long 0x0 "CFG_GCTRL,"
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.."
bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode"
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bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
line.long 0x4 "CFG_TBCTRL,"
bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0  Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
line.long 0x8 "CFG_CAPCTRL,"
bitfld.long 0x8 1. "CAPCNTR1,This bit determines  which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
bitfld.long 0x8 0. "CAPCNTR0,This bit determines  which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
line.long 0xC "CFG_COMPCTRL,"
bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register."
line.long 0x14 "CFG_UC0,"
hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x18 "CFG_CPUC0,"
hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value  which is compared with the Up Counter 0. When the compare matches  Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
rgroup.long 0x20++0x7
line.long 0x0 "CFG_CAFRC0,"
hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
line.long 0x4 "CFG_CAUC0,"
hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.."
group.long 0x30++0xB
line.long 0x0 "CFG_FRC1,"
hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register."
line.long 0x4 "CFG_UC1,"
hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x8 "CFG_CPUC1,"
hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value  which is compared with the Up Counter 1. When the compare matches  Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
rgroup.long 0x40++0x7
line.long 0x0 "CFG_CAFRC1,"
hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
line.long 0x4 "CFG_CAUC1,"
hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.."
group.long 0x50++0x27
line.long 0x0 "CFG_COMP0,"
hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x4 "CFG_UDCP0,"
hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value  which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x8 "CFG_COMP1,"
hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0xC "CFG_UDCP1,"
hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value  which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x10 "CFG_COMP2,"
hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x14 "CFG_UDCP2,"
hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value  which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x18 "CFG_COMP3,"
hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x1C "CFG_UDCP3,"
hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value  which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x20 "CFG_TBLCOMP,"
hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.."
line.long 0x24 "CFG_TBHCOMP,"
hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0  since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.."
group.long 0x80++0xB
line.long 0x0 "CFG_SETINT,"
bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
line.long 0x4 "CFG_CLEARINT,"
bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
line.long 0x8 "CFG_INTFLAG,"
bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
group.long 0x90++0xF
line.long 0x0 "CFG_DWDCTRL,"
hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.."
line.long 0x4 "CFG_DWDPRLD,"
hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.."
line.long 0x8 "CFG_WDSTATUS,"
bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated  or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
line.long 0xC "CFG_WDKEY,"
hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.."
rgroup.long 0xA0++0x3
line.long 0x0 "CFG_DWDCNTR,"
hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz  a watchdog reset will be generated in 1 second. User and.."
group.long 0xA4++0x1B
line.long 0x0 "CFG_WWDRXNCTRL,"
hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read)  privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration  or if the watchdog is not.."
line.long 0x4 "CFG_WWDSIZECTRL,"
hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read)  privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).."
line.long 0x8 "CFG_INTCLRENABLE,"
hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.."
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hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.."
line.long 0xC "CFG_COMP0CLR,"
hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 0 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x10 "CFG_COMP1CLR,"
hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 1 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x14 "CFG_COMP2CLR,"
hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 2 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x18 "CFG_COMP3CLR,"
hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 3 interrupt or DMA request line is cleared. User and privilege.."
tree.end
tree "RTI9_CFG (RTI9_CFG)"
base ad:0xE090000
group.long 0x0++0x1B
line.long 0x0 "CFG_GCTRL,"
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.."
bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode"
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bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
line.long 0x4 "CFG_TBCTRL,"
bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0  Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
line.long 0x8 "CFG_CAPCTRL,"
bitfld.long 0x8 1. "CAPCNTR1,This bit determines  which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
bitfld.long 0x8 0. "CAPCNTR0,This bit determines  which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
line.long 0xC "CFG_COMPCTRL,"
bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register."
line.long 0x14 "CFG_UC0,"
hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x18 "CFG_CPUC0,"
hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value  which is compared with the Up Counter 0. When the compare matches  Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
rgroup.long 0x20++0x7
line.long 0x0 "CFG_CAFRC0,"
hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
line.long 0x4 "CFG_CAUC0,"
hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.."
group.long 0x30++0xB
line.long 0x0 "CFG_FRC1,"
hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register."
line.long 0x4 "CFG_UC1,"
hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x8 "CFG_CPUC1,"
hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value  which is compared with the Up Counter 1. When the compare matches  Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
rgroup.long 0x40++0x7
line.long 0x0 "CFG_CAFRC1,"
hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
line.long 0x4 "CFG_CAUC1,"
hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.."
group.long 0x50++0x27
line.long 0x0 "CFG_COMP0,"
hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x4 "CFG_UDCP0,"
hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value  which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x8 "CFG_COMP1,"
hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0xC "CFG_UDCP1,"
hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value  which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x10 "CFG_COMP2,"
hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x14 "CFG_UDCP2,"
hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value  which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x18 "CFG_COMP3,"
hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x1C "CFG_UDCP3,"
hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value  which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x20 "CFG_TBLCOMP,"
hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.."
line.long 0x24 "CFG_TBHCOMP,"
hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0  since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.."
group.long 0x80++0xB
line.long 0x0 "CFG_SETINT,"
bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
line.long 0x4 "CFG_CLEARINT,"
bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
line.long 0x8 "CFG_INTFLAG,"
bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
group.long 0x90++0xF
line.long 0x0 "CFG_DWDCTRL,"
hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.."
line.long 0x4 "CFG_DWDPRLD,"
hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.."
line.long 0x8 "CFG_WDSTATUS,"
bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated  or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
line.long 0xC "CFG_WDKEY,"
hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.."
rgroup.long 0xA0++0x3
line.long 0x0 "CFG_DWDCNTR,"
hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz  a watchdog reset will be generated in 1 second. User and.."
group.long 0xA4++0x1B
line.long 0x0 "CFG_WWDRXNCTRL,"
hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read)  privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration  or if the watchdog is not.."
line.long 0x4 "CFG_WWDSIZECTRL,"
hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read)  privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).."
line.long 0x8 "CFG_INTCLRENABLE,"
hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.."
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hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.."
line.long 0xC "CFG_COMP0CLR,"
hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 0 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x10 "CFG_COMP1CLR,"
hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 1 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x14 "CFG_COMP2CLR,"
hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 2 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x18 "CFG_COMP3CLR,"
hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 3 interrupt or DMA request line is cleared. User and privilege.."
tree.end
tree "RTI10_CFG (RTI10_CFG)"
base ad:0xE0A0000
group.long 0x0++0x1B
line.long 0x0 "CFG_GCTRL,"
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.."
bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode"
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bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
line.long 0x4 "CFG_TBCTRL,"
bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0  Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
line.long 0x8 "CFG_CAPCTRL,"
bitfld.long 0x8 1. "CAPCNTR1,This bit determines  which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
bitfld.long 0x8 0. "CAPCNTR0,This bit determines  which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
line.long 0xC "CFG_COMPCTRL,"
bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register."
line.long 0x14 "CFG_UC0,"
hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x18 "CFG_CPUC0,"
hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value  which is compared with the Up Counter 0. When the compare matches  Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
rgroup.long 0x20++0x7
line.long 0x0 "CFG_CAFRC0,"
hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
line.long 0x4 "CFG_CAUC0,"
hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.."
group.long 0x30++0xB
line.long 0x0 "CFG_FRC1,"
hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register."
line.long 0x4 "CFG_UC1,"
hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x8 "CFG_CPUC1,"
hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value  which is compared with the Up Counter 1. When the compare matches  Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
rgroup.long 0x40++0x7
line.long 0x0 "CFG_CAFRC1,"
hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
line.long 0x4 "CFG_CAUC1,"
hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.."
group.long 0x50++0x27
line.long 0x0 "CFG_COMP0,"
hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x4 "CFG_UDCP0,"
hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value  which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x8 "CFG_COMP1,"
hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0xC "CFG_UDCP1,"
hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value  which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x10 "CFG_COMP2,"
hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x14 "CFG_UDCP2,"
hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value  which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x18 "CFG_COMP3,"
hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x1C "CFG_UDCP3,"
hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value  which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x20 "CFG_TBLCOMP,"
hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.."
line.long 0x24 "CFG_TBHCOMP,"
hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0  since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.."
group.long 0x80++0xB
line.long 0x0 "CFG_SETINT,"
bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
line.long 0x4 "CFG_CLEARINT,"
bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
line.long 0x8 "CFG_INTFLAG,"
bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
group.long 0x90++0xF
line.long 0x0 "CFG_DWDCTRL,"
hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.."
line.long 0x4 "CFG_DWDPRLD,"
hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.."
line.long 0x8 "CFG_WDSTATUS,"
bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated  or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
line.long 0xC "CFG_WDKEY,"
hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.."
rgroup.long 0xA0++0x3
line.long 0x0 "CFG_DWDCNTR,"
hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz  a watchdog reset will be generated in 1 second. User and.."
group.long 0xA4++0x1B
line.long 0x0 "CFG_WWDRXNCTRL,"
hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read)  privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration  or if the watchdog is not.."
line.long 0x4 "CFG_WWDSIZECTRL,"
hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read)  privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).."
line.long 0x8 "CFG_INTCLRENABLE,"
hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.."
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hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.."
line.long 0xC "CFG_COMP0CLR,"
hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 0 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x10 "CFG_COMP1CLR,"
hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 1 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x14 "CFG_COMP2CLR,"
hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 2 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x18 "CFG_COMP3CLR,"
hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 3 interrupt or DMA request line is cleared. User and privilege.."
tree.end
tree "RTI11_CFG (RTI11_CFG)"
base ad:0xE0B0000
group.long 0x0++0x1B
line.long 0x0 "CFG_GCTRL,"
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.."
bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode"
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bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters"
line.long 0x4 "CFG_TBCTRL,"
bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0  Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
line.long 0x8 "CFG_CAPCTRL,"
bitfld.long 0x8 1. "CAPCNTR1,This bit determines  which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
bitfld.long 0x8 0. "CAPCNTR0,This bit determines  which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
line.long 0xC "CFG_COMPCTRL,"
bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
newline
bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register."
line.long 0x14 "CFG_UC0,"
hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x18 "CFG_CPUC0,"
hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value  which is compared with the Up Counter 0. When the compare matches  Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
rgroup.long 0x20++0x7
line.long 0x0 "CFG_CAFRC0,"
hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
line.long 0x4 "CFG_CAUC0,"
hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.."
group.long 0x30++0xB
line.long 0x0 "CFG_FRC1,"
hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register."
line.long 0x4 "CFG_UC1,"
hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters  without having the problem of a.."
line.long 0x8 "CFG_CPUC1,"
hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value  which is compared with the Up Counter 1. When the compare matches  Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
rgroup.long 0x40++0x7
line.long 0x0 "CFG_CAFRC1,"
hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs  controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
line.long 0x4 "CFG_CAUC1,"
hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs  controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.."
group.long 0x50++0x27
line.long 0x0 "CFG_COMP0,"
hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x4 "CFG_UDCP0,"
hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value  which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x8 "CFG_COMP1,"
hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0xC "CFG_UDCP1,"
hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value  which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x10 "CFG_COMP2,"
hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x14 "CFG_UDCP2,"
hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value  which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x18 "CFG_COMP3,"
hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  an interrupt is flagged. With this register it is also possible to initiate a.."
line.long 0x1C "CFG_UDCP3,"
hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value  which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.."
line.long 0x20 "CFG_TBLCOMP,"
hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.."
line.long 0x24 "CFG_TBHCOMP,"
hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0  since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.."
group.long 0x80++0xB
line.long 0x0 "CFG_SETINT,"
bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
line.long 0x4 "CFG_CLEARINT,"
bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
newline
bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
line.long 0x8 "CFG_INTFLAG,"
bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
group.long 0x90++0xF
line.long 0x0 "CFG_DWDCTRL,"
hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.."
line.long 0x4 "CFG_DWDPRLD,"
hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.."
line.long 0x8 "CFG_WDSTATUS,"
bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated  or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0"
newline
bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0"
bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
line.long 0xC "CFG_WDKEY,"
hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.."
rgroup.long 0xA0++0x3
line.long 0x0 "CFG_DWDCNTR,"
hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz  a watchdog reset will be generated in 1 second. User and.."
group.long 0xA4++0x1B
line.long 0x0 "CFG_WWDRXNCTRL,"
hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read)  privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration  or if the watchdog is not.."
line.long 0x4 "CFG_WWDSIZECTRL,"
hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read)  privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).."
line.long 0x8 "CFG_INTCLRENABLE,"
hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.."
newline
hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.."
hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.."
line.long 0xC "CFG_COMP0CLR,"
hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 0 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x10 "CFG_COMP1CLR,"
hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 1 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x14 "CFG_COMP2CLR,"
hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 2 interrupt or DMA request line is cleared. User and privilege.."
line.long 0x18 "CFG_COMP3CLR,"
hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value  which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value  the compare 3 interrupt or DMA request line is cleared. User and privilege.."
tree.end
tree.end
tree "SPINLOCK0 (SPINLOCK0)"
base ad:0x2A000000
rgroup.long 0x0++0x3
line.long 0x0 "REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family."
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z"
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bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z"
group.long 0x10++0x3
line.long 0x0 "REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock"
bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads  it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module"
hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n  the total number of spinlocks divided by 32. e.g. For 256 spin locks  this will return the number 0x08"
bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range  then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224"
newline
bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range  then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192"
bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range  then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160"
newline
bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range  then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128"
bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range  then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96"
newline
bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range  then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64"
bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range  then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32"
newline
bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range  then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0"
group.long 0x800++0x3
line.long 0x0 "REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'"
bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect"
tree.end
tree "STM0"
base ad:0x0
tree "STM0_CTI_CSCTI (STM0_CTI_CSCTI)"
base ad:0x73D201000
group.long 0x0++0x3
line.long 0x0 "CTI__CFG__CSCTI_CFG_CTICONTROL,The CTI Control Register enables the CTI. >"
bitfld.long 0x0 0. "GLBEN,Enables or disables the ECT." "0,1"
group.long 0x10++0x2F
line.long 0x0 "CTI__CFG__CSCTI_CFG_CTIINTACK,The CTI Interrupt Acknowledge Register is write-only. Any bits written as a 1 cause the ctitrigout output signal to be acknowledged. The acknowledgement is cleared when MAPTRIGOUT is deactivated. This register is used when.."
hexmask.long.byte 0x0 0.--7. 1. "INTACK,Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register  the corresponding ctitrigout is acknowledged and is cleared when MAPTRIGOUT is LOW."
line.long 0x4 "CTI__CFG__CSCTI_CFG_CTIAPPSET,The CTI Application Trigger Set Register is read/write. A write to this register causes a channel event to be raised. corresponding to the bit written to."
hexmask.long.byte 0x4 0.--3. 1. "APPSET,Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel. Read : 0 = application trigger inactive (reset). 1 = application trigger active. Write : 0 = no effect. 1 = generate.."
line.long 0x8 "CTI__CFG__CSCTI_CFG_CTIAPPCLEAR,The CTI Interrupt Acknowledge Register is write-only. A write to this register causes a channel event to be cleared. corresponding to the bit written to."
hexmask.long.byte 0x8 0.--3. 1. "APPCLEAR,Clears corresponding bits in the CTIAPPSET register. There is one bit of the register for each channel. When a 1 is written to a bit in this register  the corresponding application trigger is disabled in the CTIAPPSET register. Writing a 0 to.."
line.long 0xC "CTI__CFG__CSCTI_CFG_CTIAPPPULSE,The CTI Application Pulse Register is write-only. A write to this register causes a channel event pulse. one cticlk period. to be generated. corresponding to the bit written to. The pulse external to the ECT can be.."
hexmask.long.byte 0xC 0.--3. 1. "APPULSE,Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. When a 1 is written to a bit in this register  a corresponding channel event pulse is generated for one cticlk.."
line.long 0x10 "CTI__CFG__CSCTI_CFG_CTIINEN0,The CTI Trigger 0 to Channel Enable Register enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.."
hexmask.long.byte 0x10 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register  it enables the ctitrigin signal to generate.."
line.long 0x14 "CTI__CFG__CSCTI_CFG_CTIINEN1,The CTI Trigger 1 to Channel Enable Register enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.."
hexmask.long.byte 0x14 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register  it enables the ctitrigin signal to generate.."
line.long 0x18 "CTI__CFG__CSCTI_CFG_CTIINEN2,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.."
hexmask.long.byte 0x18 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register  it enables the ctitrigin signal to generate.."
line.long 0x1C "CTI__CFG__CSCTI_CFG_CTIINEN3,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.."
hexmask.long.byte 0x1C 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register  it enables the ctitrigin signal to generate.."
line.long 0x20 "CTI__CFG__CSCTI_CFG_CTIINEN4,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.."
hexmask.long.byte 0x20 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register  it enables the ctitrigin signal to generate.."
line.long 0x24 "CTI__CFG__CSCTI_CFG_CTIINEN5,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.."
hexmask.long.byte 0x24 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register  it enables the ctitrigin signal to generate.."
line.long 0x28 "CTI__CFG__CSCTI_CFG_CTIINEN6,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.."
hexmask.long.byte 0x28 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register  it enables the ctitrigin signal to generate.."
line.long 0x2C "CTI__CFG__CSCTI_CFG_CTIINEN7,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.."
hexmask.long.byte 0x2C 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register  it enables the ctitrigin signal to generate.."
group.long 0xA0++0x1F
line.long 0x0 "CTI__CFG__CSCTI_CFG_CTIOUTEN0,The CTI Channel to Trigger 0 Enable Registers define which channels can generate a ctitrigout[0] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.."
hexmask.long.byte 0x0 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[1] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.."
line.long 0x4 "CTI__CFG__CSCTI_CFG_CTIOUTEN1,The CTI Channel to Trigger 1 Enable Registers define which channels can generate a ctitrigout[1] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.."
hexmask.long.byte 0x4 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[1] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.."
line.long 0x8 "CTI__CFG__CSCTI_CFG_CTIOUTEN2,The CTI Channel to Trigger 2 Enable Registers define which channels can generate a ctitrigout[2] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.."
hexmask.long.byte 0x8 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[2] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.."
line.long 0xC "CTI__CFG__CSCTI_CFG_CTIOUTEN3,The CTI Channel to Trigger 3 Enable Registers define which channels can generate a ctitrigout[3] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.."
hexmask.long.byte 0xC 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[3] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.."
line.long 0x10 "CTI__CFG__CSCTI_CFG_CTIOUTEN4,The CTI Channel to Trigger 4 Enable Registers define which channels can generate a ctitrigout[4] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.."
hexmask.long.byte 0x10 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[4] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.."
line.long 0x14 "CTI__CFG__CSCTI_CFG_CTIOUTEN5,The CTI Channel to Trigger 5 Enable Registers define which channels can generate a ctitrigout[5] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.."
hexmask.long.byte 0x14 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[5] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.."
line.long 0x18 "CTI__CFG__CSCTI_CFG_CTIOUTEN6,The CTI Channel to Trigger 6 Enable Registers define which channels can generate a ctitrigout[6] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.."
hexmask.long.byte 0x18 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[6] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.."
line.long 0x1C "CTI__CFG__CSCTI_CFG_CTIOUTEN7,The CTI Channel to Trigger 7 Enable Registers define which channels can generate a ctitrigout[7] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.."
hexmask.long.byte 0x1C 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[7] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.."
rgroup.long 0x130++0xF
line.long 0x0 "CTI__CFG__CSCTI_CFG_CTITRIGINSTATUS,The CTI Trigger In Status Register provides the status of the ctitrigin inputs."
hexmask.long.byte 0x0 0.--7. 1. "TRIGINSTATUS,Shows the status of the ctitrigin inputs. 1 = ctitrigin is active. 0 = ctitrigin is inactive. Because the register provides a view of the raw ctitrigin inputs  the reset value is unknown. There is one bit of the field for each trigger.."
line.long 0x4 "CTI__CFG__CSCTI_CFG_CTITRIGOUTSTATUS,The CTI Trigger Out Status Register provides the status of the ctitrigout outputs."
hexmask.long.byte 0x4 0.--7. 1. "TRIGOUTSTATUS,Shows the status of the ctitrigout outputs. 1 = ctitrigout is active. 0 = ctitrigout is inactive. There is one bit of the field for each trigger output."
line.long 0x8 "CTI__CFG__CSCTI_CFG_CTICHINSTATUS,The CTI Channel In Status Register provides the status of the ctichin inputs."
hexmask.long.byte 0x8 0.--3. 1. "CTICHINSTATUS,Shows the status of the ctichin inputs. 1 = ctichin is active. 0 = ctichin is inactive. Because the register provides a view of the raw ctichin inputs  the reset value is unknown. There is one bit of the field for each channel input."
line.long 0xC "CTI__CFG__CSCTI_CFG_CTICHOUTSTATUS,The CTI Channel Out Status Register provides the status of the CTI ctichout outputs."
hexmask.long.byte 0xC 0.--3. 1. "CTICHOUTSTATUS,Shows the status of the ctichout outputs. 1 = ctichout is active. 0 = ctichout is inactive. There is one bit of the field for each channel output."
group.long 0x140++0x7
line.long 0x0 "CTI__CFG__CSCTI_CFG_CTIGATE,The Gate Enable Register prevents the channels from propagating through the CTM to other CTIs. This enables local cross-triggering. for example for causing an interrupt when the ETM trigger occurs. It can be used effectively.."
bitfld.long 0x0 3. "CTIGATEEN3,Enable CTICHOUT3. Set to 0 to disable channel propagation." "0,1"
bitfld.long 0x0 2. "CTIGATEEN2,Enable CTICHOUT2. Set to 0 to disable channel propagation." "0,1"
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bitfld.long 0x0 1. "CTIGATEEN1,Enable CTICHOUT1. Set to 0 to disable channel propagation." "0,1"
bitfld.long 0x0 0. "CTIGATEEN0,Enable CTICHOUT0. Set to 0 to disable channel propagation." "0,1"
line.long 0x4 "CTI__CFG__CSCTI_CFG_ASICCTL,Implementation-defined ASIC control. value written to the register is output on asicctl[7 : 0]."
hexmask.long.byte 0x4 0.--7. 1. "ASICCTL,Implementation-defined ASIC control  value written to the register is output on asicctl[7 : 0]. If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be reflected within the.."
group.long 0xEDC++0xF
line.long 0x0 "CTI__CFG__CSCTI_CFG_ITCHINACK,This register is a write-only register. It can be used to set the value of the CTCHINACK outputs."
hexmask.long.byte 0x0 0.--3. 1. "CTCHINACK,Set the value of the CTCHINACK outputs."
line.long 0x4 "CTI__CFG__CSCTI_CFG_ITTRIGINACK,This register is a write-only register. It can be used to set the value of the CTTRIGINACK outputs."
hexmask.long.byte 0x4 0.--7. 1. "CTTRIGINACK,Set the value of the CTTRIGINACK outputs."
line.long 0x8 "CTI__CFG__CSCTI_CFG_ITCHOUT,This register is a write-only register. It can be used to set the value of the CTCHOUT outputs."
hexmask.long.byte 0x8 0.--3. 1. "CTCHOUT,Set the value of the CTCHOUT outputs."
line.long 0xC "CTI__CFG__CSCTI_CFG_ITTRIGOUT,This register is a write-only register. It can be used to set the value of the CTTRIGOUT outputs."
hexmask.long.byte 0xC 0.--7. 1. "CTTRIGOUT,Set the value of the CTTRIGOUT outputs."
rgroup.long 0xEEC++0xF
line.long 0x0 "CTI__CFG__CSCTI_CFG_ITCHOUTACK,This register is a read-only register. It can be used to read the values of the CTCHOUTACK inputs."
hexmask.long.byte 0x0 0.--3. 1. "CTCHOUTACK,Read the values of the CTCHOUTACK inputs."
line.long 0x4 "CTI__CFG__CSCTI_CFG_ITTRIGOUTACK,This register is a read-only register. It can be used to read the values of the CTTRIGOUTACK inputs."
hexmask.long.byte 0x4 0.--7. 1. "CTTRIGOUTACK,Read the value of the CTTRIGOUTACK inputs."
line.long 0x8 "CTI__CFG__CSCTI_CFG_ITCHIN,This register is a read-only register. It can be used to read the values of the CTCHIN inputs."
hexmask.long.byte 0x8 0.--3. 1. "CTCHIN,Read the value of the CTCHIN inputs."
line.long 0xC "CTI__CFG__CSCTI_CFG_ITTRIGIN,This register is a read-only register. It can be used to read the values of the CTTRIGIN inputs."
hexmask.long.byte 0xC 0.--7. 1. "CTTRIGIN,Read the values of the CTTRIGIN inputs."
group.long 0xF00++0x3
line.long 0x0 "CTI__CFG__CSCTI_CFG_ITCTRL,This register is used to enable topology detection. For more information see the CoreSight Architecture Specification. This register enables the component to switch from a functional mode. the default behavior. to integration.."
bitfld.long 0x0 0. "INTEGRATION_MODE,Allows the component to switch from functional mode to integration mode or back." "0,1"
group.long 0xFA0++0x7
line.long 0x0 "CTI__CFG__CSCTI_CFG_CLAIMSET,This is used in conjunction with Claim Tag Clear Register. CLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set. write. and returns the number of bits that can be set..."
hexmask.long.byte 0x0 0.--3. 1. "CLAIMSET,This claim tag bit is implemented"
line.long 0x4 "CTI__CFG__CSCTI_CFG_CLAIMCLR,This register is used in conjunction with Claim Tag Set Register. CLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared. write. and returns the current Claim Tag.."
hexmask.long.byte 0x4 0.--3. 1. "CLAIMCLR,The value present reflects the current setting of the Claim Tag."
group.long 0xFB0++0x3
line.long 0x0 "CTI__CFG__CSCTI_CFG_LAR,This is used to enable write access to device registers. External accesses from a debugger (paddrdbg31 = 1) are not subject to the Lock Registers. A debugger does not have to unlock the component in order to write and modify the.."
hexmask.long 0x0 0.--31. 1. "ACCESS_W,A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the affect of removing write access."
rgroup.long 0xFB4++0x7
line.long 0x0 "CTI__CFG__CSCTI_CFG_LSR,This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. When locked. write access is blocked to all registers. except the Lock Access Register. External accesses from a.."
bitfld.long 0x0 2. "LOCKTYPE,Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit" "0,1"
bitfld.long 0x0 1. "LOCKGRANT,Returns the current status of the Lock. This bit reads as 0 when read from an external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers." "0,1"
newline
bitfld.long 0x0 0. "LOCKEXIST,Indicates that a lock control mechanism exists for this device. This bit reads as 0 when read from an external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers." "0,1"
line.long 0x4 "CTI__CFG__CSCTI_CFG_AUTHSTATUS,Reports what functionality is currently permitted by the authentication interface."
bitfld.long 0x4 6.--7. "SNID,Indicates the security level for secure non-invasive debug" "0,1,2,3"
bitfld.long 0x4 4.--5. "SID,Indicates the security level for secure invasive debug" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "NSNID,Indicates the security level for non-secure non-invasive debug" "0,1,2,3"
bitfld.long 0x4 0.--1. "NSID,Indicates the security level for non-secure invasive debug" "0,1,2,3"
rgroup.long 0xFC8++0xB
line.long 0x0 "CTI__CFG__CSCTI_CFG_DEVID,This register indicates the capabilities of the CTI."
hexmask.long.byte 0x0 16.--19. 1. "NUMCH,Number of ECT channels available."
hexmask.long.byte 0x0 8.--15. 1. "NUMTRIG,Number of ECT triggers available."
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hexmask.long.byte 0x0 0.--4. 1. "EXTMUXNUM,Indicates the number of multiplexing available on Trigger Inputs and Trigger Outputs using asicctl. Default value of 5'b00000 indicating no multiplexing present. Reflects the value of the Verilog define EXTMUXNUM that the user must alter.."
line.long 0x4 "CTI__CFG__CSCTI_CFG_DEVTYPE,It provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information."
hexmask.long.byte 0x4 4.--7. 1. "SUB_TYPE,Sub-classification within the major category"
hexmask.long.byte 0x4 0.--3. 1. "MAJOR_TYPE,Major classification grouping for this debug/trace component"
line.long 0x8 "CTI__CFG__CSCTI_CFG_PERIPHID4,Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator."
hexmask.long.byte 0x8 4.--7. 1. "SIZE,This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read as 0x0  4KB only  for 8KB set to.."
hexmask.long.byte 0x8 0.--3. 1. "DES_2,JEDEC continuation code indicating the designer of the component (along with the identity code)"
rgroup.long 0xFE0++0x1F
line.long 0x0 "CTI__CFG__CSCTI_CFG_PERIPHID0,Part of the set of Peripheral Identification registers. Contains part of the designer specific part number."
hexmask.long.byte 0x0 0.--7. 1. "PART_0,Bits [7 : 0] of the component's part number. This is selected by the designer of the component."
line.long 0x4 "CTI__CFG__CSCTI_CFG_PERIPHID1,Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity."
hexmask.long.byte 0x4 4.--7. 1. "DES_0,Bits 3 : 0 of the JEDEC identity code indicating the designer of the component (along with the continuation code)"
hexmask.long.byte 0x4 0.--3. 1. "PART_1,Bits [11 : 8] of the component's part number. This is selected by the designer of the component."
line.long 0x8 "CTI__CFG__CSCTI_CFG_PERIPHID2,Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision."
hexmask.long.byte 0x8 4.--7. 1. "REVISION,The Revision field is an incremental value starting at 0x0 for the first design of this component. This only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the exact major/minor revision."
bitfld.long 0x8 3. "JEDEC,Always set. Indicates that a JEDEC assigned value is used" "0,1"
newline
bitfld.long 0x8 0.--2. "DES_1,Bits 6 : 4 of the JEDEC identity code indicating the designer of the component (along with the continuation code)" "?,?,?,?,?,?,6: 4 of the JEDEC identity code indicating the..,?"
line.long 0xC "CTI__CFG__CSCTI_CFG_PERIPHID3,Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields."
hexmask.long.byte 0xC 4.--7. 1. "REVAND,This field indicates minor errata fixes specific to this design  for example metal fixes after implementation. In most cases this field is zero. It is recommended that component designers ensure this field can be changed by a metal fix if.."
hexmask.long.byte 0xC 0.--3. 1. "CMOD,Where the component is reusable IP  this value indicates if the customer has modified the behavior of the component. In most cases this field is zero."
line.long 0x10 "CTI__CFG__CSCTI_CFG_COMPID0,Reserved Reserved Reserved A component identification register. that indicates that the identification registers are present."
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Contains bits [7 : 0] of the component identification"
line.long 0x14 "CTI__CFG__CSCTI_CFG_COMPID1,A component identification register. that indicates that the identification registers are present. This register also indicates the component class."
hexmask.long.byte 0x14 4.--7. 1. "CLASS,Class of the component. E.g. ROM table  CoreSight component etc. Constitutes bits [15 : 12] of the component identification."
hexmask.long.byte 0x14 0.--3. 1. "PRMBL_1,Contains bits [11 : 8] of the component identification"
line.long 0x18 "CTI__CFG__CSCTI_CFG_COMPID2,A component identification register. that indicates that the identification registers are present."
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Contains bits [23 : 16] of the component identification"
line.long 0x1C "CTI__CFG__CSCTI_CFG_COMPID3,A component identification register. that indicates that the identification registers are present."
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Contains bits [31 : 24] of the component identification"
tree.end
tree "STM0_CXSTM (STM0_CXSTM)"
base ad:0x73D200000
wgroup.long 0xC04++0x7
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMASTARTR,This write-only register is used to start a DMA transfer.<p/>A write of one when the DMA peripheral request interface is idle starts a DMA transfer. A write of zero has no effect. A write of one when the.."
bitfld.long 0x0 0. "START," "0,1"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMASTOPR,This write-only register is used to stop a DMA transfer.<p/>A write of one stops an active DMA transfer. A write of zero has no effect. A write of one when the DMA peripheral request interface is idle has.."
bitfld.long 0x4 0. "STOP," "0,1"
rgroup.long 0xC0C++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMASTATR,This read-only register is used to determine the status of the DMA peripheral request interface."
bitfld.long 0x0 0. "STATUS," "0,1"
group.long 0xC10++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMACTLR,Controls the DMA transfer request mechanism."
bitfld.long 0x0 2.--3. "SENS," "0,1,2,3"
rgroup.long 0xCFC++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMAIDR,This read-only register indicates the DMA features of the STM"
hexmask.long.byte 0x0 8.--11. 1. "VENDSPEC,"
hexmask.long.byte 0x0 4.--7. 1. "CLASSREV,"
hexmask.long.byte 0x0 0.--3. 1. "CLASS,"
group.long 0xD00++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEER,This read/write register is used to enable hardware events to generate trace.<p/>The register defined one bit per hardware event. Writing 1 enables the appropriate hardware event. writing 0 disables the.."
hexmask.long 0x0 0.--31. 1. "HEE,"
group.long 0xD20++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHETER,This register is used to enable trigger generation on hardware events."
hexmask.long 0x0 0.--31. 1. "HETE,"
group.long 0xD60++0xB
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEBSR,This register is used to select the Hardware Event bank"
bitfld.long 0x0 0. "HEBS," "0,1"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEMCR,This register is used to control the primary functions of Hardware Event tracing."
bitfld.long 0x4 7. "ATBTRIGEN," "0,1"
bitfld.long 0x4 6. "TRIGCLEAR," "0,1"
rbitfld.long 0x4 5. "TRIGSTATUS," "0,1"
bitfld.long 0x4 4. "TRIGCTL," "0,1"
newline
rbitfld.long 0x4 2. "ERRDETECT," "0,1"
bitfld.long 0x4 1. "COMPEN," "0,1"
bitfld.long 0x4 0. "EN," "0,1"
line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEEXTMUXR,This register is used to control hardware event multiplexors external to the STM"
hexmask.long.byte 0x8 0.--7. 1. "EXTMUX,"
rgroup.long 0xDF4++0xB
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEMASTR,Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2."
hexmask.long.word 0x0 0.--15. 1. "MASTER,"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEFEAT1R,Indicates the features of the STM."
bitfld.long 0x4 28.--30. "HEEXTMUXSIZE," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 15.--23. 1. "NUMHE,"
bitfld.long 0x4 4.--5. "HECOMP," "0,1,2,3"
bitfld.long 0x4 3. "HEMASTR," "0,1"
newline
bitfld.long 0x4 2. "HEERR," "0,1"
bitfld.long 0x4 0. "HETER," "0,1"
line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEIDR,Indicates the features of hardware event tracing in the STM."
hexmask.long.byte 0x8 8.--11. 1. "VENDSPEC,"
hexmask.long.byte 0x8 4.--7. 1. "CLASSREV,"
hexmask.long.byte 0x8 0.--3. 1. "CLASS,"
group.long 0xE00++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPER,This read/write only register is used to enable the stimulus registers to generate trace.<p/>The register defines one bit per stimulus register. Writing 1 enables the appropriate stimulus port. writing 0.."
hexmask.long 0x0 0.--31. 1. "SPE,"
group.long 0xE20++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPTER,This register is used to enable trigger generation on writes to enabled stimulus port registers."
hexmask.long 0x0 0.--31. 1. "SPTE,"
group.long 0xE60++0x13
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPSCR,This register allows a debugger to program which stimulus ports the STMSPER and STMSPTER apply to."
hexmask.long.word 0x0 20.--31. 1. "PORTSEL,"
bitfld.long 0x0 0.--1. "PORTCTL," "0,1,2,3"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPMSCR,This register allows a debugger to program which masters the STMSPSCR applies to."
hexmask.long.byte 0x4 15.--22. 1. "MASTSEL,"
bitfld.long 0x4 0. "MASTCTL," "0,1"
line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPOVERRIDER,This register allows a debugger to override various features of the STM."
hexmask.long.tbyte 0x8 15.--31. 1. "PORTSEL,"
bitfld.long 0x8 2. "OVERTS," "0,1"
bitfld.long 0x8 0.--1. "OVERCTL," "0,1,2,3"
line.long 0xC "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPMOVERRIDER,This register allows a debugger to choose which masters the STMSPOVERRIDERR applies to."
hexmask.long.byte 0xC 15.--22. 1. "MASTSEL,"
bitfld.long 0xC 0. "MASTCTL," "0,1"
line.long 0x10 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPTRIGCSR,This register is used to control the STM triggers caused by STMSPTER."
bitfld.long 0x10 4. "ATBTRIGEN_DIR," "0,1"
bitfld.long 0x10 3. "ATBTRIGEN_TE," "0,1"
bitfld.long 0x10 2. "TRIGCLEAR," "0,1"
rbitfld.long 0x10 1. "TRIGSTATUS," "0,1"
newline
bitfld.long 0x10 0. "TRIGCTL," "0,1"
group.long 0xE80++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMTCSR,Controls the STM settings."
rbitfld.long 0x0 23. "BUSY," "0,1"
hexmask.long.byte 0x0 16.--22. 1. "TRACEID,"
bitfld.long 0x0 5. "COMPEN," "0,1"
rbitfld.long 0x0 2. "SYNCEN," "0,1"
newline
bitfld.long 0x0 1. "TSEN," "0,1"
bitfld.long 0x0 0. "EN," "0,1"
wgroup.long 0xE84++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMTSSTIMR,This write-only register is used to force the next packet caused by a stimulus port write to have a timestamp output."
bitfld.long 0x0 0. "FORCETS," "0,1"
group.long 0xE8C++0xB
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMTSFREQR,This read-write register is used to indicate the frequency of the timestamp counter. The unit of measurement is increments per second. When the STPv2 protocol is used. this register contains the value output.."
hexmask.long 0x0 0.--31. 1. "FREQ,"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSYNCR,This register controls the interval between synchronization packets. in terms of the number of bytes of trace generated.<p/>This register only provides a hint of the desired synchronization frequency..."
bitfld.long 0x4 12. "MODE," "0,1"
hexmask.long.word 0x4 3.--11. 1. "COUNT,"
line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMAUXCR,Used for IMPLEMENTATION DEFINED STM controls."
bitfld.long 0x8 7. "QHWEVOVERRIDE," "0,1"
bitfld.long 0x8 2. "PRIORINVDIS," "0,1"
bitfld.long 0x8 1. "ASYNCPE," "0,1"
bitfld.long 0x8 0. "FIFOAF," "0,1"
rgroup.long 0xEA0++0xB
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMFEAT1R,Indicates the features of the STM."
bitfld.long 0x0 22.--23. "SWOEN," "0,1,2,3"
bitfld.long 0x0 20.--21. "SYNCEN," "0,1,2,3"
bitfld.long 0x0 18.--19. "HWTEN," "0,1,2,3"
bitfld.long 0x0 16.--17. "TSPRESCALE," "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "TRIGCTL," "0,1,2,3"
hexmask.long.byte 0x0 10.--13. 1. "TRACEBUS,"
bitfld.long 0x0 8.--9. "SYNC," "0,1,2,3"
bitfld.long 0x0 7. "FORCETS," "0,1"
newline
bitfld.long 0x0 6. "TSFREQ," "0,1"
bitfld.long 0x0 4.--5. "TS," "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "PROT,"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMFEAT2R,Indicates the features of the STM."
bitfld.long 0x4 16.--17. "SPTYPE," "0,1,2,3"
hexmask.long.byte 0x4 12.--15. 1. "DSIZE,"
bitfld.long 0x4 9.--10. "SPTRTYPE," "0,1,2,3"
bitfld.long 0x4 7.--8. "PRIVMASK," "0,1,2,3"
newline
bitfld.long 0x4 6. "SPOVERRIDE," "0,1"
bitfld.long 0x4 4.--5. "SPCOMP," "0,1,2,3"
bitfld.long 0x4 2. "SPER," "0,1"
bitfld.long 0x4 0.--1. "SPTER," "0,1,2,3"
line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMFEAT3R,Indicates the features of the STM."
hexmask.long.byte 0x8 0.--6. 1. "NUMMAST,"
wgroup.long 0xEE8++0x7
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITTRIGGER,Integration Test for Cross-Trigger Outputs Register"
bitfld.long 0x0 3. "ASYNCOUT_W," "0,1"
bitfld.long 0x0 2. "TRIGOUTHETE_W," "0,1"
bitfld.long 0x0 1. "TRIGOUTSW_W," "0,1"
bitfld.long 0x0 0. "TRIGOUTSPTE_W," "0,1"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBDATA0,Controls the value of the ATDATAM output in integration mode:"
bitfld.long 0x4 8. "ATDATAM63_W," "0,1"
bitfld.long 0x4 7. "ATDATAM55_W," "0,1"
bitfld.long 0x4 6. "ATDATAM47_W," "0,1"
bitfld.long 0x4 5. "ATDATAM39_W," "0,1"
newline
bitfld.long 0x4 4. "ATDATAM31_W," "0,1"
bitfld.long 0x4 3. "ATDATAM23_W," "0,1"
bitfld.long 0x4 2. "ATDATAM15_W," "0,1"
bitfld.long 0x4 1. "ATDATAM7_W," "0,1"
newline
bitfld.long 0x4 0. "ATDATAM0_W," "0,1"
rgroup.long 0xEF0++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBCTR2,Returns the value of the ATREADYM and AFVALIDM inputs in integration mode."
bitfld.long 0x0 1. "AFVALIDM_R," "0,1"
bitfld.long 0x0 0. "ATREADYM_R," "0,1"
wgroup.long 0xEF4++0x7
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBID,Controls the value of the ATIDM output in integration mode."
hexmask.long.byte 0x0 0.--6. 1. "ATIDM_W,"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBCTR0,Controls the value of the ATVALIDM. AFREADYM. and ATBYTESM outputs in integration mode."
bitfld.long 0x4 8.--10. "ATBYTESM_W," "0,1,2,3,4,5,6,7"
bitfld.long 0x4 1. "AFREADYM_W," "0,1"
bitfld.long 0x4 0. "ATVALIDM_W," "0,1"
group.long 0xF00++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITCTRL,Used to enable topology detection. See the CoreSight Architecture Specification for more information. This register enables the component to switch between functional mode and integration mode. The default.."
bitfld.long 0x0 0. "IME," "0,1"
rgroup.long 0xFA0++0x7
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCLAIMSET,This is used in conjunction with Claim Tag Clear Register. STMCLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set. write. and returns the number of.."
hexmask.long.byte 0x0 0.--3. 1. "SET,"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCLAIMCLR,This register is used in conjunction with Claim Tag Set Register. STMCLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared. write. and returns.."
hexmask.long.byte 0x4 0.--3. 1. "CLR,"
wgroup.long 0xFB0++0x3
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMLAR,Enables write access to device registers."
hexmask.long 0x0 0.--31. 1. "KEY,"
rgroup.long 0xFB4++0xB
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMLSR,Indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. The lock mechanism does not impact accesses to the extended stimulus port registers. This register.."
bitfld.long 0x0 2. "NTT," "0,1"
bitfld.long 0x0 1. "SLK," "0,1"
bitfld.long 0x0 0. "SLI," "0,1"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMAUTHSTATUS,Reports the required security level and current status of the authentication interface."
bitfld.long 0x4 6.--7. "SNID," "0,1,2,3"
bitfld.long 0x4 4.--5. "SID," "0,1,2,3"
bitfld.long 0x4 2.--3. "NSNID," "0,1,2,3"
bitfld.long 0x4 0.--1. "NSID," "0,1,2,3"
line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDEVARCH,Indicates the architect and architecture of the STM. For the STM-500. the architect is ARM. and the architecture is STMv1.1"
hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,"
bitfld.long 0x8 20. "PRESENT," "0,1"
hexmask.long.byte 0x8 16.--19. 1. "REVISION,"
hexmask.long.word 0x8 0.--14. 1. "ARCHID,"
rgroup.long 0xFC8++0xB
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDEVID,Indicates the capabilities of the CoreSight STM."
hexmask.long.tbyte 0x0 0.--16. 1. "NUMSP,"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDEVTYPE,Provides a debugger with information about the component when the part number is not recognized. The debugger can then report this information."
hexmask.long.byte 0x4 4.--7. 1. "SUB,"
hexmask.long.byte 0x4 0.--3. 1. "MAJOR,"
line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR4,Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator."
hexmask.long.byte 0x8 4.--7. 1. "SIZE,"
hexmask.long.byte 0x8 0.--3. 1. "DES_2,"
group.long 0xFD4++0xB
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR5,Reserved"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR6,Reserved"
line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR7,Reserved"
rgroup.long 0xFE0++0x1F
line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR0,Part of the set of Peripheral Identification registers. Contains part of the designer specific part number."
hexmask.long.byte 0x0 0.--7. 1. "PART_0,"
line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR1,Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity."
hexmask.long.byte 0x4 4.--7. 1. "DES_0,"
hexmask.long.byte 0x4 0.--3. 1. "PART_1,"
line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR2,Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision."
hexmask.long.byte 0x8 4.--7. 1. "REVISION,"
bitfld.long 0x8 3. "JEDEC," "0,1"
bitfld.long 0x8 0.--2. "DES_1," "0,1,2,3,4,5,6,7"
line.long 0xC "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR3,Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer_Modified bit fields."
hexmask.long.byte 0xC 4.--7. 1. "REVAND,"
hexmask.long.byte 0xC 0.--3. 1. "CMOD,"
line.long 0x10 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCIDR0,A component identification register. that indicates that the identification registers are present."
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,"
line.long 0x14 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCIDR1,A component identification register. that indicates that the identification registers are present. This register also indicates the component class."
hexmask.long.byte 0x14 4.--7. 1. "CLASS,"
hexmask.long.byte 0x14 0.--3. 1. "PRMBL_1,"
line.long 0x18 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCIDR2,A component identification register. that indicates that the identification registers are present."
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,"
line.long 0x1C "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCIDR3,A component identification register. that indicates that the identification registers are present."
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,"
tree.end
tree.end
tree "TIMER"
base ad:0x0
tree "TIMER0_CFG (TIMER0_CFG)"
base ad:0x2400000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER1_CFG (TIMER1_CFG)"
base ad:0x2410000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER2_CFG (TIMER2_CFG)"
base ad:0x2420000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER3_CFG (TIMER3_CFG)"
base ad:0x2430000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER4_CFG (TIMER4_CFG)"
base ad:0x2440000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER5_CFG (TIMER5_CFG)"
base ad:0x2450000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER6_CFG (TIMER6_CFG)"
base ad:0x2460000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER7_CFG (TIMER7_CFG)"
base ad:0x2470000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER8_CFG (TIMER8_CFG)"
base ad:0x2480000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER9_CFG (TIMER9_CFG)"
base ad:0x2490000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER10_CFG (TIMER10_CFG)"
base ad:0x24A0000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER11_CFG (TIMER11_CFG)"
base ad:0x24B0000
rgroup.long 0x0++0x3
line.long 0x0 "CFG_TIDR,"
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
group.long 0x10++0x3
line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x27
line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line"
bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status."
bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status."
bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable"
bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable."
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads  it always return 0xFFFF_FFFF"
rgroup.long 0x48++0x3
line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
group.long 0x4C++0x3
line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value"
hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register"
rgroup.long 0x50++0x3
line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register"
group.long 0x54++0x3
line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1"
bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1"
bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture"
hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register"
group.long 0x5C++0x13
line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation."
hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment"
line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation."
hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment"
line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation."
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter"
line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
base ad:0x0
tree "TIMERMGR0"
tree "TIMERMGR0_CONFIG (TIMERMGR0_CONFIG)"
base ad:0x3CD00000
rgroup.long 0x0++0x3
line.long 0x0 "CONFIG_TM_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,PID function identifier"
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number"
newline
bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number"
group.long 0x4++0x3
line.long 0x0 "CONFIG_TM_CNTL,This register controls the overall behavior of the timer manager module"
bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit  all timers from 0 to the TM_CNTL.max_timer will be enabled. Useful for initial programming  to not need to loop over every TIMER_CONTROL register to enable every timer if many or all are.." "0,1"
hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers  set this to 511. All timers above this number will be ignored. Should be set once during initialization"
bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero  the timers will all be halted and will not count" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "CONFIG_TIMER_COUNTER,This register contains the current counter value"
hexmask.long 0x0 0.--31. 1. "COUNT,The current timer_counter value  in the timebase being used by all timers in this module"
rgroup.long 0xA0++0xB
line.long 0x0 "CONFIG_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is the only MMR that needs to be.."
bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0  this should always be a 1" "0,1"
hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire"
hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers"
line.long 0x4 "CONFIG_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all 1024 timers."
bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1"
hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire"
bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1"
hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire"
line.long 0x8 "CONFIG_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which banks contain expired timers. The.."
hexmask.long 0x8 0.--31. 1. "BANK_STATUS,A 1 in bit N indicates that the corresponding bank has expired timers"
rgroup.long 0x100++0x3
line.long 0x0 "CONFIG_TIMER_STATUS,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out"
hexmask.long 0x0 0.--31. 1. "STATUS,Each bit is the timeout status for an individual timer"
tree.end
tree "TIMERMGR0_TIMERS (TIMERMGR0_TIMERS)"
base ad:0x37000000
group.long 0x0++0x7
line.long 0x0 "TIMERS_TIMER_SETUP_VALUE,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via TM_CTRL and TIMER_CONTROL_N"
hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed"
line.long 0x4 "TIMERS_TIMER_CONTROL,Modifies the behavior of timer N with control signals below"
bitfld.long 0x4 8. "AUTO_RESET,Automatically reset the timer when it expires. Provides the option of a periodic timer  rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers  so the expirations can occur regularly without.." "0,1"
rbitfld.long 0x4 2. "TIMER_EXPIRED,The status of the current timer. 1 = expired" "?,1: expired"
bitfld.long 0x4 1. "SET_TIMER,This may be used to touch/set a timer. When a 1 is written  the corresponding timer will be refreshed with the current value in its TIMER_SETUP_VALUES register. Will always read 0" "0,1"
bitfld.long 0x4 0. "TIMER_ENABLED,Write 1 to enable  0 to disable the timer." "0,1"
tree.end
tree.end
tree.end
tree "TIMESYNC_EVENT_INTROUTER0_CFG (TIMESYNC_EVENT_INTROUTER0_CFG)"
base ad:0xA40000
rgroup.long 0x0++0x3
line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register"
bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function"
hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version"
bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version"
group.long 0x4++0x3
line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register"
bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "MUX_CNTL,Mux control for interrupt N"
tree.end
tree "UART"
base ad:0x0
tree "UART0 (UART0)"
base ad:0x2800000
group.long 0x0++0x3
line.long 0x0 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register"
group.long 0x0++0x7
line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x4 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.."
bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x7
line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "CTS_IT," "0,1"
newline
bitfld.long 0x0 6. "RTS_IT," "0,1"
newline
bitfld.long 0x0 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x0 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x0 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x0 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
line.long 0x4 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i"
newline
bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level  TCR[3:0]  is reached  and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i"
newline
bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable"
newline
bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7. 1: Enables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7"
newline
hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options"
group.long 0x8++0x3
line.long 0x0 "MEM_FCR,Notes:"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000  RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?"
newline
bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000  TX_FIFO_TRIG is not considered. If SCR[6]=1  TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?"
newline
bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1"
newline
bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 0. "FIFO_EN," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3"
newline
hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,"
newline
bitfld.long 0x0 0. "IT_PENDING," "0,1"
group.long 0xC++0x7
line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "DIV_EN," "0,1"
newline
bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1"
newline
bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0  the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1  the parity bit is forced to 0 in the transmitted and received.." "0,1"
newline
bitfld.long 0x0 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x0 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1"
newline
bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3"
line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x4 7. "RESERVED," "0,1"
newline
bitfld.long 0x4 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x4 5. "XON_EN," "0,1"
newline
bitfld.long 0x4 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x4 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x4 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1"
newline
bitfld.long 0x4 0. "DTR," "0,1"
group.long 0x10++0x3
line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes."
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_CIR,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "RESERVED," "0,1"
newline
bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_IRDA,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x0 3. "ABORT," "0,1"
newline
bitfld.long 0x0 2. "CRC," "0,1"
newline
bitfld.long 0x0 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_UART,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x0 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x0 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x0 4. "RX_BI," "0,1"
newline
bitfld.long 0x0 3. "RX_FE," "0,1"
newline
bitfld.long 0x0 2. "RX_PE," "0,1"
newline
bitfld.long 0x0 1. "RX_OE," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x3
line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes."
rgroup.long 0x18++0x3
line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1"
newline
bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1"
newline
bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode  it is equivalent to MCR[0]" "0,1"
newline
bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1"
newline
bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1"
newline
bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1"
newline
bitfld.long 0x0 1. "DSR_STS," "0,1"
newline
bitfld.long 0x0 0. "CTS_STS," "0,1"
group.long 0x18++0x3
line.long 0x0 "MEM_TCR,Transmission Control Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)"
newline
hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)"
group.long 0x18++0x7
line.long 0x0 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes."
line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x3
line.long 0x0 "MEM_TLR,Trigger Level Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level"
group.long 0x1C++0xB
line.long 0x0 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes."
line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1"
newline
bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1"
newline
bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1"
newline
bitfld.long 0x4 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1"
newline
bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3"
newline
bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1"
newline
bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3"
newline
rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs  the meaning of the interrupt is :" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "MEM_SFLSR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0 0. "RESERVED0," "0,1"
group.long 0x28++0x3
line.long 0x0 "MEM_TXFLL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x7
line.long 0x0 "MEM_TXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length"
line.long 0x4 "MEM_RXFLL,IrDA modes only."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x0 "MEM_SFREGL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length"
group.long 0x34++0x3
line.long 0x0 "MEM_RXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception"
rgroup.long 0x34++0x3
line.long 0x0 "MEM_SFREGH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length"
group.long 0x38++0x3
line.long 0x0 "MEM_BLR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1"
newline
bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1"
newline
hexmask.long.byte 0x0 0.--5. 1. "RESERVED,"
rgroup.long 0x38++0x3
line.long 0x0 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?"
newline
bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified"
newline
hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.."
group.long 0x3C++0xF
line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1"
newline
bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1"
newline
bitfld.long 0x0 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1  garbage data is sent over TX line." "0,1"
newline
bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission  the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1"
newline
bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1"
newline
bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1  UART IrDA will start a new transfer.." "0,1"
newline
bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1"
line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 5. "DSR_IT," "0,1"
newline
bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1"
line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x8 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1"
line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs  the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.."
rgroup.long 0x50++0x3
line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned"
bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module"
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module."
group.long 0x54++0x3
line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1"
newline
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "MEM_SYSS,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1"
group.long 0x5C++0x7
line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.."
rgroup.long 0x64++0x7
line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,"
line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,"
group.long 0x6C++0xB
line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x0 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1"
newline
bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1"
line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x4 2.--7. 1. "RESERVED,"
newline
bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6."
rgroup.long 0x78++0x7
line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused"
hexmask.long 0x0 0.--31. 1. "RESERVED,"
line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused"
hexmask.long 0x4 0.--31. 1. "RESERVED,"
group.long 0x80++0x23
line.long 0x0 "MEM_MDR3,Mode definition register 3."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0  RX: RTS=1. 1 => TX: RTS=1  RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1"
newline
bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
line.long 0x8 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x8 7. "RESERVED," "0,1"
newline
bitfld.long 0x8 6. "MODE9,9-bit character length. When '1'  overrides character length setting in LCR" "0,1"
newline
bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values  as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "MODE,New modes [when set  overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0xC "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode  when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set  signaling an address" "0,1"
line.long 0x14 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes  useful when comunicating with slower devices"
line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Lower byte of the 16 bit value]"
line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Higher byte of the 16 bit value]"
line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned  the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving  even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character  if the receiver did not acknowledge. If not acknowledged after the max value is reached  the USART transmitter will set parity error  stop and not continue until it is cleared." "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x0 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0xF
line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x4 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x8 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree "UART1 (UART1)"
base ad:0x2810000
group.long 0x0++0x3
line.long 0x0 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register"
group.long 0x0++0x7
line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x4 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.."
bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x7
line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "CTS_IT," "0,1"
newline
bitfld.long 0x0 6. "RTS_IT," "0,1"
newline
bitfld.long 0x0 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x0 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x0 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x0 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
line.long 0x4 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i"
newline
bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level  TCR[3:0]  is reached  and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i"
newline
bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable"
newline
bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7. 1: Enables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7"
newline
hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options"
group.long 0x8++0x3
line.long 0x0 "MEM_FCR,Notes:"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000  RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?"
newline
bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000  TX_FIFO_TRIG is not considered. If SCR[6]=1  TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?"
newline
bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1"
newline
bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 0. "FIFO_EN," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3"
newline
hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,"
newline
bitfld.long 0x0 0. "IT_PENDING," "0,1"
group.long 0xC++0x7
line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "DIV_EN," "0,1"
newline
bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1"
newline
bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0  the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1  the parity bit is forced to 0 in the transmitted and received.." "0,1"
newline
bitfld.long 0x0 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x0 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1"
newline
bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3"
line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x4 7. "RESERVED," "0,1"
newline
bitfld.long 0x4 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x4 5. "XON_EN," "0,1"
newline
bitfld.long 0x4 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x4 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x4 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1"
newline
bitfld.long 0x4 0. "DTR," "0,1"
group.long 0x10++0x3
line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes."
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_CIR,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "RESERVED," "0,1"
newline
bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_IRDA,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x0 3. "ABORT," "0,1"
newline
bitfld.long 0x0 2. "CRC," "0,1"
newline
bitfld.long 0x0 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_UART,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x0 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x0 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x0 4. "RX_BI," "0,1"
newline
bitfld.long 0x0 3. "RX_FE," "0,1"
newline
bitfld.long 0x0 2. "RX_PE," "0,1"
newline
bitfld.long 0x0 1. "RX_OE," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x3
line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes."
rgroup.long 0x18++0x3
line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1"
newline
bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1"
newline
bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode  it is equivalent to MCR[0]" "0,1"
newline
bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1"
newline
bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1"
newline
bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1"
newline
bitfld.long 0x0 1. "DSR_STS," "0,1"
newline
bitfld.long 0x0 0. "CTS_STS," "0,1"
group.long 0x18++0x3
line.long 0x0 "MEM_TCR,Transmission Control Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)"
newline
hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)"
group.long 0x18++0x7
line.long 0x0 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes."
line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x3
line.long 0x0 "MEM_TLR,Trigger Level Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level"
group.long 0x1C++0xB
line.long 0x0 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes."
line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1"
newline
bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1"
newline
bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1"
newline
bitfld.long 0x4 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1"
newline
bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3"
newline
bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1"
newline
bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3"
newline
rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs  the meaning of the interrupt is :" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "MEM_SFLSR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0 0. "RESERVED0," "0,1"
group.long 0x28++0x3
line.long 0x0 "MEM_TXFLL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x7
line.long 0x0 "MEM_TXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length"
line.long 0x4 "MEM_RXFLL,IrDA modes only."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x0 "MEM_SFREGL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length"
group.long 0x34++0x3
line.long 0x0 "MEM_RXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception"
rgroup.long 0x34++0x3
line.long 0x0 "MEM_SFREGH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length"
group.long 0x38++0x3
line.long 0x0 "MEM_BLR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1"
newline
bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1"
newline
hexmask.long.byte 0x0 0.--5. 1. "RESERVED,"
rgroup.long 0x38++0x3
line.long 0x0 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?"
newline
bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified"
newline
hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.."
group.long 0x3C++0xF
line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1"
newline
bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1"
newline
bitfld.long 0x0 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1  garbage data is sent over TX line." "0,1"
newline
bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission  the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1"
newline
bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1"
newline
bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1  UART IrDA will start a new transfer.." "0,1"
newline
bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1"
line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 5. "DSR_IT," "0,1"
newline
bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1"
line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x8 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1"
line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs  the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.."
rgroup.long 0x50++0x3
line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned"
bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module"
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module."
group.long 0x54++0x3
line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1"
newline
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "MEM_SYSS,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1"
group.long 0x5C++0x7
line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.."
rgroup.long 0x64++0x7
line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,"
line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,"
group.long 0x6C++0xB
line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x0 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1"
newline
bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1"
line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x4 2.--7. 1. "RESERVED,"
newline
bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6."
rgroup.long 0x78++0x7
line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused"
hexmask.long 0x0 0.--31. 1. "RESERVED,"
line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused"
hexmask.long 0x4 0.--31. 1. "RESERVED,"
group.long 0x80++0x23
line.long 0x0 "MEM_MDR3,Mode definition register 3."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0  RX: RTS=1. 1 => TX: RTS=1  RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1"
newline
bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
line.long 0x8 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x8 7. "RESERVED," "0,1"
newline
bitfld.long 0x8 6. "MODE9,9-bit character length. When '1'  overrides character length setting in LCR" "0,1"
newline
bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values  as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "MODE,New modes [when set  overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0xC "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode  when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set  signaling an address" "0,1"
line.long 0x14 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes  useful when comunicating with slower devices"
line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Lower byte of the 16 bit value]"
line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Higher byte of the 16 bit value]"
line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned  the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving  even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character  if the receiver did not acknowledge. If not acknowledged after the max value is reached  the USART transmitter will set parity error  stop and not continue until it is cleared." "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x0 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0xF
line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x4 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x8 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree "UART2 (UART2)"
base ad:0x2820000
group.long 0x0++0x3
line.long 0x0 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register"
group.long 0x0++0x7
line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x4 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.."
bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x7
line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "CTS_IT," "0,1"
newline
bitfld.long 0x0 6. "RTS_IT," "0,1"
newline
bitfld.long 0x0 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x0 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x0 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x0 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
line.long 0x4 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i"
newline
bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level  TCR[3:0]  is reached  and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i"
newline
bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable"
newline
bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7. 1: Enables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7"
newline
hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options"
group.long 0x8++0x3
line.long 0x0 "MEM_FCR,Notes:"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000  RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?"
newline
bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000  TX_FIFO_TRIG is not considered. If SCR[6]=1  TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?"
newline
bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1"
newline
bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 0. "FIFO_EN," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3"
newline
hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,"
newline
bitfld.long 0x0 0. "IT_PENDING," "0,1"
group.long 0xC++0x7
line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "DIV_EN," "0,1"
newline
bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1"
newline
bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0  the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1  the parity bit is forced to 0 in the transmitted and received.." "0,1"
newline
bitfld.long 0x0 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x0 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1"
newline
bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3"
line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x4 7. "RESERVED," "0,1"
newline
bitfld.long 0x4 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x4 5. "XON_EN," "0,1"
newline
bitfld.long 0x4 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x4 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x4 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1"
newline
bitfld.long 0x4 0. "DTR," "0,1"
group.long 0x10++0x3
line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes."
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_CIR,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "RESERVED," "0,1"
newline
bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_IRDA,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x0 3. "ABORT," "0,1"
newline
bitfld.long 0x0 2. "CRC," "0,1"
newline
bitfld.long 0x0 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_UART,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x0 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x0 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x0 4. "RX_BI," "0,1"
newline
bitfld.long 0x0 3. "RX_FE," "0,1"
newline
bitfld.long 0x0 2. "RX_PE," "0,1"
newline
bitfld.long 0x0 1. "RX_OE," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x3
line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes."
rgroup.long 0x18++0x3
line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1"
newline
bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1"
newline
bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode  it is equivalent to MCR[0]" "0,1"
newline
bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1"
newline
bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1"
newline
bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1"
newline
bitfld.long 0x0 1. "DSR_STS," "0,1"
newline
bitfld.long 0x0 0. "CTS_STS," "0,1"
group.long 0x18++0x3
line.long 0x0 "MEM_TCR,Transmission Control Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)"
newline
hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)"
group.long 0x18++0x7
line.long 0x0 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes."
line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x3
line.long 0x0 "MEM_TLR,Trigger Level Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level"
group.long 0x1C++0xB
line.long 0x0 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes."
line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1"
newline
bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1"
newline
bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1"
newline
bitfld.long 0x4 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1"
newline
bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3"
newline
bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1"
newline
bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3"
newline
rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs  the meaning of the interrupt is :" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "MEM_SFLSR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0 0. "RESERVED0," "0,1"
group.long 0x28++0x3
line.long 0x0 "MEM_TXFLL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x7
line.long 0x0 "MEM_TXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length"
line.long 0x4 "MEM_RXFLL,IrDA modes only."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x0 "MEM_SFREGL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length"
group.long 0x34++0x3
line.long 0x0 "MEM_RXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception"
rgroup.long 0x34++0x3
line.long 0x0 "MEM_SFREGH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length"
group.long 0x38++0x3
line.long 0x0 "MEM_BLR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1"
newline
bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1"
newline
hexmask.long.byte 0x0 0.--5. 1. "RESERVED,"
rgroup.long 0x38++0x3
line.long 0x0 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?"
newline
bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified"
newline
hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.."
group.long 0x3C++0xF
line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1"
newline
bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1"
newline
bitfld.long 0x0 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1  garbage data is sent over TX line." "0,1"
newline
bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission  the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1"
newline
bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1"
newline
bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1  UART IrDA will start a new transfer.." "0,1"
newline
bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1"
line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 5. "DSR_IT," "0,1"
newline
bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1"
line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x8 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1"
line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs  the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.."
rgroup.long 0x50++0x3
line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned"
bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module"
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module."
group.long 0x54++0x3
line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1"
newline
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "MEM_SYSS,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1"
group.long 0x5C++0x7
line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.."
rgroup.long 0x64++0x7
line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,"
line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,"
group.long 0x6C++0xB
line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x0 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1"
newline
bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1"
line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x4 2.--7. 1. "RESERVED,"
newline
bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6."
rgroup.long 0x78++0x7
line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused"
hexmask.long 0x0 0.--31. 1. "RESERVED,"
line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused"
hexmask.long 0x4 0.--31. 1. "RESERVED,"
group.long 0x80++0x23
line.long 0x0 "MEM_MDR3,Mode definition register 3."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0  RX: RTS=1. 1 => TX: RTS=1  RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1"
newline
bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
line.long 0x8 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x8 7. "RESERVED," "0,1"
newline
bitfld.long 0x8 6. "MODE9,9-bit character length. When '1'  overrides character length setting in LCR" "0,1"
newline
bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values  as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "MODE,New modes [when set  overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0xC "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode  when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set  signaling an address" "0,1"
line.long 0x14 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes  useful when comunicating with slower devices"
line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Lower byte of the 16 bit value]"
line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Higher byte of the 16 bit value]"
line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned  the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving  even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character  if the receiver did not acknowledge. If not acknowledged after the max value is reached  the USART transmitter will set parity error  stop and not continue until it is cleared." "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x0 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0xF
line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x4 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x8 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree "UART3 (UART3)"
base ad:0x2830000
group.long 0x0++0x3
line.long 0x0 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register"
group.long 0x0++0x7
line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x4 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.."
bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x7
line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "CTS_IT," "0,1"
newline
bitfld.long 0x0 6. "RTS_IT," "0,1"
newline
bitfld.long 0x0 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x0 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x0 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x0 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
line.long 0x4 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i"
newline
bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level  TCR[3:0]  is reached  and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i"
newline
bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable"
newline
bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7. 1: Enables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7"
newline
hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options"
group.long 0x8++0x3
line.long 0x0 "MEM_FCR,Notes:"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000  RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?"
newline
bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000  TX_FIFO_TRIG is not considered. If SCR[6]=1  TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?"
newline
bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1"
newline
bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 0. "FIFO_EN," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3"
newline
hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,"
newline
bitfld.long 0x0 0. "IT_PENDING," "0,1"
group.long 0xC++0x7
line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "DIV_EN," "0,1"
newline
bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1"
newline
bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0  the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1  the parity bit is forced to 0 in the transmitted and received.." "0,1"
newline
bitfld.long 0x0 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x0 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1"
newline
bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3"
line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x4 7. "RESERVED," "0,1"
newline
bitfld.long 0x4 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x4 5. "XON_EN," "0,1"
newline
bitfld.long 0x4 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x4 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x4 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1"
newline
bitfld.long 0x4 0. "DTR," "0,1"
group.long 0x10++0x3
line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes."
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_CIR,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "RESERVED," "0,1"
newline
bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_IRDA,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x0 3. "ABORT," "0,1"
newline
bitfld.long 0x0 2. "CRC," "0,1"
newline
bitfld.long 0x0 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_UART,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x0 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x0 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x0 4. "RX_BI," "0,1"
newline
bitfld.long 0x0 3. "RX_FE," "0,1"
newline
bitfld.long 0x0 2. "RX_PE," "0,1"
newline
bitfld.long 0x0 1. "RX_OE," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x3
line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes."
rgroup.long 0x18++0x3
line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1"
newline
bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1"
newline
bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode  it is equivalent to MCR[0]" "0,1"
newline
bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1"
newline
bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1"
newline
bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1"
newline
bitfld.long 0x0 1. "DSR_STS," "0,1"
newline
bitfld.long 0x0 0. "CTS_STS," "0,1"
group.long 0x18++0x3
line.long 0x0 "MEM_TCR,Transmission Control Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)"
newline
hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)"
group.long 0x18++0x7
line.long 0x0 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes."
line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x3
line.long 0x0 "MEM_TLR,Trigger Level Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level"
group.long 0x1C++0xB
line.long 0x0 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes."
line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1"
newline
bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1"
newline
bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1"
newline
bitfld.long 0x4 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1"
newline
bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3"
newline
bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1"
newline
bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3"
newline
rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs  the meaning of the interrupt is :" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "MEM_SFLSR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0 0. "RESERVED0," "0,1"
group.long 0x28++0x3
line.long 0x0 "MEM_TXFLL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x7
line.long 0x0 "MEM_TXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length"
line.long 0x4 "MEM_RXFLL,IrDA modes only."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x0 "MEM_SFREGL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length"
group.long 0x34++0x3
line.long 0x0 "MEM_RXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception"
rgroup.long 0x34++0x3
line.long 0x0 "MEM_SFREGH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length"
group.long 0x38++0x3
line.long 0x0 "MEM_BLR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1"
newline
bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1"
newline
hexmask.long.byte 0x0 0.--5. 1. "RESERVED,"
rgroup.long 0x38++0x3
line.long 0x0 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?"
newline
bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified"
newline
hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.."
group.long 0x3C++0xF
line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1"
newline
bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1"
newline
bitfld.long 0x0 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1  garbage data is sent over TX line." "0,1"
newline
bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission  the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1"
newline
bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1"
newline
bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1  UART IrDA will start a new transfer.." "0,1"
newline
bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1"
line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 5. "DSR_IT," "0,1"
newline
bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1"
line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x8 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1"
line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs  the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.."
rgroup.long 0x50++0x3
line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned"
bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module"
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module."
group.long 0x54++0x3
line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1"
newline
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "MEM_SYSS,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1"
group.long 0x5C++0x7
line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.."
rgroup.long 0x64++0x7
line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,"
line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,"
group.long 0x6C++0xB
line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x0 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1"
newline
bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1"
line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x4 2.--7. 1. "RESERVED,"
newline
bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6."
rgroup.long 0x78++0x7
line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused"
hexmask.long 0x0 0.--31. 1. "RESERVED,"
line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused"
hexmask.long 0x4 0.--31. 1. "RESERVED,"
group.long 0x80++0x23
line.long 0x0 "MEM_MDR3,Mode definition register 3."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0  RX: RTS=1. 1 => TX: RTS=1  RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1"
newline
bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
line.long 0x8 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x8 7. "RESERVED," "0,1"
newline
bitfld.long 0x8 6. "MODE9,9-bit character length. When '1'  overrides character length setting in LCR" "0,1"
newline
bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values  as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "MODE,New modes [when set  overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0xC "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode  when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set  signaling an address" "0,1"
line.long 0x14 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes  useful when comunicating with slower devices"
line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Lower byte of the 16 bit value]"
line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Higher byte of the 16 bit value]"
line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned  the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving  even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character  if the receiver did not acknowledge. If not acknowledged after the max value is reached  the USART transmitter will set parity error  stop and not continue until it is cleared." "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x0 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0xF
line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x4 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x8 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree "UART4 (UART4)"
base ad:0x2840000
group.long 0x0++0x3
line.long 0x0 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register"
group.long 0x0++0x7
line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x4 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.."
bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x7
line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "CTS_IT," "0,1"
newline
bitfld.long 0x0 6. "RTS_IT," "0,1"
newline
bitfld.long 0x0 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x0 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x0 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x0 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
line.long 0x4 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i"
newline
bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level  TCR[3:0]  is reached  and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i"
newline
bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable"
newline
bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7. 1: Enables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7"
newline
hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options"
group.long 0x8++0x3
line.long 0x0 "MEM_FCR,Notes:"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000  RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?"
newline
bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000  TX_FIFO_TRIG is not considered. If SCR[6]=1  TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?"
newline
bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1"
newline
bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 0. "FIFO_EN," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3"
newline
hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,"
newline
bitfld.long 0x0 0. "IT_PENDING," "0,1"
group.long 0xC++0x7
line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "DIV_EN," "0,1"
newline
bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1"
newline
bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0  the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1  the parity bit is forced to 0 in the transmitted and received.." "0,1"
newline
bitfld.long 0x0 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x0 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1"
newline
bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3"
line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x4 7. "RESERVED," "0,1"
newline
bitfld.long 0x4 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x4 5. "XON_EN," "0,1"
newline
bitfld.long 0x4 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x4 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x4 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1"
newline
bitfld.long 0x4 0. "DTR," "0,1"
group.long 0x10++0x3
line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes."
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_CIR,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "RESERVED," "0,1"
newline
bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_IRDA,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x0 3. "ABORT," "0,1"
newline
bitfld.long 0x0 2. "CRC," "0,1"
newline
bitfld.long 0x0 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_UART,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x0 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x0 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x0 4. "RX_BI," "0,1"
newline
bitfld.long 0x0 3. "RX_FE," "0,1"
newline
bitfld.long 0x0 2. "RX_PE," "0,1"
newline
bitfld.long 0x0 1. "RX_OE," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x3
line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes."
rgroup.long 0x18++0x3
line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1"
newline
bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1"
newline
bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode  it is equivalent to MCR[0]" "0,1"
newline
bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1"
newline
bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1"
newline
bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1"
newline
bitfld.long 0x0 1. "DSR_STS," "0,1"
newline
bitfld.long 0x0 0. "CTS_STS," "0,1"
group.long 0x18++0x3
line.long 0x0 "MEM_TCR,Transmission Control Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)"
newline
hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)"
group.long 0x18++0x7
line.long 0x0 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes."
line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x3
line.long 0x0 "MEM_TLR,Trigger Level Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level"
group.long 0x1C++0xB
line.long 0x0 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes."
line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1"
newline
bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1"
newline
bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1"
newline
bitfld.long 0x4 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1"
newline
bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3"
newline
bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1"
newline
bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3"
newline
rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs  the meaning of the interrupt is :" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "MEM_SFLSR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0 0. "RESERVED0," "0,1"
group.long 0x28++0x3
line.long 0x0 "MEM_TXFLL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x7
line.long 0x0 "MEM_TXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length"
line.long 0x4 "MEM_RXFLL,IrDA modes only."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x0 "MEM_SFREGL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length"
group.long 0x34++0x3
line.long 0x0 "MEM_RXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception"
rgroup.long 0x34++0x3
line.long 0x0 "MEM_SFREGH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length"
group.long 0x38++0x3
line.long 0x0 "MEM_BLR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1"
newline
bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1"
newline
hexmask.long.byte 0x0 0.--5. 1. "RESERVED,"
rgroup.long 0x38++0x3
line.long 0x0 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?"
newline
bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified"
newline
hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.."
group.long 0x3C++0xF
line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1"
newline
bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1"
newline
bitfld.long 0x0 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1  garbage data is sent over TX line." "0,1"
newline
bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission  the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1"
newline
bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1"
newline
bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1  UART IrDA will start a new transfer.." "0,1"
newline
bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1"
line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 5. "DSR_IT," "0,1"
newline
bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1"
line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x8 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1"
line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs  the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.."
rgroup.long 0x50++0x3
line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned"
bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module"
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module."
group.long 0x54++0x3
line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1"
newline
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "MEM_SYSS,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1"
group.long 0x5C++0x7
line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.."
rgroup.long 0x64++0x7
line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,"
line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,"
group.long 0x6C++0xB
line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x0 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1"
newline
bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1"
line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x4 2.--7. 1. "RESERVED,"
newline
bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6."
rgroup.long 0x78++0x7
line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused"
hexmask.long 0x0 0.--31. 1. "RESERVED,"
line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused"
hexmask.long 0x4 0.--31. 1. "RESERVED,"
group.long 0x80++0x23
line.long 0x0 "MEM_MDR3,Mode definition register 3."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0  RX: RTS=1. 1 => TX: RTS=1  RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1"
newline
bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
line.long 0x8 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x8 7. "RESERVED," "0,1"
newline
bitfld.long 0x8 6. "MODE9,9-bit character length. When '1'  overrides character length setting in LCR" "0,1"
newline
bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values  as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "MODE,New modes [when set  overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0xC "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode  when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set  signaling an address" "0,1"
line.long 0x14 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes  useful when comunicating with slower devices"
line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Lower byte of the 16 bit value]"
line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Higher byte of the 16 bit value]"
line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned  the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving  even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character  if the receiver did not acknowledge. If not acknowledged after the max value is reached  the USART transmitter will set parity error  stop and not continue until it is cleared." "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x0 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0xF
line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x4 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x8 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree "UART5 (UART5)"
base ad:0x2850000
group.long 0x0++0x3
line.long 0x0 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register"
group.long 0x0++0x7
line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x4 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.."
bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x7
line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "CTS_IT," "0,1"
newline
bitfld.long 0x0 6. "RTS_IT," "0,1"
newline
bitfld.long 0x0 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x0 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x0 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x0 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
line.long 0x4 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i"
newline
bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level  TCR[3:0]  is reached  and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i"
newline
bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable"
newline
bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7. 1: Enables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7"
newline
hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options"
group.long 0x8++0x3
line.long 0x0 "MEM_FCR,Notes:"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000  RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?"
newline
bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000  TX_FIFO_TRIG is not considered. If SCR[6]=1  TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?"
newline
bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1"
newline
bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 0. "FIFO_EN," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3"
newline
hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,"
newline
bitfld.long 0x0 0. "IT_PENDING," "0,1"
group.long 0xC++0x7
line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "DIV_EN," "0,1"
newline
bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1"
newline
bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0  the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1  the parity bit is forced to 0 in the transmitted and received.." "0,1"
newline
bitfld.long 0x0 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x0 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1"
newline
bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3"
line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x4 7. "RESERVED," "0,1"
newline
bitfld.long 0x4 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x4 5. "XON_EN," "0,1"
newline
bitfld.long 0x4 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x4 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x4 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1"
newline
bitfld.long 0x4 0. "DTR," "0,1"
group.long 0x10++0x3
line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes."
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_CIR,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "RESERVED," "0,1"
newline
bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_IRDA,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x0 3. "ABORT," "0,1"
newline
bitfld.long 0x0 2. "CRC," "0,1"
newline
bitfld.long 0x0 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_UART,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x0 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x0 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x0 4. "RX_BI," "0,1"
newline
bitfld.long 0x0 3. "RX_FE," "0,1"
newline
bitfld.long 0x0 2. "RX_PE," "0,1"
newline
bitfld.long 0x0 1. "RX_OE," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x3
line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes."
rgroup.long 0x18++0x3
line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1"
newline
bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1"
newline
bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode  it is equivalent to MCR[0]" "0,1"
newline
bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1"
newline
bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1"
newline
bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1"
newline
bitfld.long 0x0 1. "DSR_STS," "0,1"
newline
bitfld.long 0x0 0. "CTS_STS," "0,1"
group.long 0x18++0x3
line.long 0x0 "MEM_TCR,Transmission Control Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)"
newline
hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)"
group.long 0x18++0x7
line.long 0x0 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes."
line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x3
line.long 0x0 "MEM_TLR,Trigger Level Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level"
group.long 0x1C++0xB
line.long 0x0 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes."
line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1"
newline
bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1"
newline
bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1"
newline
bitfld.long 0x4 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1"
newline
bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3"
newline
bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1"
newline
bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3"
newline
rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs  the meaning of the interrupt is :" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "MEM_SFLSR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0 0. "RESERVED0," "0,1"
group.long 0x28++0x3
line.long 0x0 "MEM_TXFLL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x7
line.long 0x0 "MEM_TXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length"
line.long 0x4 "MEM_RXFLL,IrDA modes only."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x0 "MEM_SFREGL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length"
group.long 0x34++0x3
line.long 0x0 "MEM_RXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception"
rgroup.long 0x34++0x3
line.long 0x0 "MEM_SFREGH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length"
group.long 0x38++0x3
line.long 0x0 "MEM_BLR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1"
newline
bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1"
newline
hexmask.long.byte 0x0 0.--5. 1. "RESERVED,"
rgroup.long 0x38++0x3
line.long 0x0 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?"
newline
bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified"
newline
hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.."
group.long 0x3C++0xF
line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1"
newline
bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1"
newline
bitfld.long 0x0 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1  garbage data is sent over TX line." "0,1"
newline
bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission  the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1"
newline
bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1"
newline
bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1  UART IrDA will start a new transfer.." "0,1"
newline
bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1"
line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 5. "DSR_IT," "0,1"
newline
bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1"
line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x8 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1"
line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs  the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.."
rgroup.long 0x50++0x3
line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned"
bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module"
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module."
group.long 0x54++0x3
line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1"
newline
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "MEM_SYSS,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1"
group.long 0x5C++0x7
line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.."
rgroup.long 0x64++0x7
line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,"
line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,"
group.long 0x6C++0xB
line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x0 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1"
newline
bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1"
line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x4 2.--7. 1. "RESERVED,"
newline
bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6."
rgroup.long 0x78++0x7
line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused"
hexmask.long 0x0 0.--31. 1. "RESERVED,"
line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused"
hexmask.long 0x4 0.--31. 1. "RESERVED,"
group.long 0x80++0x23
line.long 0x0 "MEM_MDR3,Mode definition register 3."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0  RX: RTS=1. 1 => TX: RTS=1  RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1"
newline
bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
line.long 0x8 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x8 7. "RESERVED," "0,1"
newline
bitfld.long 0x8 6. "MODE9,9-bit character length. When '1'  overrides character length setting in LCR" "0,1"
newline
bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values  as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "MODE,New modes [when set  overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0xC "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode  when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set  signaling an address" "0,1"
line.long 0x14 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes  useful when comunicating with slower devices"
line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Lower byte of the 16 bit value]"
line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Higher byte of the 16 bit value]"
line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned  the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving  even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character  if the receiver did not acknowledge. If not acknowledged after the max value is reached  the USART transmitter will set parity error  stop and not continue until it is cleared." "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x0 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0xF
line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x4 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x8 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree "UART6 (UART6)"
base ad:0x2860000
group.long 0x0++0x3
line.long 0x0 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register"
group.long 0x0++0x7
line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x4 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.."
bitfld.long 0x0 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x3
line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x0 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
group.long 0x4++0x7
line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "CTS_IT," "0,1"
newline
bitfld.long 0x0 6. "RTS_IT," "0,1"
newline
bitfld.long 0x0 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x0 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x0 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x0 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
line.long 0x4 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i"
newline
bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level  TCR[3:0]  is reached  and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i"
newline
bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable"
newline
bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7. 1: Enables writing to IER bits 4-7  FCR bits 4-5  and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7"
newline
hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options"
group.long 0x8++0x3
line.long 0x0 "MEM_FCR,Notes:"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000  RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?"
newline
bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000  TX_FIFO_TRIG is not considered. If SCR[6]=1  TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?"
newline
bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1"
newline
bitfld.long 0x0 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x0 0. "FIFO_EN," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
bitfld.long 0x0 7. "EOF_IT," "0,1"
newline
bitfld.long 0x0 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x0 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x0 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x0 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x0 1. "THR_IT," "0,1"
newline
bitfld.long 0x0 0. "RHR_IT," "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3"
newline
hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,"
newline
bitfld.long 0x0 0. "IT_PENDING," "0,1"
group.long 0xC++0x7
line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "DIV_EN," "0,1"
newline
bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1"
newline
bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0  the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1  the parity bit is forced to 0 in the transmitted and received.." "0,1"
newline
bitfld.long 0x0 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x0 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1"
newline
bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3"
line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x4 7. "RESERVED," "0,1"
newline
bitfld.long 0x4 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x4 5. "XON_EN," "0,1"
newline
bitfld.long 0x4 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x4 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x4 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1"
newline
bitfld.long 0x4 0. "DTR," "0,1"
group.long 0x10++0x3
line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes."
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_CIR,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "RESERVED," "0,1"
newline
bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_IRDA,"
bitfld.long 0x0 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x0 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x0 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x0 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x0 3. "ABORT," "0,1"
newline
bitfld.long 0x0 2. "CRC," "0,1"
newline
bitfld.long 0x0 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "MEM_LSR_UART,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x0 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x0 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x0 4. "RX_BI," "0,1"
newline
bitfld.long 0x0 3. "RX_FE," "0,1"
newline
bitfld.long 0x0 2. "RX_PE," "0,1"
newline
bitfld.long 0x0 1. "RX_OE," "0,1"
newline
bitfld.long 0x0 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x3
line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes."
rgroup.long 0x18++0x3
line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1"
newline
bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1"
newline
bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode  it is equivalent to MCR[0]" "0,1"
newline
bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1"
newline
bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1"
newline
bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1"
newline
bitfld.long 0x0 1. "DSR_STS," "0,1"
newline
bitfld.long 0x0 0. "CTS_STS," "0,1"
group.long 0x18++0x3
line.long 0x0 "MEM_TCR,Transmission Control Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)"
newline
hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)"
group.long 0x18++0x7
line.long 0x0 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes."
line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x3
line.long 0x0 "MEM_TLR,Trigger Level Register"
hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level"
group.long 0x1C++0xB
line.long 0x0 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes."
line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1"
newline
bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1"
newline
bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1"
newline
bitfld.long 0x4 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x4 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1"
newline
bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3"
newline
bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1"
newline
bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3"
newline
rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs  the meaning of the interrupt is :" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "MEM_SFLSR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0 0. "RESERVED0," "0,1"
group.long 0x28++0x3
line.long 0x0 "MEM_TXFLL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x7
line.long 0x0 "MEM_TXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length"
line.long 0x4 "MEM_RXFLL,IrDA modes only."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x0 "MEM_SFREGL,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length"
group.long 0x34++0x3
line.long 0x0 "MEM_RXFLH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception"
rgroup.long 0x34++0x3
line.long 0x0 "MEM_SFREGH,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length"
group.long 0x38++0x3
line.long 0x0 "MEM_BLR,IrDA modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1"
newline
bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1"
newline
hexmask.long.byte 0x0 0.--5. 1. "RESERVED,"
rgroup.long 0x38++0x3
line.long 0x0 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?"
newline
bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified"
newline
hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.."
group.long 0x3C++0xF
line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1"
newline
bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1"
newline
bitfld.long 0x0 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1  garbage data is sent over TX line." "0,1"
newline
bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission  the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1"
newline
bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1"
newline
bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1  UART IrDA will start a new transfer.." "0,1"
newline
bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1"
line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x4 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x4 5. "DSR_IT," "0,1"
newline
bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x4 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x4 0. "DMA_MODE_CTL," "0,1"
line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0."
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x8 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x8 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x8 0. "TX_FIFO_FULL," "0,1"
line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only."
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs  the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.."
rgroup.long 0x50++0x3
line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned"
bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module"
newline
hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module"
newline
bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module."
group.long 0x54++0x3
line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1"
newline
bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
rgroup.long 0x58++0x3
line.long 0x0 "MEM_SYSS,"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x0 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1"
group.long 0x5C++0x7
line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.."
rgroup.long 0x64++0x7
line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,"
line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,"
group.long 0x6C++0xB
line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x0 3.--7. 1. "RESERVED,"
newline
bitfld.long 0x0 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1"
newline
bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1"
line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts."
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,"
newline
hexmask.long.byte 0x4 2.--7. 1. "RESERVED,"
newline
bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6."
rgroup.long 0x78++0x7
line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused"
hexmask.long 0x0 0.--31. 1. "RESERVED,"
line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused"
hexmask.long 0x4 0.--31. 1. "RESERVED,"
group.long 0x80++0x23
line.long 0x0 "MEM_MDR3,Mode definition register 3."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0  RX: RTS=1. 1 => TX: RTS=1  RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1"
newline
bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level."
line.long 0x8 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x8 7. "RESERVED," "0,1"
newline
bitfld.long 0x8 6. "MODE9,9-bit character length. When '1'  overrides character length setting in LCR" "0,1"
newline
bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values  as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "MODE,New modes [when set  overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0xC "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode  when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set  signaling an address" "0,1"
line.long 0x14 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes  useful when comunicating with slower devices"
line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Lower byte of the 16 bit value]"
line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks  to override the internal value  when different from 0. [Higher byte of the 16 bit value]"
line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned  the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving  even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1"
newline
rbitfld.long 0x20 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character  if the receiver did not acknowledge. If not acknowledged after the max value is reached  the USART transmitter will set parity error  stop and not continue until it is cleared." "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x0 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0xF
line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x4 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x8 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree.end
tree "VTM0"
base ad:0x0
tree "VTM0_ECCAGGR_CFG (VTM0_ECCAGGR_CFG)"
base ad:0xB02000
rgroup.long 0x0++0x3
line.long 0x0 "__ECCAGGR_CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
newline
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
newline
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
group.long 0x8++0x3
line.long 0x0 "__ECCAGGR_CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete  write of any value will clear this bit." "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x0 "__ECCAGGR_CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x10++0x3
line.long 0x0 "__ECCAGGR_CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
group.long 0x3C++0x7
line.long 0x0 "__ECCAGGR_CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "__ECCAGGR_CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x4 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
group.long 0x80++0x3
line.long 0x0 "__ECCAGGR_CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
group.long 0xC0++0x3
line.long 0x0 "__ECCAGGR_CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
group.long 0x13C++0x7
line.long 0x0 "__ECCAGGR_CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
line.long 0x4 "__ECCAGGR_CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x4 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x4 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
group.long 0x180++0x3
line.long 0x0 "__ECCAGGR_CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x0 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x0 "__ECCAGGR_CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x0 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x0 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
group.long 0x200++0xF
line.long 0x0 "__ECCAGGR_CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x4 "__ECCAGGR_CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x8 "__ECCAGGR_CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0xC "__ECCAGGR_CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
base ad:0x0
tree "VTM0_MMR_VBUSP"
tree "VTM0_MMR_VBUSP_CFG1 (VTM0_MMR_VBUSP_CFG1)"
base ad:0xB00000
rgroup.long 0x0++0x7
line.long 0x0 "MMR__VBUSP__CFG1_VTM_PID,VTM Peripheral Identification Register"
bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "BU,Business unit - Processors" "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "FUNC,Module functional identifier - CTRL MMR"
newline
hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL revision number - actual value determined by RTL"
newline
bitfld.long 0x0 8.--10. "X_MAJOR,Major revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number - actual value determined by RTL" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision number - actual value determined by RTL"
line.long 0x4 "MMR__VBUSP__CFG1_VTM_DEVINFO_PWR0,Device specific voltage domain and temp sensor information register."
hexmask.long.byte 0x4 16.--19. 1. "VTM_VD_MAP,Core voltage domain  cVD  global mapping 4-bit code  in the context of this SOC. It shows in which cVD this VTM is instantiated/placed. This field indicates in which core voltage domain  cVD  has been physically placed this VTM. Valid values:.."
newline
bitfld.long 0x4 12. "VD_RTC,RTC voltage domain presence. 0: There is NO VD_RTC in this SOC. 1: There is a VD_RTC in this SOC. Reset value is a VTM tieoff  d_vd_rtc." "0: There is NO VD_RTC in this SOC,1: There is a VD_RTC in this SOC"
newline
hexmask.long.byte 0x4 4.--7. 1. "TMPSENS_CT,Number of temperature sensors associated with this VTM. Valid values are 4'h0 - 4'h8. 0x0: NO temp-sensor associated to this VTM. 0x8: 8 temp-sensors associated to this VTM. 0x9 to 0xF: invalid values. Reset value is a VTM tieoff .."
newline
hexmask.long.byte 0x4 0.--3. 1. "CVD_CT,Number of core voltage domains in device. VD0 is always allocated to VD_RTC  if it exists  and VD1 always to VD_WKUP. The maximum number of cVDs in an SOC is 15  0xF. Reset value is a VTM tieoff  d_device_cvd_ct."
group.long 0x204++0x7
line.long 0x0 "MMR__VBUSP__CFG1_VTM_GT_TH1_INT_RAW_STAT_SET,Interrupt RAW event status and set MMR for interrupt GT_TH1 for each voltage domain. NOTE: This MMR and the companion MMR. VTM_GT_TH1_INT_EN_STAT_CLR are fully linked for write operation. but partially linked.."
hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt pending bit set for gt_th1_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the interrupt flag to be set. Used to manually force/drive an interrupt pending event. Reads return the pending stats regardless of the.."
line.long 0x4 "MMR__VBUSP__CFG1_VTM_GT_TH1_INT_EN_STAT_CLR,Enabled interrupt event status and clear MMR for interrupt GT_TH1 per voltage domain. NOTE: This MMR and the companion MMR. VTM_GT_TH1_INT_RAW_STAT_SET are fully linked for write operation. but partially linked.."
hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt masked pending bit for gt_th1_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the pending bit to be cleared. Reads return the enabled pending status that includes the corresponding enable setting."
group.long 0x214++0x7
line.long 0x0 "MMR__VBUSP__CFG1_VTM_GT_TH1_INT_EN_SET,Enable set MMR for interrupt GT_TH1 for each voltage domain. NOTE: This MMR and the companion MMR. VTM_GT_TH1_INT_EN_CLR are linked. which means that they are in fact a single common MMR. with 2 different write.."
hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th1_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be set to 1. Reads return the enable settings."
line.long 0x4 "MMR__VBUSP__CFG1_VTM_GT_TH1_INT_EN_CLR,Enable clear MMR for interrupt GT_TH1 for each voltage domain. NOTE: This MMR and the companion MMR. VTM_GT_TH1_INT_EN_SET are linked. which means that they are in fact a single common MMR. with 2 different write.."
hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th1_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be cleared. Reads return the enable settings."
group.long 0x224++0x7
line.long 0x0 "MMR__VBUSP__CFG1_VTM_GT_TH2_INT_RAW_STAT_SET,Interrupt RAW event status and set MMR for interrupt GT_TH2 for each voltage domain. NOTE: This MMR and the companion MMR. VTM_GT_TH2_INT_EN_STAT_CLR are fully linked for write operation. but partially linked.."
hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt pending bit set for gt_th2_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the interrupt flag to be set. Used to manually force/drive an interrupt pending event. Reads return the pending status regardless of the enable.."
line.long 0x4 "MMR__VBUSP__CFG1_VTM_GT_TH2_INT_EN_STAT_CLR,Enabled interrupt event status and clear MMR for interrupt GT_TH2 per voltage domain. NOTE: This MMR and the companion MMR. VTM_GT_TH2_INT_RAW_STAT_SET are fully linked for write operation. but partially linked.."
hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt enabled pending bit for gt_th2_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the pending bit to be cleared. Reads return the enabled pending status including the corresponding enable setting."
group.long 0x234++0x7
line.long 0x0 "MMR__VBUSP__CFG1_VTM_GT_TH2_INT_EN_SET,Enable set MMR for interrupt GT_TH2 for each voltage domain. NOTE: This MMR and the companion MMR. VTM_GT_TH2_INT_EN_CLR are linked. which means that they are in fact a single common MMR. with 2 different write.."
hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th2_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be set to 1. Reads return the enable settings."
line.long 0x4 "MMR__VBUSP__CFG1_VTM_GT_TH2_INT_EN_CLR,Enable clear MMR for interrupt GT_TH2 for each voltage domain. NOTE: This MMR and the companion MMR. VTM_GT_TH2_INT_EN_SET are linked. which means that they are in fact a single common MMR. with 2 different write.."
hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th2_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be cleared. Reads return the enable settings."
group.long 0x244++0x7
line.long 0x0 "MMR__VBUSP__CFG1_VTM_LT_TH0_INT_RAW_STAT_SET,Interrupt RAW event status and set MMR for interrupt LT_TH0 for each voltage domain. NOTE: This MMR and the companion MMR. VTM_LT_TH0_INT_EN_STAT_CLR are fully linked for write operation. but partially linked.."
hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt pending bit set for lt_th0_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the interrupt flag to be set. Used to manually force/drive an interrupt pending event. Reads return the raw pending status regardless of the.."
line.long 0x4 "MMR__VBUSP__CFG1_VTM_LT_TH0_INT_EN_STAT_CLR,Enabled interrupt event status and clear MMR for interrupt LT_TH0 per voltage domain. NOTE: This MMR and the companion MMR. VTM_LT_TH0_INT_RAW_STAT_SET are fully linked for write operation. but partially linked.."
hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt enabled pending status bit for lt_th0_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the pending bit to be cleared. Reads return the enabled pending status that factors in the corresponding enable along with the pending.."
group.long 0x254++0x7
line.long 0x0 "MMR__VBUSP__CFG1_VTM_LT_TH0_INT_EN_SET,Enable set MMR for interrupt LT_TH0 for each voltage domain. NOTE: This MMR and the companion MMR. VTM_LT_TH0_INT_EN_CLR are linked. which means that they are in fact a single common MMR. with 2 different write.."
hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt enable bit for lt_th0_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be set to 1. Reads return the enable settings."
line.long 0x4 "MMR__VBUSP__CFG1_VTM_LT_TH0_INT_EN_CLR,Enable clear MMR for interrupt LT_TH0 for each voltage domain. NOTE: This MMR and the companion MMR. VTM_LT_TH0_INT_EN_SET are linked. which means that they are in fact a single common MMR. with 2 different write.."
hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt enable bit for lt_th0_int from VD[7:0]. Write-operation: 0: Nothing happens. 1: Causes the bit to be cleared. Reads return the enable settings."
group.long 0x100++0x7
line.long 0x0 "MMR__VBUSP__CFG1_DEVINFO,Voltage domain a information register. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary."
bitfld.long 0x0 12. "AVS0_SUP,Indicates VD0 AVS class0 support. Indicates if the cVD associated with this VTM's VD MMR supports AVS-Class0: 0: No AVS-Class0. 1: Supports-AVS-Class0. Reset value is from e-fuse at module reset  efuse_vd[a]_avs_sup." "0: No AVS-Class0,1: Supports-AVS-Class0"
newline
hexmask.long.byte 0x0 8.--11. 1. "VD_MAP,Indicates the core voltage domain mapping of VTM VD. Device specific field. This field indicates to which SOC cVD is this VD of this VTM map to. Valid values: 0x0 to 0xE where: 0x0 = VD_RTC  not present is some SOCs  0x1 = VD_WKUP  0x2 = VD_MCU .."
line.long 0x4 "MMR__VBUSP__CFG1_OPPVID,Voltage domain a VID actual code used as reference by Firmware to set the various voltage domain supply voltages. Reset defaults are sourced from efuse for each OPP. The default reset values will not be necessarily overwritten."
hexmask.long.byte 0x4 24.--31. 1. "OPP_3,OPP 3 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific."
newline
hexmask.long.byte 0x4 16.--23. 1. "OPP_2,OPP 2 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific."
newline
hexmask.long.byte 0x4 8.--15. 1. "OPP_1,OPP 1 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific."
newline
hexmask.long.byte 0x4 0.--7. 1. "OPP_0,OPP 0 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific."
rgroup.long 0x108++0x3
line.long 0x0 "MMR__VBUSP__CFG1_EVT_STAT,Voltage domain a event and control status register."
bitfld.long 0x0 2. "LT_TH0_ALERT,This bit reflects the status of the TH0 undertemp alert resulting from the AND of all the similar alerts produced by the temp sensors selected by VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel." "0,1"
newline
bitfld.long 0x0 1. "GT_TH2_ALERT,This bit reflects the status of the merged temperature alert resulting from the combination of all the similar alerts produced by the temp-monitors selected as showed in field VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel. This field shows the actual.." "0,1"
newline
bitfld.long 0x0 0. "GT_TH1_ALERT,This bit reflects the status of the merged temperature alert resulting from the OR of all the similar alerts produced by the temp-monitors selected as showed in field VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel. This field shows the actual present.." "0,1"
group.long 0x10C++0x7
line.long 0x0 "MMR__VBUSP__CFG1_EVT_SEL_SET,Voltage domain a event select and control set register. NOTE: This MMR and the companion MMR VTM_VD[a]_EVT_SEL_CLR are linked. which means that they are in fact a single common MMR. with 2 different write.."
hexmask.long.byte 0x0 16.--23. 1. "TSENS_EVT_SEL,In this field we select which of the event contributions of the 8-maximum possible temp-monitors controlled by this VTM will contribute to generate the merged event/alerts of this VD. Any combination of them could be selected and varies.."
line.long 0x4 "MMR__VBUSP__CFG1_EVT_SEL_CLR,Voltage domain a event select and control clear register. NOTE: This MMR and the companion MMR VTM_VD[a]_EVT_SEL_SET are linked. which means that they are in fact a single common MMR. with 2 different write.."
hexmask.long.byte 0x4 16.--23. 1. "TSENS_EVT_SEL,In this field we select which of the event contributions of the 8-maximum possible temp-monitors controlled by this VTM will contribute to generate the merged event/alerts of this VD. Any combination of them could be selected and varies.."
group.long 0x300++0x3
line.long 0x0 "MMR__VBUSP__CFG1_CTRL,Temperature Sensor Band-gap control register for sensor a."
bitfld.long 0x0 10. "LT_TH0_EN,Enable under-threshold0 event. Temp event/level control: 0 = Don't generate output level. 1 = Enable generation of event/level high when temperature reading is < value set for threshold point 0. Reset value is POR only." "0: Don't generate output level,1: Enable generation of event/level high when.."
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bitfld.long 0x0 9. "GT_TH2_EN,Enable over-threshold2 event. Temp event/level control: 0 = Don't generate output level. 1 = Enable generation of event/level high when temperature reading is > value set for threshold point 2. Reset value is POR only." "0: Don't generate output level,1: Enable generation of event/level high when.."
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bitfld.long 0x0 8. "GT_TH1_EN,Enable over-threshold1 event. Temp event/level control: 0 = Don't generate output level. 1 = Enable generation of event/level high when temperature reading is > value set for threshold point 1. Reset value is POR only." "0: Don't generate output level,1: Enable generation of event/level high when.."
rgroup.long 0x308++0x3
line.long 0x0 "MMR__VBUSP__CFG1_STAT,Temperature Sensor Band-gap Status register for sensor a."
hexmask.long.byte 0x0 16.--19. 1. "VD_MAP,Indicates the core voltage domain placement of the temp sensor. Device specific field. This field indicates in which core voltage domain  cVD  has been physically placed the temp-monitor. Valid values: 0x0 to 0xE where: 0x0 = VD_RTC  not present.."
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bitfld.long 0x0 15. "MAXT_OUTRG_ALERT,This bit will be driven to a level 1 for a given temperature monitor if it has its corresponding bit maxt_outrg_en = 1  and the temperature reading is reporting to be outside the max temperature supported  temp > programmed value. The.." "0,1"
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bitfld.long 0x0 14. "LT_TH0_ALERT,This field reflects the status of the lt_th0_alert comparator result. The control MMR field lt_th0_en = 1 is required for this field to become 1. Reset value is at POR or clrz." "0,1"
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bitfld.long 0x0 13. "GT_TH2_ALERT,This field reflects the status of the gt_th2_alert comparator result. The control MMR field gt_th2_en = 1 is required for this field to become 1. Reset value is at POR or clrz." "0,1"
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bitfld.long 0x0 12. "GT_TH1_ALERT,This field reflects the status of the gt_th1_alert comparator result. The control MMR field gt_th1_en = 1 is required for this field to become 1. Reset value is at POR or clrz." "0,1"
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bitfld.long 0x0 11. "EOC_FC_UPDATE,First time end of conversion. This field is reset to 0 every time VTM.por_rst_n or VTM_TMPSENS[a]_CTRL.clrz are active  or when continuous mode is deasserted. This bit will be set to 1 after the first time after reset release that.." "0,1"
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bitfld.long 0x0 10. "DATA_VALID,Data_valid signal value from sensor: ADC End of Conversion. End of conversion indicated by 0 to 1 transition. When high data_out(9:0) out of the temp-monitor is valid. This field doesn't reflect the instantaneous output from the temp-monitor." "?,?"
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hexmask.long.word 0x0 0.--9. 1. "DATA_OUT,Data_out signal value from sensor: Temperature data from the ADC in monitor. Valid after VTM_TMPSENS[a]_STAT.eoc_fc_update = 1. This value will be latched in this VTM register every time monitor output data_valid transitions from 0 to 1. Reset.."
group.long 0x30C++0x7
line.long 0x0 "MMR__VBUSP__CFG1_TH,Temperature Sensor Band-gap Threshold register for sensor a."
hexmask.long.word 0x0 16.--25. 1. "TH1_VAL,Threshold point-1  thpt1  temp-value. Is a 10-bit temperature reference value. This is the 10-bit value that represents a high temperature point  as per sensor spec  with which to compare the present temperature reading  same 10-bit format. If.."
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hexmask.long.word 0x0 0.--9. 1. "TH0_VAL,Threshold point-0  thpt0  temp-value. Is a 10-bit temperature reference value. This is the 10-bit value that represents a high temperature point  as per sensor spec  with which to compare the present temperature reading  same 10-bit format. If.."
line.long 0x4 "MMR__VBUSP__CFG1_TH2,Temperature Sensor Band-gap Threshold register 2 for sensor a."
hexmask.long.word 0x4 0.--9. 1. "TH2_VAL,Threshold point-2  thpt2  temp-value. Is a 10-bit temperature reference value. This is the 10-bit value that represents a high temperature point  as per sensor spec  with which to compare the present temperature reading  same 10-bit format. If.."
tree.end
tree "VTM0_MMR_VBUSP_CFG2 (VTM0_MMR_VBUSP_CFG2)"
base ad:0xB01000
group.long 0x8++0xB
line.long 0x0 "MMR__VBUSP__CFG2_VTM_CLK_CTRL,VTM clock related control MMR. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary. The e-fuse.."
bitfld.long 0x0 31. "TSENS_CLK_SEL,Temperature sensor clock source selector. Device specific. 0 = fix_ref_clk as source. 1 = fix_ref2_clk as source. Reset value is at POR only." "0: fix_ref_clk as source,1: fix_ref2_clk as source"
hexmask.long.byte 0x0 0.--4. 1. "TSENS_CLK_DIV,Temperature sensor clock source divider selector. Device specific. Default set by e-fuse or tie-off. Divider uses select reference clock as source. 0 = 1x divide. 1 = 2x divide. ... 15 = 16x divide. ... 63 = 64x divide. Reset value is from.."
line.long 0x4 "MMR__VBUSP__CFG2_VTM_MISC_CTRL,VTM miscellaneous control bits."
bitfld.long 0x4 0. "ANY_MAXT_OUTRG_ALERT_EN,This bit when enabled will cause the VTM's output therm_maxtemp_outrange_alert to be driven high  if any of the sources for the maxt_outrg_alert  is set high. Whenever all the maxt_outrg_alert enabled sensor alerts  out of the 8.." "0,1"
line.long 0x8 "MMR__VBUSP__CFG2_VTM_MISC_CTRL2,VTM miscellaneous control bits."
hexmask.long.word 0x8 16.--25. 1. "MAXT_OUTRG_ALERT_THR0,This defines the global max temperature out of range safe sample value. If the alert is enabled globally and for the sensor and the sensor reads a value <= this value then the alert is cleared after being triggered. This safe.."
hexmask.long.word 0x8 0.--9. 1. "MAXT_OUTRG_ALERT_THR,This defines the global max temperature out of range sample value. If the alert is enabled globally and for the sensor and the sensor reads a value >= this value then the alert is triggered. Reset is at POR only."
group.long 0x20++0x3
line.long 0x0 "MMR__VBUSP__CFG2_VTM_SAMPLE_CTRL,VTM sample related control MMR. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary. The e-fuse.."
hexmask.long.word 0x0 0.--15. 1. "SAMPLE_PER_CNT,Temperature sensor sample period count selector. Device specific. Default set by e-fuse or tie-off. This defines the sample period or number of sensor clocks between consecutive samples of the sensor allowed  from the start of the previous.."
group.long 0x300++0x7
line.long 0x0 "MMR__VBUSP__CFG2_CTRL,Temperature Sensor Band-gap control register for sensor a."
bitfld.long 0x0 11. "MAXT_OUTRG_EN,Enable out-of-range event. This bit enables generation of the alert in case the given temperature sensors generates a temp code above a programmed max. 0 = Don't generate alert. 1 = Generate alert. Reset value is POR only." "0: Don't generate alert,1: Generate alert"
bitfld.long 0x0 6. "CLRZ,Temp-Monitor control: 0 = Reset all Temp-monitor digital outputs. 1 = Allow operation of sensor. Reset value is POR only." "0: Reset all Temp-monitor digital outputs,1: Allow operation of sensor"
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bitfld.long 0x0 5. "SOC,Temp-Monitor control: ADC Start of Conversion. A transition from 0 to 1 starts a new ADC conversion cycle. The bit with automatically clear when the conversion has completed. This mode is not valid when already in continuous mode. Reset value is POR.." "0,1"
bitfld.long 0x0 4. "CONT,Temp-Monitor control: ADC Continuous mode. Setting this mode enables the VTM to continuously monitor the sensor automatically. Each sample period the sensor will be accessed and the results captured. Reset value is POR only." "0,1"
line.long 0x4 "MMR__VBUSP__CFG2_TRIM,Temperature Sensor Band-gap trim values register for sensor a. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if.."
hexmask.long.byte 0x4 8.--13. 1. "TRIMO,Trim offset bits in the temp sensor. Reset value is from e-fuse at POR  efuse_tmpsens[a]_trimo."
hexmask.long.byte 0x4 0.--4. 1. "TRIMG,Trim gain bits in the temp sensor. Reset value is from e-fuse at POR  efuse_tmpsens[a]_trimg."
tree.end
tree.end
tree.end
endif
AUTOINDENT.OFF