; --------------------------------------------------------------------------------
; @Title: A31T21x On-Chip Peripherals
; @Props: Released
; @Author: KRZ
; @Changelog: 2023-07-28 KRZ
;             2023-11-07 KRZ
; @Manufacturer: ABOV - ABOV Semiconductor Co., Ltd.
; @Doc: Generated (TRACE32, build: 164352.), based on: A31T21x.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: A31T214CL2N, A31T214CLN, A31T214IU2N, A31T214IUN, A31T214RL2N, A31T214RLN,
;        A31T214SN2N, A31T214SNN, A31T216CL2N, A31T216CLN, A31T216RL2N, A31T216RLN,
;        A31T216SN2N, A31T216SNN
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pera31t21x.per 16938 2023-11-07 18:43:11Z kwisniewski $

AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2.  "                CLKSOURCE     ,Always reads as one" "No effect,Processor clock"
textline "                 "
bitfld.long 0x00 1.  " TICKINT      ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0.  "       ENABLE        ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2.  "                CLKSOURCE     ,Always reads as one" "External clock,Processor clock"
textline "                 "
bitfld.long 0x00 1.  " TICKINT      ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0.  "       ENABLE        ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Reads as one" "0,1"
bitfld.long 0x00 30. "                SKEW          ,Reads as zero" "0,1"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS        ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. "  SKEW          ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS        ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER  ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. "               VARIANT       ,Implementation defined variant number"
textline "                 "
hexmask.long.byte 0x00 4.--15. 1.  " PARTNO       ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. "               REVISION      ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET   ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. "      PENDSVSET     ,Set a pending PendSV interrupt" "No effect,Set pending"
textline "                 "
bitfld.long 0x00 27. " PENDSVCLR    ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. "    PENDSTSET     ,Set a pending SysTick" "No effect,Set pending"
textline "                 "
bitfld.long 0x00 25. " PENDSVCLR    ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. "    ISRPREEMPT    ,Pending exception service" "No service,Service"
textline "                 "
bitfld.long 0x00 22. " ISRPENDING   ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. "     VECTPENDING   ,Active exception number field"
textline "                 "
hexmask.long.byte 0x00 0.--5. 1.  " VECTACTIVET  ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF       ,Vector table address"
else
textline "                 "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY      ,Vector Key"
bitfld.long 0x00 15. "             ENDIANNESS    ,Data endianness bit" "Little-endian,Big-endian"
textline "                 "
bitfld.long 0x00 2. " SYSRESETREQ  ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. "        VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND    ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. "       SLEEPDEEP     ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline "                 "
bitfld.long 0x00 1. " SLEEPONEXIT  ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN     ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. "         UNALIGN_TRP   ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11       ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15       ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. "               PRI_14        ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline "                 "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION    ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "     SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "     SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "     SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "     SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "     SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "     SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "     SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "     SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "     SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "     SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "     SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "     SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "     SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "     SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "     SET/CLRENA9  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "     SET/CLRENA8  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "     SET/CLRENA6  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "     SET/CLRENA5  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "     SET/CLRENA3  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "     SET/CLRENA2  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "     SET/CLRENA0  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEN9  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEN8  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEN6  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEN5  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEN3  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEN2  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEN0  ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3  ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. "  IP_2  ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. "  IP_1  ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7.   "  IP_0  ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7  ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. "  IP_6  ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. "  IP_5  ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7.   "  IP_4  ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. "  IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. "  IP_9  ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7.   "  IP_8  ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. "  IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. "  IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7.   "  IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. "  IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. "  IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7.   "  IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. "  IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. "  IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7.   "  IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. "  IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. "  IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7.   "  IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. "  IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. "  IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7.   "  IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL          ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. "    VCATCH             ,Vector catch flag" "No occurred,Occurred"
textline "                   "
eventfld.long 0x00 2. " DWTRAP            ,Data Watchpoint flag" "No match,Match"
textline "                   "
eventfld.long 0x00 1. " BKPT              ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. "       HALTED             ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 18. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
textline "                   "
textfld "                                 "
bitfld.long 0x00 0. " C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 18. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. "     C_STEP             ,Steps the core in halted debug" "Not halted,Halted"
textline "                   "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. "     C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
textline "                   "
textfld "                                 "
bitfld.long 0x00 0. " C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. "     C_STEP             ,Steps the core in halted debug" "Not halted,Halted"
textline "                   "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. "     C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR            ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. "          REGSEL             ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA              ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA            ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. "       VC_HARDERR         ,Debug trap on a Hard Fault" "No error,Error"
textline "                   "
bitfld.long 0x04 0.  " VC_CORERESET      ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.     "              KEY  ,Key field" "No write,Write"
bitfld.long 0x00 0.     "  ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1     ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK      ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED   ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. "  FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP      ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK      ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED   ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. "  FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ADC (12-bit A/D Converter)"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CR,A/D Converter Control Register"
bitfld.long 0x0 15. "ADCEN,A/DC Module Enable bit (The A/DC is automatically disabled at power down mode)" "0: Disable A/DC module operation,1: Enable A/DC module operation"
bitfld.long 0x0 11.--13. "TRIG,A/DC Trigger Signal Selection bits" "0: ADST,1: Timer 10 A-match signal,2: Timer 11 A-match signal,3: Timer 12 A-match signal,4: A/DC trigger signal from timer 30,?,?,?"
newline
bitfld.long 0x0 10. "REFSEL,A/DC Reference Selection bit" "0: Select analog power (VDD),1: Select external reference (AVREF)"
bitfld.long 0x0 8. "ADST,A/DC Conversion Start bit. This bit is automatically cleared to '0b' after operation" "0: No effect,1: Trigger signal generation for conversion start"
newline
bitfld.long 0x0 5. "ADCIEN,A/DC Interrupt Enable bit" "0: Disable A/DC interrupt,1: Enable A/DC interrupt"
bitfld.long 0x0 4. "ADCIFLAG,A/DC Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
newline
hexmask.long.byte 0x0 0.--3. 1. "ADSEL,A/D Converter Channel Selection bits"
rgroup.long 0x4++0x3
line.long 0x0 "DR,A/D Converter Data Register"
hexmask.long.word 0x0 0.--11. 1. "ADDATA,A/D Converter Result Data bits"
group.long 0x8++0x3
line.long 0x0 "PREDR,A/D Converter Prescaler Data Register"
hexmask.long.byte 0x0 0.--5. 1. "PRED,A/D Converter Prescaler Data bits."
tree.end
tree "CRC (Cyclic Redundancy Check)"
base ad:0x40000300
group.long 0x0++0x7
line.long 0x0 "CR,CRC/Checksum Control Register. Notes: 1. The CRCRLT register and the CRC/Checksum block should be initialized by writing '1b' to the RLTCLR bit before a new CRC/Checksum calculation. 2. The CRCRUN bit should be set to '1b' last time after setting.."
bitfld.long 0x0 9. "CRCINTEN,CRC interrupt enable bit" "0,1"
bitfld.long 0x0 8. "CRCINTF,CRC interrupt flag bit" "0,1"
bitfld.long 0x0 7. "MODS,User/Auto Mode Selection bit" "0,1"
bitfld.long 0x0 6. "RLTCLR,CRC/Checksum Result Data Register (CRCRLT) Initialization bit" "0,1"
bitfld.long 0x0 5. "MDSEL,CRC/Checksum Selection bit" "0,1"
bitfld.long 0x0 4. "POLYS,Polynomial Selection bit (CRC only)" "0,1"
bitfld.long 0x0 1. "FIRSTBS,First Shifted-in Selection bit (CRC only)" "0,1"
bitfld.long 0x0 0. "CRCRUN,CRC/Checksum Start Control and Busy bit" "0,1"
line.long 0x4 "IN,CRC/Checksum Input Data Register"
hexmask.long 0x4 0.--31. 1. "INDATA,CRC Input Data bit"
rgroup.long 0x8++0x3
line.long 0x0 "RLT,CRC/Checksum Result Data Register"
hexmask.long.word 0x0 0.--15. 1. "RLTDATA,CRC Result Data bit"
group.long 0xC++0x3
line.long 0x0 "INIT,CRC/Checksum Initial Data Register"
hexmask.long.word 0x0 0.--15. 1. "INIDATA,CRC Initial Data bit"
tree.end
tree "DMA (Direct Memory Access)"
base ad:0x0
tree "DMA0"
base ad:0x40000400
group.long 0x0++0xF
line.long 0x0 "CR,DMA Channel n Control Register"
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
newline
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
line.long 0x4 "SR,DMA Channel n Status Register"
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
line.long 0xC "MAR,DMA Channel n Memory Address"
hexmask.long.word 0xC 0.--15. 1. "MAR,Target memory address of data transfer."
tree.end
tree "DMA1"
base ad:0x40000410
group.long 0x0++0xF
line.long 0x0 "CR,DMA Channel n Control Register"
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
newline
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
line.long 0x4 "SR,DMA Channel n Status Register"
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
line.long 0xC "MAR,DMA Channel n Memory Address"
hexmask.long.word 0xC 0.--15. 1. "MAR,Target memory address of data transfer."
tree.end
tree "DMA2"
base ad:0x40000420
group.long 0x0++0xF
line.long 0x0 "CR,DMA Channel n Control Register"
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
newline
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
line.long 0x4 "SR,DMA Channel n Status Register"
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
line.long 0xC "MAR,DMA Channel n Memory Address"
hexmask.long.word 0xC 0.--15. 1. "MAR,Target memory address of data transfer."
tree.end
tree "DMA3"
base ad:0x40000430
group.long 0x0++0xF
line.long 0x0 "CR,DMA Channel n Control Register"
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
newline
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
line.long 0x4 "SR,DMA Channel n Status Register"
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
line.long 0xC "MAR,DMA Channel n Memory Address"
hexmask.long.word 0xC 0.--15. 1. "MAR,Target memory address of data transfer."
tree.end
tree.end
tree "FMC (Flash Memory Controller)"
base ad:0x40000100
group.long 0x4++0xF
line.long 0x0 "MR,Flash Memory Mode Select register"
hexmask.long.byte 0x0 0.--6. 1. "ACODE,Access Code."
line.long 0x4 "CR,Flash Memory Control register"
bitfld.long 0x4 23. "SELFPGM,When this bit is set('1')  PGM/ERS/HVEN will be cleared automatically after WRBUSY falling edge. It also enable CPU wait control when HVEN bit is set(1)" "0,1"
bitfld.long 0x4 8. "BBLOCK,Boot Block(1st 4KB) protection enable/disable from Mass(bulk) erase" "0,1"
bitfld.long 0x4 7. "MAS,Mass(bulk) erase enable/disable" "0,1"
bitfld.long 0x4 6. "SECT4K,Sector 4K erase enable/disable" "0,1"
bitfld.long 0x4 5. "SECT1K,Sector 1K erase enable/disable" "0,1"
bitfld.long 0x4 4. "PMODE,PMODE enable/disable" "0,1"
bitfld.long 0x4 3. "WADCK,Program/Erase address data latch clock enable/disable" "0,1"
bitfld.long 0x4 2. "PGM,Program mode enable/disable" "0,1"
bitfld.long 0x4 1. "ERS,Erase mode enable/disable" "0,1"
bitfld.long 0x4 0. "HVEN,High Voltage cycle enable/disable" "0,1"
line.long 0x8 "AR,Flash Memory Address register"
hexmask.long.word 0x8 0.--13. 1. "FADDR,Word(32-bit) base address : 64K-word address for 256KB Flash."
line.long 0xC "DR,Flash Memory Data register"
hexmask.long 0xC 0.--31. 1. "FDATA,Word size(32-bit) data"
group.long 0x18++0x3
line.long 0x0 "BUSY,Flash Write Busy Status Register"
bitfld.long 0x0 0. "WRBUSY,Write Busy status bit" "0,1"
rgroup.long 0x20++0x3
line.long 0x0 "CRC,Flash CRC-CCITT check value"
hexmask.long.word 0x0 0.--15. 1. "CRC16,CRC16 check value read register"
group.long 0x30++0x7
line.long 0x0 "CFG,Flash Memory Config Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes  write 0x7858 to these bits  otherwise the write is ignored."
bitfld.long 0x0 8.--10. "WAIT,This bits only be written in AMBA mode and MSB 16-bit (bit [31:16]) must be 0x7858" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. "CRCINIT,When this bit is set('1')  CRC register will be initialized" "0,1"
bitfld.long 0x0 6. "CRCEN,CRC16 enable" "0,1"
line.long 0x4 "WPROT,Write Protection Register"
hexmask.long 0x4 0.--31. 1. "WPROT,Write protection"
group.long 0x3C++0x3
line.long 0x0 "LOCK,Flash LOCK register"
hexmask.long.byte 0x0 0.--7. 1. "RPROT,Read protection"
rgroup.long 0x58++0x3
line.long 0x0 "HWID,Flash Size option check register"
hexmask.long 0x0 0.--31. 1. "HWID,Flash Size Option Check"
tree.end
tree "GPIO (General Purpose Input/Output)"
base ad:0x0
tree "PA"
base ad:0x40001000
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 14 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSB7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSB6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSB5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSB4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSB3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSB2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSB1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSB0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSB15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSB14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSB13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSB12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSB11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSB10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSB9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSB8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "PIE15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "PIE14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "PIE13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "PIE12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "PIE11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "PIE10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "PIE9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "PIE8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "PIE7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "PIE6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "PIE5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "PIE4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "PIE3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "PIE2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "PIE1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "PIE0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "PIS15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "PIS14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "PIS13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "PIS12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "PIS11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "PIS10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "PIS9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "PIS8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "PIS7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "PIS6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "PIS5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "PIS4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "PIS3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "PIS2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "PIS1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "PIS0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "PIC15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "PIC14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "PIC13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "PIC12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "PIC11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "PIC10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "PIC9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "PIC8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "PIC7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "PIC6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PIC5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "PIC4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "PIC3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "PIC2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "PIC1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "PIC0,P0 interrupt control" "0,1,2,3"
tree.end
tree "PB"
base ad:0x40001100
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 14 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSB7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSB6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSB5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSB4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSB3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSB2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSB1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSB0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSB15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSB14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSB13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSB12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSB11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSB10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSB9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSB8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "PIE15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "PIE14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "PIE13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "PIE12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "PIE11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "PIE10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "PIE9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "PIE8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "PIE7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "PIE6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "PIE5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "PIE4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "PIE3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "PIE2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "PIE1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "PIE0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "PIS15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "PIS14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "PIS13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "PIS12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "PIS11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "PIS10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "PIS9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "PIS8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "PIS7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "PIS6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "PIS5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "PIS4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "PIS3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "PIS2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "PIS1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "PIS0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "PIC15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "PIC14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "PIC13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "PIC12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "PIC11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "PIC10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "PIC9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "PIC8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "PIC7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "PIC6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PIC5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "PIC4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "PIC3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "PIC2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "PIC1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "PIC0,P0 interrupt control" "0,1,2,3"
tree.end
tree "PC"
base ad:0x40001200
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 14 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSB7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSB6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSB5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSB4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSB3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSB2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSB1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSB0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSB15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSB14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSB13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSB12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSB11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSB10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSB9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSB8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "PIE15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "PIE14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "PIE13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "PIE12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "PIE11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "PIE10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "PIE9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "PIE8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "PIE7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "PIE6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "PIE5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "PIE4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "PIE3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "PIE2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "PIE1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "PIE0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "PIS15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "PIS14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "PIS13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "PIS12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "PIS11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "PIS10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "PIS9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "PIS8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "PIS7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "PIS6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "PIS5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "PIS4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "PIS3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "PIS2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "PIS1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "PIS0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "PIC15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "PIC14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "PIC13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "PIC12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "PIC11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "PIC10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "PIC9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "PIC8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "PIC7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "PIC6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PIC5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "PIC4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "PIC3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "PIC2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "PIC1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "PIC0,P0 interrupt control" "0,1,2,3"
tree.end
tree "PD"
base ad:0x40001300
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 14 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSB7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSB6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSB5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSB4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSB3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSB2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSB1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSB0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSB15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSB14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSB13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSB12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSB11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSB10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSB9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSB8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "PIE15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "PIE14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "PIE13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "PIE12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "PIE11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "PIE10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "PIE9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "PIE8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "PIE7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "PIE6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "PIE5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "PIE4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "PIE3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "PIE2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "PIE1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "PIE0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "PIS15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "PIS14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "PIS13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "PIS12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "PIS11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "PIS10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "PIS9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "PIS8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "PIS7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "PIS6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "PIS5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "PIS4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "PIS3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "PIS2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "PIS1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "PIS0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "PIC15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "PIC14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "PIC13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "PIC12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "PIC11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "PIC10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "PIC9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "PIC8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "PIC7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "PIC6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PIC5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "PIC4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "PIC3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "PIC2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "PIC1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "PIC0,P0 interrupt control" "0,1,2,3"
tree.end
tree "PE"
base ad:0x40001400
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 14 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSB7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSB6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSB5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSB4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSB3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSB2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSB1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSB0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSB15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSB14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSB13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSB12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSB11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSB10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSB9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSB8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "PIE15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "PIE14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "PIE13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "PIE12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "PIE11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "PIE10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "PIE9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "PIE8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "PIE7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "PIE6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "PIE5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "PIE4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "PIE3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "PIE2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "PIE1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "PIE0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "PIS15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "PIS14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "PIS13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "PIS12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "PIS11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "PIS10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "PIS9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "PIS8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "PIS7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "PIS6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "PIS5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "PIS4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "PIS3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "PIS2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "PIS1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "PIS0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "PIC15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "PIC14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "PIC13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "PIC12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "PIC11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "PIC10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "PIC9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "PIC8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "PIC7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "PIC6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PIC5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "PIC4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "PIC3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "PIC2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "PIC1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "PIC0,P0 interrupt control" "0,1,2,3"
tree.end
tree "PF"
base ad:0x40001500
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 14 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSB7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSB6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSB5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSB4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSB3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSB2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSB1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSB0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSB15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSB14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSB13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSB12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSB11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSB10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSB9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSB8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "PIE15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "PIE14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "PIE13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "PIE12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "PIE11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "PIE10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "PIE9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "PIE8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "PIE7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "PIE6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "PIE5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "PIE4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "PIE3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "PIE2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "PIE1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "PIE0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "PIS15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "PIS14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "PIS13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "PIS12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "PIS11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "PIS10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "PIS9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "PIS8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "PIS7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "PIS6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "PIS5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "PIS4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "PIS3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "PIS2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "PIS1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "PIS0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "PIC15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "PIC14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "PIC13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "PIC12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "PIC11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "PIC10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "PIC9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "PIC8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "PIC7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "PIC6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PIC5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "PIC4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "PIC3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "PIC2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "PIC1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "PIC0,P0 interrupt control" "0,1,2,3"
tree.end
tree.end
tree "I2C (Inter-Integrated Circuit)"
base ad:0x0
tree "I2C0"
base ad:0x40004800
group.long 0x0++0x2B
line.long 0x0 "CR,I2Cn Control Register"
bitfld.long 0x0 8.--9. "INTERVAL,I2C bus internal delay between address and data transfer" "0,1,2,3"
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block by supplying" "0,1"
bitfld.long 0x0 6. "TXDLYENBn,I2CnSDHR Register Control bit" "0,1"
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable bit" "0,1"
rbitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period. Notes) ACK signal is output (SDA = 0) for the following 3 cases. Where x = 0 and 1. 1. When received address packet equals to SLAx[6:0] bits in I2CnSARx register. 2. When received address packet.." "0,1"
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
newline
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation When I2Cn is master." "0,1"
bitfld.long 0x0 0. "STARTCn,START Condition Generation When I2Cn is master." "0,1"
line.long 0x4 "ST,I2Cn Status Register"
bitfld.long 0x4 31. "SLT,This bit shows SCL low timeout status" "0,1"
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master  this bit represents whether it received AACK (address ACK) from slave." "0,1"
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected." "0,1"
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master." "0,1"
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode." "0,1"
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status." "0,1"
newline
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal." "0,1"
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 0 in slave mode."
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode."
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode." "0,1"
line.long 0x10 "DR,I2Cn Data Register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,The I2CnDR Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the I2CnDR register. Reading the I2CnDR register returns the contents of the Receive.."
line.long 0x14 "SDHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x14 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tPCLK X (I2CnSDHR+2). In master mode  load half the value of I2CnSCLR to this register to make SDA change in the middle of SCL. In slave.."
line.long 0x18 "SCLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x18 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
line.long 0x1C "SCHR,I2Cn SCL High Period Register"
hexmask.long.word 0x1C 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCHR + 2) where tPCLK is the period of PCLK."
line.long 0x20 "SLTCR,I2Cn SCL low timeout control register"
bitfld.long 0x20 1. "SLTINT,Selection of SCL low timeout interrupt" "0,1"
bitfld.long 0x20 0. "SLTEN,SCL low timeout enable bit" "0,1"
line.long 0x24 "SLTPDR,I2Cn SCL low timeout period data register"
hexmask.long.tbyte 0x24 0.--23. 1. "PDATA,This register defines the period of SCL low timeout"
line.long 0x28 "MBCR,I2Cn manual bus control register"
rbitfld.long 0x28 9. "SCLS,SCL status bit" "0,1"
rbitfld.long 0x28 8. "SDAS,SDA status bit" "0,1"
bitfld.long 0x28 3. "SCLO,SCL output data bit" "0,1"
bitfld.long 0x28 2. "SDAO,SDA output data bit" "0,1"
bitfld.long 0x28 1. "SCLMCE,SCL manual control enable bit" "0,1"
bitfld.long 0x28 0. "SDAMCE,SDA manual control enable bit" "0,1"
tree.end
tree "I2C1"
base ad:0x40004900
group.long 0x0++0x2B
line.long 0x0 "CR,I2Cn Control Register"
bitfld.long 0x0 8.--9. "INTERVAL,I2C bus internal delay between address and data transfer" "0,1,2,3"
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block by supplying" "0,1"
bitfld.long 0x0 6. "TXDLYENBn,I2CnSDHR Register Control bit" "0,1"
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable bit" "0,1"
rbitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period. Notes) ACK signal is output (SDA = 0) for the following 3 cases. Where x = 0 and 1. 1. When received address packet equals to SLAx[6:0] bits in I2CnSARx register. 2. When received address packet.." "0,1"
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
newline
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation When I2Cn is master." "0,1"
bitfld.long 0x0 0. "STARTCn,START Condition Generation When I2Cn is master." "0,1"
line.long 0x4 "ST,I2Cn Status Register"
bitfld.long 0x4 31. "SLT,This bit shows SCL low timeout status" "0,1"
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master  this bit represents whether it received AACK (address ACK) from slave." "0,1"
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected." "0,1"
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master." "0,1"
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode." "0,1"
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status." "0,1"
newline
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal." "0,1"
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 0 in slave mode."
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode."
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode." "0,1"
line.long 0x10 "DR,I2Cn Data Register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,The I2CnDR Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the I2CnDR register. Reading the I2CnDR register returns the contents of the Receive.."
line.long 0x14 "SDHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x14 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tPCLK X (I2CnSDHR+2). In master mode  load half the value of I2CnSCLR to this register to make SDA change in the middle of SCL. In slave.."
line.long 0x18 "SCLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x18 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
line.long 0x1C "SCHR,I2Cn SCL High Period Register"
hexmask.long.word 0x1C 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCHR + 2) where tPCLK is the period of PCLK."
line.long 0x20 "SLTCR,I2Cn SCL low timeout control register"
bitfld.long 0x20 1. "SLTINT,Selection of SCL low timeout interrupt" "0,1"
bitfld.long 0x20 0. "SLTEN,SCL low timeout enable bit" "0,1"
line.long 0x24 "SLTPDR,I2Cn SCL low timeout period data register"
hexmask.long.tbyte 0x24 0.--23. 1. "PDATA,This register defines the period of SCL low timeout"
line.long 0x28 "MBCR,I2Cn manual bus control register"
rbitfld.long 0x28 9. "SCLS,SCL status bit" "0,1"
rbitfld.long 0x28 8. "SDAS,SDA status bit" "0,1"
bitfld.long 0x28 3. "SCLO,SCL output data bit" "0,1"
bitfld.long 0x28 2. "SDAO,SDA output data bit" "0,1"
bitfld.long 0x28 1. "SCLMCE,SCL manual control enable bit" "0,1"
bitfld.long 0x28 0. "SDAMCE,SDA manual control enable bit" "0,1"
tree.end
tree.end
tree "LCD (LCD Driver/Controller)"
base ad:0x40005000
group.long 0x0++0xB
line.long 0x0 "CR,LCD Driver Control Register"
bitfld.long 0x0 8. "LCDDR,LCD Driving Resistor for Bias Select" "0: Internal LCD driving resistors for bias,1: External LCD driving resistors for bias"
bitfld.long 0x0 6.--7. "IRSEL,Internal LCD Bias Dividing Resistor Selection bits" "0: RLCD3: 105/105/80[kohm] @(1/2)/(1/3)/(1/4) bias,1: RLCD1: 10/10/10[kohm] @(1/2)/(1/3)/(1/4) bias,2: RLCD2: 66/66/50[kohm] @(1/2)/(1/3)/(1/4) bias,3: RLCD4: 320/320/240[kohm] @(1/2)/(1/3)/(1/4) bias"
newline
bitfld.long 0x0 3.--5. "DBS,LCD Duty and Bias Selection bits" "0: 1/8 duty 1/4 bias,1: 1/6 duty 1/4 bias,2: 1/5 duty 1/3 bias,3: 1/4 duty 1/3 bias,4: 1/3 duty 1/3 bias,5: 1/3 duty 1/2 bias,?,?"
bitfld.long 0x0 1.--2. "LCLK,LCD Clock Selection bits (When fLCD = 32.768kHz)" "0: 128Hz,1: 256Hz,2: 512Hz,3: 1024Hz"
newline
bitfld.long 0x0 0. "DISP,LCD Display Control bit" "0: Display off,1: Normal display on"
line.long 0x4 "BCCR,LCD Automatic Bias and Contrast Control Register. Notes: 1. The above LCD contrast step is based on 1/3 bias with 66kohm RLCD and on 1/4 bias with 50kohm RLCD 2. The 'LCD driver contrast control' is disabled during the LCDABC bit (LCD automatic.."
bitfld.long 0x4 12. "LCDABC,LCD Automatic Bias Control bit" "0: LCD automatic bias is off,1: LCD automatic bias is on"
bitfld.long 0x4 8.--10. "BMSEL,'Bias Mode A' fsTime Selection bits" "0: 'Bias Mode A' for 1-clock of fLCD,1: 'Bias Mode A' for 2-clock of fLCD,2: 'Bias Mode A' for 3-clock of fLCD,3: 'Bias Mode A' for 4-clock of fLCD,4: 'Bias Mode A' for 5-clock of fLCD,5: 'Bias Mode A' for 6-clock of fLCD,6: 'Bias Mode A' for 7-clock of fLCD,7: 'Bias Mode A' for 8-clock of fLCD"
newline
bitfld.long 0x4 5. "LCTEN,LCD Driver Contrast Control bit" "0: Disable LCD driver contrast,1: Enable LCD driver contrast"
hexmask.long.byte 0x4 0.--3. 1. "VLCD,VLC0 Voltage Control when the contrast is enabled"
line.long 0x8 "BSSR,LCD source selection register"
bitfld.long 0x8 9. "LCDDR,LCD external bias path enable bit" "0,1"
bitfld.long 0x8 8. "PVLC_OPEN,LCD external bias path enable bit" "0,1"
newline
bitfld.long 0x8 7. "VLC_PE3,External bias VLC3 enable bit" "0,1"
bitfld.long 0x8 6. "VLC_PE2,External bias VLC2 enable bit" "0,1"
newline
bitfld.long 0x8 5. "VLC_PE1,External bias VLC1 enable bit" "0,1"
bitfld.long 0x8 4. "VLC_PE0,External bias VLC0 enable bit" "0,1"
group.byte 0x10++0x1F
line.byte 0x0 "DR0,LCD Display Data Register 0"
line.byte 0x1 "DR1,LCD Display Data Register 1"
line.byte 0x2 "DR2,LCD Display Data Register 2"
line.byte 0x3 "DR3,LCD Display Data Register 3"
line.byte 0x4 "DR4,LCD Display Data Register 4"
line.byte 0x5 "DR5,LCD Display Data Register 5"
line.byte 0x6 "DR6,LCD Display Data Register 6"
line.byte 0x7 "DR7,LCD Display Data Register 7"
line.byte 0x8 "DR8,LCD Display Data Register 8"
line.byte 0x9 "DR9,LCD Display Data Register 9"
line.byte 0xA "DR10,LCD Display Data Register 10"
line.byte 0xB "DR11,LCD Display Data Register 11"
line.byte 0xC "DR12,LCD Display Data Register 12"
line.byte 0xD "DR13,LCD Display Data Register 13"
line.byte 0xE "DR14,LCD Display Data Register 14"
line.byte 0xF "DR15,LCD Display Data Register 15"
line.byte 0x10 "DR16,LCD Display Data Register 16"
line.byte 0x11 "DR17,LCD Display Data Register 17"
line.byte 0x12 "DR18,LCD Display Data Register 18"
line.byte 0x13 "DR19,LCD Display Data Register 19"
line.byte 0x14 "DR20,LCD Display Data Register 20"
line.byte 0x15 "DR21,LCD Display Data Register 21"
line.byte 0x16 "DR22,LCD Display Data Register 22"
line.byte 0x17 "DR23,LCD Display Data Register 23"
line.byte 0x18 "DR24,LCD Display Data Register 24"
line.byte 0x19 "DR25,LCD Display Data Register 25"
line.byte 0x1A "DR26,LCD Display Data Register 26"
line.byte 0x1B "DR27,LCD Display Data Register 27"
line.byte 0x1C "DR28,LCD Display Data Register 28"
line.byte 0x1D "DR29,LCD Display Data Register 29"
line.byte 0x1E "DR30,LCD Display Data Register 30"
line.byte 0x1F "DR31,LCD Display Data Register 31"
tree.end
tree "LED (LED Driver/Controller)"
base ad:0x40006000
group.long 0x0++0x37
line.long 0x0 "COMOE,COM Output Enable Register"
bitfld.long 0x0 12. "COMOE12,COMn Output Enable" "0,1"
bitfld.long 0x0 11. "COMOE11,COMn Output Enable" "0,1"
bitfld.long 0x0 10. "COMOE10,COMn Output Enable" "0,1"
bitfld.long 0x0 9. "COMOE9,COMn Output Enable" "0,1"
bitfld.long 0x0 8. "COMOE8,COMn Output Enable" "0,1"
newline
bitfld.long 0x0 7. "COMOE7,COMn Output Enable" "0,1"
bitfld.long 0x0 6. "COMOE6,COMn Output Enable" "0,1"
bitfld.long 0x0 5. "COMOE5,COMn Output Enable" "0,1"
bitfld.long 0x0 4. "COMOE4,COMn Output Enable" "0,1"
bitfld.long 0x0 3. "COMOE3,COMn Output Enable" "0,1"
newline
bitfld.long 0x0 2. "COMOE2,COMn Output Enable" "0,1"
bitfld.long 0x0 1. "COMOE1,COMn Output Enable" "0,1"
bitfld.long 0x0 0. "COMOE0,COMn Output Enable" "0,1"
line.long 0x4 "SEGOE,SEG Output Enable Register"
bitfld.long 0x4 15. "SEGOE15,SEGn Output Enable" "0,1"
bitfld.long 0x4 14. "SEGOE14,SEGn Output Enable" "0,1"
bitfld.long 0x4 13. "SEGOE13,SEGn Output Enable" "0,1"
bitfld.long 0x4 12. "SEGOE12,SEGn Output Enable" "0,1"
bitfld.long 0x4 11. "SEGOE11,SEGn Output Enable" "0,1"
newline
bitfld.long 0x4 10. "SEGOE10,SEGn Output Enable" "0,1"
bitfld.long 0x4 9. "SEGOE9,SEGn Output Enable" "0,1"
bitfld.long 0x4 8. "SEGOE8,SEGn Output Enable" "0,1"
bitfld.long 0x4 7. "SEGOE7,SEGn Output Enable" "0,1"
bitfld.long 0x4 6. "SEGOE6,SEGn Output Enable" "0,1"
newline
bitfld.long 0x4 5. "SEGOE5,SEGn Output Enable" "0,1"
bitfld.long 0x4 4. "SEGOE4,SEGn Output Enable" "0,1"
bitfld.long 0x4 3. "SEGOE3,SEGn Output Enable" "0,1"
bitfld.long 0x4 2. "SEGOE2,SEGn Output Enable" "0,1"
bitfld.long 0x4 1. "SEGOE1,SEGn Output Enable" "0,1"
newline
bitfld.long 0x4 0. "SEGOE0,SEGn Output Enable" "0,1"
line.long 0x8 "PRESD,LED Prescaler Data Register"
hexmask.long.byte 0x8 0.--7. 1. "PRESD,Pre-scale value of LED clock"
line.long 0xC "COMER,COM Enable Register"
bitfld.long 0xC 12. "COMER12,Select COM or SEG Enable." "0,1"
bitfld.long 0xC 11. "COMER11,Select COM or SEG Enable." "0,1"
bitfld.long 0xC 10. "COMER10,Select COM or SEG Enable." "0,1"
bitfld.long 0xC 9. "COMER9,Select COM or SEG Enable." "0,1"
bitfld.long 0xC 8. "COMER8,Select COM or SEG Enable." "0,1"
newline
bitfld.long 0xC 7. "COMER7,Select COM or SEG Enable." "0,1"
bitfld.long 0xC 6. "COMER6,Select COM or SEG Enable." "0,1"
bitfld.long 0xC 5. "COMER5,Select COM or SEG Enable." "0,1"
bitfld.long 0xC 4. "COMER4,Select COM or SEG Enable." "0,1"
bitfld.long 0xC 3. "COMER3,Select COM or SEG Enable." "0,1"
newline
bitfld.long 0xC 2. "COMER2,Select COM or SEG Enable." "0,1"
bitfld.long 0xC 1. "COMER1,Select COM or SEG Enable." "0,1"
bitfld.long 0xC 0. "COMER0,Select COM or SEG Enable." "0,1"
line.long 0x10 "COMPWID,COM Pulse Width Control Register"
hexmask.long.byte 0x10 0.--7. 1. "COMPWID,COM Pulse Width Control bits"
line.long 0x14 "COMDIMM0,LED COM Dimming 0 Register"
hexmask.long.byte 0x14 24.--31. 1. "COM3DIMM,Dimming Control for COM3"
hexmask.long.byte 0x14 16.--23. 1. "COM2DIMM,Dimming Control for COM2"
hexmask.long.byte 0x14 8.--15. 1. "COM1DIMM,Dimming Control for COM1"
hexmask.long.byte 0x14 0.--7. 1. "COM0DIMM,Dimming Control for COM0"
line.long 0x18 "COMDIMM1,LED COM Dimming 1 Register"
hexmask.long.byte 0x18 24.--31. 1. "COM7DIMM,Dimming Control for COM7"
hexmask.long.byte 0x18 16.--23. 1. "COM6DIMM,Dimming Control for COM6"
hexmask.long.byte 0x18 8.--15. 1. "COM5DIMM,Dimming Control for COM5"
hexmask.long.byte 0x18 0.--7. 1. "COM4DIMM,Dimming Control for COM4"
line.long 0x1C "COMDIMM2,LED COM Dimming 2 Register"
hexmask.long.byte 0x1C 24.--31. 1. "COM11DIMM,Dimming Control for COM11"
hexmask.long.byte 0x1C 16.--23. 1. "COM10DIMM,Dimming Control for COM10"
hexmask.long.byte 0x1C 8.--15. 1. "COM9DIMM,Dimming Control for COM9"
hexmask.long.byte 0x1C 0.--7. 1. "COM8DIMM,Dimming Control for COM8"
line.long 0x20 "COMDIMM3,LED COM Dimming 3 Register"
hexmask.long.byte 0x20 0.--7. 1. "COM12DIMM,Dimming Control for COM12"
line.long 0x24 "LEDPD,LED Period Data Register"
hexmask.long.tbyte 0x24 0.--19. 1. "LEDPD,LED Period. Determine interval between COMx on-time"
line.long 0x28 "SR,LED STATUS Register"
bitfld.long 0x28 3. "MATCHF,LED stop counter match flag" "0,1"
bitfld.long 0x28 2. "LED_INTF,LED Interrupt Flag(in LED_INTE=1)" "0,1"
bitfld.long 0x28 1. "LED_INTE,LED Interrupt Enable" "0,1"
bitfld.long 0x28 0. "LED_ENDF,LED Operation End Flag" "0,1"
line.long 0x2C "LEDCON3,LED Control 3 Register"
hexmask.long.byte 0x2C 4.--7. 1. "SET_TIME,SEG GND start timing"
hexmask.long.byte 0x2C 0.--3. 1. "CLR_TIME,SET GND clear timing"
line.long 0x30 "LEDCON2,LED Control 2 Register"
bitfld.long 0x30 4. "SRTEN,SEG-GND function enable" "0,1"
bitfld.long 0x30 3. "OVERLAP,Overlap time configuration" "0,1"
bitfld.long 0x30 0.--2. "OVERTS,Overlap time selection" "0,1,2,3,4,5,6,7"
line.long 0x34 "LEDCON1,LED Control 1 Register"
bitfld.long 0x34 2.--4. "LED_MODE,LED operation mode selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x34 1. "LED_EN,LED Enable" "0,1"
bitfld.long 0x34 0. "LED_ST,LED Start or Stop under LEDEN=1 condition" "0,1"
group.long 0x40++0x33
line.long 0x0 "DISPRAM0,LED Display RAM"
bitfld.long 0x0 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x0 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x0 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x0 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x0 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x0 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x0 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x0 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x0 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x0 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x0 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x0 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x0 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x0 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x0 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x0 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x4 "DISPRAM1,LED Display RAM"
bitfld.long 0x4 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x4 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x4 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x4 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x4 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x4 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x4 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x4 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x4 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x4 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x4 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x4 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x4 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x4 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x4 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x4 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x8 "DISPRAM2,LED Display RAM"
bitfld.long 0x8 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x8 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x8 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x8 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x8 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x8 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x8 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x8 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x8 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x8 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x8 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x8 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x8 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x8 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x8 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x8 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0xC "DISPRAM3,LED Display RAM"
bitfld.long 0xC 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0xC 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0xC 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0xC 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0xC 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0xC 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0xC 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0xC 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0xC 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0xC 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0xC 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0xC 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0xC 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0xC 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0xC 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0xC 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x10 "DISPRAM4,LED Display RAM"
bitfld.long 0x10 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x10 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x10 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x10 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x10 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x10 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x10 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x10 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x10 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x10 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x10 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x10 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x10 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x10 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x10 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x10 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x14 "DISPRAM5,LED Display RAM"
bitfld.long 0x14 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x14 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x14 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x14 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x14 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x14 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x14 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x14 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x14 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x14 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x14 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x14 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x14 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x14 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x14 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x14 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x18 "DISPRAM6,LED Display RAM"
bitfld.long 0x18 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x18 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x18 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x18 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x18 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x18 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x18 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x18 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x18 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x18 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x18 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x18 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x18 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x18 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x18 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x18 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x1C "DISPRAM7,LED Display RAM"
bitfld.long 0x1C 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x1C 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x1C 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x1C 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x1C 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x1C 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x1C 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x1C 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x1C 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x1C 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x1C 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x1C 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x1C 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x1C 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x1C 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x1C 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x20 "DISPRAM8,LED Display RAM"
bitfld.long 0x20 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x20 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x20 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x20 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x20 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x20 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x20 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x20 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x20 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x20 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x20 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x20 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x20 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x20 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x20 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x20 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x24 "DISPRAM9,LED Display RAM"
bitfld.long 0x24 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x24 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x24 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x24 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x24 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x24 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x24 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x24 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x24 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x24 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x24 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x24 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x24 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x24 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x24 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x24 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x28 "DISPRAM10,LED Display RAM"
bitfld.long 0x28 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x28 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x28 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x28 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x28 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x28 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x28 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x28 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x28 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x28 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x28 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x28 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x28 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x28 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x28 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x28 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x2C "DISPRAM11,LED Display RAM"
bitfld.long 0x2C 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x2C 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x2C 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x2C 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x2C 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x2C 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x2C 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x2C 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x2C 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x2C 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x2C 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x2C 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x2C 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x2C 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x2C 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x2C 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
line.long 0x30 "DISPRAM12,LED Display RAM"
bitfld.long 0x30 15. "SEG15_COMx,SEG15-COMx LED lane display value" "0,1"
bitfld.long 0x30 14. "SEG14_COMx,SEG14-COMx LED lane display value" "0,1"
bitfld.long 0x30 13. "SEG13_COMx,SEG13-COMx LED lane display value" "0,1"
bitfld.long 0x30 12. "SEG12_COMx,SEG12-COMx LED lane display value" "0,1"
bitfld.long 0x30 11. "SEG11_COMx,SEG11-COMx LED lane display value" "0,1"
newline
bitfld.long 0x30 10. "SEG10_COMx,SEG10-COMx LED lane display value" "0,1"
bitfld.long 0x30 9. "SEG9_COMx,SEG9-COMx LED lane display value" "0,1"
bitfld.long 0x30 8. "SEG8_COMx,SEG8-COMx LED lane display value" "0,1"
bitfld.long 0x30 7. "SEG7_COMx,SEG7-COMx LED lane display value" "0,1"
bitfld.long 0x30 6. "SEG6_COMx,SEG6-COMx LED lane display value" "0,1"
newline
bitfld.long 0x30 5. "SEG5_COMx,SEG5-COMx LED lane display value" "0,1"
bitfld.long 0x30 4. "SEG4_COMx,SEG4-COMx LED lane display value" "0,1"
bitfld.long 0x30 3. "SEG3_COMx,SEG3-COMx LED lane display value" "0,1"
bitfld.long 0x30 2. "SEG2_COMx,SEG2-COMx LED lane display value" "0,1"
bitfld.long 0x30 1. "SEG1_COMx,SEG1-COMx LED lane display value" "?,1: COMx LED lane display value"
newline
bitfld.long 0x30 0. "SEG0_COMx,SEG0-COMx LED lane display value" "0: COMx LED lane display value,?"
group.long 0x80++0xF
line.long 0x0 "LOGDE,LED Log-scale Dimming Enable Register"
bitfld.long 0x0 12. "LOGD_EN12,Enable COMx log-scale dimming" "0,1"
bitfld.long 0x0 11. "LOGD_EN11,Enable COMx log-scale dimming" "0,1"
bitfld.long 0x0 10. "LOGD_EN10,Enable COMx log-scale dimming" "0,1"
bitfld.long 0x0 9. "LOGD_EN9,Enable COMx log-scale dimming" "0,1"
bitfld.long 0x0 8. "LOGD_EN8,Enable COMx log-scale dimming" "0,1"
newline
bitfld.long 0x0 7. "LOGD_EN7,Enable COMx log-scale dimming" "0,1"
bitfld.long 0x0 6. "LOGD_EN6,Enable COMx log-scale dimming" "0,1"
bitfld.long 0x0 5. "LOGD_EN5,Enable COMx log-scale dimming" "0,1"
bitfld.long 0x0 4. "LOGD_EN4,Enable COMx log-scale dimming" "0,1"
bitfld.long 0x0 3. "LOGD_EN3,Enable COMx log-scale dimming" "0,1"
newline
bitfld.long 0x0 2. "LOGD_EN2,Enable COMx log-scale dimming" "0,1"
bitfld.long 0x0 1. "LOGD_EN1,Enable COMx log-scale dimming" "0,1"
bitfld.long 0x0 0. "LOGD_EN0,Enable COMx log-scale dimming" "0,1"
line.long 0x4 "COMDRIVE,LED COM additional driving Register"
bitfld.long 0x4 12. "COMDRIVE12,Enable COMx additional NMOS driver" "0,1"
bitfld.long 0x4 11. "COMDRIVE11,Enable COMx additional NMOS driver" "0,1"
bitfld.long 0x4 10. "COMDRIVE10,Enable COMx additional NMOS driver" "0,1"
bitfld.long 0x4 9. "COMDRIVE9,Enable COMx additional NMOS driver" "0,1"
bitfld.long 0x4 8. "COMDRIVE8,Enable COMx additional NMOS driver" "0,1"
newline
bitfld.long 0x4 7. "COMDRIVE7,Enable COMx additional NMOS driver" "0,1"
bitfld.long 0x4 6. "COMDRIVE6,Enable COMx additional NMOS driver" "0,1"
bitfld.long 0x4 5. "COMDRIVE5,Enable COMx additional NMOS driver" "0,1"
bitfld.long 0x4 4. "COMDRIVE4,Enable COMx additional NMOS driver" "0,1"
bitfld.long 0x4 3. "COMDRIVE3,Enable COMx additional NMOS driver" "0,1"
newline
bitfld.long 0x4 2. "COMDRIVE2,Enable COMx additional NMOS driver" "0,1"
bitfld.long 0x4 1. "COMDRIVE1,Enable COMx additional NMOS driver" "0,1"
bitfld.long 0x4 0. "COMDRIVE0,Enable COMx additional NMOS driver" "0,1"
line.long 0x8 "PORTCTRL,LED Port Control Register"
hexmask.long.word 0x8 0.--15. 1. "PORTx_DIR,Select LED Port Status(0: Floating / 1: Output)"
line.long 0xC "DLYCNT,LED run signal Delay Count Register"
hexmask.long.byte 0xC 0.--7. 1. "DLYCNT,Delay time before LED_PORTCTRL"
tree.end
tree "PCU (Port Control Unit)"
base ad:0x40001F00
wgroup.long 0xF0++0x3
line.long 0x0 "PORTEN,Port Access Enable 0x15->0x51"
hexmask.long.byte 0x0 0.--7. 1. "PORTEN,Writing the sequence of 0x15 and 0x51 in this register enables"
tree.end
tree "SCU (System Control Unit)"
base ad:0x0
tree "SCU"
base ad:0x40000000
group.long 0x4++0x7
line.long 0x0 "SMR,System Mode Register"
bitfld.long 0x0 10. "ROSCAON,ROSC Always on select bit in power down mode" "0: ROSC is automatically off entering power down mode,1: ROSC isn't automatically off entering power down.."
bitfld.long 0x0 9. "BGRAON,BGR Always on select bit in power down mode" "0: BGR is automatically off entering power down mode,1: BGR isn't automatically off entering power down.."
newline
bitfld.long 0x0 8. "VDCAON,VDC Always on select bit in power down mode" "0,1"
rbitfld.long 0x0 4.--5. "PREVMODE,Previous operating mode before current reset event" "0,1,2,3"
line.long 0x4 "SCR,System Control Register"
hexmask.long.word 0x4 16.--31. 1. "WTIDKY,On writes  write 0x9EB3 to these bits  otherwise the write is ignored."
bitfld.long 0x4 0. "SWRST,Internal soft reset activation bit (check RSER[4] for reset)" "0,1"
group.long 0x10++0x3
line.long 0x0 "WUER,Wake up source enable register"
bitfld.long 0x0 13. "GPIOFWUE,Enable wakeup source of GPIOF port pin change event" "0,1"
bitfld.long 0x0 12. "GPIOEWUE,Enable wakeup source of GPIOE port pin change event" "0,1"
newline
bitfld.long 0x0 11. "GPIODWUE,Enable wakeup source of GPIOD port pin change event" "0,1"
bitfld.long 0x0 10. "GPIOCWUE,Enable wakeup source of GPIOC port pin change event" "0,1"
newline
bitfld.long 0x0 9. "GPIOBWUE,Enable wakeup source of GPIOB port pin change event" "0,1"
bitfld.long 0x0 8. "GPIOAWUE,Enable wakeup source of GPIOA port pin change event" "0,1"
newline
bitfld.long 0x0 4. "USART11WUE,Enable wakeup source of USART11 event" "0,1"
bitfld.long 0x0 3. "USART10WUE,Enable wakeup source of USART10 event" "0,1"
newline
bitfld.long 0x0 2. "WTWUE,Enable wakeup source of watch timer event" "0,1"
bitfld.long 0x0 1. "WDTWUE,Enable wakeup source of watchdog timer event" "0,1"
newline
bitfld.long 0x0 0. "LVDWUE,Enable wakeup source of LVD event" "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "WUSR,Wake up source status register"
bitfld.long 0x0 13. "GPIOFWU,Status of wakeup source of GPIOF port pin change event" "0,1"
bitfld.long 0x0 12. "GPIOEWU,Status of wakeup source of GPIOE port pin change event" "0,1"
newline
bitfld.long 0x0 11. "GPIODWU,Status of wakeup source of GPIOD port pin change event" "0,1"
bitfld.long 0x0 10. "GPIOCWU,Status of wakeup source of GPIOC port pin change event" "0,1"
newline
bitfld.long 0x0 9. "GPIOBWU,Status of wakeup source of GPIOB port pin change event" "0,1"
bitfld.long 0x0 8. "GPIOAWU,Status of wakeup source of GPIOA port pin change event" "0,1"
newline
bitfld.long 0x0 4. "USART11WU,Status of wakeup source of USART11 event" "0,1"
bitfld.long 0x0 3. "USART10WU,Status of wakeup source of USART10 event" "0,1"
newline
bitfld.long 0x0 2. "WTWU,Status of wakeup source of watch timer event" "0,1"
bitfld.long 0x0 1. "WDTWU,Status of wakeup source of watchdog timer event" "0,1"
newline
bitfld.long 0x0 0. "LVDWU,Status of wakeup source of LVD event" "0,1"
group.long 0x18++0x23
line.long 0x0 "RSER,Reset source enable register"
bitfld.long 0x0 6. "PINRST,External pin reset enable bit" "0,1"
bitfld.long 0x0 5. "CPURST,CPU request reset enable bit" "0,1"
newline
bitfld.long 0x0 4. "SWRST,Software reset enable bit" "0,1"
bitfld.long 0x0 3. "WDTRST,Watchdog Timer reset enable bit" "0,1"
newline
bitfld.long 0x0 2. "MCKFRST,MCLK Clock fail reset enable bit" "0,1"
bitfld.long 0x0 1. "MOFRST,MOSC Clock fail reset enable bit" "0,1"
newline
bitfld.long 0x0 0. "LVDRST,LVD reset enable bit" "0,1"
line.long 0x4 "RSSR,Reset source status register"
bitfld.long 0x4 7. "PORST,Power on reset status bit" "0,1"
bitfld.long 0x4 6. "PINRST,External pin reset status bit" "0,1"
newline
bitfld.long 0x4 5. "CPURST,CPU request reset status bit" "0,1"
bitfld.long 0x4 4. "SWRST,Software reset status bit" "0,1"
newline
bitfld.long 0x4 3. "WDTRST,Watchdog Timer reset status bit" "0,1"
bitfld.long 0x4 2. "MCKFRST,MCLK Clock fail reset status bit" "0,1"
newline
bitfld.long 0x4 1. "MOFRST,MOSC Clock fail reset status bit" "0,1"
bitfld.long 0x4 0. "LVDRST,LVD reset status bit" "0,1"
line.long 0x8 "PRER1,Peripheral reset enable register 1"
bitfld.long 0x8 31. "WT,WT reset mask" "0,1"
bitfld.long 0x8 26. "TIMER21,TIMER21 reset mask" "0,1"
newline
bitfld.long 0x8 25. "TIMER20,TIMER20 reset mask" "0,1"
bitfld.long 0x8 24. "TIMER30,TIMER30 reset mask" "0,1"
newline
bitfld.long 0x8 19. "TIMER13,TIMER13 reset mask" "0,1"
bitfld.long 0x8 18. "TIMER12,TIMER12 reset mask" "0,1"
newline
bitfld.long 0x8 17. "TIMER11,TIMER11 reset mask" "0,1"
bitfld.long 0x8 16. "TIMER10,TIMER10 reset mask" "0,1"
newline
bitfld.long 0x8 13. "GPIOF,GPIOF reset mask" "0,1"
bitfld.long 0x8 12. "GPIOE,GPIOE reset mask" "0,1"
newline
bitfld.long 0x8 11. "GPIOD,GPIOD reset mask" "0,1"
bitfld.long 0x8 10. "GPIOC,GPIOC reset mask" "0,1"
newline
bitfld.long 0x8 9. "GPIOB,GPIOB reset mask" "0,1"
bitfld.long 0x8 8. "GPIOA,GPIOA reset mask" "0,1"
newline
bitfld.long 0x8 4. "DMA,DMA reset mask" "0,1"
bitfld.long 0x8 3. "PCU,PCU reset mask" "0,1"
newline
bitfld.long 0x8 2. "WDT,WDT reset mask" "0,1"
bitfld.long 0x8 1. "FMC,FMC reset mask" "0,1"
newline
bitfld.long 0x8 0. "SCU,SCU reset mask" "0,1"
line.long 0xC "PRER2,Peripheral reset enable register 2"
bitfld.long 0xC 31. "CRC,CRC reset mask" "0,1"
bitfld.long 0xC 29. "LED,LED reset mask" "0,1"
newline
bitfld.long 0xC 28. "LCD,LCD reset mask" "0,1"
bitfld.long 0xC 27. "TSENSE,TSENSE reset mask" "0,1"
newline
bitfld.long 0xC 25. "TOUCH,TOUCH reset mask" "0,1"
bitfld.long 0xC 20. "ADC,ADC reset mask" "0,1"
newline
bitfld.long 0xC 15. "SPI21,SPI21 reset mask" "0,1"
bitfld.long 0xC 14. "SPI20,SPI20 reset mask" "0,1"
newline
bitfld.long 0xC 13. "UART1,UART1 reset mask" "0,1"
bitfld.long 0xC 12. "UART0,UART0 reset mask" "0,1"
newline
bitfld.long 0xC 9. "USART11,USART11 reset mask" "0,1"
bitfld.long 0xC 8. "USART10,USART10 reset mask" "0,1"
newline
bitfld.long 0xC 5. "I2C1,I2C1 reset mask" "0,1"
bitfld.long 0xC 4. "I2C0,I2C0 reset mask" "0,1"
line.long 0x10 "PER1,Peripheral enable register 1"
bitfld.long 0x10 31. "WT,WT function enable" "0,1"
bitfld.long 0x10 26. "TIMER21,TIMER21 function enable" "0,1"
newline
bitfld.long 0x10 25. "TIMER20,TIMER20 function enable" "0,1"
bitfld.long 0x10 24. "TIMER30,TIMER30 function enable" "0,1"
newline
bitfld.long 0x10 19. "TIMER13,TIMER13 function enable" "0,1"
bitfld.long 0x10 18. "TIMER12,TIMER12 function enable" "0,1"
newline
bitfld.long 0x10 17. "TIMER11,TIMER11 function enable" "0,1"
bitfld.long 0x10 16. "TIMER10,TIMER10 function enable" "0,1"
newline
bitfld.long 0x10 13. "GPIOF,GPIOF function enable" "0,1"
bitfld.long 0x10 12. "GPIOE,GPIOE function enable" "0,1"
newline
bitfld.long 0x10 11. "GPIOD,GPIOD function enable" "0,1"
bitfld.long 0x10 10. "GPIOC,GPIOC function enable" "0,1"
newline
bitfld.long 0x10 9. "GPIOB,GPIOB function enable" "0,1"
bitfld.long 0x10 8. "GPIOA,GPIOA function enable" "0,1"
newline
bitfld.long 0x10 4. "DMA,DMA function enable" "0,1"
line.long 0x14 "PER2,Peripheral enable register 2"
bitfld.long 0x14 31. "CRC,CRC function enable" "0,1"
bitfld.long 0x14 29. "LED,LED function enable" "0,1"
newline
bitfld.long 0x14 28. "LCD,LCD function enable" "0,1"
bitfld.long 0x14 27. "TSENSE,TSENSE function enable" "0,1"
newline
bitfld.long 0x14 25. "TOUCH,TOUCH function enable" "0,1"
bitfld.long 0x14 20. "ADC,ADC function enable" "0,1"
newline
bitfld.long 0x14 15. "SPI21,SPI21 function enable" "0,1"
bitfld.long 0x14 14. "SPI20,SPI20 function enable" "0,1"
newline
bitfld.long 0x14 13. "UART1,UART1 function enable" "0,1"
bitfld.long 0x14 12. "UART0,UART0 function enable" "0,1"
newline
bitfld.long 0x14 9. "USART11,USART11 function enable" "0,1"
bitfld.long 0x14 8. "USART10,USART10 function enable" "0,1"
newline
bitfld.long 0x14 5. "I2C1,I2C1 function enable" "0,1"
bitfld.long 0x14 4. "I2C0,I2C0 function enable" "0,1"
line.long 0x18 "PCER1,Peripheral clock enable register 1"
bitfld.long 0x18 31. "WT,WT clock enable" "0,1"
bitfld.long 0x18 26. "TIMER21,TIMER21 clock enable" "0,1"
newline
bitfld.long 0x18 25. "TIMER20,TIMER20 clock enable" "0,1"
bitfld.long 0x18 24. "TIMER30,TIMER30 clock enable" "0,1"
newline
bitfld.long 0x18 19. "TIMER13,TIMER13 clock enable" "0,1"
bitfld.long 0x18 18. "TIMER12,TIMER12 clock enable" "0,1"
newline
bitfld.long 0x18 17. "TIMER11,TIMER11 clock enable" "0,1"
bitfld.long 0x18 16. "TIMER10,TIMER10 clock enable" "0,1"
newline
bitfld.long 0x18 13. "GPIOF,GPIOF clock enable" "0,1"
bitfld.long 0x18 12. "GPIOE,GPIOE clock enable" "0,1"
newline
bitfld.long 0x18 11. "GPIOD,GPIOD clock enable" "0,1"
bitfld.long 0x18 10. "GPIOC,GPIOC clock enable" "0,1"
newline
bitfld.long 0x18 9. "GPIOB,GPIOB clock enable" "0,1"
bitfld.long 0x18 8. "GPIOA,GPIOA clock enable" "0,1"
newline
bitfld.long 0x18 4. "DMA,DMA clock enable" "0,1"
line.long 0x1C "PCER2,Peripheral clock enable register 2"
bitfld.long 0x1C 31. "CRC,CRC clock enable" "0,1"
bitfld.long 0x1C 29. "LED,LED clock enable" "0,1"
newline
bitfld.long 0x1C 28. "LCD,LCD clock enable" "0,1"
bitfld.long 0x1C 27. "TSENSE,TSENSE clock enable" "0,1"
newline
bitfld.long 0x1C 25. "TOUCH,TOUCH clock enable" "0,1"
bitfld.long 0x1C 20. "ADC,ADC clock enable" "0,1"
newline
bitfld.long 0x1C 15. "SPI21,SPI21 clock enable" "0,1"
bitfld.long 0x1C 14. "SPI20,SPI20 clock enable" "0,1"
newline
bitfld.long 0x1C 13. "UART1,UART1 clock enable" "0,1"
bitfld.long 0x1C 12. "UART0,UART0 clock enable" "0,1"
newline
bitfld.long 0x1C 9. "USART11,USART11 clock enable" "0,1"
bitfld.long 0x1C 8. "USART10,USART10 clock enable" "0,1"
newline
bitfld.long 0x1C 5. "I2C1,I2C1 clock enable" "0,1"
bitfld.long 0x1C 4. "I2C0,I2C0 clock enable" "0,1"
line.long 0x20 "PPCLKSR,Peripheral clock selection register"
bitfld.long 0x20 22. "T1xCLK,Timer 1x Clock Selection bit" "0,1"
bitfld.long 0x20 20. "T20CLK,Timer 20 Clock Selection bit" "0,1"
newline
bitfld.long 0x20 17. "T30CLK,Timer 30 Clock Selection bit" "0,1"
bitfld.long 0x20 10. "LEDCLK,LED Clock Selection bit" "0,1"
newline
bitfld.long 0x20 6.--7. "LCDCLK,LCD Clock Selection bit" "0,1,2,3"
bitfld.long 0x20 3.--4. "WTCLK,Watch Timer Clock Selection bit" "0,1,2,3"
newline
bitfld.long 0x20 0. "WDTCLK,Watch-dog Timer Clock Selection bit" "0,1"
group.long 0x40++0x13
line.long 0x0 "CSCR,Clock Source Control register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,On writes  write 0xA507 to these bits  otherwise the write is ignored."
hexmask.long.byte 0x0 12.--15. 1. "LSECON,External crystal sub oscillator control"
newline
hexmask.long.byte 0x0 8.--11. 1. "LSICON,Low speed internal oscillator control"
hexmask.long.byte 0x0 4.--7. 1. "HSICON,High speed internal oscillator control"
newline
hexmask.long.byte 0x0 0.--3. 1. "HSECON,External crystal main oscillator control"
line.long 0x4 "SCCR,System Clock Control register"
hexmask.long.word 0x4 16.--31. 1. "WTIDKY,On writes  write 0x570A to these bits  otherwise the write is ignored."
bitfld.long 0x4 2. "FINSEL,PLL input source FIN select register" "0,1"
newline
bitfld.long 0x4 0.--1. "MCLKSEL,System clock select register" "0,1,2,3"
line.long 0x8 "CMR,Clock Monitoring register"
bitfld.long 0x8 15. "MCLKREC,MCLK fail auto recovery" "0,1"
bitfld.long 0x8 11. "LSEMNT,External sub oscillator monitoring enable" "0,1"
newline
bitfld.long 0x8 10. "LSEIE,External sub oscillator fail interrupt enable" "0,1"
bitfld.long 0x8 9. "LSEFAIL,External sub oscillator fail interrupt" "0,1"
newline
bitfld.long 0x8 8. "LSESTS,External sub oscillator status" "0,1"
bitfld.long 0x8 7. "MCLKMNT,MCLK monitoring enable" "0,1"
newline
bitfld.long 0x8 6. "MCLKIE,MCLK fail interrupt enable" "0,1"
bitfld.long 0x8 5. "MCLKFAIL,MCLK fail interrupt" "0,1"
newline
bitfld.long 0x8 4. "MCLKSTS,MCLK clock status" "0,1"
bitfld.long 0x8 3. "HSEMNT,External main oscillator monitoring enable" "0,1"
newline
bitfld.long 0x8 2. "HSEIE,External main oscillator fail interrupt enable" "0,1"
bitfld.long 0x8 1. "HSEFAIL,External main oscillator fail interrupt" "0,1"
newline
bitfld.long 0x8 0. "HSESTS,External main oscillator status" "0,1"
line.long 0xC "NMIR,NMI control register"
hexmask.long.word 0xC 16.--31. 1. "ACCESSCODE,This field enables writing access to this register."
rbitfld.long 0xC 10. "WDTINTSTS,WDT Interrupt condition status bit" "0,1"
newline
rbitfld.long 0xC 9. "MCLKFAILSTS,MCLK Fail condition status bit" "0,1"
rbitfld.long 0xC 8. "LVDSTS,LVD condition status bit" "0,1"
newline
bitfld.long 0xC 2. "WDTINTEN,WDT Interrupt condition enable for NMI interrupt" "0,1"
bitfld.long 0xC 1. "MCLKFAILEN,MCLK Fail condition enable for NMI interrupt" "0,1"
newline
bitfld.long 0xC 0. "LVDEN,LVD Fail condition enable for NMI interrupt" "0,1"
line.long 0x10 "COR,Clock Output Control register"
bitfld.long 0x10 4. "CLKOEN,Clock output enable" "0,1"
hexmask.long.byte 0x10 0.--3. 1. "CLKODIV,Clock output divider value"
group.long 0x60++0xF
line.long 0x0 "PLLCON,PLL Control register"
rbitfld.long 0x0 31. "LOCK,LOCK status" "0,1"
rbitfld.long 0x0 30. "TIMEOUT,PLL timeout" "0,1"
newline
bitfld.long 0x0 23. "PLLRSTB,PLL reset" "0,1"
bitfld.long 0x0 22. "PLLEN,PLL enable" "0,1"
newline
bitfld.long 0x0 21. "BYPASSB,FIN bypass" "0,1"
bitfld.long 0x0 20. "PLLMODE,PLL VCO mode" "0,1"
newline
bitfld.long 0x0 16.--18. "PREDIV,FIN predivider" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--15. 1. "POSTDIV1,Feedback control 1 (N1)"
newline
hexmask.long.byte 0x0 4.--7. 1. "POSTDIV2,Feedback control 1 (N2)"
bitfld.long 0x0 0.--2. "OUTDIV,output divider control (P)" "0,1,2,3,4,5,6,7"
line.long 0x4 "VDCCON,VDC Control register"
hexmask.long.byte 0x4 20.--23. 1. "VDC15_WTIDKY,VDC15 Write Identification Key"
bitfld.long 0x4 19. "VDC15_PDBGR,VDC15 1.2V BGR / 1.0V Buffer Power Down Signal" "0,1"
newline
bitfld.long 0x4 17. "VDC15_STOP,VDC15 STOP Mode Control Signal" "0,1"
bitfld.long 0x4 16. "VDC15_IDLE,VDC15 STOP1 Mode Control Signal" "0,1"
newline
bitfld.long 0x4 15. "VDC15_LOCK,VDC15 VDCLOCK Control Signal for *BGR Stabilization" "0,1"
bitfld.long 0x4 8. "VDCWDLY_WEN,VDCWDLY value write enable. VDCWDLY value can be written with writing '1' to VDCWDLY_WEN bit simultaneously." "0,1"
newline
hexmask.long.byte 0x4 0.--6. 1. "VDCWDLY,VDC warm-up delay count value."
line.long 0x8 "TIRCCON,On chip Internal IRC for Touch control register"
bitfld.long 0x8 0. "TIRCON,Touch IRC Control signal" "0,1"
line.long 0xC "LSICON,LSI Control Register"
bitfld.long 0xC 1. "EN_LDO,Internal LDO On/Off" "0,1"
bitfld.long 0xC 0. "SKIP_LS,Internal Level Shifter control signal" "0,1"
group.long 0x80++0x3
line.long 0x0 "EOSCR,External Oscillator control register"
bitfld.long 0x0 15. "ESEN,Write enable for External SOSC" "0,1"
bitfld.long 0x0 12.--13. "ESISEL,Internal Level Shifter control signal" "0,1,2,3"
newline
bitfld.long 0x0 8. "ESNCBYPS,Noise Cancel Bypass enable for External SOSC" "0,1"
bitfld.long 0x0 7. "EMEN,Write enable for External MOSC" "0,1"
newline
bitfld.long 0x0 4.--5. "ISE,Select current for External MOSC" "0,1,2,3"
bitfld.long 0x0 2.--3. "NCOPT,Noise Cancel delay Option for External MOSC" "0,1,2,3"
newline
bitfld.long 0x0 0. "NCSKIP,Noise Cancel Bypass enable for External SOSC" "0,1"
rgroup.long 0x84++0x3
line.long 0x0 "EMODR,External mode pin read register"
bitfld.long 0x0 0. "BOOT,BOOT pin level" "0,1"
group.long 0x88++0x3
line.long 0x0 "RSTDBCR,Pin Reset Debounce Control Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key"
hexmask.long.byte 0x0 8.--13. 1. "CLKCNT,Noise Cancel delay Option for LSI"
newline
bitfld.long 0x0 0. "EN,Pin reset debounce enable bit" "0,1"
group.long 0x90++0x17
line.long 0x0 "MCCR1,Miscellaneous Clock Control Register 1"
bitfld.long 0x0 24.--26. "TEXT1CSEL,TIMER1n EXT Clock source select bit" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--23. 1. "TEXT1DIV,TIMER1n EXT Clock N divider"
newline
bitfld.long 0x0 8.--10. "STCSEL,systick clock source sel" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--7. 1. "STDIV,SYSTICK Clock N divider"
line.long 0x4 "MCCR2,Miscellaneous Clock Control Register 2"
bitfld.long 0x4 24.--26. "TEXT3CSEL,TIMER 30 EXT Clock source select bit" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 16.--23. 1. "TEXT3DIV,TIMER 30 EXT Clock N divider"
newline
bitfld.long 0x4 8.--10. "TEXT2CSEL,TEXT2CSEL" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 0.--7. 1. "TEXT2DIV,TIMER 20 EXT Clock N divider"
line.long 0x8 "MCCR3,Miscellaneous Clock Control Register 3"
bitfld.long 0x8 24.--26. "WTEXTCSEL,WTEXTCSEL" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 16.--23. 1. "WTEXTCDIV,WT External Clock N divider"
newline
bitfld.long 0x8 8.--10. "WDTCSEL,WDT clock sel" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--7. 1. "WDTDIV,WDT Clock N divider"
line.long 0xC "MCCR4,Miscellaneous Clock Control Register 4"
bitfld.long 0xC 24.--26. "PD1CSEL,Debounce Clock for PORT source select bit (PD PE PF)" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 16.--23. 1. "PD1DIV,PORT Debounce Clock N divider (PD PE PF)"
newline
bitfld.long 0xC 8.--10. "PD0CSEL,Debounce Clock for PORT source select bit (PA PB PC)" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 0.--7. 1. "PD0DIV,PORT Debounce Clock N divider (PA PB PC)"
line.long 0x10 "MCCR5,Miscellaneous Clock Control Register 5"
bitfld.long 0x10 24.--26. "LCDCSEL,LCD Clock source select bit" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 16.--23. 1. "LCDDIV,LCD Clock N divider"
newline
bitfld.long 0x10 8.--10. "LEDCSEL,LED Clock source select bit" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 0.--7. 1. "LEDDIV,LED Clock N divider"
line.long 0x14 "MCCR6,Miscellaneous Clock Control Register 6"
bitfld.long 0x14 14.--15. "TS_REF_SEL,Temp-Sensor reference clock selection" "0,1,2,3"
bitfld.long 0x14 12.--13. "TS_CLK_SEL,Temp-Sensor clock selection" "0,1,2,3"
newline
bitfld.long 0x14 11. "LSI_TS_EN,Temp-Sensor Oscillator enable selection" "0,1"
tree.end
tree "SCUCC"
base ad:0x4000F000
rgroup.long 0x0++0xB
line.long 0x0 "VENDORID,Vendor Identification Register"
hexmask.long 0x0 0.--31. 1. "VENDID,Vendor Identification bits"
line.long 0x4 "CHIPID,Chip Identification Register"
hexmask.long 0x4 0.--31. 1. "CHIPID,Chip Identification bits. 0x4D31A01E: 256KB flash memory for program"
line.long 0x8 "REVNR,Revision Number Register"
hexmask.long.byte 0x8 0.--7. 1. "REVNO,Chip Revision Number. These bits are fixed by manufacturer."
tree.end
tree "SCULV"
base ad:0x40005100
group.long 0x0++0xB
line.long 0x0 "LVICR,Low Voltage Indicator Control Register"
bitfld.long 0x0 7. "LVIEN,LVI Enable bit" "0,1"
bitfld.long 0x0 5. "LVINTEN,LVI Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "LVIFLAG,LVI Interrupt Flag bit" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "LVIVS,LVI Voltage Selection bits"
line.long 0x4 "LVRCR,Low Voltage Reset Control Register"
hexmask.long.byte 0x4 0.--7. 1. "LVREN,LVR Enable bits"
line.long 0x8 "LVRCNFIG,Configuration for Low Voltage Reset"
hexmask.long.word 0x8 16.--31. 1. "WTIDKY,Write Identification Key"
hexmask.long.byte 0x8 8.--15. 1. "LVRENM,LVR Reset Operation Control Master Configuration"
hexmask.long.byte 0x8 0.--3. 1. "LVRVS,LVR Voltage Selection bits"
tree.end
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
tree "SPI20"
base ad:0x40004C00
wgroup.long 0x0++0x3
line.long 0x0 "TDR,SPI2 n Transmit Data Register"
hexmask.long.tbyte 0x0 0.--16. 1. "TDR,Transmit Data Bit"
rgroup.long 0x0++0x3
line.long 0x0 "RDR,SPI n Received Data Register"
hexmask.long.tbyte 0x0 0.--16. 1. "RDR,Received Data Bit"
group.long 0x4++0x13
line.long 0x0 "CR,SPI Control Register"
bitfld.long 0x0 20. "TXBC,Tx Buffer Clear Bit" "0,1"
bitfld.long 0x0 19. "RXBC,Rx Buffer Clear Bit" "0,1"
bitfld.long 0x0 18. "TXDIE,DMA Tx Complete Interrupt Enable Bit" "0,1"
bitfld.long 0x0 17. "RXDIE,DMA Rx Complete Interrupt Enable Bit" "0,1"
bitfld.long 0x0 16. "SSCIE,SS Edge Changed Interrupt Enable Bit" "0,1"
bitfld.long 0x0 15. "TXIE,Transmit Interrupt Enable Bit" "0,1"
bitfld.long 0x0 14. "RXIE,Received Interrupt Enable Bit" "0,1"
bitfld.long 0x0 13. "SSMOD,SS Auto/Manual Output Selection Bit in Master Mode" "0,1"
bitfld.long 0x0 12. "SSOUT,SS Output Signal Control Bit" "0,1"
bitfld.long 0x0 11. "LBE,Loop-back Mode Selection Bit in Master Mode" "0,1"
bitfld.long 0x0 10. "SSMASK,SS Signal Masking in Slave Mode" "0,1"
newline
bitfld.long 0x0 9. "SSMO,SS Output Signal Selection Bit" "0,1"
bitfld.long 0x0 8. "SSPOL,SS Signal Polarity Selection Bit" "0,1"
bitfld.long 0x0 5. "MS,Master/Slave Selection Bit" "0,1"
bitfld.long 0x0 4. "MSBF,MSB/LSB Transmit Advance Selection Bit" "0,1"
bitfld.long 0x0 3. "CPHA,SPI Clock Phase Bit" "0,1"
bitfld.long 0x0 2. "CPOL,SPI Clock Polarity Bit" "0,1"
bitfld.long 0x0 0.--1. "BITSZ,Transmit/Receive Bit Size Selection Bit" "0: Size is 8 bit,1: Size is 9 bit,2: Size is 16 bit,3: Size is 17 bit"
line.long 0x4 "SR,SPI n Status Register"
bitfld.long 0x4 9. "TXDMAF,DMA Transmit Operation Complete Flag" "0,1"
bitfld.long 0x4 8. "RXDMAF,DMA Received Operation Complete Flag" "0,1"
rbitfld.long 0x4 7. "SBUSY,Transmit/Received Operating Flag" "0,1"
bitfld.long 0x4 6. "SSDET,SS Signal Rising or Falling Edge Detected Flag" "0,1"
bitfld.long 0x4 5. "SSON,SS Signal Status Flag" "0,1"
bitfld.long 0x4 4. "OVRF,Received Overrun Error Flag" "0,1"
bitfld.long 0x4 3. "UDRF,Transmit Underrun Error Flag" "0,1"
rbitfld.long 0x4 2. "TXIDLE,Transmit Operating Flag" "0,1"
rbitfld.long 0x4 1. "TRDY,Transmit Buffer Empty Flag" "0,1"
rbitfld.long 0x4 0. "RRDY,Received Buffer Empty Flag" "0,1"
line.long 0x8 "BR,SPI n Baud Rate Register"
hexmask.long.word 0x8 0.--15. 1. "BR,Baud Rate Setting Bit"
line.long 0xC "EN,SPI n Enable Register"
bitfld.long 0xC 0. "ENABLE,SPI Enable Bit" "0,1"
line.long 0x10 "LR,SPI n Delay Length Register"
hexmask.long.byte 0x10 16.--23. 1. "SPL,SPI STOP Length Value Bit"
hexmask.long.byte 0x10 8.--15. 1. "BTL,SPI Burst Length Value Bit"
hexmask.long.byte 0x10 0.--7. 1. "STL,SPI Start Length Value Bit"
tree.end
tree "SPI21"
base ad:0x40004D00
wgroup.long 0x0++0x3
line.long 0x0 "TDR,SPI2 n Transmit Data Register"
hexmask.long.tbyte 0x0 0.--16. 1. "TDR,Transmit Data Bit"
rgroup.long 0x0++0x3
line.long 0x0 "RDR,SPI n Received Data Register"
hexmask.long.tbyte 0x0 0.--16. 1. "RDR,Received Data Bit"
group.long 0x4++0x13
line.long 0x0 "CR,SPI Control Register"
bitfld.long 0x0 20. "TXBC,Tx Buffer Clear Bit" "0,1"
bitfld.long 0x0 19. "RXBC,Rx Buffer Clear Bit" "0,1"
bitfld.long 0x0 18. "TXDIE,DMA Tx Complete Interrupt Enable Bit" "0,1"
bitfld.long 0x0 17. "RXDIE,DMA Rx Complete Interrupt Enable Bit" "0,1"
bitfld.long 0x0 16. "SSCIE,SS Edge Changed Interrupt Enable Bit" "0,1"
bitfld.long 0x0 15. "TXIE,Transmit Interrupt Enable Bit" "0,1"
bitfld.long 0x0 14. "RXIE,Received Interrupt Enable Bit" "0,1"
bitfld.long 0x0 13. "SSMOD,SS Auto/Manual Output Selection Bit in Master Mode" "0,1"
bitfld.long 0x0 12. "SSOUT,SS Output Signal Control Bit" "0,1"
bitfld.long 0x0 11. "LBE,Loop-back Mode Selection Bit in Master Mode" "0,1"
bitfld.long 0x0 10. "SSMASK,SS Signal Masking in Slave Mode" "0,1"
newline
bitfld.long 0x0 9. "SSMO,SS Output Signal Selection Bit" "0,1"
bitfld.long 0x0 8. "SSPOL,SS Signal Polarity Selection Bit" "0,1"
bitfld.long 0x0 5. "MS,Master/Slave Selection Bit" "0,1"
bitfld.long 0x0 4. "MSBF,MSB/LSB Transmit Advance Selection Bit" "0,1"
bitfld.long 0x0 3. "CPHA,SPI Clock Phase Bit" "0,1"
bitfld.long 0x0 2. "CPOL,SPI Clock Polarity Bit" "0,1"
bitfld.long 0x0 0.--1. "BITSZ,Transmit/Receive Bit Size Selection Bit" "0: Size is 8 bit,1: Size is 9 bit,2: Size is 16 bit,3: Size is 17 bit"
line.long 0x4 "SR,SPI n Status Register"
bitfld.long 0x4 9. "TXDMAF,DMA Transmit Operation Complete Flag" "0,1"
bitfld.long 0x4 8. "RXDMAF,DMA Received Operation Complete Flag" "0,1"
rbitfld.long 0x4 7. "SBUSY,Transmit/Received Operating Flag" "0,1"
bitfld.long 0x4 6. "SSDET,SS Signal Rising or Falling Edge Detected Flag" "0,1"
bitfld.long 0x4 5. "SSON,SS Signal Status Flag" "0,1"
bitfld.long 0x4 4. "OVRF,Received Overrun Error Flag" "0,1"
bitfld.long 0x4 3. "UDRF,Transmit Underrun Error Flag" "0,1"
rbitfld.long 0x4 2. "TXIDLE,Transmit Operating Flag" "0,1"
rbitfld.long 0x4 1. "TRDY,Transmit Buffer Empty Flag" "0,1"
rbitfld.long 0x4 0. "RRDY,Received Buffer Empty Flag" "0,1"
line.long 0x8 "BR,SPI n Baud Rate Register"
hexmask.long.word 0x8 0.--15. 1. "BR,Baud Rate Setting Bit"
line.long 0xC "EN,SPI n Enable Register"
bitfld.long 0xC 0. "ENABLE,SPI Enable Bit" "0,1"
line.long 0x10 "LR,SPI n Delay Length Register"
hexmask.long.byte 0x10 16.--23. 1. "SPL,SPI STOP Length Value Bit"
hexmask.long.byte 0x10 8.--15. 1. "BTL,SPI Burst Length Value Bit"
hexmask.long.byte 0x10 0.--7. 1. "STL,SPI Start Length Value Bit"
tree.end
tree.end
tree "TC (Timer/Counter)"
base ad:0x0
tree "TIMER10"
base ad:0x40002100
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER11"
base ad:0x40002200
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER12"
base ad:0x40002300
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER13"
base ad:0x40002700
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER20"
base ad:0x40002500
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 9.--10. "CAPSEL,Timer n Capture Signal Selection bits" "0,1,2,3"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
newline
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long 0x4 0.--31. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x00000000 to 0xFFFFFFFF. Note: Do not write '00000000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long 0x8 0.--31. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x00000000 to 0xFFFFFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long 0x0 0.--31. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits.P"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER21"
base ad:0x40002600
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 9.--10. "CAPSEL,Timer n Capture Signal Selection bits" "0,1,2,3"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
newline
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long 0x4 0.--31. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x00000000 to 0xFFFFFFFF. Note: Do not write '00000000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long 0x8 0.--31. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x00000000 to 0xFFFFFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long 0x0 0.--31. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits.P"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER30"
base ad:0x40002400
group.long 0x0++0x13
line.long 0x0 "CR,Timer/Counter 30 Control Register"
bitfld.long 0x0 15. "T30EN,Timer 30 Operation Enable bit" "0: Disable timer 30 operation,1: Enable timer 30 operation (Counter clear and.."
bitfld.long 0x0 14. "T30CLK,Timer 30 Clock Selection bit (Note: This bit should be changed during T30EN bit is '0b'.)" "0: Select an internal prescaler clock,1: Select an external clock"
newline
bitfld.long 0x0 12.--13. "T30MS,Timer 30 Operation Mode Selection bits (Note: These bits should be changed during T30EN bit is '0b'.)" "0: Interval mode (All match interrupts can occur),1: Capture mode (The Period-match interrupt can..,2: Back-to-back mode (All interrupts can occur),?"
bitfld.long 0x0 11. "T30ECE,Timer 30 External Clock Edge Selection bit" "0,1"
newline
bitfld.long 0x0 10. "FORCA,Timer 30 Output Mode Selection bit. This bit should be changed when the T30EN is '0b'. Note: If this bit is changed on operation  it shall apply from the next period." "0,1"
bitfld.long 0x0 9. "DLYEN,Delay Time Insertion Enable bit" "0,1"
newline
bitfld.long 0x0 8. "DLYPOS,Delay Time Insertion Position" "0,1"
bitfld.long 0x0 6.--7. "T30CPOL,Timer 30 Capture Polarity Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "UPDT,Data Reload Time Selection bits" "0,1,2,3"
bitfld.long 0x0 1.--3. "PMOC,Period Match Interrupt Occurrence Selection (Note: A period match counter is cleared as 0x00 when the T3nCLR bit is set or the PMOC[2:0] bits are changed.)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "T30CLR,Timer 30 Counter and Prescaler Clear bit" "0: No effect,1: Clear timer 30 counter and prescaler.."
line.long 0x4 "PDR,Timer/Counter 30 Period Data Register"
hexmask.long.word 0x4 0.--15. 1. "PDATA,Timer/Counter 30 Period Data bits. The range is 0x0002 to 0xFFFF."
line.long 0x8 "ADR,Timer/Counter 30 A Data Register"
hexmask.long.word 0x8 0.--15. 1. "ADATA,Timer/Counter 30 A Data bits. The range is 0x0000 to 0xFFFF."
line.long 0xC "BDR,Timer/Counter 30 B Data Register"
hexmask.long.word 0xC 0.--15. 1. "BDATA,Timer/Counter 30 B Data bits. The range is 0x0000 to 0xFFFF."
line.long 0x10 "CDR,Timer/Counter 30 C Data Register"
hexmask.long.word 0x10 0.--15. 1. "CDATA,Timer/Counter 30 C Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0x14++0x3
line.long 0x0 "CAPDR,Timer/Counter 30 Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter 30 Capture Data bits."
group.long 0x18++0x3
line.long 0x0 "PREDR,Timer/Counter 30 Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter 30 Prescaler Data bits."
rgroup.long 0x1C++0x3
line.long 0x0 "CNT,Timer/Counter 30 Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter 30 Counter bits."
group.long 0x20++0x1B
line.long 0x0 "OUTCR,Timer/Counter 30 Output Control Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes  write 0xE06C to these bits  otherwise the write is ignored."
bitfld.long 0x0 15. "POLB,PWM30xB Output Polarity Selection bit" "0,1"
newline
bitfld.long 0x0 14. "POLA,PWM30xA Output Polarity Selection bit" "0,1"
bitfld.long 0x0 13. "PABOE,PWM30AB Output Enable bit" "0,1"
newline
bitfld.long 0x0 12. "PBBOE,PWM30BB Output Enable bit" "0,1"
bitfld.long 0x0 11. "PCBOE,PWM30CB Output Enable bit" "0,1"
newline
bitfld.long 0x0 10. "PAAOE,PWM30AA Output Enable bit" "0,1"
bitfld.long 0x0 9. "PBAOE,PWM30BA Output Enable bit" "0,1"
newline
bitfld.long 0x0 8. "PCAOE,PWM30CA Output Enable bit" "0,1"
bitfld.long 0x0 6. "LVLAB,Configure PWM30AB output When Disable" "0,1"
newline
bitfld.long 0x0 5. "LVLBB,Configure PWM30BB output When Disable" "0,1"
bitfld.long 0x0 4. "LVLCB,Configure PWM30CB output When Disable" "0,1"
newline
bitfld.long 0x0 2. "LVLAA,Configure PWM30AA output When Disable" "0,1"
bitfld.long 0x0 1. "LVLBA,Configure PWM30BA output When Disable" "0,1"
newline
bitfld.long 0x0 0. "LVLCA,Configure PWM30CA output When Disable" "0,1"
line.long 0x4 "DLY,Timer/Counter 30 PWM Output Delay Data Register"
hexmask.long.word 0x4 0.--9. 1. "DLY,Timer/Counter 30 PWM Delay Data bits. Delay time: DLY[9:0]/fT30"
line.long 0x8 "INTCR,Timer/Counter 30 Interrupt Control Register"
bitfld.long 0x8 6. "HIZIEN,Timer 30 Output High-Impedance Interrupt Enable bit" "0,1"
bitfld.long 0x8 5. "T30CIEN,Timer 30 Capture Interrupt Enable bit" "0,1"
newline
bitfld.long 0x8 4. "T30BTIEN,Timer 30 Bottom Interrupt Enable bit" "0,1"
bitfld.long 0x8 3. "T30PMIEN,Timer 30 Period Match Interrupt Enable bit" "0,1"
newline
bitfld.long 0x8 2. "T30AMIEN,Timer 30 A-ch Match Interrupt Enable bit" "0,1"
bitfld.long 0x8 1. "T30BMIEN,Timer 30 B-ch Match Interrupt Enable bit" "0,1"
newline
bitfld.long 0x8 0. "T30CMIEN,Timer 30 C-ch Match Interrupt Enable bit" "0,1"
line.long 0xC "INTFLAG,Timer/Counter 30 Interrupt Flag Register"
bitfld.long 0xC 6. "HIZIFLAG,Timer 30 Output High-Impedance Interrupt Flag bit" "0,1"
bitfld.long 0xC 5. "T30CIFLAG,Timer 30 Capture Interrupt Flag bit" "0,1"
newline
bitfld.long 0xC 4. "T30BTIFLAG,Timer 30 Bottom Interrupt Flag bit" "0,1"
bitfld.long 0xC 3. "T30PMIFLAG,Timer 30 Period Match Interrupt Flag bit" "0,1"
newline
bitfld.long 0xC 2. "T30AMIFLAG,Timer 30 A-ch Match Interrupt Flag bit" "0,1"
bitfld.long 0xC 1. "T30BMIFLAG,Timer 30 B-ch Match Interrupt Flag bit" "0,1"
newline
bitfld.long 0xC 0. "T30CMIFLAG,Timer 30 C-ch Match Interrupt Flag bit" "0,1"
line.long 0x10 "HIZCR,Timer/Counter 30 High-Impedance Control Register"
bitfld.long 0x10 7. "HIZEN,PWM30xA/PWM30xB Output High-Impedance Enable bit" "0,1"
bitfld.long 0x10 4. "HIZSW,High-Impedance Output Software Setting" "0,1"
newline
bitfld.long 0x10 2. "HEDGE,High-Impedance Edge Selection" "0,1"
rbitfld.long 0x10 1. "HIZSTA,High-Impedance Status" "0,1"
newline
bitfld.long 0x10 0. "HIZCLR,High-Impedance Output Clear bit" "0,1"
line.long 0x14 "ADTCR,Timer/Counter 30 A/DC Trigger Control Register"
bitfld.long 0x14 4. "T30BTTG,Select Timer 30 Bottom for A/DC Trigger Signal Generator" "0,1"
bitfld.long 0x14 3. "T30PMTG,Select Timer 30 Period Match for A/DC Trigger Signal Generator" "0,1"
newline
bitfld.long 0x14 2. "T30AMTG,Select Timer 30 A-ch Match for A/DC Trigger Signal Generator" "0,1"
bitfld.long 0x14 1. "T30BMTG,Select Timer 30 B-ch Match for A/DC Trigger Signal Generator" "0,1"
newline
bitfld.long 0x14 0. "T30CMTG,Select Timer 30 C-ch Match for A/DC Trigger Signal Generator" "0,1"
line.long 0x18 "ADTDR,Timer/Counter 30 A/DC Trigger Generator Data Register"
hexmask.long.word 0x18 0.--13. 1. "ADTDATA,Timer/Counter 30 A/DC Trigger Generation Data bits."
tree.end
tree.end
tree "TOUCH (Touch Sensor)"
base ad:0x40003600
rgroup.long 0x0++0xBF
line.long 0x0 "SUM_CH0_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x0 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x4 "SUM_CH0_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x4 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x8 "SUM_CH1_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x8 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0xC "SUM_CH1_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0xC 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x10 "SUM_CH2_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x10 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x14 "SUM_CH2_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x14 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x18 "SUM_CH3_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x18 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x1C "SUM_CH3_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x1C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x20 "SUM_CH4_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x20 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x24 "SUM_CH4_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x24 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x28 "SUM_CH5_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x28 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x2C "SUM_CH5_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x2C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x30 "SUM_CH6_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x30 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x34 "SUM_CH6_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x34 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x38 "SUM_CH7_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x38 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x3C "SUM_CH7_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x3C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x40 "SUM_CH8_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x40 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x44 "SUM_CH8_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x44 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x48 "SUM_CH9_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x48 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x4C "SUM_CH9_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x4C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x50 "SUM_CH10_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x50 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x54 "SUM_CH10_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x54 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x58 "SUM_CH11_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x58 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x5C "SUM_CH11_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x5C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x60 "SUM_CH12_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x60 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x64 "SUM_CH12_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x64 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x68 "SUM_CH13_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x68 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x6C "SUM_CH13_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x6C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x70 "SUM_CH14_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x70 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x74 "SUM_CH14_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x74 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x78 "SUM_CH15_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x78 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x7C "SUM_CH15_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x7C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x80 "SUM_CH16_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x80 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x84 "SUM_CH16_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x84 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x88 "SUM_CH17_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x88 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x8C "SUM_CH17_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x8C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x90 "SUM_CH18_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x90 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x94 "SUM_CH18_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x94 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x98 "SUM_CH19_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x98 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0x9C "SUM_CH19_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x9C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0xA0 "SUM_CH20_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0xA0 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0xA4 "SUM_CH20_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0xA4 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0xA8 "SUM_CH21_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0xA8 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0xAC "SUM_CH21_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0xAC 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0xB0 "SUM_CH22_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0xB0 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0xB4 "SUM_CH22_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0xB4 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0xB8 "SUM_CH23_F0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0xB8 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
line.long 0xBC "SUM_CH23_F1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0xBC 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Frequency Sum Register"
group.long 0xC0++0x93
line.long 0x0 "SCO0,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x0 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x4 "SCO1,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x4 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x8 "SCO2,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x8 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0xC "SCO3,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0xC 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x10 "SCO4,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x10 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x14 "SCO5,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x14 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x18 "SCO6,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x18 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x1C "SCO7,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x1C 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x20 "SCO8,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x20 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x24 "SCO9,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x24 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x28 "SCO10,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x28 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x2C "SCO11,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x2C 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x30 "SCO12,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x30 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x34 "SCO13,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x34 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x38 "SCO14,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x38 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x3C "SCO15,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x3C 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x40 "SCO16,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x40 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x44 "SCO17,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x44 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x48 "SCO18,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x48 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x4C "SCO19,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x4C 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x50 "SCO20,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x50 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x54 "SCO21,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x54 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x58 "SCO22,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x58 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x5C "SCO23,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x5C 0.--12. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x60 "CON,Touch Sensor Control Register"
bitfld.long 0x60 3. "LED_FLAG,LED Start Signal Sensing" "0,1"
bitfld.long 0x60 2. "TS_IF,Touch Sensor Interrupt Flag" "0,1"
bitfld.long 0x60 0. "TS_RUN,Touch Sensor Enable" "0,1"
line.long 0x64 "MODE,Touch Sensor Mode Register"
bitfld.long 0x64 15. "SADJ_OPT,Channel-Adjust path enable" "0,1"
bitfld.long 0x64 8. "LED_FLAG_EN,LED FLAG enable bit" "0,1"
bitfld.long 0x64 7. "PORT_OPT,Determine the channel and timing to apply PORT[1:0]" "0,1"
newline
bitfld.long 0x64 6. "SC_GAIN,Gain Calibration Capacitor Enable" "0: Gain Calibration Capacitor Disable,1: Gain Calibration Capacitor Enable"
bitfld.long 0x64 5. "S1_SWEEP_FIX,S1 width sweep fix" "0: S1 width = TS_S1_WIDTH + random value,1: S1 width = TS_S1_WIDTH"
bitfld.long 0x64 2.--4. "MODE,Touch Sensor Mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x64 0.--1. "PORT,Port Configuration During Inactive Status" "0: Input Floating,1: Output Low,?,?"
line.long 0x68 "SUM_CNT,Touch Sensor Sum Repeat Count Register"
hexmask.long.byte 0x68 0.--7. 1. "TS_SUM_CNT,Touch Sensor Sum Repeat Count"
line.long 0x6C "CH_SEL,Touch Sensor Channel Selection Register"
bitfld.long 0x6C 23. "CH23_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 22. "CH22_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 21. "CH21_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0x6C 20. "CH20_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 19. "CH19_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 18. "CH18_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0x6C 17. "CH17_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 16. "CH16_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 15. "CH15_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0x6C 14. "CH14_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 13. "CH13_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 12. "CH12_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0x6C 11. "CH11_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 10. "CH10_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 9. "CH9_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0x6C 8. "CH8_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 7. "CH7_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 6. "CH6_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0x6C 5. "CH5_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 4. "CH4_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 3. "CH3_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0x6C 2. "CH2_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 1. "CH1_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0x6C 0. "CH0_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
line.long 0x70 "S1_WIDTH,Touch Sensor Sum Repeat Count Register"
hexmask.long.byte 0x70 0.--7. 1. "TS_S1_WIDTH,Touch Sensor Sum Repeat Count"
line.long 0x74 "SLP_CON,Touch Sensor Low Pass Filter Control Register"
hexmask.long.byte 0x74 4.--7. 1. "SLP_C,Capacitor Trimming for Input Low Pass Filter"
hexmask.long.byte 0x74 0.--3. 1. "SLP_R,Resistor Trimming for Input Low Pass Filter"
line.long 0x78 "TRIM,Touch Sensor Trimming Register"
bitfld.long 0x78 4. "HC,High Current Enable" "0,1"
hexmask.long.byte 0x78 0.--3. 1. "IB_TRIM,Current Bias Trimming Value"
line.long 0x7C "CLK_CFG,Touch Sensor Clock Configuration Register"
bitfld.long 0x7C 7. "SCLK_EN,Select touch clock source" "0,1"
bitfld.long 0x7C 4.--5. "CLKSEL,Touch Clock source select" "0,1,2,3"
bitfld.long 0x7C 3. "TSCLKOE,Divided Touch Sensor Clock Output Enable" "0,1"
newline
bitfld.long 0x7C 0.--2. "TSCLKDIV,Touch Sensor Clock Divider(Refer to TRIM_OSC)" "0,1,2,3,4,5,6,7"
line.long 0x80 "TRIM_OSC,Touch Sensor RING Oscillator Trimming Selection Register"
hexmask.long.byte 0x80 0.--7. 1. "TRIM_OSC,Touch Sensor RING Oscillator Trimming Selection"
line.long 0x84 "DELTA_OSC,Touch Sensor RING Oscillator Delta Register"
hexmask.long.byte 0x84 0.--5. 1. "TS_DELTA_OSC,Frequency of Touch clock A = 16MHz+((TRIM_OSC_+DELTA_OSC-20H)*0.25%"
line.long 0x88 "TLED,LED stable time Register"
hexmask.long.word 0x88 0.--11. 1. "TLED,LED stable Time"
line.long 0x8C "VHS,Touch Sensor High Sense Voltage Register"
hexmask.long.word 0x8C 0.--9. 1. "VHS,Touch Sensor High Sense Voltage register"
line.long 0x90 "VREF,Touch Sensor COMP Reference Voltage Register"
hexmask.long.word 0x90 0.--9. 1. "VREF,Touch Sensor COMP Reference voltage register"
group.long 0x160++0x3
line.long 0x0 "SHLD_CON,Touch Sensor Shield Channel Control Register"
bitfld.long 0x0 31. "MESH,Shield mesh enable bit" "0,1"
bitfld.long 0x0 30. "MESH_ADD,Additional shield mesh enable bit" "0,1"
bitfld.long 0x0 29. "MODE,Shield mode bit" "0,1"
newline
bitfld.long 0x0 24. "SHLD_EN,Shield enable bit" "0,1"
hexmask.long.tbyte 0x0 0.--23. 1. "SHLD_Chx,Shield channel selection bits"
tree.end
tree "TSENSE (Temp Sensor)"
base ad:0x40006300
group.long 0x0++0x7
line.long 0x0 "CR,Temp sensor control register"
bitfld.long 0x0 8. "INTEN,Temp sensor interrupt enable" "0,1"
bitfld.long 0x0 0. "START,Start reference clock counting" "0,1"
line.long 0x4 "RCCNT,Temp sensor reference clock counter register"
hexmask.long 0x4 0.--31. 1. "RCCV,Reference clock counter initial value"
rgroup.long 0x8++0x3
line.long 0x0 "SCCNT,Temp sensor sensing clock counter register"
hexmask.long 0x0 0.--31. 1. "SCCV,Temp sensor counter value"
group.long 0xC++0x3
line.long 0x0 "SR,Temp sensor status register"
bitfld.long 0x0 8. "DONE,Reference clock counting is running" "0,1"
rbitfld.long 0x0 0. "BUSY,The status of the reference clock counter" "0,1"
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "UART0"
base ad:0x40004000
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receive Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,recevied/transmit data"
wgroup.long 0x0++0x3
line.long 0x0 "THR,Transmit Data Hold Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,recevied/transmit data"
group.long 0x4++0x13
line.long 0x0 "IER,UART Interrupt Enable Register"
bitfld.long 0x0 5. "DTXIEN,DMA transmit done interrupt enable" "0,1"
bitfld.long 0x0 4. "DRXIEN,DMA Receiver line status interrupt enable" "0,1"
bitfld.long 0x0 3. "TXEIE,Transmit Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 2. "RLSIE,receiver line status interrupt enable" "0,1"
bitfld.long 0x0 1. "THREIE,Transmit holding register empty interrupt enable" "0,1"
bitfld.long 0x0 0. "DRIE,Data receive interrupt enable" "0,1"
line.long 0x4 "IIR,UART Interrupt ID Register"
bitfld.long 0x4 4. "TXE,Interrupt source ID" "0,1"
bitfld.long 0x4 1.--2. "IID,Interrupt source ID" "0,1,2,3"
bitfld.long 0x4 0. "IPEN,Interrupt pending bit" "0,1"
line.long 0x8 "LCR,UART Line Control Register"
bitfld.long 0x8 6. "BREAK,BREAK" "0,1"
bitfld.long 0x8 5. "STICKP,STICK" "0,1"
bitfld.long 0x8 4. "PARITY,PARITY" "0,1"
bitfld.long 0x8 3. "PEN,parity bit transfer enable" "0,1"
bitfld.long 0x8 2. "STOPBIT,STOPBIT" "0,1"
bitfld.long 0x8 0.--1. "DLEN,Data length in one transfer word" "0,1,2,3"
line.long 0xC "DCR,UART Data Control Register"
bitfld.long 0xC 4. "LBON,Local loopback test mode enable" "0,1"
bitfld.long 0xC 3. "RXINV,Rx Data Inversion selection" "0,1"
bitfld.long 0xC 2. "TXINV,TX Data Inversion selection" "0,1"
line.long 0x10 "LSR,UART Line Status Register"
bitfld.long 0x10 6. "TEMT,Transmit empty" "0,1"
bitfld.long 0x10 5. "THRE,Transmit holding register empty" "0,1"
bitfld.long 0x10 4. "BI,break condition indication bit" "0,1"
bitfld.long 0x10 3. "FE,frame error" "0,1"
bitfld.long 0x10 2. "PE,parity error" "0,1"
bitfld.long 0x10 1. "OE,overrun error" "0,1"
bitfld.long 0x10 0. "DR,Data recevied" "0,1"
group.long 0x20++0x7
line.long 0x0 "BDR,Baud rate Divisor Latch Register"
hexmask.long.word 0x0 0.--15. 1. "BDR,baudrate setting"
line.long 0x4 "BFR,Baud rate Fraction Counter Register"
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction counter value"
group.long 0x30++0x3
line.long 0x0 "IDTR,Inter-frame Delay Time Register"
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable bit" "0,1"
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
bitfld.long 0x0 0.--2. "WAITVAL,wait time is decied by this value" "0,1,2,3,4,5,6,7"
tree.end
tree "UART1"
base ad:0x40004100
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receive Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,recevied/transmit data"
wgroup.long 0x0++0x3
line.long 0x0 "THR,Transmit Data Hold Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,recevied/transmit data"
group.long 0x4++0x13
line.long 0x0 "IER,UART Interrupt Enable Register"
bitfld.long 0x0 5. "DTXIEN,DMA transmit done interrupt enable" "0,1"
bitfld.long 0x0 4. "DRXIEN,DMA Receiver line status interrupt enable" "0,1"
bitfld.long 0x0 3. "TXEIE,Transmit Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 2. "RLSIE,receiver line status interrupt enable" "0,1"
bitfld.long 0x0 1. "THREIE,Transmit holding register empty interrupt enable" "0,1"
bitfld.long 0x0 0. "DRIE,Data receive interrupt enable" "0,1"
line.long 0x4 "IIR,UART Interrupt ID Register"
bitfld.long 0x4 4. "TXE,Interrupt source ID" "0,1"
bitfld.long 0x4 1.--2. "IID,Interrupt source ID" "0,1,2,3"
bitfld.long 0x4 0. "IPEN,Interrupt pending bit" "0,1"
line.long 0x8 "LCR,UART Line Control Register"
bitfld.long 0x8 6. "BREAK,BREAK" "0,1"
bitfld.long 0x8 5. "STICKP,STICK" "0,1"
bitfld.long 0x8 4. "PARITY,PARITY" "0,1"
bitfld.long 0x8 3. "PEN,parity bit transfer enable" "0,1"
bitfld.long 0x8 2. "STOPBIT,STOPBIT" "0,1"
bitfld.long 0x8 0.--1. "DLEN,Data length in one transfer word" "0,1,2,3"
line.long 0xC "DCR,UART Data Control Register"
bitfld.long 0xC 4. "LBON,Local loopback test mode enable" "0,1"
bitfld.long 0xC 3. "RXINV,Rx Data Inversion selection" "0,1"
bitfld.long 0xC 2. "TXINV,TX Data Inversion selection" "0,1"
line.long 0x10 "LSR,UART Line Status Register"
bitfld.long 0x10 6. "TEMT,Transmit empty" "0,1"
bitfld.long 0x10 5. "THRE,Transmit holding register empty" "0,1"
bitfld.long 0x10 4. "BI,break condition indication bit" "0,1"
bitfld.long 0x10 3. "FE,frame error" "0,1"
bitfld.long 0x10 2. "PE,parity error" "0,1"
bitfld.long 0x10 1. "OE,overrun error" "0,1"
bitfld.long 0x10 0. "DR,Data recevied" "0,1"
group.long 0x20++0x7
line.long 0x0 "BDR,Baud rate Divisor Latch Register"
hexmask.long.word 0x0 0.--15. 1. "BDR,baudrate setting"
line.long 0x4 "BFR,Baud rate Fraction Counter Register"
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction counter value"
group.long 0x30++0x3
line.long 0x0 "IDTR,Inter-frame Delay Time Register"
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable bit" "0,1"
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
bitfld.long 0x0 0.--2. "WAITVAL,wait time is decied by this value" "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "USART10"
base ad:0x40003800
group.long 0x0++0x7
line.long 0x0 "CR1,USARTn Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
newline
bitfld.long 0x0 7. "CPOLn,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,(null)The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable bit" "0,1"
newline
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable bit" "0,1"
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-up Interrupt Enable bit in Deep Sleep Mode. When device is in deep sleep mode  if RXD goes to low level  an interrupt can be requested to wake-up system (only UART mode)" "0,1"
bitfld.long 0x0 1. "TXEn,Enables the Transmitter unit" "0,1"
bitfld.long 0x0 0. "RXEn,Enables the Receiver unit" "0,1"
line.long 0x4 "CR2,USARTn Control Register 2"
bitfld.long 0x4 9. "USTnEN,(nActivate USARTn Block by supplyingull)" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USARTn for test mode" "0,1"
newline
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation  selects the waveform of SCK output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS pin operation (only SPI mode)" "0,1"
bitfld.long 0x4 3. "FXCHn,SPI port function exchange control bit (only SPI mode)" "0,1"
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
newline
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USTnDR register" "0,1"
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USARTn Status Register"
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-up Interrupt Flag" "0,1"
newline
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun occurs" "0,1"
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
line.long 0x4 "BDR,USARTn Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode. To prevent malfunction  do not write '0' in UART mode and do not write '0' or '1' in synchronous or SPI mode."
line.long 0x8 "DR,USARTn Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the USTnDR register. Reading the USTnDR register returns the contents of the Receive.."
tree.end
tree "USART11"
base ad:0x40003900
group.long 0x0++0x7
line.long 0x0 "CR1,USARTn Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
newline
bitfld.long 0x0 7. "CPOLn,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,(null)The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable bit" "0,1"
newline
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable bit" "0,1"
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-up Interrupt Enable bit in Deep Sleep Mode. When device is in deep sleep mode  if RXD goes to low level  an interrupt can be requested to wake-up system (only UART mode)" "0,1"
bitfld.long 0x0 1. "TXEn,Enables the Transmitter unit" "0,1"
bitfld.long 0x0 0. "RXEn,Enables the Receiver unit" "0,1"
line.long 0x4 "CR2,USARTn Control Register 2"
bitfld.long 0x4 9. "USTnEN,(nActivate USARTn Block by supplyingull)" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USARTn for test mode" "0,1"
newline
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation  selects the waveform of SCK output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS pin operation (only SPI mode)" "0,1"
bitfld.long 0x4 3. "FXCHn,SPI port function exchange control bit (only SPI mode)" "0,1"
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
newline
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USTnDR register" "0,1"
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USARTn Status Register"
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-up Interrupt Flag" "0,1"
newline
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun occurs" "0,1"
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
line.long 0x4 "BDR,USARTn Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode. To prevent malfunction  do not write '0' in UART mode and do not write '0' or '1' in synchronous or SPI mode."
line.long 0x8 "DR,USARTn Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the USTnDR register. Reading the USTnDR register returns the contents of the Receive.."
tree.end
tree.end
tree "WDT (Watchdog Timer)"
base ad:0x40001A00
group.long 0x0++0xB
line.long 0x0 "CR,Watch-dog Timer Control Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes  write 0x5A69 to these bits  otherwise the write is ignored."
hexmask.long.byte 0x0 10.--15. 1. "RSTEN,Watch-dog Timer Reset Enable bits"
newline
hexmask.long.byte 0x0 4.--9. 1. "CNTEN,Watch-dog Timer Counter Enable bits"
bitfld.long 0x0 3. "WINMIEN,Watch-dog Timer Window Match Interrupt Enable bit" "0,1"
newline
bitfld.long 0x0 2. "UNFIEN,Watch-dog Timer Underflow Interrupt Enable bit" "0,1"
bitfld.long 0x0 0.--1. "CLKDIV,Watch-dog Timer Clock Divider bits  The clock which is selected by PPCLKSR[0]" "0,1,2,3"
line.long 0x4 "SR,Watch-dog Timer Status Register"
bitfld.long 0x4 7. "DBGCNTEN,Watch-dog Timer Counter Enable bit. When the core is halted in the debug mode. Note: This bit is cleared to '0b' only by POR reset." "0: The watch-dog timer counter continues even if..,1: The watch-dog timer counter is stopped when the.."
bitfld.long 0x4 1. "WINMIFLAG,Watch-dog Timer Window Match Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
newline
bitfld.long 0x4 0. "UNFIFLAG,Watch-dog Timer Underflow Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
line.long 0x8 "DR,Watch-dog Timer Data Register"
hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Watch-dog Timer Data bits. The range is 0x000000 to 0xFFFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CNT,Watch-dog Timer Counter Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Watch-dog Timer Counter bits."
group.long 0x10++0x3
line.long 0x0 "WINDR,Watch-dog Timer Window Data Register (Note: Once any value is written to this window data register. the register can't be changed until a system reset.)"
hexmask.long.tbyte 0x0 0.--23. 1. "WDATA,Watch-dog Timer Window Data bits. The range is 0x000000 to 0xFFFFFF."
wgroup.long 0x14++0x3
line.long 0x0 "CNTR,Watch-dog Timer Counter Reload Register"
hexmask.long.byte 0x0 0.--7. 1. "CNTR,Watch-dog Timer Counter Reload bits."
tree.end
tree "WT (Watch Timer)"
base ad:0x40002000
group.long 0x0++0x7
line.long 0x0 "CR,Watch Timer Control Register"
bitfld.long 0x0 7. "WTEN,Watch Timer Operation Enable bit" "0: Disable watch timer operation,1: Enable watch timer operation"
bitfld.long 0x0 4.--5. "WTINTV,Watch Timer Interval Selection bits." "0: fWT/2^7,1: fWT/2^13,2: fWT/2^14,3: fWT/(2^14x(WTDR value + 1))"
newline
bitfld.long 0x0 3. "WTIEN,Watch Timer Interrupt Enable bit" "0: Disable watch timer interrupt,1: Enable watch timer interrupt"
bitfld.long 0x0 1. "WTIFLAG,Watch Timer Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
newline
bitfld.long 0x0 0. "WTCLR,Watch Timer Counter and Divider Clear bit" "0: No effect,1: Clear the counter and divider (Automatically.."
line.long 0x4 "DR,Watch Timer Data Register"
hexmask.long.word 0x4 0.--11. 1. "WTDATA,Watch Timer Data bits. The range is 0x001 to 0xFFF."
rgroup.long 0x8++0x3
line.long 0x0 "CNT,Watch Timer Counter Register"
hexmask.long.word 0x0 0.--11. 1. "CNT,Watch Timer Counter bits."
tree.end
AUTOINDENT.OFF