; --------------------------------------------------------------------------------
; @Title: Zynq7000 Specific Menu
; @Props: Released
; @Author: SOL
; @Changelog: 2011-04-15 SOL
; @Manufacturer: XILINX - XILINX
; @Core: Cortex-A9
; @Chip: ZYNQ-7000
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menzynq7000.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-A9MPCore)"
(
menuitem "[:chip]ID Registers"                        "per , ""Core Registers (Cortex-A9MPCore),ID Registers"""
menuitem "[:chip]System Control and Configuration"    "per , ""Core Registers (Cortex-A9MPCore),System Control and Configuration"""
menuitem "[:chip]Memory Management Unit"              "per , ""Core Registers (Cortex-A9MPCore),Memory Management Unit"""
menuitem "[:chip]Cache Control and Configuration"     "per , ""Core Registers (Cortex-A9MPCore),Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor"          "per , ""Core Registers (Cortex-A9MPCore),System Performance Monitor"""
menuitem "[:chip]Preload Engine"                      "per , ""Core Registers (Cortex-A9MPCore),Preload Engine"""
menuitem "[:chip]NEON"                                "per , ""Core Registers (Cortex-A9MPCore),NEON"""
separator
menuitem "[:chip]Debug Registers"                     "per , ""Core Registers (Cortex-A9MPCore),Debug Registers"""
menuitem "[:chip]Breakpoint Registers"                "per , ""Core Registers (Cortex-A9MPCore),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers"        "per , ""Core Registers (Cortex-A9MPCore),Watchpoint Control Registers"""
separator
menuitem "[:chip]Snoop Control Unit (SCU)"            "per , ""Core Registers (Cortex-A9MPCore),Snoop Control Unit (SCU)"""
menuitem "[:chip]Timer and Watchdog Blocks"           "per , ""Core Registers (Cortex-A9MPCore),Timer and Watchdog Blocks"""
menuitem "[:chip]Interrupt Controller (PL-390)"       "per , ""Core Registers (Cortex-A9MPCore),Interrupt Controller (PL-390)"""
)
separator
menuitem "AXI FIFO Interface"                                                   "per , ""AXI FIFO Interface"""
menuitem "Controller Area Network"                                              "per , ""Controller Area Network"""
menuitem "DDR memory controller"                                                "per , ""DDR memory controller"""
menuitem "Cross Trigger Interface"                                              "per , ""Cross Trigger Interface"""
menuitem "Cortex A9 Performance Monitoring Unit"                                "per , ""Cortex A9 Performance Monitoring Unit"""
menuitem "CoreSight PTM-A9"                                                     "per , ""CoreSight PTM-A9"""
menuitem "Debug Access Port ROM"                                                "per , ""Debug Access Port ROM"""
menuitem "Embedded Trace Buffer"                                                "per , ""Embedded Trace Buffer"""
menuitem "Fabric Trace Macrocell"                                               "per , ""Fabric Trace Macrocell"""
menuitem "CoreSight Trace Funnel"                                               "per , ""CoreSight Trace Funnel"""
menuitem "Instrumentation Trace Macrocell"                                      "per , ""Instrumentation Trace Macrocell"""
menuitem "Trace Port Interface Unit"                                            "per , ""Trace Port Interface Unit"""
menuitem "Device Configuration Interface"                                       "per , ""Device Configuration Interface"""
menuitem "DMA Controller"                                                       "per , ""DMA Controller"""
menuitem "GEM (Cadence Gigabit Ethernet MAC)"                                   "per , ""GEM (Cadence Gigabit Ethernet MAC)"""
menuitem "GPIO (General Purpose Input / Output)"                                "per , ""GPIO (General Purpose Input / Output)"""
menuitem "QOS301 (Quality of Service)"                                          "per , ""QOS301 (Quality of Service)"""
menuitem "I2C (Inter Integrated Circuit)"                                       "per , ""I2C (Inter Integrated Circuit)"""
menuitem "L2CPL310 (L2 Cache PL310)"                                            "per , ""L2CPL310 (L2 Cache PL310)"""
menuitem "MPCORE (Mpcore - SCU / Interrupt controller / Counters and Timers)"   "per , ""MPCORE (Mpcore - SCU, Interrupt controller, Counters and Timers)"""
menuitem "OCM (On-Chip Memory)"                                                 "per , ""OCM (On-Chip Memory)"""
menuitem "QSPI (Quad-SPI Controller)"                                           "per , ""QSPI (Quad-SPI Controller)"""
menuitem "SDIO (SD2.0/ SDIO2.0/ MMC3.31 AHB Host Controller)"                   "per , ""SDIO (SD2.0/ SDIO2.0/ MMC3.31 AHB Host Controller)"""
menuitem "SLCR (System Level Control Registers)"                                "per , ""SLCR (System Level Control Registers)"""
menuitem "Shared Memory Controller"                                             "per , ""Shared Memory Controller"""
menuitem "Serial Peripheral Interface"                                          "per , ""Serial Peripheral Interface"""
menuitem "System Watchdog Timer Registers"                                      "per , ""System Watchdog Timer Registers"""
menuitem "Triple Timer Counter"                                                 "per , ""Triple Timer Counter"""
menuitem "Universal Asynchronous Receiver Transmitter"                          "per , ""Universal Asynchronous Receiver Transmitter"""
menuitem "USB controller"                                                       "per , ""USB controller"""
)
)