; -------------------------------------------------------------------------------- ; @Title: TMPM036 Specific Menu ; @Props: Released ; @Author: NEJ ; @Changelog: 2022-04-07 NEJ ; @Manufacturer: TOSHIBA - Toshiba ; @Core: Cortex-M0 ; @Chip: TMPM036FWFG ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: mentmpm036.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-M0)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0),System Control""" menuitem "[:chip]Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0),Nested Vectored Interrupt Controller (NVIC)""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0),Debug,Core Debug""" menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0),Debug,Breakpoint Unit (BPU)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) separator menuitem "ADC" "per , ""ADC (10-bit Analog/Digital Converter)""" menuitem "CG" "per , ""CG (Clock Generator Registers)""" menuitem "DMACA" "per , ""DMACA (DMA Controller A)""" menuitem "DMACB" "per , ""DMACB (DMA Controller B)""" menuitem "DMACRQ" "per , ""DMACRQ (DMAC Request Control)""" menuitem "FC" "per , ""FC (Flash Control)""" popup "I2C" ( menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit),I2C0""" menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1""" ) menuitem "INTM" "per , ""INTM (Interrupt Mask and Status Flag Register)""" menuitem "LVD" "per , ""LVD (Low Voltage Detection)""" menuitem "PA" "per , ""PA (Port A)""" menuitem "PB" "per , ""PB (Port B)""" menuitem "PC" "per , ""PC (Port C)""" menuitem "PD" "per , ""PD (Port D)""" menuitem "PE" "per , ""PE (Port E)""" menuitem "PF" "per , ""PF (Port F)""" menuitem "PG" "per , ""PG (Port G)""" menuitem "PH" "per , ""PH (Port H)""" menuitem "PJ" "per , ""PJ (Port J)""" menuitem "PK" "per , ""PK (Port K)""" menuitem "PL" "per , ""PL (Port L)""" menuitem "PM" "per , ""PM (Port M)""" menuitem "PN" "per , ""PN (Port N)""" popup "SC" ( menuitem "SC0" "per , ""SC (Serial Channel with 4bytes FIFO),SC0""" menuitem "SC1" "per , ""SC (Serial Channel with 4bytes FIFO),SC1""" menuitem "SC2" "per , ""SC (Serial Channel with 4bytes FIFO),SC2""" menuitem "SC3" "per , ""SC (Serial Channel with 4bytes FIFO),SC3""" menuitem "SC4" "per , ""SC (Serial Channel with 4bytes FIFO),SC4""" menuitem "SC5" "per , ""SC (Serial Channel with 4bytes FIFO),SC5""" ) popup "TMR16A" ( menuitem "T16A0" "per , ""TMR16A (16-bit Timer A),T16A0""" menuitem "T16A1" "per , ""TMR16A (16-bit Timer A),T16A1""" menuitem "T16A2" "per , ""TMR16A (16-bit Timer A),T16A2""" menuitem "T16A3" "per , ""TMR16A (16-bit Timer A),T16A3""" ) popup "TMRB" ( menuitem "TB0" "per , ""TMRB (16-bit Timer/Event Counter),TB0""" menuitem "TB1" "per , ""TMRB (16-bit Timer/Event Counter),TB1""" menuitem "TB2" "per , ""TMRB (16-bit Timer/Event Counter),TB2""" menuitem "TB3" "per , ""TMRB (16-bit Timer/Event Counter),TB3""" menuitem "TB4" "per , ""TMRB (16-bit Timer/Event Counter),TB4""" menuitem "TB5" "per , ""TMRB (16-bit Timer/Event Counter),TB5""" menuitem "TB6" "per , ""TMRB (16-bit Timer/Event Counter),TB6""" menuitem "TB7" "per , ""TMRB (16-bit Timer/Event Counter),TB7""" menuitem "TB8" "per , ""TMRB (16-bit Timer/Event Counter),TB8""" menuitem "TB9" "per , ""TMRB (16-bit Timer/Event Counter),TB9""" ) menuitem "WDT" "per , ""WDT (Watchdog Timer)""" ) )