; --------------------------------------------------------------------------------
; @Title: TM4C Tiva Specific Menu
; @Props: Released
; @Author: STR ASK RTY
; @Changelog:
; @Manufacturer: TI
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: mentiva.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M4F)"
(
menuitem "[:chip]System Control"                                "per , ""Core Registers (Cortex-M4F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                    "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"     "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
menuitem "[:chip]FPU;Floating-point Unit"                       "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"       "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"        "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "System Control"                       "per , ""System Control"""
menuitem "System Exception Module"              "per , ""System Exception Module"""
if (cpu()=="TM4C1231C3PM")||(cpu()=="TM4C1231D5PM")||(cpu()=="TM4C1231E6PM")||(cpu()=="TM4C1231H6PM")||(cpu()=="TM4C1231D5PZ")||(cpu()=="TM4C1231E6PZ")||(cpu()=="TM4C1231H6PZ")||(cpu()=="TM4C1231H6PGE")||(cpu()=="TM4C1233C3PM")||(cpu()=="TM4C1233D5PM")||(cpu()=="TM4C1233E6PM")||(cpu()=="TM4C1233H6PM")||(cpu()=="TM4C1233D5PZ")||(cpu()=="TM4C1233E6PZ")||(cpu()=="TM4C1233H6PZ")||(cpu()=="TM4C1233H6PGE")||(cpu()=="TM4C1237D5PM")||(cpu()=="TM4C1237E6PM")||(cpu()=="TM4C1237H6PM")||(cpu()=="TM4C1237D5PZ")||(cpu()=="TM4C1237E6PZ")||(cpu()=="TM4C1237H6PZ")||(cpu()=="TM4C1237H6PGE")||(cpu()=="TM4C123GE6PM")||(cpu()=="TM4C123GH6PM")||(cpu()=="TM4C123GE6PZ")||(cpu()=="TM4C123GH6PZ")||(cpu()=="TM4C123GH6PGE")||(cpu()=="TM4C1299NCZAD")||(cpu()=="TM4C1299KCZAD")||(cpu()=="TM4C1297NCZAD")||(cpu()=="TM4C1294NCZAD")||(cpu()=="TM4C1294NCPDT")||(cpu()=="TM4C1294KCPDT")||(cpu()=="TM4C1292NCZAD")||(cpu()=="TM4C1292NCPDT")||(cpu()=="TM4C1290NCZAD")||(cpu()=="TM4C1290NCPDT")||(cpu()=="TM4C129DNCZAD")||(cpu()=="TM4C129DNCPDT")||(cpu()=="TM4C129CNCZAD")||(cpu()=="TM4C129CNCPDT")||(cpu()=="TM4C129ENCZAD")||(cpu()=="TM4C129ENCPDT")||(cpu()=="TM4C129EKCPDT")||(cpu()=="TM4C129LNCZAD")||(cpu()=="TM4C129XNCZAD")||(cpu()=="TM4C129XKCZAD")
(
menuitem "Hibernation Module"               "per , ""Hibernation Module"""
)
menuitem "Internal Memory"                      "per , ""Internal Memory"""
menuitem "uDMA"                                 "per , ""uDMA (Micro Direct Memory Access)"""
menuitem "GPIO"                                 "per , ""GPIOs (General-Purpose Input/Outputs)"""
if (cpu()=="TM4C1299NCZAD")||(cpu()=="TM4C1299KCZAD")||(cpu()=="TM4C1297NCZAD")||(cpu()=="TM4C1294NCZAD")||(cpu()=="TM4C1294NCPDT")||(cpu()=="TM4C1294KCPDT")||(cpu()=="TM4C1292NCZAD")||(cpu()=="TM4C1292NCPDT")||(cpu()=="TM4C1290NCZAD")||(cpu()=="TM4C1290NCPDT")||(cpu()=="TM4C129XNCZAD")||(cpu()=="TM4C129XKCZAD")||(cpu()=="TM4C129LNCZAD")||(cpu()=="TM4C129ENCZAD")||(cpu()=="TM4C129ENCPDT")||(cpu()=="TM4C129EKCPDT")||(cpu()=="TM4C129DNCZAD")||(cpu()=="TM4C129DNCPDT")||(cpu()=="TM4C129CNCZAD")||(cpu()=="TM4C129CNCPDT")
(
menuitem "EPI"                              "per , ""EPI (External Peripheral Interface)"""
menuitem "CRC"                              "per , ""CRC (Cyclical Redundancy Check)"""
)
if (cpu()=="TM4C129XNCZAD")||(cpu()=="TM4C129XKCZAD")||(cpu()=="TM4C129LNCZAD")||(cpu()=="TM4C129ENCZAD")||(cpu()=="TM4C129ENCPDT")||(cpu()=="TM4C129EKCPDT")||(cpu()=="TM4C129DNCZAD")||(cpu()=="TM4C129DNCPDT")||(cpu()=="TM4C129CNCZAD")||(cpu()=="TM4C129CNCPDT")
(
menuitem "AES"                              "per , ""AES (Advance Encryption Standard Accelerator)"""
menuitem "DES"                              "per , ""DES (Data Encryption Standard Accelerator)"""
menuitem "SHA"                              "per , ""SHA (SHA/MD5 Accelerator)"""
)
menuitem "GPT"                                  "per , ""General-Purpose Timers"""
menuitem "WDT"                                  "per , ""Watchdog Timer"""
menuitem "ADC"                                  "per , ""ADC (Analog-to-Digital Converter)"""
menuitem "UART"                                 "per , ""UARTs (Universal Asynchronous Receivers/Transmitters)"""
if (cpu()=="TM4C1299NCZAD")||(cpu()=="TM4C1299KCZAD")||(cpu()=="TM4C1297NCZAD")||(cpu()=="TM4C1294NCZAD")||(cpu()=="TM4C1294NCPDT")||(cpu()=="TM4C1294KCPDT")||(cpu()=="TM4C1292NCZAD")||(cpu()=="TM4C1292NCPDT")||(cpu()=="TM4C1290NCZAD")||(cpu()=="TM4C1290NCPDT")||(cpu()=="TM4C129XNCZAD")||(cpu()=="TM4C129XKCZAD"||(cpu()=="TM4C129LNCZAD")||(cpu()=="TM4C129ENCZAD")||(cpu()=="TM4C129ENCPDT")||(cpu()=="TM4C129EKCPDT")||(cpu()=="TM4C129DNCZAD")||(cpu()=="TM4C129DNCPDT")||(cpu()=="TM4C129CNCZAD")||(cpu()=="TM4C129CNCPDT"))
(
menuitem "QSSI"                             "per , ""QSSI (Quad Synchronous Serial Interface)"""
)
else
(
menuitem "SSI"                              "per , ""SSI (Synchronous Serial Interface)"""
)
menuitem "I2C"                                  "per , ""I2C (Inter-Integrated Circuit)"""
menuitem "CAN"                                  "per , ""CAN (Controller Area Network)"""
if    (cpu()=="TM4C1292NCPDT")||(cpu()=="TM4C1294NCPDT")||(cpu()=="TM4C1299NCZAD")||(cpu()=="TM4C129DNCPDT")||(cpu()=="TM4C129XNCZAD")||(cpu()=="TM4C1290NCZAD")||(cpu()=="TM4C1292NCZAD")||(cpu()=="TM4C1294KCPDT")||(cpu()=="TM4C1294NCZAD")||(cpu()=="TM4C1299KCZAD")||(cpu()=="TM4C129DNCZAD")||(cpu()=="TM4C129EKCPDT")||(cpu()=="TM4C129ENCPDT")||(cpu()=="TM4C129ENCZAD")||(cpu()=="TM4C129LNCZAD")||(cpu()=="TM4C129XKCZAD")
(
menuitem "EMAC"                             "per , ""EMAC"""
)
if (cpu()=="TM4C1237D5PM")||(cpu()=="TM4C1237E6PM")||(cpu()=="TM4C1237H6PM")||(cpu()=="TM4C1236D5PM")||(cpu()=="TM4C1236E6PM")||(cpu()=="TM4C1236H6PM")||(cpu()=="TM4C1237D5PZ")||(cpu()=="TM4C1237E6PZ")||(cpu()=="TM4C1237H6PZ")||(cpu()=="TM4C1237H6PGE")||(cpu()=="TM4C123GE6PM")||(cpu()=="TM4C123GH6PM")||(cpu()=="TM4C123FE6PM")||(cpu()=="TM4C123FH6PM")||(cpu()=="TM4C123GE6PZ")||(cpu()=="TM4C123GH6PZ")||(cpu()=="TM4C123GH6PGE")||(cpu()=="TM4C1233C3PM")||(cpu()=="TM4C1233D5PM")||(cpu()=="TM4C1233E6PM")||(cpu()=="TM4C1233H6PM")||(cpu()=="TM4C1232C3PM")||(cpu()=="TM4C1232D5PM")||(cpu()=="TM4C1232E6PM")||(cpu()=="TM4C1232H6PM")||(cpu()=="TM4C1233D5PZ")||(cpu()=="TM4C1233E6PZ")||(cpu()=="TM4C1233H6PZ")||(cpu()=="TM4C1233H6PGE")
(
menuitem "USB"                              "per , ""USB (Universal Serial Bus)"""
)
if ((cpu()=="TM4C1292NCPDT")||(cpu()=="TM4C1294NCPDT")||(cpu()=="TM4C1299NCZAD")||(cpu()=="TM4C129DNCPDT")||(cpu()=="TM4C129XNCZAD")||(cpu()=="TM4C1290NCPDT")||(cpu()=="TM4C1290NCZAD")||(cpu()=="TM4C1292NCZAD")||(cpu()=="TM4C1294KCPDT")||(cpu()=="TM4C1294NCZAD")||(cpu()=="TM4C1297NCZAD")||(cpu()=="TM4C1299KCZAD")||(cpu()=="TM4C129CNCPDT")||(cpu()=="TM4C129CNCZAD")||(cpu()=="TM4C129DNCZAD")||(cpu()=="TM4C129EKCPDT")||(cpu()=="TM4C129ENCPDT")||(cpu()=="TM4C129ENCZAD")||(cpu()=="TM4C129LNCZAD")||(cpu()=="TM4C129XKCZAD"))
(
menuitem "USB"                              "per , ""USB (Universal Serial Bus)"""
)
if ((cpu()=="TM4C1299NCZAD")||(cpu()=="TM4C129XNCZAD")||(cpu()=="TM4C1297NCZAD")||(cpu()=="TM4C1299KCZAD")||(cpu()=="TM4C129LNCZAD")||(cpu()=="TM4C129XKCZAD"))
(
menuitem "LCD Controller"                   "per , ""LCD Controller"""
)
menuitem "Analog Comparators"                   "per , ""Analog Comparators"""
if (cpu()=="TM4C123GE6PM")||(cpu()=="TM4C123GH6PM")||(cpu()=="TM4C123FE6PM")||(cpu()=="TM4C123FH6PM")||(cpu()=="TM4C123GE6PZ")||(cpu()=="TM4C123GH6PZ")||(cpu()=="TM4C123GH6PGE")||(cpu()=="TM4C123AH6PM")||(cpu()=="TM4C123GH6ZRB")||(cpu()=="TM4C123AE6PM")||(cpu()=="TM4C123BH6ZRB")||(cpu()=="TM4C123BH6PM")||(cpu()=="TM4C123BE6PM")||(cpu()=="TM4C123BE6PZ")||(cpu()=="TM4C123BH6PZ")||(cpu()=="TM4C123BH6PGE")||cpuis("TM4C1292NCPDT")||cpuis("TM4C1294NCPDT")||cpuis("TM4C1299NCZAD")||cpuis("TM4C129DNCPDT")||cpuis("TM4C129XNCZAD")||cpuis("TM4C1290NCPDT")||cpuis("TM4C1290NCZAD")||cpuis("TM4C1292NCZAD")||cpuis("TM4C129CNCPDT")||cpuis("TM4C129CNCZAD")||cpuis("TM4C129DNCZAD")||cpuis("TM4C129EKCPDT")||cpuis("TM4C129ENCPDT")||cpuis("TM4C129ENCZAD")||cpuis("TM4C129LNCZAD")||cpuis("TM4C129XKCZAD")||cpuis("TM4C1294KCPDT")||cpuis("TM4C1294NCZAD")||cpuis("TM4C1297NCZAD")||cpuis("TM4C1299KCZAD")
(
menuitem "PWM"                              "per , ""PWM (Pulse Width Modulator)"""
menuitem "QEI"                              "per , ""QEI (Quadrature Encoder Interface)"""
)
)
)