; -------------------------------------------------------------------------------- ; @Title: S32R45 Specific Menu ; @Props: Released ; @Author: KRZ ; @Changelog: 2023-10-19 KRZ ; @Manufacturer: NXP - NXP Semiconductors ; @Core: Cortex-A53, Cortex-M7F ; @Chip: S32R45-A53, S32R45-M7 ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: mens32r45.men 16789 2023-10-19 17:14:40Z kwisniewski $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( if (CORENAME()=="CORTEXA53") ( popup "[:chip]Core Registers (Cortex-A53)" ( menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers""" menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration""" menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit""" menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor""" menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers""" menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface""" separator menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers""" separator menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers""" separator menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers""" menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration""" menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit""" menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor""" menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers""" menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface""" separator menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers""" separator menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers""" separator menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)""" ) ) else if (CORENAME()=="CORTEXM7F") ( popup "[:chip]Core Registers (Cortex-M7F)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M7F),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M7F),Memory Protection Unit (MPU)""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M7F),Nested Vectored Interrupt Controller (NVIC)""" menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M7F),Floating-point Unit (FPU)""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M7F),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M7F),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M7F),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) separator popup "IVT Table (QSPI)" ( menuitem "IVT (QSPI)" "per , ""IVT Table,IVT (QSPI)""" menuitem "DCD" "per , ""IVT Table,IVT (QSPI),DCD Registers""" menuitem "DCD Self-Test" "per , ""IVT Table,IVT (QSPI),DCD Self-Test Registers""" menuitem "BOOT" "per , ""IVT Table,IVT (QSPI),BOOT Registers""" ) separator menuitem "A53_GPR;A53 Cluster General Purpose Registers" "per , ""A53_GPR (A53 Cluster General Purpose Registers)""" popup "ADC;Analog-to-Digital Converter" ( menuitem "ADC_0" "per , ""ADC (Analog-to-Digital Converter),ADC_0""" menuitem "ADC_1" "per , ""ADC (Analog-to-Digital Converter),ADC_1""" ) menuitem "ATP;Aurora Trace Port Subsystem" "per , ""ATP (Aurora Trace Port Subsystem)""" menuitem "BOOT" "per , ""BOOT""" popup "CAIU;Coherent Agent Interface Unit" ( menuitem "CAIU0" "per , ""CAIU (Coherent Agent Interface Unit),CAIU0""" menuitem "CAIU1" "per , ""CAIU (Coherent Agent Interface Unit),CAIU1""" ) menuitem "CCTI_FAULT_CTRL;CCTI Fault Controller" "per , ""CCTI_FAULT_CTRL (CCTI Fault Controller)""" popup "CM7_GPR;M7 Cluster General Purpose Registers" ( menuitem "CM7_GPR_0" "per , ""CM7_GPR (M7 Cluster General Purpose Registers),CM7_GPR_0""" menuitem "CM7_GPR_1" "per , ""CM7_GPR (M7 Cluster General Purpose Registers),CM7_GPR_1""" menuitem "CM7_GPR_2" "per , ""CM7_GPR (M7 Cluster General Purpose Registers),CM7_GPR_2""" ) menuitem "CMIU;Coherent Memory Interface Unit" "per , ""CMIU (Coherent Memory Interface Unit)""" popup "CMU_FC;Clock Monitor Unit - Frequency Check" ( menuitem "CMU_FC_0" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_0""" menuitem "CMU_FC_5" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_5""" menuitem "CMU_FC_6" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_6""" menuitem "CMU_FC_7" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_7""" menuitem "CMU_FC_8" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_8""" menuitem "CMU_FC_9" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_9""" menuitem "CMU_FC_10" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_10""" menuitem "CMU_FC_11" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_11""" menuitem "CMU_FC_12" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_12""" menuitem "CMU_FC_13" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_13""" menuitem "CMU_FC_14" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_14""" menuitem "CMU_FC_15" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_15""" menuitem "CMU_FC_16" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_16""" menuitem "CMU_FC_17" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_17""" menuitem "CMU_FC_18" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_18""" menuitem "CMU_FC_20" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_20""" menuitem "CMU_FC_21" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_21""" menuitem "CMU_FC_22" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_22""" menuitem "CMU_FC_27" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_27""" menuitem "CMU_FC_28" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_28""" menuitem "CMU_FC_38" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_38""" menuitem "CMU_FC_39" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_39""" menuitem "CMU_FC_40" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_40""" menuitem "CMU_FC_46" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_46""" menuitem "CMU_FC_51" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_51""" menuitem "CMU_FC_52" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_52""" menuitem "CMU_FC_53" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_53""" menuitem "CMU_FC_54" "per , ""CMU_FC (Clock Monitor Unit - Frequency Check),CMU_FC_54""" ) popup "CMU_FM;Clock Monitor Unit - Frequency Meter" ( menuitem "CMU_FM_1" "per , ""CMU_FM (Clock Monitor Unit - Frequency Meter),CMU_FM_1""" menuitem "CMU_FM_2" "per , ""CMU_FM (Clock Monitor Unit - Frequency Meter),CMU_FM_2""" menuitem "CMU_FM_3" "per , ""CMU_FM (Clock Monitor Unit - Frequency Meter),CMU_FM_3""" menuitem "CMU_FM_4" "per , ""CMU_FM (Clock Monitor Unit - Frequency Meter),CMU_FM_4""" ) menuitem "CRC;Cyclic Redundancy Check Unit" "per , ""CRC (Cyclic Redundancy Check Unit)""" menuitem "CSR;Coherent Subsystem" "per , ""CSR (Coherent Subsystem)""" menuitem "CTE;Cross Trigger Engine" "per , ""CTE (Cross Trigger Engine)""" menuitem "CTU;Cross-Triggering Unit" "per , ""CTU (Cross-Triggering Unit)""" popup "DDR;DDR Subsystem" ( menuitem "DDR_GPR" "per , ""DDR (DDR Subsystem),DDR_GPR""" menuitem "DDR_SUBSYSTEM" "per , ""DDR (DDR Subsystem),DDR_SUBSYSTEM""" ) popup "DFS;Digital Frequency Synthesizer" ( menuitem "CORE_DFS" "per , ""DFS (Digital Frequency Synthesizer),CORE_DFS""" menuitem "PERIPH_DFS" "per , ""DFS (Digital Frequency Synthesizer),PERIPH_DFS""" ) menuitem "DIRU;Directory Unit" "per , ""DIRU (Directory Unit)""" popup "DMA;Direct Memory Access" ( popup "DMA_CRC" ( menuitem "DMA_CRC_0" "per , ""DMA (Direct Memory Access),DMA_CRC,DMA_CRC_0""" menuitem "DMA_CRC_1" "per , ""DMA (Direct Memory Access),DMA_CRC,DMA_CRC_1""" ) popup "DMA_MP" ( menuitem "EDMA_0_MP" "per , ""DMA (Direct Memory Access),DMA_MP,EDMA_0_MP""" menuitem "EDMA_1_MP" "per , ""DMA (Direct Memory Access),DMA_MP,EDMA_1_MP""" ) popup "DMA_TCD" ( menuitem "EDMA_0_TCD" "per , ""DMA (Direct Memory Access),DMA_TCD,EDMA_0_TCD""" menuitem "EDMA_1_TCD" "per , ""DMA (Direct Memory Access),DMA_TCD,EDMA_1_TCD""" ) ) popup "EIM;Error Injection Module" ( menuitem "EIM" "per , ""EIM (Error Injection Module),EIM""" menuitem "EIM_0" "per , ""EIM (Error Injection Module),EIM_0""" menuitem "EIM_1" "per , ""EIM (Error Injection Module),EIM_1""" menuitem "EIM_2" "per , ""EIM (Error Injection Module),EIM_2""" menuitem "EIM_3" "per , ""EIM (Error Injection Module),EIM_3""" menuitem "EIM_BBE32EP_DSP" "per , ""EIM (Error Injection Module),EIM_BBE32EP_DSP""" menuitem "EIM_LAX_0" "per , ""EIM (Error Injection Module),EIM_LAX_0""" menuitem "EIM_LAX_1" "per , ""EIM (Error Injection Module),EIM_LAX_1""" menuitem "EIM_PER_1" "per , ""EIM (Error Injection Module),EIM_PER_1""" ) popup "ERM;Error Reporting Module" ( menuitem "ERM_CPU0" "per , ""ERM (Error Reporting Module),ERM_CPU0""" menuitem "ERM_CPU1" "per , ""ERM (Error Reporting Module),ERM_CPU1""" menuitem "ERM_CPU2" "per , ""ERM (Error Reporting Module),ERM_CPU2""" menuitem "ERM_EDMA0" "per , ""ERM (Error Reporting Module),ERM_EDMA0""" menuitem "ERM_EDMA1" "per , ""ERM (Error Reporting Module),ERM_EDMA1""" menuitem "ERM_LAX_0" "per , ""ERM (Error Reporting Module),ERM_LAX_0""" menuitem "ERM_LAX_1" "per , ""ERM (Error Reporting Module),ERM_LAX_1""" menuitem "ERM_PER" "per , ""ERM (Error Reporting Module),ERM_PER""" menuitem "ERM_PER_1" "per , ""ERM (Error Reporting Module),ERM_PER_1""" ) menuitem "FCCU;Fault Collection and Control Unit" "per , ""FCCU (Fault Collection and Control Unit)""" popup "FLEXCAN;FlexCAN Communication Controller" ( menuitem "CAN_0" "per , ""FLEXCAN (FlexCAN Communication Controller),CAN_0""" menuitem "CAN_1" "per , ""FLEXCAN (FlexCAN Communication Controller),CAN_1""" menuitem "CAN_2" "per , ""FLEXCAN (FlexCAN Communication Controller),CAN_2""" menuitem "CAN_3" "per , ""FLEXCAN (FlexCAN Communication Controller),CAN_3""" menuitem "CAN_4" "per , ""FLEXCAN (FlexCAN Communication Controller),CAN_4""" menuitem "CAN_5" "per , ""FLEXCAN (FlexCAN Communication Controller),CAN_5""" menuitem "CAN_6" "per , ""FLEXCAN (FlexCAN Communication Controller),CAN_6""" menuitem "CAN_7" "per , ""FLEXCAN (FlexCAN Communication Controller),CAN_7""" ) menuitem "FLEXRAY;FlexRay Communication Controller" "per , ""FLEXRAY (FlexRay Communication Controller)""" menuitem "FSC;Functional Safety Controller" "per , ""FSC (Functional Safety Controller)""" popup "FTM;FlexTimer" ( menuitem "FTM_0" "per , ""FTM (FlexTimer),FTM_0""" menuitem "FTM_1" "per , ""FTM (FlexTimer),FTM_1""" ) menuitem "FXOSC;Fast Crystal Oscillator Digital Controller" "per , ""FXOSC (Fast Crystal Oscillator Digital Controller)""" popup "GMAC;Gigabit Ethernet Media Access Controller" ( menuitem "GMAC_0" "per , ""GMAC (Gigabit Ethernet Media Access Controller),GMAC_0""" menuitem "GMAC_1" "per , ""GMAC (Gigabit Ethernet Media Access Controller),GMAC_1""" ) popup "I2C;Inter-Integrated Circuit" ( menuitem "I2C_0" "per , ""I2C (Inter-Integrated Circuit),I2C_0""" menuitem "I2C_1" "per , ""I2C (Inter-Integrated Circuit),I2C_1""" ) menuitem "JDC;JTAG Data Communication" "per , ""JDC (JTAG Data Communication)""" popup "LINFLEXD" ( menuitem "LINFLEXD_0" "per , ""LINFLEXD,LINFLEXD_0""" menuitem "LINFLEXD_1" "per , ""LINFLEXD,LINFLEXD_1""" ) popup "MC_CGM;Clock Generation Module" ( menuitem "MC_CGM_0" "per , ""MC_CGM (Clock Generation Module),MC_CGM_0""" menuitem "MC_CGM_1" "per , ""MC_CGM (Clock Generation Module),MC_CGM_1""" menuitem "MC_CGM_2" "per , ""MC_CGM (Clock Generation Module),MC_CGM_2""" menuitem "MC_CGM_5" "per , ""MC_CGM (Clock Generation Module),MC_CGM_5""" ) menuitem "MC_ME;Mode Entry Module" "per , ""MC_ME (Mode Entry Module)""" menuitem "MC_RGM;Reset Generation Module" "per , ""MC_RGM (Reset Generation Module)""" menuitem "MCM;Miscellaneous Control Module" "per , ""MCM (Miscellaneous Control Module)""" menuitem "MDM_AP;Miscellaneous Debug Module Access Port" "per , ""MDM_AP (Miscellaneous Debug Module Access Port)""" popup "MIPICSI2;MIPICSI2 Subsystem" ( menuitem "MIPICSI2_0" "per , ""MIPICSI2 (MIPICSI2 Subsystem),MIPICSI2_0""" menuitem "MIPICSI2_1" "per , ""MIPICSI2 (MIPICSI2 Subsystem),MIPICSI2_1""" menuitem "MIPICSI2_2" "per , ""MIPICSI2 (MIPICSI2 Subsystem),MIPICSI2_2""" menuitem "MIPICSI2_3" "per , ""MIPICSI2 (MIPICSI2 Subsystem),MIPICSI2_3""" ) menuitem "MSCM;Miscellaneous System Control Module" "per , ""MSCM (Miscellaneous System Control Module)""" popup "MU;Messaging Unit" ( menuitem "MU0__MUA" "per , ""MU (Messaging Unit),MU0__MUA""" menuitem "MU0__MUB" "per , ""MU (Messaging Unit),MU0__MUB""" menuitem "MU1__MUA" "per , ""MU (Messaging Unit),MU1__MUA""" menuitem "MU1__MUB" "per , ""MU (Messaging Unit),MU1__MUB""" menuitem "MU2__MUA" "per , ""MU (Messaging Unit),MU2__MUA""" menuitem "MU2__MUB" "per , ""MU (Messaging Unit),MU2__MUB""" menuitem "MU3__MUA" "per , ""MU (Messaging Unit),MU3__MUA""" menuitem "MU3__MUB" "per , ""MU (Messaging Unit),MU3__MUB""" ) popup "NCBU;Non-Coherent Bridge Unit" ( menuitem "NCBU0" "per , ""NCBU (Non-Coherent Bridge Unit),NCBU0""" menuitem "NCBU1" "per , ""NCBU (Non-Coherent Bridge Unit),NCBU1""" ) menuitem "OCOTP;On-Chip One Time Programmable Controller" "per , ""OCOTP (On-Chip One Time Programmable Controller)""" popup "PCIE;PCIe Controller" ( menuitem "PCIE_DMA" "per , ""PCIE (PCIe Controller),PCIE_DMA""" menuitem "PCIE_EP" "per , ""PCIE (PCIe Controller),PCIE_EP""" menuitem "PCIE_RC" "per , ""PCIE (PCIe Controller),PCIE_RC""" ) menuitem "PERF_REGISTERS;Performance Monitor" "per , ""PERF_REGISTERS (Performance Monitor)""" popup "PIT;Periodic Interrupt Timer" ( menuitem "PIT_0" "per , ""PIT (Periodic Interrupt Timer),PIT_0""" menuitem "PIT_1" "per , ""PIT (Periodic Interrupt Timer),PIT_1""" ) popup "PLLDIG;PLL Digital Interface" ( menuitem "ACCEL_PLL" "per , ""PLLDIG (PLL Digital Interface),ACCEL_PLL""" menuitem "CORE_PLL" "per , ""PLLDIG (PLL Digital Interface),CORE_PLL""" menuitem "DDR_PLL" "per , ""PLLDIG (PLL Digital Interface),DDR_PLL""" menuitem "PERIPH_PLL" "per , ""PLLDIG (PLL Digital Interface),PERIPH_PLL""" ) menuitem "PMC;Power Management Controller" "per , ""PMC (Power Management Controller)""" menuitem "PMUEVENTOBSERVER;PMUEVENT Observer" "per , ""PMUEVENTOBSERVER (PMUEVENT Observer)""" popup "QUADSPI;Quad Serial Peripheral Interface" ( menuitem "QUADSPI" "per , ""QUADSPI (Quad Serial Peripheral Interface),QUADSPI""" menuitem "QUADSPI_ARDB" "per , ""QUADSPI (Quad Serial Peripheral Interface),QUADSPI_ARDB""" ) menuitem "RDC;Reset Domain Controller" "per , ""RDC (Reset Domain Controller)""" menuitem "SBSW;Safety by Software" "per , ""SBSW (Safety by Software)""" menuitem "SECURITY;Security Subsystem" "per , ""SECURITY (Security Subsystem)""" popup "SELFTEST_GPR;Selftest General Purpose Registers" ( menuitem "SELFTEST_GPR" "per , ""SELFTEST_GPR (Selftest General Purpose Registers),SELFTEST_GPR""" menuitem "SELFTEST_GPR_TOP" "per , ""SELFTEST_GPR (Selftest General Purpose Registers),SELFTEST_GPR_TOP""" ) menuitem "SEMA42;Semaphores2" "per , ""SEMA42 (Semaphores2)""" popup "SERDES;SerDes Subsystem" ( menuitem "SERDES_0_GPR" "per , ""SERDES (SerDes Subsystem),SERDES_0_GPR""" menuitem "SERDES_1_GPR" "per , ""SERDES (SerDes Subsystem),SERDES_1_GPR""" menuitem "SERDES_DMA_PCIE_1" "per , ""SERDES (SerDes Subsystem),SERDES_DMA_PCIE_1""" menuitem "SERDES_EP_PCIE_1" "per , ""SERDES (SerDes Subsystem),SERDES_EP_PCIE_1""" menuitem "SERDES_PHY" "per , ""SERDES (SerDes Subsystem),SERDES_PHY""" menuitem "SERDES_PHY_PCIE_1" "per , ""SERDES (SerDes Subsystem),SERDES_PHY_PCIE_1""" menuitem "SERDES_RC_PCIE_1" "per , ""SERDES (SerDes Subsystem),SERDES_RC_PCIE_1""" menuitem "SERDES_SS" "per , ""SERDES (SerDes Subsystem),SERDES_SS""" menuitem "SERDES_SS_PCIE_1" "per , ""SERDES (SerDes Subsystem),SERDES_SS_PCIE_1""" menuitem "SERDES_XPCS_0" "per , ""SERDES (SerDes Subsystem),SERDES_XPCS_0""" menuitem "SERDES_XPCS_0_PCIE_1" "per , ""SERDES (SerDes Subsystem),SERDES_XPCS_0_PCIE_1""" menuitem "SERDES_XPCS_1" "per , ""SERDES (SerDes Subsystem),SERDES_XPCS_1""" menuitem "SERDES_XPCS_1_PCIE_1" "per , ""SERDES (SerDes Subsystem),SERDES_XPCS_1_PCIE_1""" ) popup "SIUL2;System Integration Unit Lite2" ( menuitem "SIUL2_0" "per , ""SIUL2 (System Integration Unit Lite2),SIUL2_0""" menuitem "SIUL2_1" "per , ""SIUL2 (System Integration Unit Lite2),SIUL2_1""" ) popup "SPI;Serial Peripheral Interface" ( menuitem "SPI_0" "per , ""SPI (Serial Peripheral Interface),SPI_0""" menuitem "SPI_1" "per , ""SPI (Serial Peripheral Interface),SPI_1""" menuitem "SPI_2" "per , ""SPI (Serial Peripheral Interface),SPI_2""" menuitem "SPI_3" "per , ""SPI (Serial Peripheral Interface),SPI_3""" menuitem "SPI_4" "per , ""SPI (Serial Peripheral Interface),SPI_4""" menuitem "SPI_5" "per , ""SPI (Serial Peripheral Interface),SPI_5""" ) menuitem "SPT;Signal Processing Tool" "per , ""SPT (Signal Processing Tool)""" popup "SRAMC;System RAM Controller" ( menuitem "CHIRPBUFFER_RAM_CONTROLLER" "per , ""SRAMC (System RAM Controller),CHIRPBUFFER_RAM_CONTROLLER""" menuitem "RETENTION_RAM_CONTROLLER" "per , ""SRAMC (System RAM Controller),RETENTION_RAM_CONTROLLER""" menuitem "SRAMC_0" "per , ""SRAMC (System RAM Controller),SRAMC_0""" menuitem "SRAMC_1" "per , ""SRAMC (System RAM Controller),SRAMC_1""" ) popup "SRC;System Resource Controller" ( menuitem "SRC" "per , ""SRC (System Resource Controller),SRC""" menuitem "SRC_1" "per , ""SRC (System Resource Controller),SRC_1""" menuitem "SRC_GPR" "per , ""SRC (System Resource Controller),SRC_GPR""" ) menuitem "STCU2;Self-Test Control Unit" "per , ""STCU2 (Self-Test Control Unit)""" popup "STM;System Timer Module" ( menuitem "STM_0" "per , ""STM (System Timer Module),STM_0""" menuitem "STM_1" "per , ""STM (System Timer Module),STM_1""" menuitem "STM_2" "per , ""STM (System Timer Module),STM_2""" menuitem "STM_3" "per , ""STM (System Timer Module),STM_3""" menuitem "STM_4" "per , ""STM (System Timer Module),STM_4""" menuitem "STM_5" "per , ""STM (System Timer Module),STM_5""" menuitem "STM_6" "per , ""STM (System Timer Module),STM_6""" menuitem "STM_7" "per , ""STM (System Timer Module),STM_7""" ) popup "SWT;Software Watchdog Timer" ( menuitem "SWT_0" "per , ""SWT (Software Watchdog Timer),SWT_0""" menuitem "SWT_1" "per , ""SWT (Software Watchdog Timer),SWT_1""" menuitem "SWT_2" "per , ""SWT (Software Watchdog Timer),SWT_2""" menuitem "SWT_3" "per , ""SWT (Software Watchdog Timer),SWT_3""" menuitem "SWT_4" "per , ""SWT (Software Watchdog Timer),SWT_4""" menuitem "SWT_5" "per , ""SWT (Software Watchdog Timer),SWT_5""" menuitem "SWT_6" "per , ""SWT (Software Watchdog Timer),SWT_6""" ) menuitem "TMU;Thermal Monitoring Unit" "per , ""TMU (Thermal Monitoring Unit)""" popup "UMCTL2" ( menuitem "UMCTL2_MP" "per , ""UMCTL2,UMCTL2_MP""" menuitem "UMCTL2_REGS" "per , ""UMCTL2,UMCTL2_REGS""" ) menuitem "USDHC;Ultra Secured Digital Host Controller" "per , ""USDHC (Ultra Secured Digital Host Controller)""" popup "VSPA" ( menuitem "LAX_0" "per , ""VSPA,LAX_0""" menuitem "LAX_0_DBG" "per , ""VSPA,LAX_0_DBG""" menuitem "LAX_1" "per , ""VSPA,LAX_1""" menuitem "LAX_1_DBG" "per , ""VSPA,LAX_1_DBG""" ) menuitem "WKPU;Wakeup Unit" "per , ""WKPU (Wakeup Unit)""" popup "XRDC;Extended Resource Domain Controller" ( menuitem "XRDC_0" "per , ""XRDC (Extended Resource Domain Controller),XRDC_0""" menuitem "XRDC_1" "per , ""XRDC (Extended Resource Domain Controller),XRDC_1""" ) ) )