; -------------------------------------------------------------------------------- ; @Title: S32R41 Specific Menu ; @Props: Released ; @Author: KWI, JON, NEJ ; @Changelog: 2020-10-16 KWI ; 2021-07-29 KWI ; 2022-01-20 JON ; 2022-07-20 NEJ ; 2022-10-27 NEJ ; 2022-11-25 NEJ ; @Manufacturer: NXP - NXP Semiconductors ; @Core: Cortex-A53, Cortex-M7F ; @Chip: S32R41-A53, S32R41-M7-0, S32R41-M7-1, S32R41-M7-HSE ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: mens32r41.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( if (CORENAME()=="CORTEXA53") ( popup "[:chip]Core Registers (Cortex-A53)" ( menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers""" menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration""" menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit""" menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor""" menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers""" menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface""" separator menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers""" separator menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers""" separator menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers""" menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration""" menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit""" menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor""" menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers""" menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface""" separator menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers""" separator menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers""" separator menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)""" ) ) else ( popup "[:chip]Core Registers (Cortex-M7F)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M7F),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M7F),Memory Protection Unit (MPU)""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M7F),Nested Vectored Interrupt Controller (NVIC)""" menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M7F),Floating-point Unit (FPU)""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M7F),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M7F),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M7F),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) separator popup "IVT Table (QSPI)" ( menuitem "IVT (QSPI)" "per , ""IVT Table,IVT (QSPI)""" menuitem "DCD" "per , ""IVT Table,IVT (QSPI),DCD Registers""" menuitem "DCD Self-Test" "per , ""IVT Table,IVT (QSPI),DCD Self-Test Registers""" menuitem "BOOT" "per , ""IVT Table,IVT (QSPI),BOOT Registers""" ) menuitem "A53_GPR" "per , ""A53_GPR""" menuitem "ADC;SAR_ADC" "per , ""ADC (SAR_ADC)""" menuitem "ATP" "per , ""ATP""" popup "BOOT;Boot_BMR" ( menuitem "BOOT_BMR" "per , ""BOOT (Boot_BMR),BOOT_BMR""" menuitem "BOOT_POR" "per , ""BOOT (Boot_BMR),BOOT_POR""" ) popup "CM7_GPR" ( menuitem "CM7_GPR_0" "per , ""CM7_GPR,CM7_GPR_0""" menuitem "CM7_GPR_1" "per , ""CM7_GPR,CM7_GPR_1""" ) popup "CMU_FC" ( menuitem "CMU_FC_0" "per , ""CMU_FC,CMU_FC_0""" menuitem "CMU_FC_1" "per , ""CMU_FC,CMU_FC_1""" menuitem "CMU_FC_3" "per , ""CMU_FC,CMU_FC_3""" menuitem "CMU_FC_5" "per , ""CMU_FC,CMU_FC_5""" menuitem "CMU_FC_6" "per , ""CMU_FC,CMU_FC_6""" menuitem "CMU_FC_7" "per , ""CMU_FC,CMU_FC_7""" menuitem "CMU_FC_8" "per , ""CMU_FC,CMU_FC_8""" menuitem "CMU_FC_10" "per , ""CMU_FC,CMU_FC_10""" menuitem "CMU_FC_11" "per , ""CMU_FC,CMU_FC_11""" menuitem "CMU_FC_12" "per , ""CMU_FC,CMU_FC_12""" menuitem "CMU_FC_13" "per , ""CMU_FC,CMU_FC_13""" menuitem "CMU_FC_14" "per , ""CMU_FC,CMU_FC_14""" menuitem "CMU_FC_15" "per , ""CMU_FC,CMU_FC_15""" menuitem "CMU_FC_16" "per , ""CMU_FC,CMU_FC_16""" menuitem "CMU_FC_17" "per , ""CMU_FC,CMU_FC_17""" menuitem "CMU_FC_21" "per , ""CMU_FC,CMU_FC_21""" menuitem "CMU_FC_22" "per , ""CMU_FC,CMU_FC_22""" menuitem "CMU_FC_23" "per , ""CMU_FC,CMU_FC_23""" menuitem "CMU_FC_24" "per , ""CMU_FC,CMU_FC_24""" menuitem "CMU_FC_25" "per , ""CMU_FC,CMU_FC_25""" menuitem "CMU_FC_26" "per , ""CMU_FC,CMU_FC_26""" menuitem "CMU_FC_27" "per , ""CMU_FC,CMU_FC_27""" menuitem "CMU_FC_28" "per , ""CMU_FC,CMU_FC_28""" menuitem "CMU_FC_29" "per , ""CMU_FC,CMU_FC_29""" menuitem "CMU_FC_30" "per , ""CMU_FC,CMU_FC_30""" menuitem "CMU_FC_31" "per , ""CMU_FC,CMU_FC_31""" ) menuitem "CRC;CRC" "per , ""CRC""" menuitem "CTE" "per , ""CTE""" menuitem "CTU" "per , ""CTU""" menuitem "PERIPH_DFS;DFS" "per , ""DFS""" menuitem "EDMA_0_MP;DMA MP" "per , ""DMA (DMA MP)""" menuitem "DMA_CRC_0;DMA_CRC" "per , ""DMA_CRC""" menuitem "EDMA_0_TCD" "per , ""DMA_TCD""" popup "DMAMUX" ( menuitem "DMAMUX_0" "per , ""DMAMUX,DMAMUX_0""" menuitem "DMAMUX_1" "per , ""DMAMUX,DMAMUX_1""" ) popup "EIM" ( menuitem "EIM_A53" "per , ""EIM,EIM_A53""" menuitem "EIM_AP1" "per , ""EIM,EIM_AP1""" menuitem "EIM_CM7_0" "per , ""EIM,EIM_CM7_0""" menuitem "EIM_CM7_1" "per , ""EIM,EIM_CM7_1""" menuitem "EIM_DSP" "per , ""EIM,EIM_DSP""" menuitem "EIM_RT0" "per , ""EIM,EIM_RT0""" menuitem "EIM_RT2" "per , ""EIM,EIM_RT2""" ) popup "ERM" ( menuitem "ERM_AP1" "per , ""ERM,ERM_AP1""" menuitem "ERM_CM7_0" "per , ""ERM,ERM_CM7_0""" menuitem "ERM_CM7_1" "per , ""ERM,ERM_CM7_1""" menuitem "ERM_RT0" "per , ""ERM,ERM_RT0""" menuitem "ERM_RT1" "per , ""ERM,ERM_RT1""" menuitem "ERM_RT2" "per , ""ERM,ERM_RT2""" menuitem "ERM_SPT" "per , ""ERM,ERM_SPT""" ) menuitem "FCCU" "per , ""FCCU""" popup "FLEXCAN;CAN" ( menuitem "CAN_0" "per , ""FLEXCAN (CAN),CAN_0""" menuitem "CAN_1" "per , ""FLEXCAN (CAN),CAN_1""" ) menuitem "FTM_0;FTM" "per , ""FLEXTIMER (FTM)""" menuitem "FXOSC" "per , ""FXOSC""" popup "GMAC;Realtime GMAC" ( menuitem "GMAC_0" "per , ""GMAC (Realtime GMAC),GMAC_0""" menuitem "GMAC_1" "per , ""GMAC (Realtime GMAC),GMAC_1""" ) popup "I2C;Inter-Integrated Circuit" ( menuitem "I2C_0" "per , ""I2C (Inter-Integrated Circuit),I2C_0""" menuitem "I2C_1" "per , ""I2C (Inter-Integrated Circuit),I2C_1""" ) menuitem "JDC" "per , ""JDC""" menuitem "LINFLEXD_0" "per , ""LINFLEXD""" popup "MC_CGM" ( menuitem "MC_CGM_0" "per , ""MC_CGM,MC_CGM_0""" menuitem "MC_CGM_1" "per , ""MC_CGM,MC_CGM_1""" menuitem "MC_CGM_2" "per , ""MC_CGM,MC_CGM_2""" menuitem "MC_CGM_3" "per , ""MC_CGM,MC_CGM_3""" ) menuitem "MC_ME" "per , ""MC_ME""" menuitem "MC_RGM" "per , ""MC_RGM""" menuitem "MCM" "per , ""MCM""" menuitem "MDM_AP" "per , ""MDM_AP""" popup "MIPICSI2" ( menuitem "MIPICSI2_0" "per , ""MIPICSI2,MIPICSI2_0""" menuitem "MIPICSI2_1" "per , ""MIPICSI2,MIPICSI2_1""" ) menuitem "MSCM" "per , ""MSCM""" popup "MU;MUA" ( menuitem "MU0__MUA" "per , ""MU (MUA),MU0__MUA""" menuitem "MU0__MUB" "per , ""MU (MUA),MU0__MUB""" menuitem "MU1__MUA" "per , ""MU (MUA),MU1__MUA""" menuitem "MU1__MUB" "per , ""MU (MUA),MU1__MUB""" ) menuitem "OCOTP" "per , ""OCOTP""" popup "PIT" ( menuitem "PIT_0" "per , ""PIT,PIT_0""" menuitem "PIT_2" "per , ""PIT,PIT_2""" ) popup "PLLDIG" ( menuitem "CORE_PLL" "per , ""PLLDIG,CORE_PLL""" menuitem "PERIPH_PLL" "per , ""PLLDIG,PERIPH_PLL""" ) menuitem "PMC" "per , ""PMC""" menuitem "PMUEVENTOBSERVER;PMUEVENT observer" "per , ""PMUEVENTOBSERVER (PMUEVENT observer)""" menuitem "QUADSPI;QuadSPI" "per , ""QUADSPI (QuadSPI)""" menuitem "QUADSPI_ARDB;ARDB" "per , ""QUADSPI_ARDB (ARDB)""" menuitem "RDC;Reset domain controller (RDC)" "per , ""RESET (Reset Control)""" menuitem "SDA_AP" "per , ""SDA_AP""" menuitem "SECURITY;Security subsystem" "per , ""SECURITY (Security subsystem)""" popup "SELFTEST_GPR" ( menuitem "SELFTEST_GPR_APP_MAIN_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_APP_MAIN_LBIST_PARTITION""" menuitem "SELFTEST_GPR_APP_MEM_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_APP_MEM_LBIST_PARTITION""" menuitem "SELFTEST_GPR_APP_NOC_REST_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_APP_NOC_REST_LBIST_PARTITION""" menuitem "SELFTEST_GPR_CLUSTER0" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER0""" menuitem "SELFTEST_GPR_CM7_0_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_CM7_0_LBIST_PARTITION""" menuitem "SELFTEST_GPR_CM7_1_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_CM7_1_LBIST_PARTITION""" menuitem "SELFTEST_GPR_CORE_NIU_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_CORE_NIU_LBIST_PARTITION""" menuitem "SELFTEST_GPR_HSE_RUN_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_HSE_RUN_LBIST_PARTITION""" menuitem "SELFTEST_GPR_MIPICSI2_SS_1" "per , ""SELFTEST_GPR,SELFTEST_GPR_MIPICSI2_SS_1""" menuitem "SELFTEST_GPR_RADAR_NIU_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_RADAR_NIU_LBIST_PARTITION""" menuitem "SELFTEST_GPR_RADAR_SS" "per , ""SELFTEST_GPR,SELFTEST_GPR_RADAR_SS""" menuitem "SELFTEST_GPR_RADAR_SS_SPT_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_RADAR_SS_SPT_PARTITION""" menuitem "SELFTEST_GPR_RT_AXBS0_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_RT_AXBS0_LBIST_PARTITION""" menuitem "SELFTEST_GPR_RT_AXBS1_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_RT_AXBS1_LBIST_PARTITION""" ) menuitem "SELFTEST_GPR_TOP" "per , ""SELFTEST_GPR_TOP""" popup "SEMA42" ( menuitem "SEMA42_0" "per , ""SEMA42,SEMA42_0""" menuitem "SEMA42_1" "per , ""SEMA42,SEMA42_1""" ) menuitem "SIUL2;SIUL2" "per , ""SIUL2""" popup "SPI" ( menuitem "SPI_0" "per , ""SPI,SPI_0""" menuitem "SPI_1" "per , ""SPI,SPI_1""" menuitem "SPI_2" "per , ""SPI,SPI_2""" menuitem "SPI_3" "per , ""SPI,SPI_3""" ) menuitem "SPT" "per , ""SPT""" popup "SRAM_CTL" ( menuitem "RETENTION_RAM" "per , ""SRAM_CTL,RETENTION_RAM""" menuitem "SRAM_CTRL_1" "per , ""SRAM_CTL,SRAM_CTRL_1""" menuitem "SRAM_CTRL_2" "per , ""SRAM_CTL,SRAM_CTRL_2""" menuitem "SRAM_CTRL_3" "per , ""SRAM_CTL,SRAM_CTRL_3""" menuitem "SRAM_CTRL_4" "per , ""SRAM_CTL,SRAM_CTRL_4""" menuitem "SRAM_CTRL_5" "per , ""SRAM_CTL,SRAM_CTRL_5""" menuitem "SRAM_CTRL_6" "per , ""SRAM_CTL,SRAM_CTRL_6""" menuitem "SRAM_CTRL_7" "per , ""SRAM_CTL,SRAM_CTRL_7""" menuitem "SRAM_CTRL_8" "per , ""SRAM_CTL,SRAM_CTRL_8""" ) menuitem "SRAMC" "per , ""SRAMC""" menuitem "SRC" "per , ""SRC (System Reset Controller)""" menuitem "SRC_GPR_TOP" "per , ""SRC_GPR_TOP""" menuitem "STCU2" "per , ""STCU2""" popup "STM;System Timer" ( menuitem "STM_0" "per , ""STM (System Timer),STM_0""" menuitem "STM_1" "per , ""STM (System Timer),STM_1""" menuitem "STM_2" "per , ""STM (System Timer),STM_2""" ) popup "SWT" ( menuitem "SWT_0" "per , ""SWT,SWT_0""" menuitem "SWT_1" "per , ""SWT,SWT_1""" menuitem "SWT_2" "per , ""SWT,SWT_2""" menuitem "SWT_3" "per , ""SWT,SWT_3""" ) menuitem "TMU" "per , ""TMU (Thermal Monitoring Unit)""" menuitem "WKPU" "per , ""WKPU""" popup "XBIC" ( menuitem "XBIC_0" "per , ""XBIC,XBIC_0""" menuitem "XBIC_1" "per , ""XBIC,XBIC_1""" menuitem "XBIC_2" "per , ""XBIC,XBIC_2""" menuitem "XBIC_3" "per , ""XBIC,XBIC_3""" menuitem "XBIC_4" "per , ""XBIC,XBIC_4""" menuitem "XBIC_5" "per , ""XBIC,XBIC_5""" ) popup "XRDC" ( menuitem "XRDC_0" "per , ""XRDC,XRDC_0""" menuitem "XRDC_1" "per , ""XRDC,XRDC_1""" ) ) )