; -------------------------------------------------------------------------------- ; @Title: RZT2M Specific Menu ; @Props: Released ; @Author: KRZ, ADR ; @Changelog: 2021-10-28 KRZ ; 2022-01-28 ADR ; 2022-06-23 KRZ ; @Manufacturer: RENESAS - Renesas Technology, Corp. ; @Core: Cortex-R52 ; @Chip: RZT2M ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menrzt2m.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-R52)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R52),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R52),System Control and Configuration""" menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R52),MPU Control and Configuration""" menuitem "[:chip]Memory Protection Unit PL1" "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL1""" menuitem "[:chip]Memory Protection Unit PL2" "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL2""" menuitem "[:chip]Virtualization Extensions" "per , ""Core Registers (Cortex-R52),Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R52),Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R52),System Performance Monitor""" menuitem "[:chip]System Timer Registers" "per , ""Core Registers (Cortex-R52),System Timer Registers""" menuitem "[:chip]Generic Interrupt Controller CPU Interface" "per , ""Core Registers (Cortex-R52),Generic Interrupt Controller CPU Interface""" separator menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R52),Debug Registers""" separator menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R52),Breakpoint Registers""" menuitem "[:chip]Watchpoint Registers" "per , ""Core Registers (Cortex-R52),Watchpoint Registers""" separator menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-R52),Interrupt Controller (GIC-500)""" ) separator popup "ADC (12-Bit A/D converter)" ( menuitem "ADC120" "per , ""ADC (12-Bit A/D converter),ADC120""" menuitem "ADC121" "per , ""ADC (12-Bit A/D converter),ADC121""" ) menuitem "BSC;Bus State Controller" "per , ""BSC (Bus State Controller)""" menuitem "CANFD;CAN-FD" "per , ""CANFD (CAN-FD)""" popup "CLMA (Clock Monitor Circuit)" ( menuitem "CLMA0" "per , ""CLMA (Clock Monitor Circuit),CLMA0""" menuitem "CLMA1" "per , ""CLMA (Clock Monitor Circuit),CLMA1""" menuitem "CLMA2" "per , ""CLMA (Clock Monitor Circuit),CLMA2""" menuitem "CLMA3" "per , ""CLMA (Clock Monitor Circuit),CLMA3""" ) popup "CMT (Compare Match Timer)" ( menuitem "CMT0" "per , ""CMT (Compare Match Timer),CMT0""" menuitem "CMT1" "per , ""CMT (Compare Match Timer),CMT1""" menuitem "CMT2" "per , ""CMT (Compare Match Timer),CMT2""" menuitem "CMT3" "per , ""CMT (Compare Match Timer),CMT3""" menuitem "CMT4" "per , ""CMT (Compare Match Timer),CMT4""" menuitem "CMT5" "per , ""CMT (Compare Match Timer),CMT5""" ) menuitem "CMTC;Compare Match Timer Control" "per , ""CMTC (Compare Match Timer Control)""" popup "CMTW (Compare Match Timer W)" ( menuitem "CMTW0" "per , ""CMTW (Compare Match Timer W),CMTW0""" menuitem "CMTW1" "per , ""CMTW (Compare Match Timer W),CMTW1""" ) popup "CRC (CRC Unit)" ( menuitem "CRC0" "per , ""CRC (CRC Unit),CRC0""" menuitem "CRC1" "per , ""CRC (CRC Unit),CRC1""" ) menuitem "DMA;DMAC Configuration" "per , ""DMA (DMAC Configuration)""" popup "DMAC (DMA Controller)" ( menuitem "DMAC0" "per , ""DMAC (DMA Controller),DMAC0""" menuitem "DMAC1" "per , ""DMAC (DMA Controller),DMAC1""" ) menuitem "DOC;Data Operation Circuit" "per , ""DOC (Data Operation Circuit)""" popup "DSMIF (Delta-sigma Interface)" ( menuitem "DSMIF0" "per , ""DSMIF (Delta-sigma Interface),DSMIF0""" menuitem "DSMIF1" "per , ""DSMIF (Delta-sigma Interface),DSMIF1""" ) menuitem "ELC;Evnet Link Controller" "per , ""ELC (Evnet Link Controller)""" menuitem "ELO;Evnet Link Option Setting" "per , ""ELO (Evnet Link Option Setting)""" menuitem "ESC;EtherCAT Slave Controller" "per , ""ESC (EtherCAT Slave Controller)""" menuitem "ESC_INI;Initial Configuration 1 for EtherCAT Slave.." "per , ""ESC_INI (Initial Configuration 1 for EtherCAT Slave Controller)""" menuitem "ETHSS;Ethernet Subsystem" "per , ""ETHSS (Ethernet Subsystem)""" menuitem "ETHSW;Ethernet Switch" "per , ""ETHSW (Ethernet Switch)""" menuitem "ETHSW_PTP;Ethernet Switch for PTP" "per , ""ETHSW_PTP (Ethernet Switch for PTP)""" menuitem "GMAC;Ethernet MAC" "per , ""GMAC (Ethernet MAC)""" popup "GPT (General Purpose Timer)" ( menuitem "GPT0" "per , ""GPT (General Purpose Timer),GPT0""" menuitem "GPT1" "per , ""GPT (General Purpose Timer),GPT1""" menuitem "GPT2" "per , ""GPT (General Purpose Timer),GPT2""" menuitem "GPT3" "per , ""GPT (General Purpose Timer),GPT3""" menuitem "GPT4" "per , ""GPT (General Purpose Timer),GPT4""" menuitem "GPT5" "per , ""GPT (General Purpose Timer),GPT5""" menuitem "GPT6" "per , ""GPT (General Purpose Timer),GPT6""" menuitem "GPT7" "per , ""GPT (General Purpose Timer),GPT7""" menuitem "GPT8" "per , ""GPT (General Purpose Timer),GPT8""" menuitem "GPT9" "per , ""GPT (General Purpose Timer),GPT9""" menuitem "GPT10" "per , ""GPT (General Purpose Timer),GPT10""" menuitem "GPT11" "per , ""GPT (General Purpose Timer),GPT11""" menuitem "GPT12" "per , ""GPT (General Purpose Timer),GPT12""" menuitem "GPT13" "per , ""GPT (General Purpose Timer),GPT13""" menuitem "GPT14" "per , ""GPT (General Purpose Timer),GPT14""" menuitem "GPT15" "per , ""GPT (General Purpose Timer),GPT15""" menuitem "GPT16" "per , ""GPT (General Purpose Timer),GPT16""" menuitem "GPT17" "per , ""GPT (General Purpose Timer),GPT17""" ) menuitem "GSC;Global System Counter" "per , ""GSC (Global System Counter)""" menuitem "ICU;Interrupt Controller" "per , ""ICU (Interrupt Controller)""" menuitem "ICU_NS;Interrupt Controller in Non Safety Domain" "per , ""ICU_NS (Interrupt Controller in Non Safety Domain)""" popup "IIC (I2C Bus Interface)" ( menuitem "IIC0" "per , ""IIC (I2C Bus Interface),IIC0""" menuitem "IIC1" "per , ""IIC (I2C Bus Interface),IIC1""" menuitem "IIC2" "per , ""IIC (I2C Bus Interface),IIC2""" ) menuitem "MPU_AC;Master MPU Access Control" "per , ""MPU_AC (Master MPU Access Control)""" popup "MPU (Master MPU)" ( menuitem "MPU0" "per , ""MPU (Master MPU),MPU0""" menuitem "MPU1" "per , ""MPU (Master MPU),MPU1""" menuitem "MPU2" "per , ""MPU (Master MPU),MPU2""" menuitem "MPU3" "per , ""MPU (Master MPU),MPU3""" menuitem "MPU4" "per , ""MPU (Master MPU),MPU4""" menuitem "MPU6" "per , ""MPU (Master MPU),MPU6""" ) menuitem "MTU;Multi-Function Timer Pulse Unit" "per , ""MTU (Memory Test Unit)""" menuitem "MTU_NF;Multi-Function Timer Pulse Unit Noise Filter" "per , ""MTU_NF (Multi-Function Timer Pulse Unit Noise Filter)""" popup "MTU (Memory Test Unit)" ( menuitem "MTU0" "per , ""MTU (Memory Test Unit),MTU0""" menuitem "MTU1" "per , ""MTU (Memory Test Unit),MTU1""" menuitem "MTU2" "per , ""MTU (Memory Test Unit),MTU2""" menuitem "MTU3" "per , ""MTU (Memory Test Unit),MTU3""" menuitem "MTU4" "per , ""MTU (Memory Test Unit),MTU4""" menuitem "MTU5" "per , ""MTU (Memory Test Unit),MTU5""" menuitem "MTU6" "per , ""MTU (Memory Test Unit),MTU6""" menuitem "MTU7" "per , ""MTU (Memory Test Unit),MTU7""" menuitem "MTU8" "per , ""MTU (Memory Test Unit),MTU8""" ) menuitem "OTP;One-Time Programmable Memory" "per , ""OTP (One-Time Programmable Memory)""" menuitem "POE3;Port Output Enable 3" "per , ""POE3 (Port Output Enable 3)""" popup "POEG (GPT Port Output Enable)" ( menuitem "POEG0" "per , ""POEG (GPT Port Output Enable),POEG0""" menuitem "POEG1" "per , ""POEG (GPT Port Output Enable),POEG1""" menuitem "POEG2" "per , ""POEG (GPT Port Output Enable),POEG2""" ) menuitem "PORT_NSR;I/O Ports (Non safety region)" "per , ""PORT_NSR (I/O Ports (Non safety region))""" menuitem "PORT_SR;I/O Ports (Safety region)" "per , ""PORT_SR (I/O Ports (Safety region))""" menuitem "PTADR;Port Address Selection" "per , ""PTADR (Port Address Selection)""" menuitem "RTC;Real Time Clock" "per , ""RTC (Real-time Counter)""" menuitem "RWP_NS;Register Write Protection for Non-safety Area" "per , ""RWP_NS (Register Write Protection for Non-safety Area)""" menuitem "RWP_S;Register Write Protection for Safety Area" "per , ""RWP_S (Register Write Protection for Safety Area)""" popup "SCI (Serial Communication Interface)" ( menuitem "SCI0" "per , ""SCI (Serial Communication Interface),SCI0""" menuitem "SCI1" "per , ""SCI (Serial Communication Interface),SCI1""" menuitem "SCI2" "per , ""SCI (Serial Communication Interface),SCI2""" menuitem "SCI3" "per , ""SCI (Serial Communication Interface),SCI3""" menuitem "SCI4" "per , ""SCI (Serial Communication Interface),SCI4""" menuitem "SCI5" "per , ""SCI (Serial Communication Interface),SCI5""" ) menuitem "SEM;Semaphore" "per , ""SEM (Semaphore)""" popup "SPI (Serial Peripheral Interface)" ( menuitem "SPI0" "per , ""SPI (Serial Peripheral Interface),SPI0""" menuitem "SPI1" "per , ""SPI (Serial Peripheral Interface),SPI1""" menuitem "SPI2" "per , ""SPI (Serial Peripheral Interface),SPI2""" menuitem "SPI3" "per , ""SPI (Serial Peripheral Interface),SPI3""" ) menuitem "SYSC_NS;System Control for Non-safety region" "per , ""SYSC_NS (System Control for Non-safety region)""" menuitem "SYSC_S;Register Write Protection for Safety Area" "per , ""SYSC_S (Register Write Protection for Safety Area)""" menuitem "SYSRAM_CTL;System SRAM Control" "per , ""SYSRAM_CTL (System SRAM Control)""" popup "SYSRAM (System SRAM)" ( menuitem "SYSRAM0" "per , ""SYSRAM (System SRAM),SYSRAM0""" menuitem "SYSRAM1" "per , ""SYSRAM (System SRAM),SYSRAM1""" menuitem "SYSRAM2" "per , ""SYSRAM (System SRAM),SYSRAM2""" menuitem "SYSRAM3" "per , ""SYSRAM (System SRAM),SYSRAM3""" ) menuitem "TCMAW;TCM access wait state" "per , ""TCMAW (TCM access wait state)""" menuitem "TFU;Arithmetic Unit for Trigonometric Functions" "per , ""TFU (Arithmetic Unit for Trigonometric Functions)""" menuitem "TSU;Temperature Sensor Unit" "per , ""TSU (Temperature Sensor Unit)""" menuitem "USBF;USB 2.0 Host and Function Module" "per , ""USBF (USB 2.0 Host and Function Module)""" menuitem "USBHC;USB 2.0 HS Host Module" "per , ""USBHC (USB 2.0 HS Host Module)""" popup "WDT (Watchdog Timer Unit)" ( menuitem "WDT0" "per , ""WDT (Watchdog Timer Unit),WDT0""" menuitem "WDT1" "per , ""WDT (Watchdog Timer Unit),WDT1""" ) popup "XSPI (xSPI)" ( menuitem "XSPI0" "per , ""XSPI (xSPI),XSPI0""" menuitem "XSPI1" "per , ""XSPI (xSPI),XSPI1""" ) ) )