; --------------------------------------------------------------------------------
; @Title: RM48Lxx Specific Menu
; @Props: Released
; @Author: ZAK, JAM
; @Changelog: 2012-09-28 ZAK
;             2019-02-13 JAM
; @Manufacturer: TI - Texas Instruments
; @Core: Cortex-R4
; @Chip: RM48L940-ZWT, RM48L950-PGE, RM48L950-ZWT, RM48L952-PGE
; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menrm48l.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-R4)"
(
menuitem "[:chip]ID Registers"                      "per , ""Core Registers (Cortex-R4),ID Registers"""
menuitem "[:chip]System Control and Configuration"  "per , ""Core Registers (Cortex-R4),System Control and Configuration"""
menuitem "[:chip]MPU Control and Configuration"     "per , ""Core Registers (Cortex-R4),MPU Control and Configuration"""
menuitem "[:chip]Cache Control and Configuration"   "per , ""Core Registers (Cortex-R4),Cache Control and Configuration"""
menuitem "[:chip]TCM Control and Configuration"     "per , ""Core Registers (Cortex-R4),TCM Control and Configuration"""
menuitem "[:chip]System Performance Monitor"        "per , ""Core Registers (Cortex-R4),System Performance Monitor"""
separator
menuitem "[:chip]Debug Registers"                   "per , ""Core Registers (Cortex-R4),Debug Registers"""
menuitem "[:chip]Breakpoint Registers"              "per , ""Core Registers (Cortex-R4),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers"      "per , ""Core Registers (Cortex-R4),Watchpoint Control Registers"""
)
separator
menuitem "SYS"                                      "per , ""SYS (Primary System Control Registers)"""
if (cpu()!="RM42L432")
(
menuitem "PMM"                                  "per , ""PMM (Power Management Module)"""
)
menuitem "IOMM"                                     "per , ""IOMM (I/O Multiplexing and Control Module)"""
menuitem "F021"                                     "per , ""F021 Flash Module"""
menuitem "TCRAM"                                    "per , ""TCRAM (Tightly-Coupled RAM Module)"""
menuitem "PBIST"                                    "per , ""PBIST (Programmable Built-In Self-Test)"""
menuitem "STC"                                      "per , ""STC (Self-Test Controller)"""
menuitem "CCM-R4F"                                  "per , ""CCM-R4F (CPU Compare Module - CortexR4)"""
if (cpu()=="RM42L432")
(
menuitem "Oscilator PLL and Clock Monitoring"   "per , ""Oscilator PLL and Clock Monitoring"""
)
else
(
menuitem "Oscilator and PLL"                    "per , ""Oscilator and PLL"""
)
menuitem "DCC"                                      "per , ""DCC (Dual-Clock Comparator)"""
menuitem "ESM"                                      "per , ""ESM (Error Signaling Module)"""
menuitem "RTI"                                      "per , ""RTI (Real Time Interrupt)"""
menuitem "CRC"                                      "per , ""CRC (Cyclic Redundancy Check Controller)"""
menuitem "VIM"                                      "per , ""VIM (Vectored Interrupt Manager),VIM"""
if (cpu()!="RM42L432")
(
menuitem "DMA"                                  "per , ""DMA (Direct Memory Access)"""
menuitem "EMIF"                                 "per , ""EMIF (External Memory Interface)"""
)
else
(
menuitem "eQEP"                                 "per , ""eQEP (Enhanced QEP)"""
)
if (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE")
(
menuitem "POM (Parameter Overlay Module)"       "per , ""POM (Parameter Overlay Module)"""
menuitem "eQEP"                                 "per , ""eQEP (Enhanced QEP)"""
menuitem "ePWM"                                 "per , ""ePWM (Enhanced Pulse Width Modulator)"""
menuitem "eCAP"                                 "per , ""eCAP (Enhanced Capture)"""
)
menuitem "ADC"                                      "per , ""ADC (Analog to Digital Converter)"""
menuitem "N2HET"                                    "per , ""N2HET (Enhanced High-End Timer)"""
menuitem "HTU"                                      "per , ""HTU (High End Timer Transfer Unit)"""
menuitem "GIO"                                      "per , ""GIO (General-Purpose Input/Output)"""
menuitem "DCAN"                                     "per , ""DCAN (Controller Area Network)"""
menuitem "SPI"                                      "per , ""SPI (Serial Peripheral Interface)"""
menuitem "SCI/LIN"                                  "per , ""SCI/LIN (Serial Communication Interface / Local Interconnect Network)"""
if (cpu()!="RM42L432")
(
menuitem "SCI"                                  "per , ""SCI (Serial Communication Interface)"""
menuitem "I2C"                                  "per , ""I2C (Inter-Integrated Circuit)"""
if (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE")
(
menuitem "EMAC/MDIO"                            "per , ""EMAC/MDIO (Ethernet Media Access Controller)"""
)
if (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE")
(
menuitem "USB Host"                             "per , ""USB (USB Host Controller Registers)"""
menuitem "USB Device"                           "per , ""USB (USB Device Controller Registers)"""
)
if (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE")
(
menuitem "eFUSE"                                "per , ""eFUSE (eFuse Controller Registers)"""
)
menuitem "DMM"                                  "per , ""DMM (Data Modification Module)"""
menuitem "RTP"                                  "per , ""RTP (RAM Trace Port)"""
)
else
(
menuitem "eFUSE"                                "per , ""eFUSE (eFuse Controller Registers)"""
)
)
)