; --------------------------------------------------------------------------------
; @Title: RA2E1 Specific Menu
; @Props: Released
; @Author: KWI, ADR, NEJ
; @Changelog: 2021-02-10 KWI
;             2022-01-28 ADR
;             2023-09-08 NEJ
; @Manufacturer: RENESAS - Renesas Technology, Corp.
; @Core: Cortex-M23
; @Chip: R7FA2E1A52DBV, R7FA2E1A52DFJ, R7FA2E1A52DFL, R7FA2E1A52DLM,
;        R7FA2E1A52DLM, R7FA2E1A52DNH, R7FA2E1A53CBV, R7FA2E1A53CFJ,
;        R7FA2E1A53CFL, R7FA2E1A53CLM, R7FA2E1A53CNE, R7FA2E1A53CNH,
;        R7FA2E1A72DBU, R7FA2E1A72DBV, R7FA2E1A72DFJ, R7FA2E1A72DFK,
;        R7FA2E1A72DFL, R7FA2E1A72DFM, R7FA2E1A72DLM, R7FA2E1A72DNE,
;        R7FA2E1A72DNH, R7FA2E1A73CBU, R7FA2E1A73CBV, R7FA2E1A73CFJ,
;        R7FA2E1A73CFK, R7FA2E1A73CFL, R7FA2E1A73CFM, R7FA2E1A73CLM,
;        R7FA2E1A73CNE, R7FA2E1A73CNH, R7FA2E1A92DBU, R7FA2E1A92DBV,
;        R7FA2E1A92DFJ, R7FA2E1A92DFJ, R7FA2E1A92DFL, R7FA2E1A92DFM,
;        R7FA2E1A92DLM, R7FA2E1A92DNE, R7FA2E1A92DNH, R7FA2E1A93CBU,
;        R7FA2E1A93CBV, R7FA2E1A93CFJ, R7FA2E1A93CFK, R7FA2E1A93CFL,
;        R7FA2E1A93CFM, R7FA2E1A93CLM, R7FA2E1A93CNE, R7FA2E1A93CNH
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menra2e1.men 16620 2023-09-14 10:36:24Z apopow $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M23)"
(
menuitem "[:chip]System Control"                                   "per , ""Core Registers (Cortex-M23),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                       "per , ""Core Registers (Cortex-M23),Memory Protection Unit (MPU)"""
menuitem "[:chip]SAU;Security Attribution Unit"                    "per , ""Core Registers (Cortex-M23),Security Attribution Unit (SAU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"        "per , ""Core Registers (Cortex-M23),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                   "per , ""Core Registers (Cortex-M23),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"          "per , ""Core Registers (Cortex-M23),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"           "per , ""Core Registers (Cortex-M23),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "ACMPLP;Low-Power Analog Comparator"                   "per , ""ACMPLP (Low-Power Analog Comparator)"""
menuitem "ADC120;12-bit A/D Converter"                          "per , ""ADC120 (12-bit A/D Converter)"""
popup "AGT;Low Power Asynchronous General Purpose Timer"
(
menuitem "AGT0"                                             "per , ""AGT (Low Power Asynchronous General Purpose Timer),AGT0"""
menuitem "AGT1"                                             "per , ""AGT (Low Power Asynchronous General Purpose Timer),AGT1"""
)
menuitem "BUS;BUS Control"                                      "per , ""BUS (BUS Control)"""
menuitem "CAC;Clock Frequency Accuracy Measurement Circuit"     "per , ""CAC (Clock Frequency Accuracy Measurement Circuit)"""
menuitem "CRC;Cyclic Redundancy Check Calculator"               "per , ""CRC (Cyclic Redundancy Check Calculator)"""
menuitem "CTSU;Capacitive Touch Sensing Unit"                   "per , ""CTSU (Capacitive Touch Sensing Unit)"""
menuitem "DBG;Debug Function"                                   "per , ""DBG (Debug Function)"""
menuitem "DOC;Data Operation Circuit"                           "per , ""DOC (Data Operation Circuit)"""
menuitem "DTC;Data Transfer Controller"                         "per , ""DTC (Data Transfer Controller)"""
menuitem "ELC;Event Link Controller"                            "per , ""ELC (Event Link Controller)"""
menuitem "FLCN;Flash I/O Registers"                             "per , ""FLCN (Flash I/O Registers)"""
popup "GPT;General Purpose Timer"
(
menuitem "GPT164"                                           "per , ""GPT (General Purpose Timer),GPT164"""
menuitem "GPT165"                                           "per , ""GPT (General Purpose Timer),GPT165"""
menuitem "GPT166"                                           "per , ""GPT (General Purpose Timer),GPT166"""
menuitem "GPT167"                                           "per , ""GPT (General Purpose Timer),GPT167"""
menuitem "GPT168"                                           "per , ""GPT (General Purpose Timer),GPT168"""
menuitem "GPT169"                                           "per , ""GPT (General Purpose Timer),GPT169"""
menuitem "GPT320"                                           "per , ""GPT (General Purpose Timer),GPT320"""
)
menuitem "GPT_OPS;Output Phase Switching Controller"            "per , ""GPT_OPS (Output Phase Switching Controller)"""
menuitem "ICU;ICU for CPU"                                      "per , ""ICU (ICU for CPU)"""
menuitem "IIC0;Inter-Integrated Circuit 0"                      "per , ""IIC0 (Inter-Integrated Circuit 0)"""
menuitem "IIC0WU;Inter-Integrated Circuit 0 Wake-up Unit"       "per , ""IIC0WU (Inter-Integrated Circuit 0 Wake-up Unit)"""
menuitem "IWDT;Independent Watchdog Timer"                      "per , ""IWDT (Independent Watchdog Timer)"""
menuitem "KINT;Key Interrupt Function"                          "per , ""KINT (Key Interrupt Function)"""
menuitem "MSTP;Module Stop Control B  C  D"                     "per , ""MSTP (Module Stop Control B  C  D)"""
menuitem "PFS;Pmn Pin Function Control Register"                "per , ""PFS (Pmn Pin Function Control Register)"""
menuitem "POEG;Port Output Enable Module for GPT"               "per , ""POEG (Port Output Enable Module for GPT)"""
popup "PORT;Port Control Registers"
(
menuitem "PORT0"                                            "per , ""PORT (Port Control Registers),PORT0"""
menuitem "PORT1"                                            "per , ""PORT (Port Control Registers),PORT1"""
menuitem "PORT2"                                            "per , ""PORT (Port Control Registers),PORT2"""
menuitem "PORT3"                                            "per , ""PORT (Port Control Registers),PORT3"""
menuitem "PORT4"                                            "per , ""PORT (Port Control Registers),PORT4"""
menuitem "PORT5"                                            "per , ""PORT (Port Control Registers),PORT5"""
menuitem "PORT9"                                            "per , ""PORT (Port Control Registers),PORT9"""
)
menuitem "RMPU;Renesas Memory Protection Unit"                  "per , ""RMPU (Renesas Memory Protection Unit)"""
menuitem "RTC;Realtime Clock"                                   "per , ""RTC (Realtime Clock)"""
popup "SCI;Serial Communication Interface"
(
menuitem "SCI0"                                             "per , ""SCI (Serial Communication Interface),SCI0"""
menuitem "SCI1"                                             "per , ""SCI (Serial Communication Interface),SCI1"""
menuitem "SCI2"                                             "per , ""SCI (Serial Communication Interface),SCI2"""
menuitem "SCI9"                                             "per , ""SCI (Serial Communication Interface),SCI9"""
)
menuitem "SPI0;Serial Peripheral Interface"                     "per , ""SPI0 (Serial Peripheral Interface)"""
menuitem "SRAM;SRAM Control"                                    "per , ""SRAM (SRAM Control)"""
menuitem "SYSC;System Control"                                  "per , ""SYSC (System Control)"""
menuitem "WDT;Watchdog Timer"                                   "per , ""WDT (Watchdog Timer)"""
)
)