; --------------------------------------------------------------------------------
; @Title: RA2A1 Specific Menu
; @Props: Released
; @Author: NEJ
; @Changelog: 2022-05-19 NEJ
; @Manufacturer: RENESAS - Renesas Technology, Corp.
; @Core: Cortex-M23
; @Chip: R7FA2A1AB2CBT, R7FA2A1AB3CFJ, R7FA2A1AB3CFM, R7FA2A1AB3CNE,
;        R7FA2A1AB3CNF
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menra2a1.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M23)"
(
menuitem "[:chip]System Control"                                   "per , ""Core Registers (Cortex-M23),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                       "per , ""Core Registers (Cortex-M23),Memory Protection Unit (MPU)"""
menuitem "[:chip]SAU;Security Attribution Unit"                    "per , ""Core Registers (Cortex-M23),Security Attribution Unit (SAU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"        "per , ""Core Registers (Cortex-M23),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                   "per , ""Core Registers (Cortex-M23),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"          "per , ""Core Registers (Cortex-M23),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"           "per , ""Core Registers (Cortex-M23),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "ACMPHS"       "per , ""ACMPHS (High-Speed Analog Comparator)"""
menuitem "ACMPLP"       "per , ""ACMPLP (Low-Power Analog Comparator)"""
menuitem "ADC16"        "per , ""ADC16 (16-bit A/D Converter)"""
popup "AGT (Asynchronous General Purpose Timer)"
(
menuitem "AGT0"     "per , ""AGT (Asynchronous General Purpose Timer),AGT0"""
)
menuitem "BUS"          "per , ""BUS (BUS Control)"""
menuitem "CAC"          "per , ""CAC (Clock Frequency Accuracy Measurement Circuit)"""
menuitem "CAN"          "per , ""CAN (CAN Module)"""
menuitem "CRC"          "per , ""CRC (CRC Calculator)"""
menuitem "CTSU"         "per , ""CTSU (Capacitive Touch Sensing Unit)"""
popup "DAC (D/A Converter)"
(
menuitem "DAC8"     "per , ""DAC (D/A Converter),DAC8"""
menuitem "DAC12"    "per , ""DAC (D/A Converter),DAC12"""
)
menuitem "DBG"          "per , ""DBG (Debug Function)"""
menuitem "DOC"          "per , ""DOC (Data Operation Circuit)"""
menuitem "DTC"          "per , ""DTC (Data Transfer Controller)"""
menuitem "FCACHE"       "per , ""FCACHE (Flash Cache)"""
menuitem "GPT_OPS"      "per , ""GPT_OPS (Output Phase Switching Controller)"""
menuitem "ELC"          "per , ""ELC (Event Link Controller)"""
popup "GPT (General Purpose Timer)"
(
menuitem "GPT161"   "per , ""GPT (General Purpose Timer),GPT161"""
menuitem "GPT320"   "per , ""GPT (General Purpose Timer),GPT320"""
)
menuitem "ICU"          "per , ""ICU (Interrupt Controller)"""
popup "IIC (Inter-Integrated Circuit)"
(
menuitem "IIC0"     "per , ""IIC (Inter-Integrated Circuit),IIC0"""
menuitem "IIC1"     "per , ""IIC (Inter-Integrated Circuit),IIC1"""
)
menuitem "IWDT"         "per , ""IWDT (Independent Watchdog Timer)"""
menuitem "KINT"         "per , ""KINT (Key Interrupt Function)"""
menuitem "MMF"          "per , ""MMF (Memory Mirror Function)"""
menuitem "MMPU"         "per , ""MMPU (Bus Master MPU)"""
menuitem "MSTP"         "per , ""MSTP (Module Stop Control)"""
menuitem "OPAMP"        "per , ""OPAMP (Operational Amplifier)"""
menuitem "PFS"          "per , ""PFS (Pmn Pin Function Control Register)"""
menuitem "PMISC"        "per , ""PMISC (Miscellaneous Port Control Register)"""
menuitem "POEG"         "per , ""POEG (Port Output Enable Module for GPT)"""
popup "PORT (Port Control Registers)"
(
menuitem "PORT0"    "per , ""PORT (Port Control Registers),PORT0"""
menuitem "PORT1"    "per , ""PORT (Port Control Registers),PORT1"""
)
menuitem "RTC"          "per , ""RTC (Real-time Counter)"""
popup "SCI (Serial Communication Interface)"
(
menuitem "SCI0"     "per , ""SCI (Serial Communication Interface),SCI0"""
menuitem "SCI1"     "per , ""SCI (Serial Communication Interface),SCI1"""
)
menuitem "SDADC24"      "per , ""SDADC24 (24-bit Sigma-Delta A/D Converter)"""
menuitem "SMPU"         "per , ""SMPU (Bus Slave MPU)"""
popup "SPI (Serial Peripheral Interface)"
(
menuitem "SPI0"     "per , ""SPI (Serial Peripheral Interface),SPI0"""
)
menuitem "SPMON"        "per , ""SPMON (CPU Stack Pointer Monitor)"""
menuitem "SRAM"         "per , ""SRAM (SRAM Control)"""
menuitem "SYSTEM"       "per , ""SYSTEM (System Control)"""
menuitem "TSN"          "per , ""TSN (Temperature Sensor)"""
menuitem "USBFS"        "per , ""USBFS (USB 2.0 FS Module)"""
menuitem "WDT"          "per , ""WDT (Watchdog Timer Unit)"""
)
)