; -------------------------------------------------------------------------------- ; @Title: QN908x Specific Menu ; @Props: Released ; @Author: PID, LST ; @Changelog: 2019-03-19 PID ; @Manufacturer: NXP - NXP Semiconductors ; @Core: Cortex-M4F ; @Chip: QN9080DHN, QN9083DUK ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menqn908x.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-M4F)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller""" menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) separator menuitem "SYSCON" "per , ""SYSCON (System Architecture And Configuration)""" menuitem "NVIC" "per , ""NVIC (Nested Vectored Interrupt Control)""" menuitem "Input MUX" "per , ""Input MUX (Input Multiplexing)""" popup "GPIO" ( menuitem "GPIOA" "per , ""GPIO (General Purpose I/O),GPIOA""" menuitem "GPIOB" "per , ""GPIO (General Purpose I/O),GPIOB""" ) menuitem "PINT" "per , ""PINT (Pin Interrupt And Pattern Match)""" menuitem "DMA " "per , ""DMA (DMA Controller)""" menuitem "SCT" "per , ""SCT (SCTimer/PWM)""" popup "CTIMER" ( menuitem "CTIMER0" "per , ""CTIMER (Standard Counter/Timers),CTIMER0""" menuitem "CTIMER1" "per , ""CTIMER (Standard Counter/Timers),CTIMER1""" menuitem "CTIMER2" "per , ""CTIMER (Standard Counter/Timers),CTIMER2""" menuitem "CTIMER3" "per , ""CTIMER (Standard Counter/Timers),CTIMER3""" ) menuitem "WDT" "per , ""WDT (WatchDog Timer)""" menuitem "RTC" "per , ""RTC (Real-Time Clock)""" menuitem "SYSTICK" "per , ""SYSTICK (CPU System Tick Timer)""" menuitem "FSP" "per , ""FSP (Fusion Signal Processing)""" menuitem "USB 2.0" "per , ""USB 2.0 (USB 2.0 Device Controller)""" popup "FISC" ( menuitem "Flexcomm 0" "per , ""FISC (Flexcomm Interface Serial Communication),Flexcomm 0""" menuitem "Flexcomm 1" "per , ""FISC (Flexcomm Interface Serial Communication),Flexcomm 1""" menuitem "Flexcomm 2" "per , ""FISC (Flexcomm Interface Serial Communication),Flexcomm 2""" menuitem "Flexcomm 3" "per , ""FISC (Flexcomm Interface Serial Communication),Flexcomm 3""" ) popup "USART" ( menuitem "USART0" "per , ""USART,USART0""" menuitem "USART1" "per , ""USART,USART1""" ) popup "SPI" ( menuitem "SPI0" "per , ""SPI,SPI0""" menuitem "SPI1" "per , ""SPI,SPI1""" ) popup "I2C" ( menuitem "I2C0" "per , ""I2C,I2C0""" menuitem "I2C1" "per , ""I2C,I2C1""" ) popup "QDEC" ( menuitem "QDEC0" "per , ""QDEC (Quadrature Decoder),QDEC0""" menuitem "QDEC1" "per , ""QDEC (Quadrature Decoder),QDEC1""" ) menuitem "SPIFI" "per , ""SPIFI (SPI Flash Interface)""" menuitem "RNG" "per , ""RNG (Random Number Generator)""" menuitem "CRC Engine" "per , ""CRC Engine""" menuitem "Flash Memory Controller" "per , ""Flash Memory Controller""" menuitem "DAC" "per , ""DAC""" menuitem "ADC" "per , ""ADC (SD ADC Controller)""" menuitem "Capacitive Sense" "per , ""Capacitive Sense""" menuitem "Radio" "per , ""Radio""" ) )