; --------------------------------------------------------------------------------
; @Title: Mpsoc Specific Menu
; @Props: Released
; @Author: AMM, WYS, KKW, SEB, JRK
; @Manufacturer: XILINX - XILINX
; @Changelog: 2015-02-12 AMM
;             2016-03-07 KKW
;             2016-07-01 SEB
;             2016-08-08 JRK
;             2019-04-26 KMB
; @Core: CORTEX-A53, CORTEX-R5MPCORE
; @Chip: UltraScale+ MPSoC
; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menmpsoc.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXA53")
(
popup "[:chip]Core Registers (Cortex-A53)"
(
menuitem "[:chip]ID Registers[AArch64]"                                     "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch64]"                 "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch64]"                           "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch64]"                        "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch64]"                  "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch64]"                       "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch64]"                           "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]"       "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch64]"                                  "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch64]"                             "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers[AArch64]"                     "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
separator
menuitem "[:chip]ID Registers[AArch32]"                                     "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch32]"                 "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch32]"                           "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch32]"                        "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch32]"                  "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch32]"                       "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch32]"                           "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]"       "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch32]"                                  "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch32]"                             "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers[AArch32]"                     "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
separator
menuitem "[:chip]Interrupt Controller (GIC-400)"                            "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-400)"""
)
menuitem "[:chip]GIC-400;(ARM Generic Interrupt Controller)"            "per , ""GIC400 (ARM Generic Interrupt Controller)"""
menuitem "[:chip]ARMv8 SMMUv2"                                          "per , ""ARMv8 SMMUv2"""
)
else if (CORENAME()=="CORTEXR5MPCORE")
(
popup "[:chip]Core Registers (Cortex-R5MPCore)"
(
menuitem "[:chip]ID Registers"                      "per , ""Core Registers (Cortex-R5MPCore),ID Registers"""
menuitem "[:chip]System Control and Configuration"  "per , ""Core Registers (Cortex-R5MPCore),System Control and Configuration"""
menuitem "[:chip]MPU Control and Configuration"     "per , ""Core Registers (Cortex-R5MPCore),MPU Control and Configuration"""
menuitem "[:chip]Cache Control and Configuration"   "per , ""Core Registers (Cortex-R5MPCore),Cache Control and Configuration"""
menuitem "[:chip]TCM Control and Configuration"     "per , ""Core Registers (Cortex-R5MPCore),TCM Control and Configuration"""
menuitem "[:chip]System Performance Monitor"        "per , ""Core Registers (Cortex-R5MPCore),System Performance Monitor"""
separator
menuitem "[:chip]Debug Registers"                   "per , ""Core Registers (Cortex-R5MPCore),Debug Registers"""
menuitem "[:chip]Breakpoint Registers"              "per , ""Core Registers (Cortex-R5MPCore),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers"      "per , ""Core Registers (Cortex-R5MPCore),Watchpoint Control Registers"""
separator
menuitem "[:chip]Interrupt Controller (PL-390)"     "per , ""Core Registers (Cortex-R5MPCore),Interrupt Controller (PL-390)"""
)
)
separator
popup "ZDMA;(General Purpose DMA)"
(
menuitem "ADMA_CH0"                                                     "per , ""ZDMA (General Purpose DMA),ADMA_CH0"""
menuitem "ADMA_CH1"                                                     "per , ""ZDMA (General Purpose DMA),ADMA_CH1"""
menuitem "ADMA_CH2"                                                     "per , ""ZDMA (General Purpose DMA),ADMA_CH2"""
menuitem "ADMA_CH3"                                                     "per , ""ZDMA (General Purpose DMA),ADMA_CH3"""
menuitem "ADMA_CH4"                                                     "per , ""ZDMA (General Purpose DMA),ADMA_CH4"""
menuitem "ADMA_CH5"                                                     "per , ""ZDMA (General Purpose DMA),ADMA_CH5"""
menuitem "ADMA_CH6"                                                     "per , ""ZDMA (General Purpose DMA),ADMA_CH6"""
menuitem "ADMA_CH7"                                                     "per , ""ZDMA (General Purpose DMA),ADMA_CH7"""
separator
menuitem "GDMA_CH0"                                                     "per , ""ZDMA (General Purpose DMA),GDMA_CH0"""
menuitem "GDMA_CH1"                                                     "per , ""ZDMA (General Purpose DMA),GDMA_CH1"""
menuitem "GDMA_CH2"                                                     "per , ""ZDMA (General Purpose DMA),GDMA_CH2"""
menuitem "GDMA_CH3"                                                     "per , ""ZDMA (General Purpose DMA),GDMA_CH3"""
menuitem "GDMA_CH4"                                                     "per , ""ZDMA (General Purpose DMA),GDMA_CH4"""
menuitem "GDMA_CH5"                                                     "per , ""ZDMA (General Purpose DMA),GDMA_CH5"""
menuitem "GDMA_CH6"                                                     "per , ""ZDMA (General Purpose DMA),GDMA_CH6"""
menuitem "GDMA_CH7"                                                     "per , ""ZDMA (General Purpose DMA),GDMA_CH7"""
)
popup "AFIFM;(AXI Fabric Master Interface and Configuration)"
(
menuitem "AFIFM 0"                                                      "per , ""AFIFM (AXI Fabric Master Interface and Configuration),AFIFM 0"""
menuitem "AFIFM 1"                                                      "per , ""AFIFM (AXI Fabric Master Interface and Configuration),AFIFM 1"""
menuitem "AFIFM 2"                                                      "per , ""AFIFM (AXI Fabric Master Interface and Configuration),AFIFM 2"""
menuitem "AFIFM 3"                                                      "per , ""AFIFM (AXI Fabric Master Interface and Configuration),AFIFM 3"""
menuitem "AFIFM 4"                                                      "per , ""AFIFM (AXI Fabric Master Interface and Configuration),AFIFM 4"""
menuitem "AFIFM 5"                                                      "per , ""AFIFM (AXI Fabric Master Interface and Configuration),AFIFM 5"""
menuitem "AFIFM 6"                                                      "per , ""AFIFM (AXI Fabric Master Interface and Configuration),AFIFM 6"""
)
popup "AMS;(Analog Monitor System)"
(
menuitem "Control"                                                      "per , ""AMS (Analog Monitor System),Control"""
menuitem "PL SYSMON"                                                    "per , ""AMS (Analog Monitor System),PL SYSMON"""
menuitem "PS SYSMON"                                                    "per , ""AMS (Analog Monitor System),PS SYSMON"""
)
popup "APM;(AXI Performance Monitor)"
(
menuitem "APM_CCI_INTC"                                                 "per , ""APM (AXI Performance Monitor),APM_CCI_INTC"""
menuitem "APM_INTC_OCM"                                                 "per , ""APM (AXI Performance Monitor),APM_INTC_OCM"""
menuitem "APM_LPD_FPD"                                                  "per , ""APM (AXI Performance Monitor),APM_LPD_FPD"""
menuitem "APMDDR"                                                       "per , ""APM (AXI Performance Monitor),APMDDR"""
)
menuitem "APU;(Application Processing Unit)"                                "per , ""APU (Application Processing Unit)"""
popup "AXIPCIE;(AXI to PCIe Bridge)"
(
menuitem "DMA0"                                                         "per , ""AXIPCIE (AXI to PCIe Bridge),DMA0"""
menuitem "DMA1"                                                         "per , ""AXIPCIE (AXI to PCIe Bridge),DMA1"""
menuitem "DMA2"                                                         "per , ""AXIPCIE (AXI to PCIe Bridge),DMA2"""
menuitem "DMA3"                                                         "per , ""AXIPCIE (AXI to PCIe Bridge),DMA3"""
separator
menuitem "Egress Address Channel Control and Status 0"                  "per , ""AXIPCIE (AXI to PCIe Bridge),Egress Address Channel Control and Status 0"""
menuitem "Egress Address Channel Control and Status 1"                  "per , ""AXIPCIE (AXI to PCIe Bridge),Egress Address Channel Control and Status 1"""
menuitem "Egress Address Channel Control and Status 2"                  "per , ""AXIPCIE (AXI to PCIe Bridge),Egress Address Channel Control and Status 2"""
menuitem "Egress Address Channel Control and Status 3"                  "per , ""AXIPCIE (AXI to PCIe Bridge),Egress Address Channel Control and Status 3"""
menuitem "Egress Address Channel Control and Status 4"                  "per , ""AXIPCIE (AXI to PCIe Bridge),Egress Address Channel Control and Status 4"""
menuitem "Egress Address Channel Control and Status 5"                  "per , ""AXIPCIE (AXI to PCIe Bridge),Egress Address Channel Control and Status 5"""
menuitem "Egress Address Channel Control and Status 6"                  "per , ""AXIPCIE (AXI to PCIe Bridge),Egress Address Channel Control and Status 6"""
menuitem "Egress Address Channel Control and Status 7"                  "per , ""AXIPCIE (AXI to PCIe Bridge),Egress Address Channel Control and Status 7"""
separator
menuitem "Ingress Address Channel Control and Status 0"                 "per , ""AXIPCIE (AXI to PCIe Bridge),Ingress Address Channel Control and Status 0"""
menuitem "Ingress Address Channel Control and Status 1"                 "per , ""AXIPCIE (AXI to PCIe Bridge),Ingress Address Channel Control and Status 1"""
menuitem "Ingress Address Channel Control and Status 2"                 "per , ""AXIPCIE (AXI to PCIe Bridge),Ingress Address Channel Control and Status 2"""
menuitem "Ingress Address Channel Control and Status 3"                 "per , ""AXIPCIE (AXI to PCIe Bridge),Ingress Address Channel Control and Status 3"""
menuitem "Ingress Address Channel Control and Status 4"                 "per , ""AXIPCIE (AXI to PCIe Bridge),Ingress Address Channel Control and Status 4"""
menuitem "Ingress Address Channel Control and Status 5"                 "per , ""AXIPCIE (AXI to PCIe Bridge),Ingress Address Channel Control and Status 5"""
menuitem "Ingress Address Channel Control and Status 6"                 "per , ""AXIPCIE (AXI to PCIe Bridge),Ingress Address Channel Control and Status 6"""
menuitem "Ingress Address Channel Control and Status 7"                 "per , ""AXIPCIE (AXI to PCIe Bridge),Ingress Address Channel Control and Status 7"""
separator
menuitem "Main Control and Status"                                      "per , ""AXIPCIE (AXI to PCIe Bridge),Main Control and Status"""
)
menuitem "BBRAM;(Battery Backed RAM)"                                       "per , ""BBRAM (Battery Backed RAM)"""
popup "CAN;(Controller Area Network)"
(
menuitem "CAN0"                                                         "per , ""CAN (Controller Area Network),CAN0"""
menuitem "CAN1"                                                         "per , ""CAN (Controller Area Network),CAN1"""
)
menuitem "CCI400;(Cache Coherent Interconnect)"                             "per , ""CCI400 (Cache Coherent Interconnect)"""
menuitem "CRF_APB;(Clock Controller Full Power Domain)"                     "per , ""CRF_APB (Clock Controller Full Power Domain)"""
menuitem "CRL_APB;(Clock Controller Low Power Domain)"                      "per , ""CRL_APB (Clock Controller Low Power Domain)"""
popup "CSU;(Configuration Security Unit)"
(
menuitem "CSU"                                                          "per , ""CSU (Configuration Security Unit),CSU"""
menuitem "CSUDMA"                                                       "per , ""CSU (Configuration Security Unit),CSUDMA"""
)
popup "SWDT;(System Watchdog Timer)"
(
menuitem "CSU_WDT"                                                      "per , ""SWDT (System Watchdog Timer),CSU_WDT"""
menuitem "SWDT"                                                         "per , ""SWDT (System Watchdog Timer),SWDT"""
menuitem "WDT"                                                          "per , ""SWDT (System Watchdog Timer),WDT"""
)
menuitem "DDRC;(DDR Controller)"                                            "per , ""DDRC (DDR Controller)"""
menuitem "DDR_PHY;(DDR_PHY Module)"                                         "per , ""DDR_PHY (DDR_PHY Module)"""
menuitem "DDR_QOS_CTRL;(Quality of Service Controller)"                     "per , ""DDR_QOS_CTRL (Quality of Service Controller)"""
popup "XMPU_DDR;(Xilinx Memory Protection)"
(
menuitem "DDR_XMPU0_CFG"                                                "per , ""XMPU_DDR (Xilinx Memory Protection),DDR_XMPU0_CFG"""
menuitem "DDR_XMPU1_CFG"                                                "per , ""XMPU_DDR (Xilinx Memory Protection),DDR_XMPU1_CFG"""
menuitem "DDR_XMPU2_CFG"                                                "per , ""XMPU_DDR (Xilinx Memory Protection),DDR_XMPU2_CFG"""
menuitem "DDR_XMPU3_CFG"                                                "per , ""XMPU_DDR (Xilinx Memory Protection),DDR_XMPU3_CFG"""
menuitem "DDR_XMPU4_CFG"                                                "per , ""XMPU_DDR (Xilinx Memory Protection),DDR_XMPU4_CFG"""
menuitem "DDR_XMPU5_CFG"                                                "per , ""XMPU_DDR (Xilinx Memory Protection),DDR_XMPU5_CFG"""
)
popup "DP;(Display Port Subsystem)"
(
menuitem "DP"                                                           "per , ""DP (Display Port Subsystem),DP"""
menuitem "DPDMA"                                                        "per , ""DP (Display Port Subsystem),DPDMA"""
)
menuitem "EFUSE;(EFUSE Module)"                                             "per , ""EFUSE (EFUSE Module)"""
menuitem "FPD_GPV;(Full Power Domain GPV)"                                  "per , ""FPD_GPV (Full Power Domain GPV)"""
menuitem "FPD_SLCR;(Full Power Domain SLCR)"                                "per , ""FPD_SLCR (Full Power Domain SLCR)"""
menuitem "FPD_SLCR_SECURE;(Secure Full Power Domain SLCR)"                  "per , ""FPD_SLCR_SECURE (Secure Full Power Domain SLCR)"""
menuitem "XMPU_FPD;(XMPU FPD Module)"                                       "per , ""XMPU_FPD (XMPU FPD Module)"""
menuitem "XMPU_SINK;(XMPU Default Sink)"                                    "per , ""XMPU_SINK (XMPU Default Sink)"""
popup "GEM;(Gigabit Ethernet Controller)"
(
menuitem "GEM0"                                                         "per , ""GEM (Gigabit Ethernet Controller),GEM0"""
menuitem "GEM1"                                                         "per , ""GEM (Gigabit Ethernet Controller),GEM1"""
menuitem "GEM2"                                                         "per , ""GEM (Gigabit Ethernet Controller),GEM2"""
menuitem "GEM3"                                                         "per , ""GEM (Gigabit Ethernet Controller),GEM3"""
)
menuitem "GPIO;(General Purpose Input/Output)"                              "per , ""GPIO (General Purpose Input/Output)"""
popup "GPU;(Graphics Processing Unit)"
(
menuitem "GPU"                                                          "per , ""GPU (Graphics Processing Unit),GPU"""
menuitem "PP0"                                                          "per , ""GPU (Graphics Processing Unit),PP0"""
menuitem "PP1"                                                          "per , ""GPU (Graphics Processing Unit),PP1"""
)
popup "I2C;(Inter Integrated Circuit)"
(
menuitem "I2C0"                                                         "per , ""I2C (Inter Integrated Circuit),I2C0"""
menuitem "I2C1"                                                         "per , ""I2C (Inter Integrated Circuit),I2C1"""
)
menuitem "IOU_GPV;(IOU GPV Module)"                                         "per , ""IOU_GPV (IOU GPV Module)"""
popup "CXTSGEN;(CXTSGEN Module)"
(
menuitem "IOU_SCNTR"                                                    "per , ""CXTSGEN (CXTSGEN Module),IOU_SCNTR"""
menuitem "IOU_SCNTRS"                                                   "per , ""CXTSGEN (CXTSGEN Module),IOU_SCNTRS"""
)
menuitem "IOU_SLCR_SECURE;(Secure IOU SLCR)"                                "per , ""IOU_SLCR_SECURE (Secure IOU SLCR)"""
menuitem "IOU_SLCR;(IOU SLCR Registers)"                                    "per , ""IOU_SLCR (IOU SLCR Registers)"""
menuitem "IPI;(Inter Processor Interrupts)"                                 "per , ""IPI (Inter Processor Interrupts)"""
menuitem "LPD_GPV;(LPD GPV Module)"                                         "per , ""LPD_GPV (LPD GPV Module)"""
menuitem "LPD_SLCR;(Low Power Domain SLCR)"                                 "per , ""LPD_SLCR (Low Power Domain SLCR)"""
menuitem "LPD_SLCR_SECURE;(Secure Low Power Domain SLCR)"                   "per , ""LPD_SLCR_SECURE (Secure Low Power Domain SLCR)"""
menuitem "LPD_XPPU;(XPPU Module)"                                           "per , ""LPD_XPPU (XPPU Module)"""
menuitem "XPPU_SINK;(XPPU Default Sink)"                                    "per , ""XPPU_SINK (XPPU Default Sink)"""
menuitem "MBISTJTAG;(MBIST JTAG-AP Bridge)"                                 "per , ""MBISTJTAG (MBIST JTAG-AP Bridge)"""
menuitem "NAND;(Nand Configuration Controller)"                             "per , ""NAND (Nand Configuration Controller)"""
menuitem "OCM;(On-Chip Memory)"                                             "per , ""OCM (On-Chip Memory)"""
menuitem "XMPU_OCMl;(XMPU_OCM Module)"                                      "per , ""XMPU_OCM (XMPU_OCM Module)"""
menuitem "PCIE_ATTRIB;(PCIe Controller Configuration)"                      "per , ""PCIE_ATTRIB (PCIe Controller Configuration)"""
menuitem "PMU_GLOBAL;(PMU Global)"                                          "per , ""PMU_GLOBAL (PMU Global)"""
menuitem "QSPI;(Quad-SPI Controller)"                                       "per , ""QSPI (Quad-SPI Controller)"""
menuitem "RPU;(Realtime Processing Unit)"                                   "per , ""RPU (Realtime Processing Unit)"""
popup "RSA;(RSA Module)"
(
menuitem "RSA"                                                          "per , ""RSA (RSA Module),RSA"""
menuitem "RSA_CORE"                                                     "per , ""RSA (RSA Module),RSA_CORE"""
)
menuitem "RTC;(Real-Time Clock)"                                            "per , ""RTC (Real-Time Clock)"""
popup "SATA;(Serial ATA)"
(
menuitem "SATA_AHCI_HBA"                                                "per , ""SATA (Serial ATA),SATA_AHCI_HBA"""
menuitem "SATA_AHCI_PORT0_CNTRL"                                        "per , ""SATA (Serial ATA),SATA_AHCI_PORT0_CNTRL"""
menuitem "SATA_AHCI_PORT1_CNTRL"                                        "per , ""SATA (Serial ATA),SATA_AHCI_PORT1_CNTRL"""
menuitem "SATA_AHCI_VENDOR"                                             "per , ""SATA (Serial ATA),SATA_AHCI_VENDOR"""
)
popup "SDIO;(SD3.0/SDIO3.0/MMC4.51 Host Controller)"
(
menuitem "SD0"                                                          "per , ""SDIO (SD3.0/SDIO3.0/MMC4.51 Host Controller),SD0"""
menuitem "SD1"                                                          "per , ""SDIO (SD3.0/SDIO3.0/MMC4.51 Host Controller),SD1"""
)
menuitem "SERDES;(Serializer/deserializer)"                                 "per , ""SERDES (Serializer/deserializer)"""
menuitem "SIOU;(Serial Input Output Unit)"                                  "per , ""SIOU (Serial Input Output Unit)"""
popup "SPI;(SPI Controller)"
(
menuitem "SPI 0"                                                        "per , ""SPI (SPI Controller),SPI 0"""
menuitem "SPI 1"                                                        "per , ""SPI (SPI Controller),SPI 1"""
)
popup "TTC;(Triple Timer Counter)"
(
menuitem "TTC0"                                                         "per , ""TTC (Triple Timer Counter),TTC0"""
menuitem "TTC1"                                                         "per , ""TTC (Triple Timer Counter),TTC1"""
menuitem "TTC2"                                                         "per , ""TTC (Triple Timer Counter),TTC2"""
menuitem "TTC3"                                                         "per , ""TTC (Triple Timer Counter),TTC3"""
)
popup "UART;(UART Controller)"
(
menuitem "UART 0"                                                       "per , ""UART (UART Controller),UART 0"""
menuitem "UART 1"                                                       "per , ""UART (UART Controller),UART 1"""
)
popup "USB3_REGS;(Universal Serial Bus 3.0)"
(
menuitem "USB3_0"                                                       "per , ""USB3_REGS (Universal Serial Bus 3.0),USB3_0"""
menuitem "USB3_1"                                                       "per , ""USB3_REGS (Universal Serial Bus 3.0),USB3_1"""
)
popup "USB3;(USB 2.0/3.0 Host, Device, and OTG Controller)"
(
menuitem "USB3_0_XHCI"                                                  "per , ""USB3 (USB 2.0/3.0 Host, Device, and OTG Controller),USB3_0_XHCI"""
menuitem "USB3_1_XHCI"                                                  "per , ""USB3 (USB 2.0/3.0 Host, Device, and OTG Controller),USB3_1_XHCI"""
)
popup "VCU;(Video Codec Unit)"
(
menuitem "VCU_SLCR"                                                     "per , ""VCU (Video Codec Unit),VCU_SLCR"""
menuitem "ALG_VCU_DEC_TOP"                                              "per , ""VCU (Video Codec Unit),ALG_VCU_DEC_TOP"""
menuitem "ALG_VCU_ENC_TOP"                                              "per , ""VCU (Video Codec Unit),ALG_VCU_ENC_TOP"""
)
)
)