; -------------------------------------------------------------------------------- ; @Title: MB86R12/MB86R11F Specific Menu ; @Props: Released ; @Author: AMM ; @Manufacturer: Fujitsu ; @Core: Cortex-A9 ; @Chip: MB86R12, MB86R11F ; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menmb86r1x.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-A9)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A9),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A9),System Control and Configuration""" menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A9),Memory Management Unit""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A9),Cache Control and Configuration""" menuitem "[:chip]L2 Preload Engine" "per , ""Core Registers (Cortex-A9),L2 Preload Engine""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A9),System Performance Monitor""" separator menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A9),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A9),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A9),Watchpoint Control Registers""" ) separator menuitem "CRG" "per , ""CRG (Clock reset generator)""" menuitem "Boot Controller" "per , ""Boot Controller""" menuitem "EBC " "per , ""EBC (External Bus Controller)""" menuitem "DDR Controller" "per , ""DDR Controller""" menuitem "HDMAC " "per , ""HDMAC (AHB-DMA Controller)""" menuitem "XDMAC " "per , ""XDMAC (AXI-DMA Controller)""" menuitem "GPIO " "per , ""GPIO (General Purpose Input/Output)""" menuitem "PWM " "per , ""PWM (Pulse Width Modulator)""" menuitem "ADC " "per , ""ADC (Analog-to-Digital Converter)""" menuitem "GDC " "per , ""GDC (Graphics display controller)""" menuitem "I2S Serial audio interface" "per , ""I2S Serial audio interface""" menuitem "UART" "per , ""UART""" menuitem "USART" "per , ""USART""" menuitem "I2C BUS interface" "per , ""I2C BUS interface""" menuitem "SFI " "per , ""SFI (Serial Flash Interface)""" if (CPU()=="MB86R11F") ( menuitem "USBHC " "per , ""USBHC (USB Host Controller)""" menuitem "USB " "per , ""USB HOST/FUNC Controller""" ) menuitem "IDE66 " "per , ""IDE66 (IDE Host Controller)""" menuitem "CCNT " "per , ""CCNT (Chip Controller)""" menuitem "EXIRC " "per , ""EXIRC (External interrupt controller)""" menuitem "IRDA " "per , ""IRDA (Infrared Data Association)""" menuitem "SIG " "per , ""SIG (Signature Unit)""" menuitem "Ethernet Link Controller" "per , ""Ethernet Link Controller""" menuitem "TCON " "per , ""TCON (Timing Controller)""" menuitem "RLD " "per , ""RLD (Run-Length Decompression)""" menuitem "HS-SPI " "per , ""HS-SPI (High Speed serial peripheral interface)""" menuitem "WDT " "per , ""WDT (Watchdog)""" menuitem "PMU " "per , ""PMU (Power Management Unit)""" menuitem "TS " "per , ""TS (Transport Stream Interface)""" if !(CPU()=="MB86R11F") ( menuitem "APIX_TX" "per , ""APIX_TX""" menuitem "APIX_RX" "per , ""APIX_RX""" menuitem "APIX_PHY" "per , ""APIX_PHY""" ) menuitem "AXI " "per , ""AXI (Bus Interconnect)""" if (CPU()=="MB86R11F") ( menuitem "CAN" "per , ""CAN""" ) ) )