; --------------------------------------------------------------------------------
; @Title: MAX32655 Specific Menu
; @Props: Released
; @Author: PIW
; @Changelog: 2022-05-11 PIW
; @Manufacturer: MAXIM - Maxim Integrated Products, Inc.
; @Core: Cortex-M4F
; @Chip: MAX32655GXG+, MAX32655GXG+T, MAX32655GWY+, MAX32655GWY+T
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menmax32655.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M4F)"
(
menuitem "[:chip]System Control"                                "per , ""Core Registers (Cortex-M4F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                    "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"     "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
menuitem "[:chip]FPU;Floating-point Unit"                       "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"       "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"        "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "ADC"          "per , ""ADC (Inter-Integrated Circuit)"""
menuitem "AES"          "per , ""AES (AES Keys)"""
menuitem "AES_KEY"      "per , ""AES_KEY (AES Key Registers)"""
menuitem "CRC"          "per , ""CRC (CRC Registers)"""
menuitem "DMA"          "per , ""DMA (DMA Controller Fully programmable chaining capable DMA channels)"""
menuitem "FCR"          "per , ""FCR (Function Control Register)"""
menuitem "FLC"          "per , ""FLC (Flash Memory Control)"""
menuitem "GCR"          "per , ""GCR (Global Control Registers)"""
popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
(
menuitem "GPIO0"    "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO0"""
menuitem "GPIO1"    "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO1"""
)
popup "I2C (Inter-Integrated Circuit)"
(
menuitem "I2C0"     "per , ""I2C (Inter-Integrated Circuit),I2C0"""
menuitem "I2C1"     "per , ""I2C (Inter-Integrated Circuit),I2C1"""
menuitem "I2C2"     "per , ""I2C (Inter-Integrated Circuit),I2C2"""
)
menuitem "I2S"          "per , ""I2S (Inter-Integrated Sound Bus Controller)"""
menuitem "ICC0"         "per , ""ICC0 (Instruction Cache Controller Registers)"""
menuitem "LPGCR"        "per , ""LPGCR (Low Power Global Control)"""
menuitem "MCR"          "per , ""MCR (Misc Control)"""
menuitem "OWM"          "per , ""OWM (1-Wire Master Interface)"""
popup "PULSE_TRAIN (Pulse Train)"
(
menuitem "PT"       "per , ""PULSE_TRAIN (Pulse Train),PT"""
menuitem "PT1"      "per , ""PULSE_TRAIN (Pulse Train),PT1"""
menuitem "PT2"      "per , ""PULSE_TRAIN (Pulse Train),PT2"""
menuitem "PT3"      "per , ""PULSE_TRAIN (Pulse Train),PT3"""
menuitem "PTG"      "per , ""PULSE_TRAIN (Pulse Train),PTG"""
)
menuitem "PWRSEQ"       "per , ""PWRSEQ (Power Sequencer / Low Power Control Register)"""
menuitem "RTC"          "per , ""RTC (Real-time Counter)"""
menuitem "SEMA"         "per , ""SEMA"""
menuitem "SIMO"         "per , ""SIMO (Single Inductor Multiple Output Switching Converter)"""
menuitem "SIR"          "per , ""SIR (System Initialization Registers)"""
popup "SPI (SPI peripheral)"
(
menuitem "SPI0"     "per , ""SPI (SPI peripheral),SPI0"""
menuitem "SPI1"     "per , ""SPI (SPI peripheral),SPI1"""
menuitem "SPI2"     "per , ""SPI (SPI peripheral),SPI2"""
)
popup "TMR (Low-Power Configurable Timer)"
(
menuitem "TMR"      "per , ""TMR (Low-Power Configurable Timer),TMR"""
menuitem "TMR1"     "per , ""TMR (Low-Power Configurable Timer),TMR1"""
menuitem "TMR2"     "per , ""TMR (Low-Power Configurable Timer),TMR2"""
menuitem "TMR3"     "per , ""TMR (Low-Power Configurable Timer),TMR3"""
menuitem "TMR4"     "per , ""TMR (Low-Power Configurable Timer),TMR4"""
menuitem "TMR5"     "per , ""TMR (Low-Power Configurable Timer),TMR5"""
)
menuitem "TRIMSIR"      "per , ""TRIMSIR (Trim System Initialization Registers)"""
menuitem "TRNG"         "per , ""TRNG (Random Number Generator)"""
popup "UART (Universal Asynchronous Receiver/Transmitter)"
(
menuitem "UART"     "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART"""
menuitem "UART1"    "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1"""
menuitem "UART2"    "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART2"""
menuitem "UART3"    "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART3"""
)
popup "WDT (Watchdog Timer Unit)"
(
menuitem "WDT"      "per , ""WDT (Watchdog Timer Unit),WDT"""
menuitem "WDT1"     "per , ""WDT (Watchdog Timer Unit),WDT1"""
)
menuitem "WUT"          "per , ""WUT (32-bit reloadable timer)"""
)
)