; -------------------------------------------------------------------------------- ; @Title: LPC55Sxx Specific Menu ; @Props: Released ; @Author: JAM, RSA, KRZ ; @Changelog: 2019-05-27 JAM ; 2022-02-18 RSA ; 2023-01-31 KRZ ; @Manufacturer: NXP - NXP Semiconductors ; @Core: Cortex-M33 / Cortex-M33F ; @Chip: LPC55S04JBD64, LPC55S04JHI48, LPC55S06JBD64, LPC55S06JHI48, ; LPC55S14JBD100, LPC55S14JBD64, LPC55S16JBD100, LPC55S16JBD64, ; LPC55S16JEV98, LPC55S26JBD100, LPC55S26JBD64, LPC55S26JEV98, ; LPC55S28JBD100, LPC55S28JBD64, LPC55S28JEV98, LPC55S66JBD100-CPU0, ; LPC55S66JBD100-CPU1, LPC55S66JBD64-CPU0, LPC55S66JBD64-CPU1, ; LPC55S66JEV98-CPU0, LPC55S66JEV98-CPU1, LPC55S69JBD100-CPU0, ; LPC55S69JBD100-CPU1, LPC55S69JBD64-CPU0, LPC55S69JBD64-CPU1, ; LPC55S69JEV98-CPU0, LPC55S69JEV98-CPU1 ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menlpc55sxx.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( if (CORENAME()=="CORTEXM33F") ( popup "[:chip]Core Registers (Cortex-M33F)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M33F),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M33F),Memory Protection Unit (MPU)""" menuitem "[:chip]SAU;Security Attribution Unit" "per , ""Core Registers (Cortex-M33F),Security Attribution Unit (SAU)""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M33F),Nested Vectored Interrupt Controller (NVIC)""" menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M33F),Floating-point Unit (FPU)""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M33F),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M33F),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M33F),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) else if (CORENAME()=="CORTEXM33") ( popup "[:chip]Core Registers (Cortex-M33)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M33),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M33),Memory Protection Unit (MPU)""" menuitem "[:chip]SAU;Security Attribution Unit" "per , ""Core Registers (Cortex-M33),Security Attribution Unit (SAU)""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M33),Nested Vectored Interrupt Controller (NVIC)""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M33),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M33),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M33),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) separator menuitem "ADC;Analog-to-Digital Converter" "per , ""ADC (Analog-to-Digital Converter)""" menuitem "AHB_SECURE_CTRL;AHB Secure Controller" "per , ""AHB_SECURE_CTRL (AHB Secure Controller)""" menuitem "ANACTRL;ANALOGCTRL" "per , ""ANACTRL (ANALOGCTRL)""" if (cpuis("LPC55S16*")||cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")) ( menuitem "CAN;Controller Area Network Flexible Data" "per , ""CAN (Controller Area Network Flexible Data),CAN""" ) menuitem "CASPER" "per , ""CASPER""" if (cpuis("LPC55S16*")||cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")) ( menuitem "CDOG" "per , ""CDOG,CDOG""" ) menuitem "CRC_ENGINE;CRC engine" "per , ""CRC (CRC engine)""" popup "CTIMER;Standard counter/timers" ( menuitem "CTIMER0" "per , ""CTIMER (Standard counter/timers),CTIMER0""" menuitem "CTIMER1" "per , ""CTIMER (Standard counter/timers),CTIMER1""" menuitem "CTIMER2" "per , ""CTIMER (Standard counter/timers),CTIMER2""" menuitem "CTIMER3" "per , ""CTIMER (Standard counter/timers),CTIMER3""" menuitem "CTIMER4" "per , ""CTIMER (Standard counter/timers),CTIMER4""" ) menuitem "DBGMAILBOX;MCU Debugger Mailbox" "per , ""DBGMAILBOX (MCU Debugger Mailbox)""" popup "DMA;DMA controller" ( menuitem "DMA0" "per , ""DMA (DMA controller),DMA0""" menuitem "DMA1" "per , ""DMA (DMA controller),DMA1""" ) menuitem "FLASH" "per , ""FLASH""" popup "FLASH_CFPA" ( menuitem "FLASH_CFPA0" "per , ""FLASH_CFPA,FLASH_CFPA0""" menuitem "FLASH_CFPA1" "per , ""FLASH_CFPA,FLASH_CFPA1""" menuitem "FLASH_CFPA_SCRATCH" "per , ""FLASH_CFPA,FLASH_CFPA_SCRATCH""" ) menuitem "FLASH_CMPA" "per , ""FLASH_CMPA,FLASH_CMPA""" menuitem "FLASH_KEY_STORE" "per , ""FLASH_KEY_STORE,FLASH_KEY_STORE""" if (cpuis("LPC55S16*")||cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")) ( menuitem "FLASH_NMPA" "per , ""FLASH_NMPA,FLASH_NMPA""" menuitem "FLASH_ROMPATCH" "per , ""FLASH_ROMPATCH,FLASH_ROMPATCH""" ) popup "FLEXCOMM;Flexcomm serial communication" ( menuitem "FLEXCOMM0" "per , ""FLEXCOMM (Flexcomm serial communication),FLEXCOMM0""" menuitem "FLEXCOMM1" "per , ""FLEXCOMM (Flexcomm serial communication),FLEXCOMM1""" menuitem "FLEXCOMM2" "per , ""FLEXCOMM (Flexcomm serial communication),FLEXCOMM2""" menuitem "FLEXCOMM3" "per , ""FLEXCOMM (Flexcomm serial communication),FLEXCOMM3""" menuitem "FLEXCOMM4" "per , ""FLEXCOMM (Flexcomm serial communication),FLEXCOMM4""" menuitem "FLEXCOMM5" "per , ""FLEXCOMM (Flexcomm serial communication),FLEXCOMM5""" menuitem "FLEXCOMM6" "per , ""FLEXCOMM (Flexcomm serial communication),FLEXCOMM6""" menuitem "FLEXCOMM7" "per , ""FLEXCOMM (Flexcomm serial communication),FLEXCOMM7""" menuitem "FLEXCOMM8" "per , ""FLEXCOMM (Flexcomm serial communication),FLEXCOMM8""" ) popup "GINT;Group GPIO input interrupt (GINT0/1)" ( menuitem "GINT0" "per , ""GINT (Group GPIO input interrupt (GINT0/1)),GINT0""" menuitem "GINT1" "per , ""GINT (Group GPIO input interrupt (GINT0/1)),GINT1""" ) popup "GPIO;General Purpose I/O Ports And Peripheral I/O Lines" ( menuitem "GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO""" menuitem "SECGPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),SECGPIO""" ) menuitem "HASHCRYPT;Hash-Crypt peripheral" "per , ""HASHCRYPT (Hash-Crypt peripheral)""" popup "I2C;Inter-Integrated Circuit" ( menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit),I2C0""" menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1""" menuitem "I2C2" "per , ""I2C (Inter-Integrated Circuit),I2C2""" menuitem "I2C3" "per , ""I2C (Inter-Integrated Circuit),I2C3""" menuitem "I2C4" "per , ""I2C (Inter-Integrated Circuit),I2C4""" menuitem "I2C5" "per , ""I2C (Inter-Integrated Circuit),I2C5""" menuitem "I2C6" "per , ""I2C (Inter-Integrated Circuit),I2C6""" menuitem "I2C7" "per , ""I2C (Inter-Integrated Circuit),I2C7""" ) popup "I2S;Inter-Integrated Sound Bus Controller" ( menuitem "I2S0" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S0""" menuitem "I2S1" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S1""" menuitem "I2S2" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S2""" menuitem "I2S3" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S3""" menuitem "I2S4" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S4""" menuitem "I2S5" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S5""" menuitem "I2S6" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S6""" menuitem "I2S7" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S7""" ) menuitem "INPUTMUX;Input multiplexing" "per , ""INPUTMUX (Input multiplexing)""" menuitem "IOCON;I/O pin configuration" "per , ""IOCON (I/O pin configuration)""" if (cpuis("LPC55S66*")||cpuis("LPC55S69*")) ( menuitem "MAILBOX;Mailbox" "per , ""MAILBOX (Mailbox),MAILBOX""" ) if (cpuis("LPC55S16*")||cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")) ( menuitem "MPU;Memory Protection Unit" "per , ""MPU (Memory Protection Unit),MPU""" ) menuitem "MRT;Multi-Rate Timer" "per , ""MRT (Multi-Rate Timer)""" menuitem "NVIC;no description available" "per , ""NVIC""" menuitem "OSTIMER;Synchronous OS/Event timer with Wakeup Timer" "per , ""OSTIMER (Synchronous OS/Event timer with Wakeup Timer)""" popup "PINT;Pin interrupt and pattern match" ( menuitem "PINT" "per , ""PINT (Pin interrupt and pattern match),PINT""" menuitem "SECPINT" "per , ""PINT (Pin interrupt and pattern match),SECPINT""" ) menuitem "PLU;LPC80X Programmable Logic Unit" "per , ""PLU (LPC80X Programmable Logic Unit)""" menuitem "PMC" "per , ""PMC""" if (cpuis("LPC55S66*")||cpuis("LPC55S69*")) ( menuitem "POWERQUAD;Digital Signal Co-Processing companion to a.." "per , ""POWERQUAD (Digital Signal Co-Processing companion to a Cortex-M v8M CPU core),POWERQUAD""" ) menuitem "PRINCE" "per , ""PRINCE""" menuitem "PUF;PUFCTRL" "per , ""PUF (PUFCTRL)""" if (cpuis("LPC55S16*")||cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")) ( menuitem "PUF_SRAM_CTRL;PUF SRAM Control" "per , ""PUF_SRAM_CTRL (PUF SRAM Control),PUF_SRAM_CTRL""" ) menuitem "RNG" "per , ""RNG (Random Number Generator)""" menuitem "RTC;Real-Time Clock (RTC)" "per , ""RTC (Real-time Counter)""" menuitem "SAU" "per , ""SAU""" menuitem "SCB" "per , ""SCB""" menuitem "SCNSCB" "per , ""SCNSCB""" menuitem "SCT0;SCTimer/PWM" "per , ""SCT (SCTimer/PWM)""" if (cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")) ( menuitem "SDIF;SDMMC" "per , ""SDIF (SDMMC),SDIF""" ) popup "SPI;Serial Peripheral Interfaces" ( menuitem "SPI0" "per , ""SPI (Serial Peripheral Interfaces),SPI0""" menuitem "SPI1" "per , ""SPI (Serial Peripheral Interfaces),SPI1""" if (cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")) ( menuitem "SPI2" "per , ""SPI (Serial Peripheral Interfaces),SPI2""" ) menuitem "SPI3" "per , ""SPI (Serial Peripheral Interfaces),SPI3""" menuitem "SPI4" "per , ""SPI (Serial Peripheral Interfaces),SPI4""" if (cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")) ( menuitem "SPI5" "per , ""SPI (Serial Peripheral Interfaces),SPI5""" ) menuitem "SPI6" "per , ""SPI (Serial Peripheral Interfaces),SPI6""" menuitem "SPI7" "per , ""SPI (Serial Peripheral Interfaces),SPI7""" menuitem "SPI8" "per , ""SPI (Serial Peripheral Interfaces),SPI8""" ) menuitem "SYSCON" "per , ""SYSCON""" menuitem "SYSCTL;System Controller" "per , ""SYSCTL (System Controller)""" popup "USART;USARTs" ( menuitem "USART0" "per , ""USART (USARTs),USART0""" menuitem "USART1" "per , ""USART (USARTs),USART1""" menuitem "USART2" "per , ""USART (USARTs),USART2""" menuitem "USART3" "per , ""USART (USARTs),USART3""" menuitem "USART4" "per , ""USART (USARTs),USART4""" menuitem "USART5" "per , ""USART (USARTs),USART5""" menuitem "USART6" "per , ""USART (USARTs),USART6""" menuitem "USART7" "per , ""USART (USARTs),USART7""" ) if (cpuis("LPC55S16*")||cpuis("LPC55S14*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")) ( menuitem "USB0;USB 2.0 Device Controller" "per , ""USB (Universal Serial Bus),USB0""" menuitem "USBFSH;USB0 Full-speed Host controller" "per , ""USBFSH (USB0 Full-speed Host controller),USBFSH""" menuitem "USBHSD;USB1 High-speed Device Controller" "per , ""USBHSD (USB1 High-speed Device Controller),USBHSD""" menuitem "USBHSH;USB1 High-speed Host Controller" "per , ""USBHSH (USB1 High-speed Host Controller),USBHSH""" menuitem "USBPHY;Universal System Bus Physical Layer" "per , ""USBPHY (Universal System Bus Physical Layer),USBPHY""" ) menuitem "UTICK0;Micro-tick Timer" "per , ""UTICK (Micro-tick Timer)""" menuitem "WWDT;Windowed Watchdog Timer" "per , ""WWDT (Windowed Watchdog Timer)""" ) )