; -------------------------------------------------------------------------------- ; @Title: LPC15xx Specific Menu ; @Props: Released ; @Author: MKK, LSD ; @Changelog: 2016-06-07 LSD ; @Manufacturer: NXP - NXP Semiconductors ; @Core: Cortex-M3 ; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menlpc15xx.men 17505 2024-02-19 12:15:25Z kwisniewski $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-M3)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M3),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M3),Memory Protection Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M3),Nested Vectored Interrupt Controller""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M3),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M3),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M3),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) separator menuitem "SYSCON" "per , ""SYSCON (System Control)""" menuitem "PMU" "per , ""PMU (Power Management Unit)""" menuitem "IOCON" "per , ""IOCON (I/O pin configuration)""" menuitem "SWM" "per , ""SWM (Switch Matrix)""" menuitem "INPUT MUX " "per , ""INPUT MUX (Input multiplexing)""" menuitem "GPIO" "per , ""GPIO (General Purpose I/O)""" popup "GINT" ( menuitem "GINT0" "per , ""GINT (Group GPIO input interrupt),GINT0""" menuitem "GINT1" "per , ""GINT (Group GPIO input interrupt),GINT1""" ) menuitem "PINT" "per , ""PINT (Pin interrupt and pattern match)""" menuitem "DMA controller" "per , ""DMA controller""" menuitem "SCTIPU" "per , ""SCTIPU (SCT Input Processing Unit)""" popup "Large SCTimers" ( menuitem "SCTimer 0" "per , ""Large SCTimers,SCTimer 0""" menuitem "SCTimer 1" "per , ""Large SCTimers,SCTimer 1""" ) popup "Small SCTimers" ( menuitem "SCTimer 2" "per , ""Small SCTimers,SCTimer 2""" menuitem "SCTimer 3" "per , ""Small SCTimers,SCTimer 3""" ) menuitem "WWDT" "per , ""WWDT (Windowed Watchdog Timer)""" menuitem "RTC" "per , ""RTC (Real-Time Clock)""" menuitem "MRT" "per , ""MRT (Multi-Rate Timer)""" menuitem "RIT" "per , ""RIT (Repetitive Interrupt Timer)""" menuitem "QEI" "per , ""QEI (Quadrature Encoder Interface)""" if cpuis("LPC154?") ( menuitem "USB" "per , ""USB (Universal Serial Bus)""" ) popup "USART" ( menuitem "USART0" "per , ""USART (Universal Synchronous-Asynchronous Receiver/Transmitter),USART0""" menuitem "USART1" "per , ""USART (Universal Synchronous-Asynchronous Receiver/Transmitter),USART1""" menuitem "USART2" "per , ""USART (Universal Synchronous-Asynchronous Receiver/Transmitter),USART2""" ) popup "SPI" ( menuitem "SPI 0" "per , ""SPI (Serial Peripheral Interface),SPI 0""" menuitem "SPI 1" "per , ""SPI (Serial Peripheral Interface),SPI 1""" ) menuitem "I2C-bus interface" "per , ""I2C-bus interface""" menuitem "C_CAN" "per , ""C_CAN (Controller Area Network)""" popup "ADC" ( menuitem "ADC0" "per , ""ADC (12-bit Analog-Digital Converter),ADC0""" menuitem "ADC1" "per , ""ADC (12-bit Analog-Digital Converter),ADC1""" ) menuitem "DAC" "per , ""DAC (12-bit Digital-Analog Converter)""" menuitem "Analog comparators" "per , ""Analog comparators""" menuitem "CRC engine" "per , ""CRC engine (Cyclic Redundancy Check engine)""" menuitem "Flash controller" "per , ""Flash controller""" ) )