; --------------------------------------------------------------------------------
; @Title: LM4F Specific Menu
; @Props: Released
; @Author: LEM, STR
; @Changelog: 2012-03-19
; @Manufacturer: TI - Texas Instruments
; @Core: CORTEX-M4
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menlm4f.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M4F)"
(
menuitem "[:chip]System Control"                                "per , ""Core Registers (Cortex-M4F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                    "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"     "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
menuitem "[:chip]FPU;Floating-point Unit"                       "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"       "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"        "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "System Control"                   "per , ""System Control"""
menuitem "System Exception Module"          "per , ""System Exception Module"""
if (cpu()=="LM4F110B2QR")||(cpu()=="LM4F110C4QR")||(cpu()=="LM4F110E5QR")||(cpu()=="LM4F110H5QR")||(cpu()=="LM4F112C4QC")||(cpu()=="LM4F112E5QC")||(cpu()=="LM4F112H5QC")||(cpu()=="LM4F112H5QD")||(cpu()=="LM4F120B2QR")||(cpu()=="LM4F120C4QR")||(cpu()=="LM4F120E5QR")||(cpu()=="LM4F120H5QR")||(cpu()=="LM4F122C4QC")||(cpu()=="LM4F122E5QC")||(cpu()=="LM4F122H5QC")||(cpu()=="LM4F122H5QD")||(cpu()=="LM4F130C4QR")||(cpu()=="LM4F130E5QR")||(cpu()=="LM4F130H5QR")||(cpu()=="LM4F132C4QC")||(cpu()=="LM4F132E5QC")||(cpu()=="LM4F132H5QC")||(cpu()=="LM4F132H5QD")||(cpu()=="LM4F230E5QR")||(cpu()=="LM4F230H5QR")||(cpu()=="LM4F232E5QC")||(cpu()=="LM4F232H5QC")||(cpu()=="LM4F232H5QD")
(
menuitem "Hibernation Module"           "per , ""Hibernation Module"""
)
menuitem "Internal Memory"                  "per , ""Internal Memory"""
menuitem "uDMA"                             "per , ""uDMA (Micro Direct Memory Access)"""
menuitem "GPIO"                             "per , ""GPIOs (General-Purpose Input/Outputs)"""
menuitem "GPT"                              "per , ""General-Purpose Timers"""
menuitem "WDT"                              "per , ""Watchdog Timer"""
menuitem "ADC"                              "per , ""ADC (Analog-to-Digital Converter)"""
menuitem "UART"                             "per , ""UARTs (Universal Asynchronous Receivers/Transmitters)"""
menuitem "SSI"                              "per , ""SSI (Synchronous Serial Interface)"""
menuitem "I2C"                              "per , ""I2C (Inter-Integrated Circuit)"""
menuitem "CAN"                              "per , ""CAN (Controller Area Network)"""
menuitem "USB"                              "per , ""USB (Universal Serial Bus)"""
menuitem "Analog Comparators"               "per , ""Analog Comparators"""
if (cpu()=="LM4F230E5QR")||(cpu()=="LM4F230H5QR")||(cpu()=="LM4F231E5QR")||(cpu()=="LM4F231H5QR")||(cpu()=="LM4F232E5QC")||(cpu()=="LM4F232H5QC")||(cpu()=="LM4F232H5QD")
(
menuitem "PWM"                          "per , ""PWM (Pulse Width Modulator)"""
menuitem "QEI"                          "per , ""QEI (Quadrature Encoder Interface)"""
)
)
)