; -------------------------------------------------------------------------------- ; @Title: Kinetis K0x Specific Menu ; @Props: Released ; @Author: ADP, PBU, DPR, PCC ; @Changelog: 2015-11-16 ADP ; 2018-01-18 DPR ; @Manufacturer: NXP ; @Core: Cortex-M4 ; @Chip: MK02FN128VFM10, MK02FN128VLF10, MK02FN128VLH10, MK02FN64VFM10, ; MK02FN64VLF10, MK02FN64VLH10 ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menk00.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-M4F)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller""" menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) separator popup "Ports" ( menuitem "PORT A" "per , ""PORT (Pin control and interrupts),PORT A""" menuitem "PORT B" "per , ""PORT (Pin control and interrupts),PORT B""" menuitem "PORT C" "per , ""PORT (Pin control and interrupts),PORT C""" menuitem "PORT D" "per , ""PORT (Pin control and interrupts),PORT D""" menuitem "PORT E" "per , ""PORT (Pin control and interrupts),PORT E""" ) popup "System Modules" ( menuitem "SIM;System Integration Module" "per , ""System Modules,SIM (System Integration Module)""" menuitem "RCM;Reset Control Module" "per , ""System Modules,RCM (Reset Control Module)""" menuitem "SMC;System Mode Controller" "per , ""System Modules,SMC (System Mode Controller)""" menuitem "PMC;Power Management Controller" "per , ""System Modules,PMC (Power Management Controller)""" menuitem "LLWU;Low-Leakage Wake-up Unit" "per , ""System Modules,LLWU (Low-Leakage Wake-up Unit)""" menuitem "MCM;Miscellaneous Control Module" "per , ""System Modules,MCM (Miscellaneous Control Module)""" menuitem "DMAMUX;Direct Memory Access Multiplexer" "per , ""System Modules,DMAMUX (Direct Memory Access Multiplexer)""" menuitem "eDMA;Enhanced Direct Memory Access" "per , ""System Modules,eDMA (Enhanced Direct Memory Access)""" menuitem "EWM;External Watchdog Monitor" "per , ""System Modules,EWM (External Watchdog Monitor)""" menuitem "WDOG;Watchdog Timer" "per , ""System Modules,WDOG (Watchdog Timer)""" ) popup "Clock Modules" ( menuitem "MCG;Multipurpose Clock Generator" "per , ""Clock Modules,MCG (Multipurpose Clock Generator)""" menuitem "OSC;Oscillator" "per , ""Clock Modules,OSC (Oscillator)""" ) popup "Memories and Memory Interfaces" ( menuitem "FMC;Flash Memory Controller" "per , ""Memories and Memory Interfaces,FMC (Flash Memory Controller)""" menuitem "FTFA;Flash Memory Module" "per , ""Memories and Memory Interfaces,FTFA (Flash Memory Module)""" ) popup "Security and Integrity Modules" ( menuitem "CRC;Cyclic Redundancy Check" "per , ""Security and integrity modules,CRC (Cyclic Redundancy Check)""" ) popup "Analog Modules" ( menuitem "ADC;Analog-to-Digital Converter" "per , ""Analog Modules,ADC (Analog-to-Digital Converter),ADC""" popup "HSCMP;Comparator/6-bit DAC Converter" ( menuitem "CMP 0" "per , ""Analog Modules,HSCMP (Comparator/6-bit DAC Converter),CMP 0""" menuitem "CMP 1" "per , ""Analog Modules,HSCMP (Comparator/6-bit DAC Converter),CMP 1""" ) menuitem "DAC;12-bit Digital-to-Analog Converter" "per , ""Analog Modules,DAC (12-bit Digital-to-Analog Converter)""" menuitem "VREFV1;Voltage Reference" "per , ""Analog Modules,VREFV1 (Voltage Reference)""" ) popup "Timers" ( menuitem "PDB;Programmable Delay Block" "per , ""Timers,PDB (Programmable Delay Block)""" popup "FTM;FlexTimer" ( menuitem "FTM 0" "per , ""Timers,FTM (FlexTimer),FTM 0""" menuitem "FTM 1" "per , ""Timers,FTM (FlexTimer),FTM 1""" menuitem "FTM 2" "per , ""Timers,FTM (FlexTimer),FTM 2""" ) menuitem "PIT;Periodic Interrupt Timer" "per , ""Timers,PIT (Periodic Interrupt Timer)""" menuitem "LPT;Low Power Timer" "per , ""Timers,LPT (Low Power Timer)""" ) popup "Communication Interfaces" ( popup "SPI;Serial Peripheral Interface" ( menuitem "SPI 0" "per , ""Communication Interfaces,SPI (Serial Peripheral Interface),SPI 0""" ) popup "I2C;Inter-Integrated Circuit" ( menuitem "I2C 0" "per , ""Communication Interfaces,I2C (Inter-Integrated Circuit),I2C 0""" ) popup "UART;Universal Asynchronous Rx/Tx" ( menuitem "UART 0" "per , ""Communication Interfaces,UART (Universal Asynchronous Receiver/Transmitter),UART 0""" menuitem "UART 1" "per , ""Communication Interfaces,UART (Universal Asynchronous Receiver/Transmitter),UART 1""" ) ) popup "Human-Machine Interfaces" ( popup "GPIO;GPIO Controller" ( menuitem "GPIO A" "per , ""Human-Machine Interfaces,GPIO (GPIO Controller),GPIO A""" menuitem "GPIO B" "per , ""Human-Machine Interfaces,GPIO (GPIO Controller),GPIO B""" menuitem "GPIO C" "per , ""Human-Machine Interfaces,GPIO (GPIO Controller),GPIO C""" menuitem "GPIO D" "per , ""Human-Machine Interfaces,GPIO (GPIO Controller),GPIO D""" menuitem "GPIO E" "per , ""Human-Machine Interfaces,GPIO (GPIO Controller),GPIO E""" ) ) ) )