; -------------------------------------------------------------------------------- ; @Title: J721E Specific Menu ; @Props: Released ; @Author: BGI, KWI, PIW ; @Changelog: 2019-04-25 BGI ; 2019-08-06 BGI ; 2020-02-03 KWI ; 2022-05-13 PIW ; @Manufacturer: TI - Texas Instruments ; @Core: Cortex-A72, CORTEX-M3, CORTEX-R5F, C66X, C71X ; @Chip: AM752X ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menj721e.men 17376 2024-01-24 12:02:44Z kwisniewski $ add menu ( if (CPUFAMILY()=="C6000") ( popup "&CPU" ( after "FPU Registers" separator popup "[:cache]Cache" ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) popup "&Trace" ( IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("AET") ( menuitem "[:oconfig]AET settings..." "AET.state" ) ) popup "&Perf" ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) else if (CPUFAMILY()=="C7000") ( popup "&CPU" ( after "FPU Registers" menuitem "[:fpureg]Vector Registers" "VPU.view" separator popup "[:cache]Cache" ( menuitem "[:cache]Cache Control" "CACHE.view" menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) popup "&Trace" ( IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("TRC") ( menuitem "[:oconfig]TRC settings..." "TRC.state" ) ) popup "&Perf" ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) else ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) ) popup "Peripherals" ( if (CORENAME()!="PRU") ( if (CORENAME()=="CORTEXM3") ( popup "[:chip]Core Registers (Cortex-M3)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M3),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M3),Memory Protection Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M3),Nested Vectored Interrupt Controller""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M3),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M3),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M3),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) else ( if (CORENAME()=="CORTEXR5F") ( popup "[:chip]Core Registers (Cortex-R5F)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R5F),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R5F),System Control and Configuration""" menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R5F),MPU Control and Configuration""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R5F),Cache Control and Configuration""" menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R5F),TCM Control and Configuration""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R5F),System Performance Monitor""" separator menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R5F),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R5F),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R5F),Watchpoint Control Registers""" ) ) else if (CORENAME()=="CORTEXA72") ( popup "[:chip]Core Registers (Cortex-A72)" ( menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,ID Registers""" menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,System Control and Configuration""" menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Memory Management Unit""" menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,System Performance Monitor""" menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,System Timer Registers""" menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Generic Interrupt Controller CPU Interface""" separator menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Debug Registers""" separator menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Breakpoint Registers""" menuitem "[:chip]Watchpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Watchpoint Control Registers""" separator menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,ID Registers""" menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,System Control and Configuration""" menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Memory Management Unit""" menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,System Performance Monitor""" menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,System Timer Registers""" menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Generic Interrupt Controller CPU Interface""" separator menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Debug Registers""" separator menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Breakpoint Registers""" menuitem "[:chip]Watchpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Watchpoint Control Registers""" separator menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A72),Interrupt Controller (GIC-500)""" ) ) else if (CORENAME()=="C66X") ( popup "[:chip]Core Registers (c66x)" ( menuitem "[:chip]L1P;L1P Registers" "per , ""Core Registers (c66x),Cache,L1P Cache""" menuitem "[:chip]L1D;L1D Registers" "per , ""Core Registers (c66x),Cache,L1D Cache""" menuitem "[:chip]L2;L2 Registers" "per , ""Core Registers (c66x),Cache,L2 Cache""" menuitem "[:chip]IDMA;IDMA Registers" "per , ""Core Registers (c66x),IDMA (Internal Direct Memory Access Controller)""" menuitem "[:chip]XMC;XMC Registers" "per , ""Core Registers (c66x),XMC (Extended Memory Controller)""" menuitem "[:chip]BM;BM Registers" "per , ""Core Registers (c66x),Bandwith Management""" menuitem "[:chip]IC;IC Registers" "per , ""Core Registers (c66x),Interrupt Controller""" menuitem "[:chip]PD;PD Registers" "per , ""Core Registers (c66x),Power-Down Controller""" ) ) else if (CORENAME()=="C71X") ( popup "[:chip]Core Registers (c71x)" ( menuitem "[:chip]GR;General Registers" "per , ""Core Registers (c71x),GR (General Registers)""" menuitem "[:chip]CR;Computation Registers" "per , ""Core Registers (c71x),CR (Computation Registers)""" menuitem "[:chip]ER;Exception Registers" "per , ""Core Registers (c71x),ER (Exception Registers)""" enable CPU.FEATURE("luthist") menuitem "[:chip]LUT;LUT Registers" "per , ""Core Registers (c71x),LUT (LUT Registers)""" menuitem "[:chip]SAR;Streaming Address Registers" "per , ""Core Registers (c71x),SAR (Streaming Address Registers)""" menuitem "[:chip]DEBUG;Registers Useful For Debug" "per , ""Core Registers (c71x),DEBUG (Registers Useful For Debug)""" menuitem "[:chip]MMA;MMA Registers" "per , ""Core Registers (c71x),MMA (MMA Registers)""" menuitem "[:chip]CMMU;CMMU Registers" "per , ""Core Registers (c71x),CMMU (CMMU Registers)""" menuitem "[:chip]L1D;L1D Registers" "per , ""Core Registers (c71x),L1D (L1D Registers)""" menuitem "[:chip]L2;L2 Registers" "per , ""Core Registers (c71x),L2 (L2 Registers)""" menuitem "[:chip]SE;SE Registers" "per , ""Core Registers (c71x),SE (SE Registers)""" ) ) separator popup "_2_L_SerDes" ( menuitem "SERDES_16G0" "per , ""_2_L_SerDes,SERDES_16G0""" menuitem "SERDES_16G1" "per , ""_2_L_SerDes,SERDES_16G1""" menuitem "SERDES_16G2" "per , ""_2_L_SerDes,SERDES_16G2""" menuitem "SERDES_16G3" "per , ""_2_L_SerDes,SERDES_16G3""" ) popup "_4_L_SerDes" ( menuitem "SERDES_10G0" "per , ""_4_L_SerDes,SERDES_10G0""" ) popup "AASRC" ( menuitem "AASRC0_CFG" "per , ""AASRC,AASRC0_CFG""" menuitem "AASRC0_DATA_R0" "per , ""AASRC,AASRC0_DATA_R0""" menuitem "AASRC0_DATA_R1" "per , ""AASRC,AASRC0_DATA_R1""" ) popup "ADC" ( menuitem "MCU_ADC0" "per , ""ADC,MCU_ADC0""" menuitem "MCU_ADC1" "per , ""ADC,MCU_ADC1""" menuitem "MCU_ADC0_ECC" "per , ""ADC,MCU_ADC0_ECC""" menuitem "MCU_ADC1_ECC" "per , ""ADC,MCU_ADC1_ECC""" menuitem "MCU_ADC0_FIFO" "per , ""ADC,MCU_ADC0_FIFO""" menuitem "MCU_ADC1_FIFO" "per , ""ADC,MCU_ADC1_FIFO""" ) popup "ATL" ( menuitem "ATL0_REG" "per , ""ATL,ATL0_REG""" ) popup "C66x_DSP_Subsystem" ( menuitem "C66_COREPAC_C66_RATCFG" "per , ""C66x_DSP_Subsystem,C66_COREPAC_C66_RATCFG""" ) popup "C71SS_ECC_AGGR" ( menuitem "COMPUTE_CLUSTER0_C71SS0_ECC_AGGR" "per , ""C71SS_ECC_AGGR,COMPUTE_CLUSTER0_C71SS0_ECC_AGGR""" ) popup "CCMR5" ( menuitem "MCU_R5FSS0_COMPARE_CFG" "per , ""CCMR5,MCU_R5FSS0_COMPARE_CFG""" menuitem "R5FSS0_COMPARE_CFG" "per , ""CCMR5,R5FSS0_COMPARE_CFG""" menuitem "R5FSS1_COMPARE_CFG" "per , ""CCMR5,R5FSS1_COMPARE_CFG""" ) popup "CLEC" ( menuitem "COMPUTE_CLUSTER0_CLEC_REGS" "per , ""CLEC,COMPUTE_CLUSTER0_CLEC_REGS""" ) popup "Compute_Cluster" ( menuitem "COMPUTE_CLUSTER0_DMSC_BOOT" "per , ""Compute_Cluster,COMPUTE_CLUSTER0_DMSC_BOOT""" ) popup "COMPUTE_CLUSTER0_MSMC_ECC_AGGR0" ( menuitem "COMPUTE_CLUSTER0_MSMC_ECC_AGGR0" "per , ""COMPUTE_CLUSTER0_MSMC_ECC_AGGR0,COMPUTE_CLUSTER0_MSMC_ECC_AGGR0""" ) popup "COMPUTE_CLUSTER0_MSMC_ECC_AGGR1" ( menuitem "COMPUTE_CLUSTER0_MSMC_ECC_AGGR1" "per , ""COMPUTE_CLUSTER0_MSMC_ECC_AGGR1,COMPUTE_CLUSTER0_MSMC_ECC_AGGR1""" ) popup "COMPUTE_CLUSTER0_MSMC_ECC_AGGR2" ( menuitem "COMPUTE_CLUSTER0_MSMC_ECC_AGGR2" "per , ""COMPUTE_CLUSTER0_MSMC_ECC_AGGR2,COMPUTE_CLUSTER0_MSMC_ECC_AGGR2""" ) popup "CPSW0_ALE" ( menuitem "CPSW0_NUSS_ALE" "per , ""CPSW0_ALE,CPSW0_NUSS_ALE""" ) popup "CPSW0_CONTROL" ( menuitem "CPSW0_NUSS_CONTROL" "per , ""CPSW0_CONTROL,CPSW0_NUSS_CONTROL""" ) popup "CPSW0_CPINT" ( menuitem "CPSW0_NUSS_CPINT" "per , ""CPSW0_CPINT,CPSW0_NUSS_CPINT""" ) popup "CPSW0_CPTS" ( menuitem "CPSW0_NUSS_CPTS" "per , ""CPSW0_CPTS,CPSW0_NUSS_CPTS""" ) popup "CPSW0_ECC" ( menuitem "CPSW0_ECC" "per , ""CPSW0_ECC,CPSW0_ECC""" ) popup "CPSW0_MDIO" ( menuitem "CPSW0_NUSS_MDIO" "per , ""CPSW0_MDIO,CPSW0_NUSS_MDIO""" ) popup "CPSW0_NUSS_Subsystem__SS_" ( menuitem "CPSW0_NUSS_SS" "per , ""CPSW0_NUSS_Subsystem__SS_,CPSW0_NUSS_SS""" ) popup "CPSW0_PCSR" ( menuitem "CPSW0_NUSS_PCSR" "per , ""CPSW0_PCSR,CPSW0_NUSS_PCSR""" ) popup "CPSW0_RAM" ( menuitem "CPSW0_NUSS_RAM" "per , ""CPSW0_RAM,CPSW0_NUSS_RAM""" ) popup "CPSW0_SGMII" ( menuitem "CPSW0_NUSS_SGMII" "per , ""CPSW0_SGMII,CPSW0_NUSS_SGMII""" ) popup "CPSW0_STAT" ( menuitem "CPSW0_NUSS_STAT" "per , ""CPSW0_STAT,CPSW0_NUSS_STAT""" ) popup "CPU0_ECC_AGGR_CFG_REGS" ( menuitem "MCU_R5FSS0_CORE0_ECC_AGGR" "per , ""CPU0_ECC_AGGR_CFG_REGS,MCU_R5FSS0_CORE0_ECC_AGGR""" menuitem "R5FSS0_CORE0_ECC_AGGR" "per , ""CPU0_ECC_AGGR_CFG_REGS,R5FSS0_CORE0_ECC_AGGR""" menuitem "R5FSS1_CORE0_ECC_AGGR" "per , ""CPU0_ECC_AGGR_CFG_REGS,R5FSS1_CORE0_ECC_AGGR""" ) popup "CPU1_ECC_AGGR_CFG_REGS" ( menuitem "MCU_R5FSS0_ECC_AGGR" "per , ""CPU1_ECC_AGGR_CFG_REGS,MCU_R5FSS0_ECC_AGGR""" menuitem "R5FSS0_ECC_AGGR" "per , ""CPU1_ECC_AGGR_CFG_REGS,R5FSS0_ECC_AGGR""" menuitem "R5FSS1_ECC_AGGR" "per , ""CPU1_ECC_AGGR_CFG_REGS,R5FSS1_ECC_AGGR""" ) popup "CSI_RX_IF" ( menuitem "CSI_RX_IF0_CP_INTD_CFG_INTD_CFG" "per , ""CSI_RX_IF,CSI_RX_IF0_CP_INTD_CFG_INTD_CFG""" menuitem "CSI_RX_IF1_CP_INTD_CFG_INTD_CFG" "per , ""CSI_RX_IF,CSI_RX_IF1_CP_INTD_CFG_INTD_CFG""" menuitem "CSI_RX_IF0_ECC_AGGR_CFG" "per , ""CSI_RX_IF,CSI_RX_IF0_ECC_AGGR_CFG""" menuitem "CSI_RX_IF1_ECC_AGGR_CFG" "per , ""CSI_RX_IF,CSI_RX_IF1_ECC_AGGR_CFG""" menuitem "CSI_RX_IF0_RX_SHIM_VBUSP_MMR_CSI2RXIF" "per , ""CSI_RX_IF,CSI_RX_IF0_RX_SHIM_VBUSP_MMR_CSI2RXIF""" menuitem "CSI_RX_IF1_RX_SHIM_VBUSP_MMR_CSI2RXIF" "per , ""CSI_RX_IF,CSI_RX_IF1_RX_SHIM_VBUSP_MMR_CSI2RXIF""" menuitem "CSI_RX_IF_VBUS2APB0" "per , ""CSI_RX_IF,CSI_RX_IF_VBUS2APB0""" menuitem "CSI_RX_IF_VBUS2APB1" "per , ""CSI_RX_IF,CSI_RX_IF_VBUS2APB1""" ) popup "CSI_TX_IF" ( menuitem "CSI_TX_IF0_CP_INTD_CFG_INTD_CFG" "per , ""CSI_TX_IF,CSI_TX_IF0_CP_INTD_CFG_INTD_CFG""" menuitem "CSI_TX_IF0_ECC_AGGR_BYTE_CFG" "per , ""CSI_TX_IF,CSI_TX_IF0_ECC_AGGR_BYTE_CFG""" menuitem "CSI_TX_IF0_ECC_AGGR_CFG" "per , ""CSI_TX_IF,CSI_TX_IF0_ECC_AGGR_CFG""" menuitem "CSI_TX_IF0_TX_SHIM_VBUSP_MMR_CSI2TXIF" "per , ""CSI_TX_IF,CSI_TX_IF0_TX_SHIM_VBUSP_MMR_CSI2TXIF""" menuitem "CSI_TX_IF0_VBUS2APB_WRAP_VBUSP_APB_CSI2TX" "per , ""CSI_TX_IF,CSI_TX_IF0_VBUS2APB_WRAP_VBUSP_APB_CSI2TX""" ) popup "CTRL_MMR0" ( menuitem "CTRL_MMR0" "per , ""CTRL_MMR0,CTRL_MMR0""" ) popup "DCC" ( menuitem "MCU_DCC0" "per , ""DCC,MCU_DCC0""" menuitem "MCU_DCC1" "per , ""DCC,MCU_DCC1""" menuitem "MCU_DCC2" "per , ""DCC,MCU_DCC2""" menuitem "DCC0" "per , ""DCC,DCC0""" menuitem "DCC1" "per , ""DCC,DCC1""" menuitem "DCC10" "per , ""DCC,DCC10""" menuitem "DCC11" "per , ""DCC,DCC11""" menuitem "DCC12" "per , ""DCC,DCC12""" menuitem "DCC2" "per , ""DCC,DCC2""" menuitem "DCC3" "per , ""DCC,DCC3""" menuitem "DCC4" "per , ""DCC,DCC4""" menuitem "DCC5" "per , ""DCC,DCC5""" menuitem "DCC6" "per , ""DCC,DCC6""" menuitem "DCC7" "per , ""DCC,DCC7""" menuitem "DCC8" "per , ""DCC,DCC8""" menuitem "DCC9" "per , ""DCC,DCC9""" ) popup "DDR_Controller" ( menuitem "COMPUTE_CLUSTER0_CTL_CFG" "per , ""DDR_Controller,COMPUTE_CLUSTER0_CTL_CFG""" ) popup "DDR_PHY" ( menuitem "COMPUTE_CLUSTER0_CTL_CFG_PHY" "per , ""DDR_PHY,COMPUTE_CLUSTER0_CTL_CFG_PHY""" ) popup "DDR_Subsystem" ( menuitem "COMPUTE_CLUSTER0_SS_CFG" "per , ""DDR_Subsystem,COMPUTE_CLUSTER0_SS_CFG""" ) popup "DDRSS0_ECC_AGGR_CFG" ( menuitem "COMPUTE_CLUSTER0_ECC_AGGR_CFG" "per , ""DDRSS0_ECC_AGGR_CFG,COMPUTE_CLUSTER0_ECC_AGGR_CFG""" ) popup "DDRSS0_ECC_AGGR_CTL" ( menuitem "COMPUTE_CLUSTER0_ECC_AGGR_CTL" "per , ""DDRSS0_ECC_AGGR_CTL,COMPUTE_CLUSTER0_ECC_AGGR_CTL""" ) popup "DDRSS0_ECC_AGGR_VBUS" ( menuitem "COMPUTE_CLUSTER0_ECC_AGGR_VBUS" "per , ""DDRSS0_ECC_AGGR_VBUS,COMPUTE_CLUSTER0_ECC_AGGR_VBUS""" ) popup "DECODER" ( menuitem "DECODER0_IMG_VIDEO_BUS4_MMU" "per , ""DECODER,DECODER0_IMG_VIDEO_BUS4_MMU""" menuitem "DECODER0_IMG_VIDEO_BUS4_MMU2" "per , ""DECODER,DECODER0_IMG_VIDEO_BUS4_MMU2""" menuitem "DECODER0_MSVDX_AXI" "per , ""DECODER,DECODER0_MSVDX_AXI""" menuitem "DECODER0_MSVDX_AXI2" "per , ""DECODER,DECODER0_MSVDX_AXI2""" ) popup "DMPAC_CFG" ( menuitem "DMPAC_TOP_MAIN_0_DMPAC_REGS_DMPAC_REGS_CFG_IP_MMRS" "per , ""DMPAC_CFG,DMPAC_TOP_MAIN_0_DMPAC_REGS_DMPAC_REGS_CFG_IP_MMRS""" ) popup "DMPAC_CP_INTD" ( menuitem "DMPAC_TOP_MAIN_0_DMPAC_REGS_DMPAC_REGS_CFG_IP_MMRS" "per , ""DMPAC_CP_INTD,DMPAC_TOP_MAIN_0_DMPAC_REGS_DMPAC_REGS_CFG_IP_MMRS""" ) popup "DMPAC_CTSET" ( menuitem "DMPAC0_CTSET2_WRAP_CFG_CTSET2_CFG" "per , ""DMPAC_CTSET,DMPAC0_CTSET2_WRAP_CFG_CTSET2_CFG""" ) popup "DMPAC_DOF_CORE" ( menuitem "DMPAC0_PAR_DOF_CFG_VP_MEM_MMRRAM_VBUSP_MMR_RAM" "per , ""DMPAC_DOF_CORE,DMPAC0_PAR_DOF_CFG_VP_MEM_MMRRAM_VBUSP_MMR_RAM""" menuitem "DMPAC0_PAR_DOF_CFG_VP_MMR_VBUSP_DOFCORE" "per , ""DMPAC_DOF_CORE,DMPAC0_PAR_DOF_CFG_VP_MMR_VBUSP_DOFCORE""" ) popup "DMPAC_ECC_AGGR" ( menuitem "DMPAC0_KSDW_ECC_AGGR_CFG" "per , ""DMPAC_ECC_AGGR,DMPAC0_KSDW_ECC_AGGR_CFG""" ) popup "DMPAC_FOCO_0" ( menuitem "DMPAC0_DMPAC_FOCO_0_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS" "per , ""DMPAC_FOCO_0,DMPAC0_DMPAC_FOCO_0_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS""" menuitem "DMPAC0_DMPAC_FOCO_0_CFG_SLV_VPAC_FOCO_LSE_CFG_VP" "per , ""DMPAC_FOCO_0,DMPAC0_DMPAC_FOCO_0_CFG_SLV_VPAC_FOCO_LSE_CFG_VP""" ) popup "DMPAC_FOCO_1" ( menuitem "DMPAC0_DMPAC_FOCO_1_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS" "per , ""DMPAC_FOCO_1,DMPAC0_DMPAC_FOCO_1_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS""" menuitem "DMPAC0_DMPAC_FOCO_1_CFG_SLV_VPAC_FOCO_LSE_CFG_VP" "per , ""DMPAC_FOCO_1,DMPAC0_DMPAC_FOCO_1_CFG_SLV_VPAC_FOCO_LSE_CFG_VP""" ) popup "DMPAC_HTS" ( menuitem "DMPAC0_HTS_S_VBUSP" "per , ""DMPAC_HTS,DMPAC0_HTS_S_VBUSP""" ) popup "DMPAC_SDE" ( menuitem "DMPAC0_PAR_PAR_SDE_S_VBUSP_MEM_MMRRAM_VBUSP_MMR_RAM" "per , ""DMPAC_SDE,DMPAC0_PAR_PAR_SDE_S_VBUSP_MEM_MMRRAM_VBUSP_MMR_RAM""" menuitem "DMPAC0_PAR_PAR_SDE_S_VBUSP_MMR_VBUSP_MMR" "per , ""DMPAC_SDE,DMPAC0_PAR_PAR_SDE_S_VBUSP_MMR_VBUSP_MMR""" ) popup "DMPAC_UTC_DRU" ( menuitem "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU" "per , ""DMPAC_UTC_DRU,DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU""" menuitem "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE" "per , ""DMPAC_UTC_DRU,DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE""" menuitem "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG" "per , ""DMPAC_UTC_DRU,DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG""" menuitem "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT" "per , ""DMPAC_UTC_DRU,DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT""" menuitem "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHRT" "per , ""DMPAC_UTC_DRU,DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHRT""" menuitem "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE" "per , ""DMPAC_UTC_DRU,DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE""" menuitem "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_SET" "per , ""DMPAC_UTC_DRU,DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_SET""" ) popup "DPHY_RX" ( menuitem "DPHY_RX0_MMR_SLV_K3_DPHY_WRAP" "per , ""DPHY_RX,DPHY_RX0_MMR_SLV_K3_DPHY_WRAP""" menuitem "DPHY_RX1_MMR_SLV_K3_DPHY_WRAP" "per , ""DPHY_RX,DPHY_RX1_MMR_SLV_K3_DPHY_WRAP""" menuitem "DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX" "per , ""DPHY_RX,DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX""" menuitem "DPHY_RX1_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX" "per , ""DPHY_RX,DPHY_RX1_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX""" ) popup "DPHY_TX" ( menuitem "DPHY_TX0" "per , ""DPHY_TX,DPHY_TX0""" ) popup "DRU" ( menuitem "COMPUTE_CLUSTER0_MMR_DRU_MMR_CFG_DRU" "per , ""DRU,COMPUTE_CLUSTER0_MMR_DRU_MMR_CFG_DRU""" ) popup "DRU_FW" ( menuitem "COMPUTE_CLUSTER0_DRU_FW" "per , ""DRU_FW,COMPUTE_CLUSTER0_DRU_FW""" ) popup "DRU_FW_GLB" ( menuitem "COMPUTE_CLUSTER0_DRU_FW_GLB" "per , ""DRU_FW_GLB,COMPUTE_CLUSTER0_DRU_FW_GLB""" ) popup "DRU_MMR_FW" ( menuitem "COMPUTE_CLUSTER0_DRU_MMR_FW" "per , ""DRU_MMR_FW,COMPUTE_CLUSTER0_DRU_MMR_FW""" ) popup "DRU_MMR_FW_GLB" ( menuitem "COMPUTE_CLUSTER0_DRU_MMR_FW_GLB" "per , ""DRU_MMR_FW_GLB,COMPUTE_CLUSTER0_DRU_MMR_FW_GLB""" ) popup "DSI_ECC_AGGR" ( menuitem "DSS_DSI0_DSI_TOP_ECC_AGGR_SYS_CFG" "per , ""DSI_ECC_AGGR,DSS_DSI0_DSI_TOP_ECC_AGGR_SYS_CFG""" ) popup "DSI_TOP" ( menuitem "DSS_DSI0_DSI_TOP_VBUSP_CFG_DSI_0_DSI" "per , ""DSI_TOP,DSS_DSI0_DSI_TOP_VBUSP_CFG_DSI_0_DSI""" ) popup "DSI_WRAP" ( menuitem "DSS_DSI0_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP" "per , ""DSI_WRAP,DSS_DSI0_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP""" ) popup "DSS_COMMON" ( menuitem "DSS0_DISPC_0_COMMON_M" "per , ""DSS_COMMON,DSS0_DISPC_0_COMMON_M""" ) popup "DSS_OVR" ( menuitem "DSS0_OVR1" "per , ""DSS_OVR,DSS0_OVR1""" menuitem "DSS0_OVR2" "per , ""DSS_OVR,DSS0_OVR2""" menuitem "DSS0_OVR3" "per , ""DSS_OVR,DSS0_OVR3""" menuitem "DSS0_OVR4" "per , ""DSS_OVR,DSS0_OVR4""" ) popup "DSS_VID" ( menuitem "DSS0_VID1" "per , ""DSS_VID,DSS0_VID1""" menuitem "DSS0_VID2" "per , ""DSS_VID,DSS0_VID2""" menuitem "DSS0_VIDL1" "per , ""DSS_VID,DSS0_VIDL1""" menuitem "DSS0_VIDL2" "per , ""DSS_VID,DSS0_VIDL2""" ) popup "DSS_VP" ( menuitem "DSS0_VP1" "per , ""DSS_VP,DSS0_VP1""" menuitem "DSS0_VP2" "per , ""DSS_VP,DSS0_VP2""" menuitem "DSS0_VP3" "per , ""DSS_VP,DSS0_VP3""" menuitem "DSS0_VP4" "per , ""DSS_VP,DSS0_VP4""" ) popup "DSS_WB" ( menuitem "DSS0_WB" "per , ""DSS_WB,DSS0_WB""" ) popup "ECAP" ( menuitem "ECAP0" "per , ""ECAP,ECAP0""" menuitem "ECAP1" "per , ""ECAP,ECAP1""" menuitem "ECAP2" "per , ""ECAP,ECAP2""" ) popup "EDP_CFG" ( menuitem "DSS_EDP0_INTG_CFG_VP" "per , ""EDP_CFG,DSS_EDP0_INTG_CFG_VP""" ) popup "EDP_CORE_APB" ( menuitem "DSS_EDP0_V2A_CORE_VP_REGS_APB" "per , ""EDP_CORE_APB,DSS_EDP0_V2A_CORE_VP_REGS_APB""" ) popup "EDP_CORE_SAPB" ( menuitem "DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB" "per , ""EDP_CORE_SAPB,DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB""" ) popup "EDP_ECC_CORE" ( menuitem "DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_CORE_CFG" "per , ""EDP_ECC_CORE,DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_CORE_CFG""" ) popup "EDP_ECC_DSC" ( menuitem "DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_DSC_CFG" "per , ""EDP_ECC_DSC,DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_DSC_CFG""" ) popup "EDP_ECC_PHY" ( menuitem "DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_PHY_CFG" "per , ""EDP_ECC_PHY,DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_PHY_CFG""" ) popup "ELM" ( menuitem "ELM0" "per , ""ELM,ELM0""" ) popup "ENCODER" ( menuitem "ENCODER0_REG_AXI" "per , ""ENCODER,ENCODER0_REG_AXI""" ) popup "EPWM" ( menuitem "EHRPWM0_EPWM" "per , ""EPWM,EHRPWM0_EPWM""" menuitem "EHRPWM1_EPWM" "per , ""EPWM,EHRPWM1_EPWM""" menuitem "EHRPWM2_EPWM" "per , ""EPWM,EHRPWM2_EPWM""" menuitem "EHRPWM3_EPWM" "per , ""EPWM,EHRPWM3_EPWM""" menuitem "EHRPWM4_EPWM" "per , ""EPWM,EHRPWM4_EPWM""" menuitem "EHRPWM5_EPWM" "per , ""EPWM,EHRPWM5_EPWM""" ) popup "EQEP" ( menuitem "EQEP0" "per , ""EQEP,EQEP0""" menuitem "EQEP1" "per , ""EQEP,EQEP1""" menuitem "EQEP2" "per , ""EQEP,EQEP2""" ) popup "ESM" ( menuitem "ESM0_CFG" "per , ""ESM,ESM0_CFG""" menuitem "MCU_ESM0_CFG" "per , ""ESM,MCU_ESM0_CFG""" menuitem "WKUP_ESM0_CFG" "per , ""ESM,WKUP_ESM0_CFG""" ) popup "Firewall_Exception" ( menuitem "CBASS_AASRC0_GLB" "per , ""Firewall_Exception,CBASS_AASRC0_GLB""" menuitem "CBASS_AC0_GLB" "per , ""Firewall_Exception,CBASS_AC0_GLB""" menuitem "CBASS_CSI0_GLB" "per , ""Firewall_Exception,CBASS_CSI0_GLB""" menuitem "CBASS_DATADEBUG0_GLB" "per , ""Firewall_Exception,CBASS_DATADEBUG0_GLB""" menuitem "CBASS_HC0_GLB" "per , ""Firewall_Exception,CBASS_HC0_GLB""" menuitem "CBASS_HC2_0_GLB" "per , ""Firewall_Exception,CBASS_HC2_0_GLB""" menuitem "CBASS_HC_CFG0_GLB" "per , ""Firewall_Exception,CBASS_HC_CFG0_GLB""" menuitem "CBASS_INFRA0_GLB" "per , ""Firewall_Exception,CBASS_INFRA0_GLB""" menuitem "CBASS_IPPHY0_GLB" "per , ""Firewall_Exception,CBASS_IPPHY0_GLB""" menuitem "CBASS_MCASP_G0_0_GLB" "per , ""Firewall_Exception,CBASS_MCASP_G0_0_GLB""" menuitem "CBASS_MCASP_G1_0_GLB" "per , ""Firewall_Exception,CBASS_MCASP_G1_0_GLB""" menuitem "CBASS_RC0_GLB" "per , ""Firewall_Exception,CBASS_RC0_GLB""" menuitem "CBASS_RC_CFG0_GLB" "per , ""Firewall_Exception,CBASS_RC_CFG0_GLB""" ) popup "FSS" ( menuitem "MCU_FSS0_CFG" "per , ""FSS,MCU_FSS0_CFG""" ) popup "GIC_ECC_AGGR" ( menuitem "COMPUTE_CLUSTER0_ECC_AGGR" "per , ""GIC_ECC_AGGR,COMPUTE_CLUSTER0_ECC_AGGR""" ) popup "GPIO" ( menuitem "WKUP_GPIO0" "per , ""GPIO,WKUP_GPIO0""" menuitem "WKUP_GPIO1" "per , ""GPIO,WKUP_GPIO1""" menuitem "GPIO0" "per , ""GPIO,GPIO0""" menuitem "GPIO1" "per , ""GPIO,GPIO1""" menuitem "GPIO2" "per , ""GPIO,GPIO2""" menuitem "GPIO3" "per , ""GPIO,GPIO3""" menuitem "GPIO4" "per , ""GPIO,GPIO4""" menuitem "GPIO5" "per , ""GPIO,GPIO5""" menuitem "GPIO6" "per , ""GPIO,GPIO6""" menuitem "GPIO7" "per , ""GPIO,GPIO7""" ) popup "GPMC" ( menuitem "GPMC0_CFG" "per , ""GPMC,GPMC0_CFG""" ) popup "GPU" ( menuitem "GPU0_PBIST_CFG" "per , ""GPU,GPU0_PBIST_CFG""" ) popup "GTC0_GTC_CFG0" ( menuitem "GTC0_GTC_CFG0" "per , ""GTC0_GTC_CFG0,GTC0_GTC_CFG0""" ) popup "GTC0_GTC_CFG1" ( menuitem "GTC0_GTC_CFG1" "per , ""GTC0_GTC_CFG1,GTC0_GTC_CFG1""" ) popup "GTC0_GTC_CFG2" ( menuitem "GTC0_GTC_CFG2" "per , ""GTC0_GTC_CFG2,GTC0_GTC_CFG2""" ) popup "GTC0_GTC_CFG3" ( menuitem "GTC0_GTC_CFG3" "per , ""GTC0_GTC_CFG3,GTC0_GTC_CFG3""" ) popup "HyperBus" ( menuitem "MCU_FSS0_HPB_CTRL" "per , ""HyperBus,MCU_FSS0_HPB_CTRL""" menuitem "MCU_FSS0_HPB_ECC_AGGR" "per , ""HyperBus,MCU_FSS0_HPB_ECC_AGGR""" menuitem "MCU_FSS0_HPB_SS_CFG" "per , ""HyperBus,MCU_FSS0_HPB_SS_CFG""" ) popup "I2C" ( menuitem "I2C0_CFG" "per , ""I2C,I2C0_CFG""" menuitem "I2C1_CFG" "per , ""I2C,I2C1_CFG""" menuitem "I2C2_CFG" "per , ""I2C,I2C2_CFG""" menuitem "I2C3_CFG" "per , ""I2C,I2C3_CFG""" menuitem "I2C4_CFG" "per , ""I2C,I2C4_CFG""" menuitem "I2C5_CFG" "per , ""I2C,I2C5_CFG""" menuitem "I2C6_CFG" "per , ""I2C,I2C6_CFG""" menuitem "MCU_I2C0_CFG" "per , ""I2C,MCU_I2C0_CFG""" menuitem "MCU_I2C1_CFG" "per , ""I2C,MCU_I2C1_CFG""" menuitem "WKUP_I2C0_CFG" "per , ""I2C,WKUP_I2C0_CFG""" ) popup "I3C" ( menuitem "I3C0_MMR_MMRVBP" "per , ""I3C,I3C0_MMR_MMRVBP""" menuitem "MCU_I3C0_MMR_MMRVBP" "per , ""I3C,MCU_I3C0_MMR_MMRVBP""" menuitem "MCU_I3C1_MMR_MMRVBP" "per , ""I3C,MCU_I3C1_MMR_MMRVBP""" menuitem "I3C0_P_ECC_AGGR_CFG" "per , ""I3C,I3C0_P_ECC_AGGR_CFG""" menuitem "I3C0_S_ECC_AGGR_CFG" "per , ""I3C,I3C0_S_ECC_AGGR_CFG""" menuitem "MCU_I3C0_P_ECC_AGGR_CFG" "per , ""I3C,MCU_I3C0_P_ECC_AGGR_CFG""" menuitem "MCU_I3C0_S_ECC_AGGR_CFG" "per , ""I3C,MCU_I3C0_S_ECC_AGGR_CFG""" menuitem "MCU_I3C1_P_ECC_AGGR_CFG" "per , ""I3C,MCU_I3C1_P_ECC_AGGR_CFG""" menuitem "MCU_I3C1_S_ECC_AGGR_CFG" "per , ""I3C,MCU_I3C1_S_ECC_AGGR_CFG""" menuitem "I3C0_S_ECC_AGGR_CFG" "per , ""I3C,I3C0_S_ECC_AGGR_CFG""" menuitem "MCU_I3C0_S_ECC_AGGR_CFG" "per , ""I3C,MCU_I3C0_S_ECC_AGGR_CFG""" menuitem "MCU_I3C1_S_ECC_AGGR_CFG" "per , ""I3C,MCU_I3C1_S_ECC_AGGR_CFG""" menuitem "I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST" "per , ""I3C,I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST""" menuitem "MCU_I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST" "per , ""I3C,MCU_I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST""" menuitem "MCU_I3C1_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST" "per , ""I3C,MCU_I3C1_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST""" ) popup "INTR0_INTR_ROUTER_CFG" ( menuitem "MCU_NAVSS0_INTR0_CFG" "per , ""INTR0_INTR_ROUTER_CFG,MCU_NAVSS0_INTR0_CFG""" menuitem "NAVSS0_INTR0_INTR_ROUTER_CFG" "per , ""INTR0_INTR_ROUTER_CFG,NAVSS0_INTR0_INTR_ROUTER_CFG""" ) popup "Mailbox" ( menuitem "MAILBOX0_REGS0" "per , ""Mailbox,MAILBOX0_REGS0""" menuitem "MAILBOX0_REGS1" "per , ""Mailbox,MAILBOX0_REGS1""" menuitem "MAILBOX0_REGS10" "per , ""Mailbox,MAILBOX0_REGS10""" menuitem "MAILBOX0_REGS11" "per , ""Mailbox,MAILBOX0_REGS11""" menuitem "MAILBOX0_REGS2" "per , ""Mailbox,MAILBOX0_REGS2""" menuitem "MAILBOX0_REGS3" "per , ""Mailbox,MAILBOX0_REGS3""" menuitem "MAILBOX0_REGS4" "per , ""Mailbox,MAILBOX0_REGS4""" menuitem "MAILBOX0_REGS5" "per , ""Mailbox,MAILBOX0_REGS5""" menuitem "MAILBOX0_REGS6" "per , ""Mailbox,MAILBOX0_REGS6""" menuitem "MAILBOX0_REGS7" "per , ""Mailbox,MAILBOX0_REGS7""" menuitem "MAILBOX0_REGS8" "per , ""Mailbox,MAILBOX0_REGS8""" menuitem "MAILBOX0_REGS9" "per , ""Mailbox,MAILBOX0_REGS9""" ) popup "MCAN_Core" ( menuitem "MCAN0_CFG" "per , ""MCAN_Core,MCAN0_CFG""" menuitem "MCAN10_CFG" "per , ""MCAN_Core,MCAN10_CFG""" menuitem "MCAN11_CFG" "per , ""MCAN_Core,MCAN11_CFG""" menuitem "MCAN12_CFG" "per , ""MCAN_Core,MCAN12_CFG""" menuitem "MCAN13_CFG" "per , ""MCAN_Core,MCAN13_CFG""" menuitem "MCAN1_CFG" "per , ""MCAN_Core,MCAN1_CFG""" menuitem "MCAN2_CFG" "per , ""MCAN_Core,MCAN2_CFG""" menuitem "MCAN3_CFG" "per , ""MCAN_Core,MCAN3_CFG""" menuitem "MCAN4_CFG" "per , ""MCAN_Core,MCAN4_CFG""" menuitem "MCAN5_CFG" "per , ""MCAN_Core,MCAN5_CFG""" menuitem "MCAN6_CFG" "per , ""MCAN_Core,MCAN6_CFG""" menuitem "MCAN7_CFG" "per , ""MCAN_Core,MCAN7_CFG""" menuitem "MCAN8_CFG" "per , ""MCAN_Core,MCAN8_CFG""" menuitem "MCAN9_CFG" "per , ""MCAN_Core,MCAN9_CFG""" menuitem "MCU_MCAN0_CFG" "per , ""MCAN_Core,MCU_MCAN0_CFG""" menuitem "MCU_MCAN1_CFG" "per , ""MCAN_Core,MCU_MCAN1_CFG""" ) popup "MCAN_ECC_Aggregator" ( menuitem "MCAN0_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN0_ECC_AGGR""" menuitem "MCAN10_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN10_ECC_AGGR""" menuitem "MCAN11_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN11_ECC_AGGR""" menuitem "MCAN12_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN12_ECC_AGGR""" menuitem "MCAN13_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN13_ECC_AGGR""" menuitem "MCAN1_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN1_ECC_AGGR""" menuitem "MCAN2_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN2_ECC_AGGR""" menuitem "MCAN3_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN3_ECC_AGGR""" menuitem "MCAN4_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN4_ECC_AGGR""" menuitem "MCAN5_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN5_ECC_AGGR""" menuitem "MCAN6_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN6_ECC_AGGR""" menuitem "MCAN7_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN7_ECC_AGGR""" menuitem "MCAN8_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN8_ECC_AGGR""" menuitem "MCAN9_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN9_ECC_AGGR""" menuitem "MCU_MCAN0_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCU_MCAN0_ECC_AGGR""" menuitem "MCU_MCAN1_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCU_MCAN1_ECC_AGGR""" ) popup "MCAN_Subsystem" ( menuitem "MCAN0_SS" "per , ""MCAN_Subsystem,MCAN0_SS""" menuitem "MCAN10_SS" "per , ""MCAN_Subsystem,MCAN10_SS""" menuitem "MCAN11_SS" "per , ""MCAN_Subsystem,MCAN11_SS""" menuitem "MCAN12_SS" "per , ""MCAN_Subsystem,MCAN12_SS""" menuitem "MCAN13_SS" "per , ""MCAN_Subsystem,MCAN13_SS""" menuitem "MCAN1_SS" "per , ""MCAN_Subsystem,MCAN1_SS""" menuitem "MCAN2_SS" "per , ""MCAN_Subsystem,MCAN2_SS""" menuitem "MCAN3_SS" "per , ""MCAN_Subsystem,MCAN3_SS""" menuitem "MCAN4_SS" "per , ""MCAN_Subsystem,MCAN4_SS""" menuitem "MCAN5_SS" "per , ""MCAN_Subsystem,MCAN5_SS""" menuitem "MCAN6_SS" "per , ""MCAN_Subsystem,MCAN6_SS""" menuitem "MCAN7_SS" "per , ""MCAN_Subsystem,MCAN7_SS""" menuitem "MCAN8_SS" "per , ""MCAN_Subsystem,MCAN8_SS""" menuitem "MCAN9_SS" "per , ""MCAN_Subsystem,MCAN9_SS""" menuitem "MCU_MCAN0_SS" "per , ""MCAN_Subsystem,MCU_MCAN0_SS""" menuitem "MCU_MCAN1_SS" "per , ""MCAN_Subsystem,MCU_MCAN1_SS""" ) popup "MCASP" ( menuitem "MCASP0_CFG" "per , ""MCASP,MCASP0_CFG""" menuitem "MCASP10_CFG" "per , ""MCASP,MCASP10_CFG""" menuitem "MCASP11_CFG" "per , ""MCASP,MCASP11_CFG""" menuitem "MCASP1_CFG" "per , ""MCASP,MCASP1_CFG""" menuitem "MCASP2_CFG" "per , ""MCASP,MCASP2_CFG""" menuitem "MCASP3_CFG" "per , ""MCASP,MCASP3_CFG""" menuitem "MCASP4_CFG" "per , ""MCASP,MCASP4_CFG""" menuitem "MCASP5_CFG" "per , ""MCASP,MCASP5_CFG""" menuitem "MCASP6_CFG" "per , ""MCASP,MCASP6_CFG""" menuitem "MCASP7_CFG" "per , ""MCASP,MCASP7_CFG""" menuitem "MCASP8_CFG" "per , ""MCASP,MCASP8_CFG""" menuitem "MCASP9_CFG" "per , ""MCASP,MCASP9_CFG""" menuitem "MCASP0_DMA" "per , ""MCASP,MCASP0_DMA""" menuitem "MCASP10_DMA" "per , ""MCASP,MCASP10_DMA""" menuitem "MCASP11_DMA" "per , ""MCASP,MCASP11_DMA""" menuitem "MCASP1_DMA" "per , ""MCASP,MCASP1_DMA""" menuitem "MCASP2_DMA" "per , ""MCASP,MCASP2_DMA""" menuitem "MCASP3_DMA" "per , ""MCASP,MCASP3_DMA""" menuitem "MCASP4_DMA" "per , ""MCASP,MCASP4_DMA""" menuitem "MCASP5_DMA" "per , ""MCASP,MCASP5_DMA""" menuitem "MCASP6_DMA" "per , ""MCASP,MCASP6_DMA""" menuitem "MCASP7_DMA" "per , ""MCASP,MCASP7_DMA""" menuitem "MCASP8_DMA" "per , ""MCASP,MCASP8_DMA""" menuitem "MCASP9_DMA" "per , ""MCASP,MCASP9_DMA""" ) popup "MCSPI" ( menuitem "MCSPI0_CFG" "per , ""MCSPI,MCSPI0_CFG""" menuitem "MCSPI1_CFG" "per , ""MCSPI,MCSPI1_CFG""" menuitem "MCSPI2_CFG" "per , ""MCSPI,MCSPI2_CFG""" menuitem "MCSPI3_CFG" "per , ""MCSPI,MCSPI3_CFG""" menuitem "MCSPI4_CFG" "per , ""MCSPI,MCSPI4_CFG""" menuitem "MCSPI5_CFG" "per , ""MCSPI,MCSPI5_CFG""" menuitem "MCSPI6_CFG" "per , ""MCSPI,MCSPI6_CFG""" menuitem "MCSPI7_CFG" "per , ""MCSPI,MCSPI7_CFG""" menuitem "MCU_MCSPI0_CFG" "per , ""MCSPI,MCU_MCSPI0_CFG""" menuitem "MCU_MCSPI1_CFG" "per , ""MCSPI,MCU_MCSPI1_CFG""" menuitem "MCU_MCSPI2_CFG" "per , ""MCSPI,MCU_MCSPI2_CFG""" ) popup "MCU_CPSW0_ALE" ( menuitem "MCU_CPSW0_NUSS_ALE" "per , ""MCU_CPSW0_ALE,MCU_CPSW0_NUSS_ALE""" ) popup "MCU_CPSW0_CONTROL" ( menuitem "MCU_CPSW0_NUSS_CONTROL" "per , ""MCU_CPSW0_CONTROL,MCU_CPSW0_NUSS_CONTROL""" ) popup "MCU_CPSW0_CPINT" ( menuitem "MCU_CPSW0_NUSS_CPINT" "per , ""MCU_CPSW0_CPINT,MCU_CPSW0_NUSS_CPINT""" ) popup "MCU_CPSW0_CPTS" ( menuitem "MCU_CPSW0_NUSS_CPTS" "per , ""MCU_CPSW0_CPTS,MCU_CPSW0_NUSS_CPTS""" ) popup "MCU_CPSW0_ECC" ( menuitem "MCU_CPSW0_ECC" "per , ""MCU_CPSW0_ECC,MCU_CPSW0_ECC""" ) popup "MCU_CPSW0_MDIO" ( menuitem "MCU_CPSW0_NUSS_MDIO" "per , ""MCU_CPSW0_MDIO,MCU_CPSW0_NUSS_MDIO""" ) popup "MCU_CPSW0_NUSS_Subsystem__SS_" ( menuitem "MCU_CPSW0_NUSS_SS" "per , ""MCU_CPSW0_NUSS_Subsystem__SS_,MCU_CPSW0_NUSS_SS""" ) popup "MCU_CPSW0_RAM" ( menuitem "MCU_CPSW0_NUSS_RAM" "per , ""MCU_CPSW0_RAM,MCU_CPSW0_NUSS_RAM""" ) popup "MCU_CPSW0_SGMII" ( menuitem "MCU_CPSW0_NUSS_SGMII" "per , ""MCU_CPSW0_SGMII,MCU_CPSW0_NUSS_SGMII""" ) popup "MCU_CPSW0_STAT0" ( menuitem "MCU_CPSW0_NUSS_STAT0" "per , ""MCU_CPSW0_STAT0,MCU_CPSW0_NUSS_STAT0""" ) popup "MCU_CPSW0_STAT1" ( menuitem "MCU_CPSW0_NUSS" "per , ""MCU_CPSW0_STAT1,MCU_CPSW0_NUSS""" ) popup "MCU_CTRL_MMR0" ( menuitem "MCU_CTRL_MMR0" "per , ""MCU_CTRL_MMR0,MCU_CTRL_MMR0""" ) popup "MCU_NAVSS0_UDMASS_ECCAGGR0" ( menuitem "MCU_NAVSS0_UDMASS_ECCAGGR0" "per , ""MCU_NAVSS0_UDMASS_ECCAGGR0,MCU_NAVSS0_UDMASS_ECCAGGR0""" ) popup "MCU_PLL0_CFG" ( menuitem "MCU_PLL0_CFG" "per , ""MCU_PLL0_CFG,MCU_PLL0_CFG""" ) popup "MCU_SEC_MMR0_DBG_CTRL" ( menuitem "MCU_SEC_MMR0_CFG0" "per , ""MCU_SEC_MMR0_DBG_CTRL,MCU_SEC_MMR0_CFG0""" menuitem "MCU_SEC_MMR0_DBG_CTRL" "per , ""MCU_SEC_MMR0_DBG_CTRL,MCU_SEC_MMR0_DBG_CTRL""" ) popup "MLBSS" ( menuitem "MLB0_MMR_MMRVBP" "per , ""MLBSS,MLB0_MMR_MMRVBP""" ) popup "MLBSS_Configuration" ( menuitem "MLB0_VBP2APB_WRAP_MLB_CFG_VBP_MLBDIM" "per , ""MLBSS_Configuration,MLB0_VBP2APB_WRAP_MLB_CFG_VBP_MLBDIM""" ) popup "MLBSS_ECC_Aggregator" ( menuitem "MLB0_MLBDIM_WRAP_ECC_AGGR_VBP" "per , ""MLBSS_ECC_Aggregator,MLB0_MLBDIM_WRAP_ECC_AGGR_VBP""" ) popup "MLBSS_RAT" ( menuitem "MLB0_RAT_WRAP_RAT_CFG_VBP_MMRS" "per , ""MLBSS_RAT,MLB0_RAT_WRAP_RAT_CFG_VBP_MMRS""" ) popup "MMCSD0_Host_Controller" ( menuitem "MMCSD0_CTL_CFG" "per , ""MMCSD0_Host_Controller,MMCSD0_CTL_CFG""" ) popup "MMCSD0_RX_RAM_ECC_Aggregator" ( menuitem "MMCSD0_ECC_AGGR_RXMEM" "per , ""MMCSD0_RX_RAM_ECC_Aggregator,MMCSD0_ECC_AGGR_RXMEM""" ) popup "MMCSD0_Subsystem" ( menuitem "MMCSD0_SS_CFG" "per , ""MMCSD0_Subsystem,MMCSD0_SS_CFG""" ) popup "MMCSD0_TX_RAM_ECC_Aggregator" ( menuitem "MMCSD0_ECC_AGGR_TXMEM" "per , ""MMCSD0_TX_RAM_ECC_Aggregator,MMCSD0_ECC_AGGR_TXMEM""" ) popup "MMCSD1___MMCSD2_Host_Controller" ( menuitem "MMCSD1_CTL_CFG" "per , ""MMCSD1___MMCSD2_Host_Controller,MMCSD1_CTL_CFG""" menuitem "MMCSD2_CTL_CFG" "per , ""MMCSD1___MMCSD2_Host_Controller,MMCSD2_CTL_CFG""" ) popup "MMCSD1___MMCSD2_RX_RAM_ECC_Aggregator" ( menuitem "MMCSD1_ECC_AGGR_RXMEM" "per , ""MMCSD1___MMCSD2_RX_RAM_ECC_Aggregator,MMCSD1_ECC_AGGR_RXMEM""" menuitem "MMCSD2_ECC_AGGR_RXMEM" "per , ""MMCSD1___MMCSD2_RX_RAM_ECC_Aggregator,MMCSD2_ECC_AGGR_RXMEM""" ) popup "MMCSD1___MMCSD2_Subsystem" ( menuitem "MMCSD1_SS_CFG" "per , ""MMCSD1___MMCSD2_Subsystem,MMCSD1_SS_CFG""" menuitem "MMCSD2_SS_CFG" "per , ""MMCSD1___MMCSD2_Subsystem,MMCSD2_SS_CFG""" ) popup "MMCSD1___MMCSD2_TX_RAM_ECC_Aggregator" ( menuitem "MMCSD1_ECC_AGGR_TXMEM" "per , ""MMCSD1___MMCSD2_TX_RAM_ECC_Aggregator,MMCSD1_ECC_AGGR_TXMEM""" menuitem "MMCSD2_ECC_AGGR_TXMEM" "per , ""MMCSD1___MMCSD2_TX_RAM_ECC_Aggregator,MMCSD2_ECC_AGGR_TXMEM""" ) popup "MODSS_INTA_CFG" ( menuitem "NAVSS0_MODSS_INTA0_CFG" "per , ""MODSS_INTA_CFG,NAVSS0_MODSS_INTA0_CFG""" menuitem "NAVSS0_MODSS_INTA1_CFG" "per , ""MODSS_INTA_CFG,NAVSS0_MODSS_INTA1_CFG""" ) popup "MODSS_INTA_CFG_IMAP" ( menuitem "NAVSS0_MODSS_INTA0_CFG_IMAP" "per , ""MODSS_INTA_CFG_IMAP,NAVSS0_MODSS_INTA0_CFG_IMAP""" menuitem "NAVSS0_MODSS_INTA1_CFG_IMAP" "per , ""MODSS_INTA_CFG_IMAP,NAVSS0_MODSS_INTA1_CFG_IMAP""" ) popup "MODSS_INTA_CFG_INTR" ( menuitem "NAVSS0_MODSS_INTA0_CFG_INTR" "per , ""MODSS_INTA_CFG_INTR,NAVSS0_MODSS_INTA0_CFG_INTR""" menuitem "NAVSS0_MODSS_INTA1_CFG_INTR" "per , ""MODSS_INTA_CFG_INTR,NAVSS0_MODSS_INTA1_CFG_INTR""" ) popup "MSMC" ( menuitem "COMPUTE_CLUSTER0_MSMC_CFGS0" "per , ""MSMC,COMPUTE_CLUSTER0_MSMC_CFGS0""" ) popup "NAVSS0_CFG" ( menuitem "NAVSS0_CFG" "per , ""NAVSS0_CFG,NAVSS0_CFG""" ) popup "NAVSS0_CPTS" ( menuitem "NAVSS0_CPTS" "per , ""NAVSS0_CPTS,NAVSS0_CPTS""" ) popup "NAVSS0_MCRC" ( menuitem "MCU_NAVSS0_MCRC" "per , ""NAVSS0_MCRC,MCU_NAVSS0_MCRC""" menuitem "NAVSS0_MCRC" "per , ""NAVSS0_MCRC,NAVSS0_MCRC""" ) popup "NAVSS0_NBSS_CFG_REGS0_MMRS" ( menuitem "NAVSS0_NBSS_CFG_REGS0_MMRS" "per , ""NAVSS0_NBSS_CFG_REGS0_MMRS,NAVSS0_NBSS_CFG_REGS0_MMRS""" ) popup "NAVSS0_NBSS_NB0_MEM_ATTR0_CFG" ( menuitem "NAVSS0_NBSS_NB0_MEM_ATTR0_CFG" "per , ""NAVSS0_NBSS_NB0_MEM_ATTR0_CFG,NAVSS0_NBSS_NB0_MEM_ATTR0_CFG""" ) popup "NAVSS0_NBSS_NB0_MEM_ATTR1_CFG" ( menuitem "NAVSS0_NBSS_NB0_MEM_ATTR1_CFG" "per , ""NAVSS0_NBSS_NB0_MEM_ATTR1_CFG,NAVSS0_NBSS_NB0_MEM_ATTR1_CFG""" ) popup "NAVSS0_NBSS_NB1_MEM_ATTR0_CFG" ( menuitem "NAVSS0_NBSS_NB1_MEM_ATTR0_CFG" "per , ""NAVSS0_NBSS_NB1_MEM_ATTR0_CFG,NAVSS0_NBSS_NB1_MEM_ATTR0_CFG""" ) popup "NAVSS0_NBSS_NB1_MEM_ATTR1_CFG" ( menuitem "NAVSS0_NBSS_NB1_MEM_ATTR1_CFG" "per , ""NAVSS0_NBSS_NB1_MEM_ATTR1_CFG,NAVSS0_NBSS_NB1_MEM_ATTR1_CFG""" ) popup "NAVSS0_NBSS_NB_CFG_MMRS" ( menuitem "NAVSS0_NBSS_NB0_CFG_MMRS" "per , ""NAVSS0_NBSS_NB_CFG_MMRS,NAVSS0_NBSS_NB0_CFG_MMRS""" menuitem "NAVSS0_NBSS_NB1_CFG_MMRS" "per , ""NAVSS0_NBSS_NB_CFG_MMRS,NAVSS0_NBSS_NB1_CFG_MMRS""" ) popup "NAVSS0_PROXY0_BUF_CFG" ( menuitem "MCU_NAVSS0_PROXY0_BUF_CFG" "per , ""NAVSS0_PROXY0_BUF_CFG,MCU_NAVSS0_PROXY0_BUF_CFG""" menuitem "NAVSS0_PROXY0_BUF_CFG" "per , ""NAVSS0_PROXY0_BUF_CFG,NAVSS0_PROXY0_BUF_CFG""" ) popup "NAVSS0_PROXY0_CFG_BUF_CFG" ( menuitem "MCU_NAVSS0_PROXY_CFG_GCFG" "per , ""NAVSS0_PROXY0_CFG_BUF_CFG,MCU_NAVSS0_PROXY_CFG_GCFG""" menuitem "NAVSS0_PROXY0_CFG_BUF_CFG" "per , ""NAVSS0_PROXY0_CFG_BUF_CFG,NAVSS0_PROXY0_CFG_BUF_CFG""" ) popup "NAVSS0_PROXY_BUF" ( menuitem "MCU_NAVSS0_PROXY_CFG_BUF" "per , ""NAVSS0_PROXY_BUF,MCU_NAVSS0_PROXY_CFG_BUF""" menuitem "NAVSS0_PROXY_BUF" "per , ""NAVSS0_PROXY_BUF,NAVSS0_PROXY_BUF""" ) popup "NAVSS0_PROXY_TARGET0_DATA" ( menuitem "MCU_NAVSS0_PROXY0_TARGET0_DATA" "per , ""NAVSS0_PROXY_TARGET0_DATA,MCU_NAVSS0_PROXY0_TARGET0_DATA""" menuitem "NAVSS0_PROXY_TARGET0_DATA" "per , ""NAVSS0_PROXY_TARGET0_DATA,NAVSS0_PROXY_TARGET0_DATA""" ) popup "NAVSS0_PVU_CFG_TLBIF" ( menuitem "NAVSS0_DMA_PVU1_CFG_TLBIF" "per , ""NAVSS0_PVU_CFG_TLBIF,NAVSS0_DMA_PVU1_CFG_TLBIF""" menuitem "NAVSS0_IO_PVU0_CFG_TLBIF" "per , ""NAVSS0_PVU_CFG_TLBIF,NAVSS0_IO_PVU0_CFG_TLBIF""" menuitem "NAVSS0_IO_PVU1_CFG_TLBIF" "per , ""NAVSS0_PVU_CFG_TLBIF,NAVSS0_IO_PVU1_CFG_TLBIF""" ) popup "NAVSS0_SEC_PROXY0_CFG_MMRS" ( menuitem "MCU_NAVSS0_SEC_PROXY0_CFG" "per , ""NAVSS0_SEC_PROXY0_CFG_MMRS,MCU_NAVSS0_SEC_PROXY0_CFG""" menuitem "NAVSS0_SEC_PROXY0_CFG_MMRS" "per , ""NAVSS0_SEC_PROXY0_CFG_MMRS,NAVSS0_SEC_PROXY0_CFG_MMRS""" ) popup "NAVSS0_SEC_PROXY0_CFG_RT" ( menuitem "MCU_NAVSS0_SEC_PROXY0_CFG_RT" "per , ""NAVSS0_SEC_PROXY0_CFG_RT,MCU_NAVSS0_SEC_PROXY0_CFG_RT""" menuitem "NAVSS0_SEC_PROXY0_CFG_RT" "per , ""NAVSS0_SEC_PROXY0_CFG_RT,NAVSS0_SEC_PROXY0_CFG_RT""" ) popup "NAVSS0_SEC_PROXY0_CFG_SCFG" ( menuitem "MCU_NAVSS0_SEC_PROXY0_CFG_SCFG" "per , ""NAVSS0_SEC_PROXY0_CFG_SCFG,MCU_NAVSS0_SEC_PROXY0_CFG_SCFG""" menuitem "NAVSS0_SEC_PROXY0_CFG_SCFG" "per , ""NAVSS0_SEC_PROXY0_CFG_SCFG,NAVSS0_SEC_PROXY0_CFG_SCFG""" ) popup "NAVSS0_SEC_PROXY0_SRC_TARGET_DATA" ( menuitem "MCU_NAVSS0_SEC_PROXY0_TARGET_DATA" "per , ""NAVSS0_SEC_PROXY0_SRC_TARGET_DATA,MCU_NAVSS0_SEC_PROXY0_TARGET_DATA""" menuitem "NAVSS0_SEC_PROXY0_SRC_TARGET_DATA" "per , ""NAVSS0_SEC_PROXY0_SRC_TARGET_DATA,NAVSS0_SEC_PROXY0_SRC_TARGET_DATA""" ) popup "NAVSS0_UDMASS_RINGACC0_CFG" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG" "per , ""NAVSS0_UDMASS_RINGACC0_CFG,MCU_NAVSS0_UDMASS_RINGACC0_CFG""" menuitem "NAVSS0_UDMASS_RINGACC0_CFG" "per , ""NAVSS0_UDMASS_RINGACC0_CFG,NAVSS0_UDMASS_RINGACC0_CFG""" ) popup "NAVSS0_UDMASS_RINGACC0_CFG_MON" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_MON,MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON""" menuitem "NAVSS0_UDMASS_RINGACC0_CFG_MON" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_MON,NAVSS0_UDMASS_RINGACC0_CFG_MON""" ) popup "NAVSS0_UDMASS_RINGACC0_CFG_RT" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_RT,MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT""" menuitem "NAVSS0_UDMASS_RINGACC0_CFG_RT" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_RT,NAVSS0_UDMASS_RINGACC0_CFG_RT""" ) popup "NAVSS0_UDMASS_RINGACC0_GCFG" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG" "per , ""NAVSS0_UDMASS_RINGACC0_GCFG,MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG""" menuitem "NAVSS0_UDMASS_RINGACC0_GCFG" "per , ""NAVSS0_UDMASS_RINGACC0_GCFG,NAVSS0_UDMASS_RINGACC0_GCFG""" ) popup "NAVSS0_UDMASS_RINGACC0_SRC_FIFOS" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_FIFOS" "per , ""NAVSS0_UDMASS_RINGACC0_SRC_FIFOS,MCU_NAVSS0_UDMASS_RINGACC0_FIFOS""" menuitem "NAVSS0_UDMASS_RINGACC0_SRC_FIFOS" "per , ""NAVSS0_UDMASS_RINGACC0_SRC_FIFOS,NAVSS0_UDMASS_RINGACC0_SRC_FIFOS""" ) popup "NAVSS_PVU_CFG" ( menuitem "NAVSS0_DMA_PVU1_CFG" "per , ""NAVSS_PVU_CFG,NAVSS0_DMA_PVU1_CFG""" menuitem "NAVSS0_IO_PVU0_CFG" "per , ""NAVSS_PVU_CFG,NAVSS0_IO_PVU0_CFG""" menuitem "NAVSS0_IO_PVU1_CFG" "per , ""NAVSS_PVU_CFG,NAVSS0_IO_PVU1_CFG""" ) popup "Null_Error_Reporting" ( menuitem "CBASS_AASRC0_ERR" "per , ""Null_Error_Reporting,CBASS_AASRC0_ERR""" menuitem "CBASS_AC0_ERR" "per , ""Null_Error_Reporting,CBASS_AC0_ERR""" menuitem "CBASS_CSI0_ERR" "per , ""Null_Error_Reporting,CBASS_CSI0_ERR""" menuitem "CBASS_DATADEBUG0_ERR" "per , ""Null_Error_Reporting,CBASS_DATADEBUG0_ERR""" menuitem "CBASS_FW0_ERR" "per , ""Null_Error_Reporting,CBASS_FW0_ERR""" menuitem "CBASS_HC0_ERR" "per , ""Null_Error_Reporting,CBASS_HC0_ERR""" menuitem "CBASS_HC2_0_ERR" "per , ""Null_Error_Reporting,CBASS_HC2_0_ERR""" menuitem "CBASS_HC_CFG0_ERR" "per , ""Null_Error_Reporting,CBASS_HC_CFG0_ERR""" menuitem "CBASS_INFRA0_ERR" "per , ""Null_Error_Reporting,CBASS_INFRA0_ERR""" menuitem "CBASS_IPPHY0_ERR" "per , ""Null_Error_Reporting,CBASS_IPPHY0_ERR""" menuitem "CBASS_MCASP_G0_0_ERR" "per , ""Null_Error_Reporting,CBASS_MCASP_G0_0_ERR""" menuitem "CBASS_MCASP_G1_0_ERR" "per , ""Null_Error_Reporting,CBASS_MCASP_G1_0_ERR""" menuitem "CBASS_RC0_ERR" "per , ""Null_Error_Reporting,CBASS_RC0_ERR""" menuitem "CBASS_RC_CFG0_ERR" "per , ""Null_Error_Reporting,CBASS_RC_CFG0_ERR""" menuitem "MCU_CBASS_FW0_ERR" "per , ""Null_Error_Reporting,MCU_CBASS_FW0_ERR""" menuitem "WKUP_CBASS_FW0_ERR" "per , ""Null_Error_Reporting,WKUP_CBASS_FW0_ERR""" ) popup "OSPI" ( menuitem "MCU_FSS0_OSPI0_CTRL" "per , ""OSPI,MCU_FSS0_OSPI0_CTRL""" menuitem "MCU_FSS0_OSPI1_CTRL" "per , ""OSPI,MCU_FSS0_OSPI1_CTRL""" menuitem "MCU_FSS0_OSPI0_SS_CFG" "per , ""OSPI,MCU_FSS0_OSPI0_SS_CFG""" menuitem "MCU_FSS0_OSPI1_SS_CFG" "per , ""OSPI,MCU_FSS0_OSPI1_SS_CFG""" menuitem "MCU_FSS0_OSPI0_ECC_AGGR" "per , ""OSPI,MCU_FSS0_OSPI0_ECC_AGGR""" menuitem "MCU_FSS0_OSPI1_ECC_AGGR" "per , ""OSPI,MCU_FSS0_OSPI1_ECC_AGGR""" ) popup "PAT_CFG_MMRS" ( menuitem "PAT0_CFG_MMRS" "per , ""PAT_CFG_MMRS,PAT0_CFG_MMRS""" menuitem "PAT1_CFG_MMRS" "per , ""PAT_CFG_MMRS,PAT1_CFG_MMRS""" menuitem "PAT2_CFG_MMRS" "per , ""PAT_CFG_MMRS,PAT2_CFG_MMRS""" menuitem "PAT3_CFG_MMRS" "per , ""PAT_CFG_MMRS,PAT3_CFG_MMRS""" menuitem "PAT4_CFG_MMRS" "per , ""PAT_CFG_MMRS,PAT4_CFG_MMRS""" menuitem "PAT0_CFG_SCRATCH" "per , ""PAT_CFG_MMRS,PAT0_CFG_SCRATCH""" menuitem "PAT1_CFG_SCRATCH" "per , ""PAT_CFG_MMRS,PAT1_CFG_SCRATCH""" menuitem "PAT2_CFG_SCRATCH" "per , ""PAT_CFG_MMRS,PAT2_CFG_SCRATCH""" menuitem "PAT3_CFG_SCRATCH" "per , ""PAT_CFG_MMRS,PAT3_CFG_SCRATCH""" menuitem "PAT4_CFG_SCRATCH" "per , ""PAT_CFG_MMRS,PAT4_CFG_SCRATCH""" menuitem "PAT0_CFG_TABLE" "per , ""PAT_CFG_MMRS,PAT0_CFG_TABLE""" menuitem "PAT1_CFG_TABLE" "per , ""PAT_CFG_MMRS,PAT1_CFG_TABLE""" menuitem "PAT2_CFG_TABLE" "per , ""PAT_CFG_MMRS,PAT2_CFG_TABLE""" menuitem "PAT3_CFG_TABLE" "per , ""PAT_CFG_MMRS,PAT3_CFG_TABLE""" menuitem "PAT4_CFG_TABLE" "per , ""PAT_CFG_MMRS,PAT4_CFG_TABLE""" ) popup "PCIE_CORE_AXI" ( menuitem "PCIE0_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_AXI,PCIE0_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE1_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_AXI,PCIE1_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE2_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_AXI,PCIE2_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE3_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_AXI,PCIE3_CORE_DBN_CFG_PCIE_CORE""" ) popup "PCIE_CORE_EP" ( menuitem "PCIE0_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP,PCIE0_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE1_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP,PCIE1_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE2_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP,PCIE2_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE3_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP,PCIE3_CORE_DBN_CFG_PCIE_CORE""" ) popup "PCIE_CORE_EP_PF" ( menuitem "PCIE0_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP_PF,PCIE0_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE1_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP_PF,PCIE1_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE2_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP_PF,PCIE2_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE3_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP_PF,PCIE3_CORE_DBN_CFG_PCIE_CORE""" ) popup "PCIE_CORE_EP_VF" ( menuitem "PCIE0_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP_VF,PCIE0_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE1_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP_VF,PCIE1_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE2_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP_VF,PCIE2_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE3_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_EP_VF,PCIE3_CORE_DBN_CFG_PCIE_CORE""" ) popup "PCIE_CORE_LM" ( menuitem "PCIE0_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_LM,PCIE0_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE1_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_LM,PCIE1_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE2_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_LM,PCIE2_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE3_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_LM,PCIE3_CORE_DBN_CFG_PCIE_CORE""" ) menuitem "PCIE0_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE0_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE1_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE1_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE2_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE2_CORE_DBN_CFG_PCIE_CORE""" menuitem "PCIE3_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE3_CORE_DBN_CFG_PCIE_CORE""" popup "PCIE_CPTS" ( menuitem "PCIE0_CORE_CPTS_CFG_CPTS_VBUSP" "per , ""PCIE_CPTS,PCIE0_CORE_CPTS_CFG_CPTS_VBUSP""" menuitem "PCIE1_CORE_CPTS_CFG_CPTS_VBUSP" "per , ""PCIE_CPTS,PCIE1_CORE_CPTS_CFG_CPTS_VBUSP""" menuitem "PCIE2_CORE_CPTS_CFG_CPTS_VBUSP" "per , ""PCIE_CPTS,PCIE2_CORE_CPTS_CFG_CPTS_VBUSP""" menuitem "PCIE3_CORE_CPTS_CFG_CPTS_VBUSP" "per , ""PCIE_CPTS,PCIE3_CORE_CPTS_CFG_CPTS_VBUSP""" ) popup "PCIE_ECC_AGGR0" ( menuitem "PCIE0_CORE_ECC_AGGR0" "per , ""PCIE_ECC_AGGR0,PCIE0_CORE_ECC_AGGR0""" menuitem "PCIE1_CORE_ECC_AGGR0" "per , ""PCIE_ECC_AGGR0,PCIE1_CORE_ECC_AGGR0""" menuitem "PCIE2_CORE_ECC_AGGR0" "per , ""PCIE_ECC_AGGR0,PCIE2_CORE_ECC_AGGR0""" menuitem "PCIE3_CORE_ECC_AGGR0" "per , ""PCIE_ECC_AGGR0,PCIE3_CORE_ECC_AGGR0""" ) popup "PCIE_ECC_AGGR1" ( menuitem "PCIE0_CORE_ECC_AGGR1" "per , ""PCIE_ECC_AGGR1,PCIE0_CORE_ECC_AGGR1""" menuitem "PCIE1_CORE_ECC_AGGR1" "per , ""PCIE_ECC_AGGR1,PCIE1_CORE_ECC_AGGR1""" menuitem "PCIE2_CORE_ECC_AGGR1" "per , ""PCIE_ECC_AGGR1,PCIE2_CORE_ECC_AGGR1""" menuitem "PCIE3_CORE_ECC_AGGR1" "per , ""PCIE_ECC_AGGR1,PCIE3_CORE_ECC_AGGR1""" ) popup "PCIE_HP_DAT0" ( menuitem "PCIE0_DAT0" "per , ""PCIE_HP_DAT0,PCIE0_DAT0""" menuitem "PCIE1_DAT0" "per , ""PCIE_HP_DAT0,PCIE1_DAT0""" menuitem "PCIE2_DAT0" "per , ""PCIE_HP_DAT0,PCIE2_DAT0""" menuitem "PCIE3_DAT0" "per , ""PCIE_HP_DAT0,PCIE3_DAT0""" ) popup "PCIE_HP_DAT1" ( menuitem "PCIE0_DAT1" "per , ""PCIE_HP_DAT1,PCIE0_DAT1""" menuitem "PCIE1_DAT1" "per , ""PCIE_HP_DAT1,PCIE1_DAT1""" menuitem "PCIE2_DAT1" "per , ""PCIE_HP_DAT1,PCIE2_DAT1""" menuitem "PCIE3_DAT1" "per , ""PCIE_HP_DAT1,PCIE3_DAT1""" ) popup "PCIE_INTD" ( menuitem "PCIE0_CORE_PCIE_INTD_CFG_INTD_CFG" "per , ""PCIE_INTD,PCIE0_CORE_PCIE_INTD_CFG_INTD_CFG""" menuitem "PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG" "per , ""PCIE_INTD,PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG""" menuitem "PCIE2_CORE_PCIE_INTD_CFG_INTD_CFG" "per , ""PCIE_INTD,PCIE2_CORE_PCIE_INTD_CFG_INTD_CFG""" menuitem "PCIE3_CORE_PCIE_INTD_CFG_INTD_CFG" "per , ""PCIE_INTD,PCIE3_CORE_PCIE_INTD_CFG_INTD_CFG""" ) popup "PCIE_LP_DAT0" ( menuitem "PCIE0_DAT0" "per , ""PCIE_LP_DAT0,PCIE0_DAT0""" menuitem "PCIE1_DAT0" "per , ""PCIE_LP_DAT0,PCIE1_DAT0""" menuitem "PCIE2_DAT0" "per , ""PCIE_LP_DAT0,PCIE2_DAT0""" menuitem "PCIE3_DAT0" "per , ""PCIE_LP_DAT0,PCIE3_DAT0""" ) popup "PCIE_LP_DAT1" ( menuitem "PCIE0_DAT1" "per , ""PCIE_LP_DAT1,PCIE0_DAT1""" menuitem "PCIE1_DAT1" "per , ""PCIE_LP_DAT1,PCIE1_DAT1""" menuitem "PCIE2_DAT1" "per , ""PCIE_LP_DAT1,PCIE2_DAT1""" menuitem "PCIE3_DAT1" "per , ""PCIE_LP_DAT1,PCIE3_DAT1""" ) popup "PCIE_USER_CFG" ( menuitem "PCIE0_CORE_USER_CFG_USER_CFG" "per , ""PCIE_USER_CFG,PCIE0_CORE_USER_CFG_USER_CFG""" menuitem "PCIE1_CORE_USER_CFG_USER_CFG" "per , ""PCIE_USER_CFG,PCIE1_CORE_USER_CFG_USER_CFG""" menuitem "PCIE2_CORE_USER_CFG_USER_CFG" "per , ""PCIE_USER_CFG,PCIE2_CORE_USER_CFG_USER_CFG""" menuitem "PCIE3_CORE_USER_CFG_USER_CFG" "per , ""PCIE_USER_CFG,PCIE3_CORE_USER_CFG_USER_CFG""" ) popup "PCIE_VMAP_HP" ( menuitem "PCIE0_CORE_VMAP_HP_MMRS" "per , ""PCIE_VMAP_HP,PCIE0_CORE_VMAP_HP_MMRS""" menuitem "PCIE1_CORE_VMAP_HP_MMRS" "per , ""PCIE_VMAP_HP,PCIE1_CORE_VMAP_HP_MMRS""" menuitem "PCIE2_CORE_VMAP_HP_MMRS" "per , ""PCIE_VMAP_HP,PCIE2_CORE_VMAP_HP_MMRS""" menuitem "PCIE3_CORE_VMAP_HP_MMRS" "per , ""PCIE_VMAP_HP,PCIE3_CORE_VMAP_HP_MMRS""" ) popup "PCIE_VMAP_LP" ( menuitem "PCIE0_CORE_VMAP_LP_MMRS" "per , ""PCIE_VMAP_LP,PCIE0_CORE_VMAP_LP_MMRS""" menuitem "PCIE1_CORE_VMAP_LP_MMRS" "per , ""PCIE_VMAP_LP,PCIE1_CORE_VMAP_LP_MMRS""" menuitem "PCIE2_CORE_VMAP_LP_MMRS" "per , ""PCIE_VMAP_LP,PCIE2_CORE_VMAP_LP_MMRS""" menuitem "PCIE3_CORE_VMAP_LP_MMRS" "per , ""PCIE_VMAP_LP,PCIE3_CORE_VMAP_LP_MMRS""" ) popup "PDMA5_ECC" ( menuitem "PDMA5_REGS" "per , ""PDMA5_ECC,PDMA5_REGS""" ) popup "PI" ( menuitem "COMPUTE_CLUSTER0_CTL_CFG_PI" "per , ""PI,COMPUTE_CLUSTER0_CTL_CFG_PI""" ) popup "PLL0_CFG" ( menuitem "PLL0_CFG" "per , ""PLL0_CFG,PLL0_CFG""" ) popup "PLLCTRL0" ( menuitem "PLLCTRL0" "per , ""PLLCTRL0,PLLCTRL0""" menuitem "WKUP_PLLCTRL0" "per , ""PLLCTRL0,WKUP_PLLCTRL0""" ) popup "PSC" ( menuitem "PSC0" "per , ""PSC,PSC0""" menuitem "WKUP_PSC0" "per , ""PSC,WKUP_PSC0""" ) popup "PSI_L_CFG_PROXY" ( menuitem "MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY" "per , ""PSI_L_CFG_PROXY,MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY""" menuitem "NAVSS0_UDMASS_PSILCFG0_CFG_PROXY" "per , ""PSI_L_CFG_PROXY,NAVSS0_UDMASS_PSILCFG0_CFG_PROXY""" ) popup "RAT" ( menuitem "ARMSS_RAT_CFG" "per , ""RAT,ARMSS_RAT_CFG""" menuitem "MCU_ARMSS_RAT_CFG" "per , ""RAT,MCU_ARMSS_RAT_CFG""" ) popup "RTI" ( menuitem "MCU_RTI0_CFG" "per , ""RTI,MCU_RTI0_CFG""" menuitem "MCU_RTI1_CFG" "per , ""RTI,MCU_RTI1_CFG""" menuitem "RTI0_CFG" "per , ""RTI,RTI0_CFG""" menuitem "RTI15_CFG" "per , ""RTI,RTI15_CFG""" menuitem "RTI16_CFG" "per , ""RTI,RTI16_CFG""" menuitem "RTI1_CFG" "per , ""RTI,RTI1_CFG""" menuitem "RTI24_CFG" "per , ""RTI,RTI24_CFG""" menuitem "RTI25_CFG" "per , ""RTI,RTI25_CFG""" menuitem "RTI28_CFG" "per , ""RTI,RTI28_CFG""" menuitem "RTI29_CFG" "per , ""RTI,RTI29_CFG""" menuitem "RTI30_CFG" "per , ""RTI,RTI30_CFG""" menuitem "RTI31_CFG" "per , ""RTI,RTI31_CFG""" ) popup "SEC_MMR0_DBG_CTRL" ( menuitem "SEC_MMR0_BOOT_CTRL" "per , ""SEC_MMR0_DBG_CTRL,SEC_MMR0_BOOT_CTRL""" menuitem "SEC_MMR0_DBG_CTRL" "per , ""SEC_MMR0_DBG_CTRL,SEC_MMR0_DBG_CTRL""" ) popup "Spinlock" ( menuitem "SPINLOCK" "per , ""Spinlock,SPINLOCK""" ) popup "Time_Sync_Routers" ( menuitem "CMPEVENT_INTRTR0_INTR_ROUTER_CFG" "per , ""Time_Sync_Routers,CMPEVENT_INTRTR0_INTR_ROUTER_CFG""" menuitem "TIMESYNC_INTRTR0_INTR_ROUTER_CFG" "per , ""Time_Sync_Routers,TIMESYNC_INTRTR0_INTR_ROUTER_CFG""" ) popup "TIMERMGR_CFG_CFG" ( menuitem "NAVSS0_TIMERMGR0_CFG" "per , ""TIMERMGR_CFG_CFG,NAVSS0_TIMERMGR0_CFG""" menuitem "NAVSS0_TIMERMGR1_CFG" "per , ""TIMERMGR_CFG_CFG,NAVSS0_TIMERMGR1_CFG""" ) popup "TIMERMGR_CFG_OES" ( menuitem "NAVSS0_TIMERMGR0_CFG_OES" "per , ""TIMERMGR_CFG_OES,NAVSS0_TIMERMGR0_CFG_OES""" menuitem "NAVSS0_TIMERMGR1_CFG_OES" "per , ""TIMERMGR_CFG_OES,NAVSS0_TIMERMGR1_CFG_OES""" ) popup "TIMERMGR_CFG_TIMERS" ( menuitem "NAVSS0_TIMERMGR0_CFG_TIMERS" "per , ""TIMERMGR_CFG_TIMERS,NAVSS0_TIMERMGR0_CFG_TIMERS""" menuitem "NAVSS0_TIMERMGR1_CFG_TIMERS" "per , ""TIMERMGR_CFG_TIMERS,NAVSS0_TIMERMGR1_CFG_TIMERS""" ) popup "Timers" ( menuitem "MCU_TIMER0_CFG" "per , ""Timers,MCU_TIMER0_CFG""" menuitem "MCU_TIMER1_CFG" "per , ""Timers,MCU_TIMER1_CFG""" menuitem "MCU_TIMER2_CFG" "per , ""Timers,MCU_TIMER2_CFG""" menuitem "MCU_TIMER3_CFG" "per , ""Timers,MCU_TIMER3_CFG""" menuitem "MCU_TIMER4_CFG" "per , ""Timers,MCU_TIMER4_CFG""" menuitem "MCU_TIMER5_CFG" "per , ""Timers,MCU_TIMER5_CFG""" menuitem "MCU_TIMER6_CFG" "per , ""Timers,MCU_TIMER6_CFG""" menuitem "MCU_TIMER7_CFG" "per , ""Timers,MCU_TIMER7_CFG""" menuitem "MCU_TIMER8_CFG" "per , ""Timers,MCU_TIMER8_CFG""" menuitem "MCU_TIMER9_CFG" "per , ""Timers,MCU_TIMER9_CFG""" menuitem "TIMER0_CFG" "per , ""Timers,TIMER0_CFG""" menuitem "TIMER10_CFG" "per , ""Timers,TIMER10_CFG""" menuitem "TIMER11_CFG" "per , ""Timers,TIMER11_CFG""" menuitem "TIMER12_CFG" "per , ""Timers,TIMER12_CFG""" menuitem "TIMER13_CFG" "per , ""Timers,TIMER13_CFG""" menuitem "TIMER14_CFG" "per , ""Timers,TIMER14_CFG""" menuitem "TIMER15_CFG" "per , ""Timers,TIMER15_CFG""" menuitem "TIMER16_CFG" "per , ""Timers,TIMER16_CFG""" menuitem "TIMER17_CFG" "per , ""Timers,TIMER17_CFG""" menuitem "TIMER18_CFG" "per , ""Timers,TIMER18_CFG""" menuitem "TIMER19_CFG" "per , ""Timers,TIMER19_CFG""" menuitem "TIMER1_CFG" "per , ""Timers,TIMER1_CFG""" menuitem "TIMER2_CFG" "per , ""Timers,TIMER2_CFG""" menuitem "TIMER3_CFG" "per , ""Timers,TIMER3_CFG""" menuitem "TIMER4_CFG" "per , ""Timers,TIMER4_CFG""" menuitem "TIMER5_CFG" "per , ""Timers,TIMER5_CFG""" menuitem "TIMER6_CFG" "per , ""Timers,TIMER6_CFG""" menuitem "TIMER7_CFG" "per , ""Timers,TIMER7_CFG""" menuitem "TIMER8_CFG" "per , ""Timers,TIMER8_CFG""" menuitem "TIMER9_CFG" "per , ""Timers,TIMER9_CFG""" ) popup "UART" ( menuitem "MCU_UART0" "per , ""UART,MCU_UART0""" menuitem "UART0" "per , ""UART,UART0""" menuitem "UART1" "per , ""UART,UART1""" menuitem "UART2" "per , ""UART,UART2""" menuitem "UART3" "per , ""UART,UART3""" menuitem "UART4" "per , ""UART,UART4""" menuitem "UART5" "per , ""UART,UART5""" menuitem "UART6" "per , ""UART,UART6""" menuitem "UART7" "per , ""UART,UART7""" menuitem "UART8" "per , ""UART,UART8""" menuitem "UART9" "per , ""UART,UART9""" menuitem "WKUP_UART0" "per , ""UART,WKUP_UART0""" ) popup "UDMASS_INTA0_CFG" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG" "per , ""UDMASS_INTA0_CFG,MCU_NAVSS0_UDMASS_INTA0_CFG""" menuitem "NAVSS0_UDMASS_INTA0_CFG" "per , ""UDMASS_INTA0_CFG,NAVSS0_UDMASS_INTA0_CFG""" ) popup "UDMASS_INTA0_CFG_GCNTCFG" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG" "per , ""UDMASS_INTA0_CFG_GCNTCFG,MCU_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG""" menuitem "NAVSS0_UDMASS_INTA0_CFG_GCNTCFG" "per , ""UDMASS_INTA0_CFG_GCNTCFG,NAVSS0_UDMASS_INTA0_CFG_GCNTCFG""" ) popup "UDMASS_INTA0_CFG_GCNTRTI" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_GCNTRTI" "per , ""UDMASS_INTA0_CFG_GCNTRTI,MCU_NAVSS0_UDMASS_INTA0_GCNTRTI""" menuitem "NAVSS0_UDMASS_INTA0_CFG_GCNTRTI" "per , ""UDMASS_INTA0_CFG_GCNTRTI,NAVSS0_UDMASS_INTA0_CFG_GCNTRTI""" ) popup "UDMASS_INTA0_CFG_IMAP" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP" "per , ""UDMASS_INTA0_CFG_IMAP,MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP""" menuitem "NAVSS0_UDMASS_INTA0_CFG_IMAP" "per , ""UDMASS_INTA0_CFG_IMAP,NAVSS0_UDMASS_INTA0_CFG_IMAP""" ) popup "UDMASS_INTA0_CFG_INTR" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_INTR" "per , ""UDMASS_INTA0_CFG_INTR,MCU_NAVSS0_UDMASS_INTA0_CFG_INTR""" menuitem "NAVSS0_UDMASS_INTA0_CFG_INTR" "per , ""UDMASS_INTA0_CFG_INTR,NAVSS0_UDMASS_INTA0_CFG_INTR""" ) popup "UDMASS_INTA0_CFG_L2G" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_L2G" "per , ""UDMASS_INTA0_CFG_L2G,MCU_NAVSS0_UDMASS_INTA0_CFG_L2G""" menuitem "NAVSS0_UDMASS_INTA0_CFG_L2G" "per , ""UDMASS_INTA0_CFG_L2G,NAVSS0_UDMASS_INTA0_CFG_L2G""" ) popup "UDMASS_INTA0_CFG_MCAST" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST" "per , ""UDMASS_INTA0_CFG_MCAST,MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST""" menuitem "NAVSS0_UDMASS_INTA0_CFG_MCAST" "per , ""UDMASS_INTA0_CFG_MCAST,NAVSS0_UDMASS_INTA0_CFG_MCAST""" ) popup "UDMASS_RINGACC0_ISC_ISC" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC" "per , ""UDMASS_RINGACC0_ISC_ISC,MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC""" menuitem "NAVSS0_UDMASS_RINGACC0_ISC_ISC" "per , ""UDMASS_RINGACC0_ISC_ISC,NAVSS0_UDMASS_RINGACC0_ISC_ISC""" ) popup "UDMASS_UDMAP0_CFG" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG" "per , ""UDMASS_UDMAP0_CFG,MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG" "per , ""UDMASS_UDMAP0_CFG,NAVSS0_UDMASS_UDMAP0_CFG""" ) popup "UDMASS_UDMAP0_CFG_RCHAN" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP0_RCHAN" "per , ""UDMASS_UDMAP0_CFG_RCHAN,MCU_NAVSS0_UDMASS_UDMAP0_RCHAN""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG_RCHAN" "per , ""UDMASS_UDMAP0_CFG_RCHAN,NAVSS0_UDMASS_UDMAP0_CFG_RCHAN""" ) popup "UDMASS_UDMAP0_CFG_RCHANRT" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" "per , ""UDMASS_UDMAP0_CFG_RCHANRT,MCU_NAVSS0_UDMASS_UDMAP_RCHANRT""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT" "per , ""UDMASS_UDMAP0_CFG_RCHANRT,NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT""" ) popup "UDMASS_UDMAP0_CFG_RFLOW" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW" "per , ""UDMASS_UDMAP0_CFG_RFLOW,MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG_RFLOW" "per , ""UDMASS_UDMAP0_CFG_RFLOW,NAVSS0_UDMASS_UDMAP0_CFG_RFLOW""" ) popup "UDMASS_UDMAP0_CFG_TCHAN" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP0_TCHAN" "per , ""UDMASS_UDMAP0_CFG_TCHAN,MCU_NAVSS0_UDMASS_UDMAP0_TCHAN""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG_TCHAN" "per , ""UDMASS_UDMAP0_CFG_TCHAN,NAVSS0_UDMASS_UDMAP0_CFG_TCHAN""" ) popup "UDMASS_UDMAP0_CFG_TCHANRT" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" "per , ""UDMASS_UDMAP0_CFG_TCHANRT,MCU_NAVSS0_UDMASS_UDMAP_TCHANRT""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT" "per , ""UDMASS_UDMAP0_CFG_TCHANRT,NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT""" ) popup "UFS0_HCLK_ECC_AGGR_CFG" ( menuitem "UFS0_HCLK_ECC_AGGR_CFG" "per , ""UFS0_HCLK_ECC_AGGR_CFG,UFS0_HCLK_ECC_AGGR_CFG""" ) popup "UFS0_IPS_TCLK_ERR_INJ_CFG" ( menuitem "UFS0_IPS_TCLK_ERR_INJ_CFG" "per , ""UFS0_IPS_TCLK_ERR_INJ_CFG,UFS0_IPS_TCLK_ERR_INJ_CFG""" ) popup "UFS0_P2A_WRAP_CFG_VBP_UFSHCI" ( menuitem "UFS0_P2A_WRAP_CFG_VBP_UFSHCI" "per , ""UFS0_P2A_WRAP_CFG_VBP_UFSHCI,UFS0_P2A_WRAP_CFG_VBP_UFSHCI""" ) popup "UFS0_SYSCFG_SS_CFG" ( menuitem "UFS0_SYSCFG_SS_CFG" "per , ""UFS0_SYSCFG_SS_CFG,UFS0_SYSCFG_SS_CFG""" ) popup "USB3P0SS_MMR_MMRVBP_USBSS_CMN" ( menuitem "USB0_MMR_MMRVBP_USBSS_CMN" "per , ""USB3P0SS_MMR_MMRVBP_USBSS_CMN,USB0_MMR_MMRVBP_USBSS_CMN""" menuitem "USB1_MMR_MMRVBP_USBSS_CMN" "per , ""USB3P0SS_MMR_MMRVBP_USBSS_CMN,USB1_MMR_MMRVBP_USBSS_CMN""" ) popup "USB_ECC_AGGR_CFG" ( menuitem "USB0_ECC_AGGR" "per , ""USB_ECC_AGGR_CFG,USB0_ECC_AGGR""" menuitem "USB1_ECC_AGGR" "per , ""USB_ECC_AGGR_CFG,USB1_ECC_AGGR""" ) popup "USB_RAMS_INJ_CFG" ( menuitem "USB0_RAMS_INJ_CFG" "per , ""USB_RAMS_INJ_CFG,USB0_RAMS_INJ_CFG""" menuitem "USB1_RAMS_INJ_CFG" "per , ""USB_RAMS_INJ_CFG,USB1_RAMS_INJ_CFG""" ) popup "VIM" ( menuitem "ARMSS_VIC_CFG" "per , ""VIM,ARMSS_VIC_CFG""" menuitem "MCU_ARMSS_VIC_CFG" "per , ""VIM,MCU_ARMSS_VIC_CFG""" ) popup "VIRTID_CFG_MMRS" ( menuitem "NAV_DDR0_VIRTID_CFG_MMRS" "per , ""VIRTID_CFG_MMRS,NAV_DDR0_VIRTID_CFG_MMRS""" menuitem "NAV_DDR1_VIRTID_CFG_MMRS" "per , ""VIRTID_CFG_MMRS,NAV_DDR1_VIRTID_CFG_MMRS""" menuitem "NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS" "per , ""VIRTID_CFG_MMRS,NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS""" ) popup "VPAC_CP_INTD" ( menuitem "VPAC0_CP_INTD_CFG_INTD_CFG" "per , ""VPAC_CP_INTD,VPAC0_CP_INTD_CFG_INTD_CFG""" ) popup "VPAC_CTSET" ( menuitem "VPAC0_CTSET2_WRAP_CFG_CTSET2_CFG" "per , ""VPAC_CTSET,VPAC0_CTSET2_WRAP_CFG_CTSET2_CFG""" ) popup "VPAC_ECC_AGGR" ( menuitem "VPAC0_KSDW_ECC_AGGR_CFG" "per , ""VPAC_ECC_AGGR,VPAC0_KSDW_ECC_AGGR_CFG""" ) popup "VPAC_HTS" ( menuitem "VPAC0_HTS_S_VBUSP" "per , ""VPAC_HTS,VPAC0_HTS_S_VBUSP""" ) popup "VPAC_LDC" ( menuitem "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP" "per , ""VPAC_LDC,VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP""" ) popup "VPAC_LDC_LSE" ( menuitem "VPAC0_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP" "per , ""VPAC_LDC_LSE,VPAC0_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP""" ) popup "VPAC_LDC_MEMCFG_LOOP_CBCR" ( menuitem "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_CBCR_VBUSPI_CBCR_MEM" "per , ""VPAC_LDC_MEMCFG_LOOP_CBCR,VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_CBCR_VBUSPI_CBCR_MEM""" ) popup "VPAC_LDC_MEMCFG_LOOP_MESH" ( menuitem "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_MESH_VBUSPI_MESH_MEM" "per , ""VPAC_LDC_MEMCFG_LOOP_MESH,VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_MESH_VBUSPI_MESH_MEM""" ) popup "VPAC_LDC_MEMCFG_LOOP_Y" ( menuitem "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_Y_VBUSPI_Y_MEM" "per , ""VPAC_LDC_MEMCFG_LOOP_Y,VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_Y_VBUSPI_Y_MEM""" ) popup "VPAC_LDC_PIXWRINTF_DUALC_LUT" ( menuitem "VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALC_LUTCFG_DUALC_LUT" "per , ""VPAC_LDC_PIXWRINTF_DUALC_LUT,VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALC_LUTCFG_DUALC_LUT""" ) popup "VPAC_LDC_PIXWRINTF_DUALY_LUT" ( menuitem "VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALY_LUTCFG_DUALY_LUT" "per , ""VPAC_LDC_PIXWRINTF_DUALY_LUT,VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALY_LUTCFG_DUALY_LUT""" ) popup "VPAC_MSC_CORE" ( menuitem "VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP" "per , ""VPAC_MSC_CORE,VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP""" ) popup "VPAC_MSC_LSE" ( menuitem "VPAC0_PAR_VPAC_MSC_CFG_VP_LSE_CFG_VP" "per , ""VPAC_MSC_LSE,VPAC0_PAR_VPAC_MSC_CFG_VP_LSE_CFG_VP""" ) popup "VPAC_NF_CORE" ( menuitem "VPAC0_PAR_VPAC_NF_S_VBUSP_MMR_VBUSP_NF_CFG" "per , ""VPAC_NF_CORE,VPAC0_PAR_VPAC_NF_S_VBUSP_MMR_VBUSP_NF_CFG""" ) popup "VPAC_NF_LSE" ( menuitem "VPAC0_PAR_VPAC_NF_S_VBUSP_VPAC_NF_LSE_CFG_VP" "per , ""VPAC_NF_LSE,VPAC0_PAR_VPAC_NF_S_VBUSP_VPAC_NF_LSE_CFG_VP""" ) popup "VPAC_TOP" ( menuitem "VPAC0_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS" "per , ""VPAC_TOP,VPAC0_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS""" ) popup "VPAC_UTC0_RT_DRU" ( menuitem "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU" "per , ""VPAC_UTC0_RT_DRU,VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU""" ) popup "VPAC_UTC0_RT_DRU_CAUSE" ( menuitem "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE" "per , ""VPAC_UTC0_RT_DRU_CAUSE,VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE""" ) popup "VPAC_UTC0_RT_DRU_CHATOMIC_DEBUG" ( menuitem "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG" "per , ""VPAC_UTC0_RT_DRU_CHATOMIC_DEBUG,VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG""" ) popup "VPAC_UTC0_RT_DRU_CHNRT" ( menuitem "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT" "per , ""VPAC_UTC0_RT_DRU_CHNRT,VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT""" ) popup "VPAC_UTC0_RT_DRU_CHRT" ( menuitem "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHRT" "per , ""VPAC_UTC0_RT_DRU_CHRT,VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHRT""" ) popup "VPAC_UTC0_RT_DRU_QUEUE" ( menuitem "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE" "per , ""VPAC_UTC0_RT_DRU_QUEUE,VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE""" ) popup "VPAC_UTC0_RT_DRU_SET" ( menuitem "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_SET" "per , ""VPAC_UTC0_RT_DRU_SET,VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_SET""" ) popup "VPAC_UTC1_NRT_DRU" ( menuitem "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU" "per , ""VPAC_UTC1_NRT_DRU,VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU""" ) popup "VPAC_UTC1_NRT_DRU_CAUSE" ( menuitem "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CAUSE" "per , ""VPAC_UTC1_NRT_DRU_CAUSE,VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CAUSE""" ) popup "VPAC_UTC1_NRT_DRU_CHATOMIC_DEBUG" ( menuitem "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG" "per , ""VPAC_UTC1_NRT_DRU_CHATOMIC_DEBUG,VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG""" ) popup "VPAC_UTC1_NRT_DRU_CHNRT" ( menuitem "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHNRT" "per , ""VPAC_UTC1_NRT_DRU_CHNRT,VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHNRT""" ) popup "VPAC_UTC1_NRT_DRU_CHRT" ( menuitem "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHRT" "per , ""VPAC_UTC1_NRT_DRU_CHRT,VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHRT""" ) popup "VPAC_UTC1_NRT_DRU_QUEUE" ( menuitem "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_QUEUE" "per , ""VPAC_UTC1_NRT_DRU_QUEUE,VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_QUEUE""" ) popup "VPAC_UTC1_NRT_DRU_SET" ( menuitem "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_SET" "per , ""VPAC_UTC1_NRT_DRU_SET,VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_SET""" ) popup "VPAC_VISS_ECC_AGGR" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_KSDW_ECC_AGGR_CFG" "per , ""VPAC_VISS_ECC_AGGR,VPAC0_PAR_VPAC_VISS0_S_VBUSP_KSDW_ECC_AGGR_CFG""" ) popup "VPAC_VISS_FCP_CFA" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA" "per , ""VPAC_VISS_FCP_CFA,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA""" ) popup "VPAC_VISS_FCP_EE" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_EE_VBUSP_FLEXEE" "per , ""VPAC_VISS_FCP_EE,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_EE_VBUSP_FLEXEE""" ) popup "VPAC_VISS_FCP_FCC" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC" "per , ""VPAC_VISS_FCP_FCC,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC""" ) popup "VPAC_VISS_FCP_FCC_C8G8" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_C8G8" "per , ""VPAC_VISS_FCP_FCC_C8G8,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_C8G8""" ) popup "VPAC_VISS_FCP_FCC_CONTRASTC1" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC1" "per , ""VPAC_VISS_FCP_FCC_CONTRASTC1,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC1""" ) popup "VPAC_VISS_FCP_FCC_CONTRASTC2" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC2" "per , ""VPAC_VISS_FCP_FCC_CONTRASTC2,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC2""" ) popup "VPAC_VISS_FCP_FCC_CONTRASTC3" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC3" "per , ""VPAC_VISS_FCP_FCC_CONTRASTC3,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC3""" ) popup "VPAC_VISS_FCP_FCC_HIST" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_HIST" "per , ""VPAC_VISS_FCP_FCC_HIST,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_HIST""" ) popup "VPAC_VISS_FCP_FCC_LINE" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_LINE" "per , ""VPAC_VISS_FCP_FCC_LINE,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_LINE""" ) popup "VPAC_VISS_FCP_FCC_S8B8" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_S8B8" "per , ""VPAC_VISS_FCP_FCC_S8B8,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_S8B8""" ) popup "VPAC_VISS_FCP_FCC_Y8R8" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_Y8R8" "per , ""VPAC_VISS_FCP_FCC_Y8R8,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_Y8R8""" ) popup "VPAC_VISS_GLBCE_STATMEM" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_STATMEM_CFG_GLBCE_STATMEM" "per , ""VPAC_VISS_GLBCE_STATMEM,VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_STATMEM_CFG_GLBCE_STATMEM""" ) popup "VPAC_VISS_GLBCE_TOP" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_CFG_GLBCE" "per , ""VPAC_VISS_GLBCE_TOP,VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_CFG_GLBCE""" ) popup "VPAC_VISS_LSE" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VPAC_VISS_LSE_CFG_VP" "per , ""VPAC_VISS_LSE,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VPAC_VISS_LSE_CFG_VP""" ) popup "VPAC_VISS_NSF4V" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MMR_VBUSP_NSF4VCORE" "per , ""VPAC_VISS_NSF4V,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MMR_VBUSP_NSF4VCORE""" ) popup "VPAC_VISS_NSF4V_RAM" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MEM_MMRRAM_VBUSP_MMR_RAM" "per , ""VPAC_VISS_NSF4V_RAM,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MEM_MMRRAM_VBUSP_MMR_RAM""" ) popup "VPAC_VISS_RAWFE" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_MMR_S_VBUSP_RAWFE_CFG" "per , ""VPAC_VISS_RAWFE,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_MMR_S_VBUSP_RAWFE_CFG""" ) popup "VPAC_VISS_RAWFE_H3A" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_CFG_RAWFE_H3A_CFG" "per , ""VPAC_VISS_RAWFE_H3A,VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_CFG_RAWFE_H3A_CFG""" ) popup "VPAC_VISS_TOP" ( menuitem "VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP" "per , ""VPAC_VISS_TOP,VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP""" ) popup "VPFE" ( menuitem "VPFE0_MMRS" "per , ""VPFE,VPFE0_MMRS""" menuitem "VPFE0_VPFE" "per , ""VPFE,VPFE0_VPFE""" ) popup "WKUP_CTRL_MMR0" ( menuitem "WKUP_CTRL_MMR0" "per , ""WKUP_CTRL_MMR0,WKUP_CTRL_MMR0""" ) popup "WKUP_GPIOMUX_INTRTR0" ( menuitem "C66SS0_INTROUTER0_INTR_ROUTER_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,C66SS0_INTROUTER0_INTR_ROUTER_CFG""" menuitem "C66SS1_INTROUTER0_INTR_ROUTER_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,C66SS1_INTROUTER0_INTR_ROUTER_CFG""" menuitem "GPIOMUX_INTRTR0_INTR_ROUTER_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,GPIOMUX_INTRTR0_INTR_ROUTER_CFG""" menuitem "MAIN2MCU_LVL_INTRTR0_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,MAIN2MCU_LVL_INTRTR0_CFG""" menuitem "MAIN2MCU_PLS_INTRTR0_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,MAIN2MCU_PLS_INTRTR0_CFG""" menuitem "R5FSS0_INTROUTER0_INTR_ROUTER_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,R5FSS0_INTROUTER0_INTR_ROUTER_CFG""" menuitem "R5FSS1_INTROUTER0_INTR_ROUTER_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,R5FSS1_INTROUTER0_INTR_ROUTER_CFG""" menuitem "WKUP_GPIOMUX_INTRTR0_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,WKUP_GPIOMUX_INTRTR0_CFG""" ) popup "WKUP_VTM0" ( menuitem "WKUP_VTM0_ECCAGGR_CFG" "per , ""WKUP_VTM0,WKUP_VTM0_ECCAGGR_CFG""" menuitem "WKUP_VTM0_MMR_VBUSP_CFG1" "per , ""WKUP_VTM0,WKUP_VTM0_MMR_VBUSP_CFG1""" menuitem "WKUP_VTM0_MMR_VBUSP_CFG2" "per , ""WKUP_VTM0,WKUP_VTM0_MMR_VBUSP_CFG2""" ) ) ) else ( popup "PRU_ICSSG_CFG" ( menuitem "PRU_ICSSG0_PR1_CFG_SLV" "per , ""PRU_ICSSG_CFG,PRU_ICSSG0_PR1_CFG_SLV""" menuitem "PRU_ICSSG1_PR1_CFG_SLV" "per , ""PRU_ICSSG_CFG,PRU_ICSSG1_PR1_CFG_SLV""" ) popup "PRU_ICSSG_DRAM" ( menuitem "PRU_ICSSG0_DRAM0_SLV_RAM" "per , ""PRU_ICSSG_DRAM,PRU_ICSSG0_DRAM0_SLV_RAM""" menuitem "PRU_ICSSG0_DRAM1_SLV_RAM" "per , ""PRU_ICSSG_DRAM,PRU_ICSSG0_DRAM1_SLV_RAM""" menuitem "PRU_ICSSG1_DRAM0_SLV_RAM" "per , ""PRU_ICSSG_DRAM,PRU_ICSSG1_DRAM0_SLV_RAM""" menuitem "PRU_ICSSG1_DRAM1_SLV_RAM" "per , ""PRU_ICSSG_DRAM,PRU_ICSSG1_DRAM1_SLV_RAM""" ) popup "PRU_ICSSG_ECAP0" ( menuitem "PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV" "per , ""PRU_ICSSG_ECAP0,PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV""" menuitem "PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV" "per , ""PRU_ICSSG_ECAP0,PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV""" ) popup "PRU_ICSSG_ECC_AGGR" ( menuitem "PRU_ICSSG0_ECC_AGGR" "per , ""PRU_ICSSG_ECC_AGGR,PRU_ICSSG0_ECC_AGGR""" menuitem "PRU_ICSSG1_ECC_AGGR" "per , ""PRU_ICSSG_ECC_AGGR,PRU_ICSSG1_ECC_AGGR""" ) popup "PRU_ICSSG_IEP" ( menuitem "PRU_ICSSG1_IEP$1" "per , ""PRU_ICSSG_IEP,PRU_ICSSG1_IEP$1""" menuitem "PRU_ICSSG0_IEP$1" "per , ""PRU_ICSSG_IEP,PRU_ICSSG0_IEP$1""" ) popup "PRU_ICSSG_INTC" ( menuitem "PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV" "per , ""PRU_ICSSG_INTC,PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV""" menuitem "PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV" "per , ""PRU_ICSSG_INTC,PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV""" ) popup "PRU_ICSSG_MDIO" ( menuitem "PRU_ICSSG0_PR1_MDIO_V1P7_MDIO" "per , ""PRU_ICSSG_MDIO,PRU_ICSSG0_PR1_MDIO_V1P7_MDIO""" menuitem "PRU_ICSSG1_PR1_MDIO_V1P7_MDIO" "per , ""PRU_ICSSG_MDIO,PRU_ICSSG1_PR1_MDIO_V1P7_MDIO""" ) popup "PRU_ICSSG_MII_G_RT" ( menuitem "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" "per , ""PRU_ICSSG_MII_G_RT,PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G""" menuitem "PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" "per , ""PRU_ICSSG_MII_G_RT,PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G""" ) popup "PRU_ICSSG_MII_RT" ( menuitem "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG" "per , ""PRU_ICSSG_MII_RT,PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG""" menuitem "PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG" "per , ""PRU_ICSSG_MII_RT,PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG""" ) popup "PRU_ICSSG_PROTECT" ( menuitem "PRU_ICSSG0_PR1_PROT_SLV" "per , ""PRU_ICSSG_PROTECT,PRU_ICSSG0_PR1_PROT_SLV""" menuitem "PRU_ICSSG1_PR1_PROT_SLV" "per , ""PRU_ICSSG_PROTECT,PRU_ICSSG1_PR1_PROT_SLV""" ) popup "PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL" ( menuitem "PRU_ICSSG0_PR1_PDSP0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_PDSP0_IRAM""" menuitem "PRU_ICSSG0_PR1_PDSP1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_PDSP1_IRAM""" menuitem "PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM""" menuitem "PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM""" menuitem "PRU_ICSSG0_PR1_TX_PDSP0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_TX_PDSP0_IRAM""" menuitem "PRU_ICSSG0_PR1_TX_PDSP1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_TX_PDSP1_IRAM""" menuitem "PRU_ICSSG1_PR1_PDSP0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_PDSP0_IRAM""" menuitem "PRU_ICSSG1_PR1_PDSP1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_PDSP1_IRAM""" menuitem "PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM""" menuitem "PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM""" menuitem "PRU_ICSSG1_PR1_TX_PDSP0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_TX_PDSP0_IRAM""" menuitem "PRU_ICSSG1_PR1_TX_PDSP1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_TX_PDSP1_IRAM""" ) popup "PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG" ( menuitem "PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG""" menuitem "PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG""" menuitem "PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG""" menuitem "PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG""" menuitem "PRU_ICSSG0_PR1_TX_PDSP0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_TX_PDSP0_IRAM_DEBUG""" menuitem "PRU_ICSSG0_PR1_TX_PDSP1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_TX_PDSP1_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_TX_PDSP0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_TX_PDSP0_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_TX_PDSP1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_TX_PDSP1_IRAM_DEBUG""" ) popup "PRU_ICSSG_RAM" ( menuitem "PRU_ICSSG0_RAM_SLV_RAM" "per , ""PRU_ICSSG_RAM,PRU_ICSSG0_RAM_SLV_RAM""" menuitem "PRU_ICSSG1_RAM_SLV_RAM" "per , ""PRU_ICSSG_RAM,PRU_ICSSG1_RAM_SLV_RAM""" ) popup "PRU_ICSSG_RAT_SLICE" ( menuitem "PRU_ICSSG0_RAT_SLICE0_CFG" "per , ""PRU_ICSSG_RAT_SLICE,PRU_ICSSG0_RAT_SLICE0_CFG""" menuitem "PRU_ICSSG0_RAT_SLICE1_CFG" "per , ""PRU_ICSSG_RAT_SLICE,PRU_ICSSG0_RAT_SLICE1_CFG""" menuitem "PRU_ICSSG1_RAT_SLICE0_CFG" "per , ""PRU_ICSSG_RAT_SLICE,PRU_ICSSG1_RAT_SLICE0_CFG""" menuitem "PRU_ICSSG1_RAT_SLICE1_CFG" "per , ""PRU_ICSSG_RAT_SLICE,PRU_ICSSG1_RAT_SLICE1_CFG""" ) popup "PRU_ICSSG_SGMII" ( menuitem "PRU_ICSSG1_PR1_MII_RT_PR1_SGMII0_CFG_SGMII0" "per , ""PRU_ICSSG_SGMII,PRU_ICSSG1_PR1_MII_RT_PR1_SGMII0_CFG_SGMII0""" menuitem "PRU_ICSSG1_PR1_MII_RT_PR1_SGMII1_CFG_SGMII1" "per , ""PRU_ICSSG_SGMII,PRU_ICSSG1_PR1_MII_RT_PR1_SGMII1_CFG_SGMII1""" ) popup "PRU_ICSSG_TASKS_MGR_PRU_RTU" ( menuitem "PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR" "per , ""PRU_ICSSG_TASKS_MGR_PRU_RTU,PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR""" menuitem "PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR" "per , ""PRU_ICSSG_TASKS_MGR_PRU_RTU,PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR""" menuitem "PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR" "per , ""PRU_ICSSG_TASKS_MGR_PRU_RTU,PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR""" menuitem "PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR" "per , ""PRU_ICSSG_TASKS_MGR_PRU_RTU,PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR""" menuitem "PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR" "per , ""PRU_ICSSG_TASKS_MGR_PRU_RTU,PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR""" menuitem "PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR" "per , ""PRU_ICSSG_TASKS_MGR_PRU_RTU,PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR""" menuitem "PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR" "per , ""PRU_ICSSG_TASKS_MGR_PRU_RTU,PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR""" menuitem "PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR" "per , ""PRU_ICSSG_TASKS_MGR_PRU_RTU,PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR""" ) popup "PRU_ICSSG_UART0" ( menuitem "PRU_ICSSG0_PR1_ICSS_UART_UART_SLV" "per , ""PRU_ICSSG_UART0,PRU_ICSSG0_PR1_ICSS_UART_UART_SLV""" menuitem "PRU_ICSSG1_PR1_ICSS_UART_UART_SLV" "per , ""PRU_ICSSG_UART0,PRU_ICSSG1_PR1_ICSS_UART_UART_SLV""" ) ) ) )