; -------------------------------------------------------------------------------- ; @Title: tbd. ; @Props: Released ; @Author: - ; @Changelog: ; @Manufacturer: ; @Core: ; @Chip: ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: mendra72xapp.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-A15MPCore)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A15MPCore),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A15MPCore),System Control and Configuration""" menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A15MPCore),Memory Management Unit""" menuitem "[:chip]Virtualization Extensions" "per , ""Core Registers (Cortex-A15MPCore),Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A15MPCore),Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A15MPCore),System Performance Monitor""" menuitem "[:chip]System Timer Register" "per , ""Core Registers (Cortex-A15MPCore),System Timer Register""" separator menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A15MPCore),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A15MPCore),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A15MPCore),Watchpoint Control Registers""" ) separator menuitem "PRCM" "PER , ""PRCM""" menuitem "Cortex_A15_MPU_Subsystem" "PER , ""Cortex_A15_MPU_Subsystem""" menuitem "DSP_Subsystem" "PER , ""DSP_Subsystem""" menuitem "IVA_Overview" "PER , ""IVA_Overview""" menuitem "IVA_Video_Direct_Memory_Access" "PER , ""IVA_Video_Direct_Memory_Access""" menuitem "IVA_Synchronization_Box" "PER , ""IVA_Synchronization_Box""" menuitem "IVA_Load_and_Store_Engine" "PER , ""IVA_Load_and_Store_Engine""" menuitem "IVA_Motion_Estimation" "PER , ""IVA_Motion_Estimation""" menuitem "IVA_Intra_Prediction_Estimation" "PER , ""IVA_Intra_Prediction_Estimation""" menuitem "IVA_Loop_Filter" "PER , ""IVA_Loop_Filter""" menuitem "IVA_Motion_Compensation" "PER , ""IVA_Motion_Compensation""" menuitem "IVA_CALCulation_Engine_3" "PER , ""IVA_CALCulation_Engine_3""" menuitem "IVA_Entropy_Coder_Decoder" "PER , ""IVA_Entropy_Coder_Decoder""" menuitem "Dual_Cortex_M4_IPU_Subsystem" "PER , ""Dual_Cortex_M4_IPU_Subsystem""" menuitem "CAMSS" "PER , ""CAMSS""" menuitem "VIP" "PER , ""VIP""" menuitem "VPE" "PER , ""VPE""" menuitem "Display_Subsystem_Overview" "PER , ""Display_Subsystem_Overview""" menuitem "Display_Controller" "PER , ""Display_Controller""" menuitem "GPU" "PER , ""GPU""" menuitem "BB2D" "PER , ""BB2D""" menuitem "L3_MAIN_Interconnect" "PER , ""L3_MAIN_Interconnect""" menuitem "L4_Interconnects" "PER , ""L4_Interconnects""" menuitem "Dynamic_Memory_Manager" "PER , ""Dynamic_Memory_Manager""" menuitem "EMIF_Controller" "PER , ""EMIF_Controller""" menuitem "General_Purpose_Memory_Controller" "PER , ""General_Purpose_Memory_Controller""" menuitem "Error_Location_Module" "PER , ""Error_Location_Module""" menuitem "On_Chip_Memory_OCM_Subsystem" "PER , ""On_Chip_Memory_OCM_Subsystem""" menuitem "System_DMA" "PER , ""System_DMA""" menuitem "Control_Module" "PER , ""Control_Module""" menuitem "Mailbox" "PER , ""Mailbox""" menuitem "MMU" "PER , ""MMU""" menuitem "Spinlock" "PER , ""Spinlock""" menuitem "General_Purpose_Timers" "PER , ""General_Purpose_Timers""" menuitem "Watchdog_Timers" "PER , ""Watchdog_Timers""" menuitem "_32_kHz_Synchronized_Timer_COUNTER_32K_" "PER , ""_32_kHz_Synchronized_Timer_COUNTER_32K_""" menuitem "RTC_Overview" "PER , ""RTC_Overview""" menuitem "Multimaster_High_Speed_I2C_Controller" "PER , ""Multimaster_High_Speed_I2C_Controller""" menuitem "HDQ_1_Wire" "PER , ""HDQ_1_Wire""" menuitem "UART_IrDA_CIR" "PER , ""UART_IrDA_CIR""" menuitem "Multichannel_Serial_Peripheral_Interface" "PER , ""Multichannel_Serial_Peripheral_Interface""" menuitem "Quad_Serial_Peripheral_Interface" "PER , ""Quad_Serial_Peripheral_Interface""" menuitem "Multichannel_Audio_Serial_Ports" "PER , ""Multichannel_Audio_Serial_Ports""" menuitem "SuperSpeed_USB_DRD" "PER , ""SuperSpeed_USB_DRD""" menuitem "SATA_Controller" "PER , ""SATA_Controller""" menuitem "PCIe_Controllers" "PER , ""PCIe_Controllers""" menuitem "DCAN" "PER , ""DCAN""" menuitem "Gigabit_Ethernet_Switch_GMAC_SW" "PER , ""Gigabit_Ethernet_Switch_GMAC_SW""" menuitem "Media_Local_Bus_MLB" "PER , ""Media_Local_Bus_MLB""" menuitem "eMMC_SD_SDIO" "PER , ""eMMC_SD_SDIO""" menuitem "SATA_PHY_Subsystem" "PER , ""SATA_PHY_Subsystem""" menuitem "USB3_PHY_Subsystem" "PER , ""USB3_PHY_Subsystem""" menuitem "PCIe_Shared_PHY_Subsystem" "PER , ""PCIe_Shared_PHY_Subsystem""" menuitem "General_Purpose_Interface" "PER , ""General_Purpose_Interface""" menuitem "Keyboard_Controller" "PER , ""Keyboard_Controller""" menuitem "PWM_Subsystem_Resources" "PER , ""PWM_Subsystem_Resources""" menuitem "VCP" "PER , ""VCP""" menuitem "ATL" "PER , ""ATL""" menuitem "EDMA" "PER , ""EDMA""" ) )