; --------------------------------------------------------------------------------
; @Title: AM/DM37xx Specific Menu
; @Props: Released
; @Author: LEM, SOL, TAT
; @Changelog: 2010-12-22
; @Manufacturer: TI - Texas Instruments
; @Core: Cortex-A8
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menamdm37x.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-A8)"
(
menuitem "[:chip]ID Registers"                          "per , ""Core Registers (Cortex-A8),ID Registers"""
menuitem "[:chip]System Control and Configuration"      "per , ""Core Registers (Cortex-A8),System Control and Configuration"""
menuitem "[:chip]Memory Management Unit"                "per , ""Core Registers (Cortex-A8),Memory Management Unit"""
menuitem "[:chip]Cache Control and Configuration"       "per , ""Core Registers (Cortex-A8),Cache Control and Configuration"""
menuitem "[:chip]L2 Cache Control and Configuration"    "per , ""Core Registers (Cortex-A8),L2 Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor"            "per , ""Core Registers (Cortex-A8),System Performance Monitor"""
menuitem "[:chip]Debug Registers"                       "per , ""Core Registers (Cortex-A8),Debug Registers"""
menuitem "[:chip]Breakpoint Registers"                  "per , ""Core Registers (Cortex-A8),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers"          "per , ""Core Registers (Cortex-A8),Watchpoint Control Registers"""
)
separator
menuitem "PRCM"                                                 "per , ""PRCM (Power Reset and Clock Management)"""
menuitem "Camera ISP"                                           "per , ""Camera ISP"""
menuitem "Display Subsystem"                                    "per , ""Display Subsystem"""
if (cpu()=="DM3730"||cpu()=="AM3715")
(
menuitem "SGX_OCP"                                          "per , ""SGX_OCP (2D/3D Graphics Accelerator)"""
)
menuitem "L3 Interconnect"                                      "per , ""L3 Interconnect"""
menuitem "L4 Interconnect"                                      "per , ""L4 Interconnect"""
menuitem "Memory Subsystem"                                     "per , ""Memory Subsystem"""
menuitem "SDMA"                                                 "per , ""SDMA"""
menuitem "Interrupt Controller"                                 "per , ""Interrupt Controller"""
menuitem "System Control"                                       "per , ""System Control"""
menuitem "Interprocessor Communication"                         "per , ""Interprocessor Communication"""
menuitem "MMU"                                                  "per , ""MMU (Memory Management Unit)"""
menuitem "Timers"                                               "per , ""Timers"""
menuitem "High-Speed I2C Controller"                            "per , ""High-Speed I2C Controller"""
menuitem "HDQ/1-Wire"                                           "per , ""HDQ/1-Wire"""
menuitem "UART/IrDA/CIR"                                        "per , ""UART/IrDA/CIR"""
menuitem "Multichannel SPI"                                     "per , ""Multichannel SPI"""
menuitem "McBSP"                                                "per , ""McBSP (Multi-Channel Buffered Serial Port)"""
menuitem "High-Speed USB Host Subsystem/On-The-Go Controller"   "per , ""High-Speed USB Host Subsystem/On-The-Go Controller"""
menuitem "MMC/SD/SDIO Card Interface"                           "per , ""MMC/SD/SDIO Card Interface"""
menuitem "GPIO"                                                 "per , ""GPIO"""
menuitem "Debug and Emulation"                                  "per , ""Debug and Emulation"""
)
)