; -------------------------------------------------------------------------------- ; @Title: AM65xx Specific Menu ; @Props: Released ; @Author: KOL, KWI, PIW ; @Changelog: 2019-01-09 KOL ; 2019-12-06 KOL ; 2020-02-18 KWI ; 2022-04-25 PIW ; @Manufacturer: TI - Texas Instruments ; @Core: Cortex-A53, Cortex-R5F ; @Chip: AM6526, AM6526-CR7, AM6527-CR7, AM6528, AM6528-CR7, AM6546, DRA804M-CR7 ; AM6546-CR7, AM6548, AM6548-CR7, DRA802M, DRA802M-CR7, DRA804M, AM6527 ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menam65xx.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( separator if (CORENAME()!="PRU") ( if (CORENAME()=="CORTEXA53") ( popup "[:chip]Core Registers (Cortex-A53)" ( menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers""" menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration""" menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit""" menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor""" menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers""" menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface""" separator menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers""" separator menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers""" separator menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers""" menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration""" menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit""" menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor""" menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers""" menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface""" separator menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers""" separator menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers""" separator menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)""" ) ) else ( popup "[:chip]Core Registers (Cortex-R5F)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R5F),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R5F),System Control and Configuration""" menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R5F),MPU Control and Configuration""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R5F),Cache Control and Configuration""" menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R5F),TCM Control and Configuration""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R5F),System Performance Monitor""" separator menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R5F),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R5F),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R5F),Watchpoint Control Registers""" ) ) separator popup "ADC" ( menuitem "MCU_ADC0" "per , ""ADC,MCU_ADC0""" menuitem "MCU_ADC1" "per , ""ADC,MCU_ADC1""" menuitem "MCU_ADC0_ECC" "per , ""ADC,MCU_ADC0_ECC""" menuitem "MCU_ADC1_ECC" "per , ""ADC,MCU_ADC1_ECC""" menuitem "MCU_ADC0_FIFO" "per , ""ADC,MCU_ADC0_FIFO""" menuitem "MCU_ADC1_FIFO" "per , ""ADC,MCU_ADC1_FIFO""" ) menuitem "CALSS" "per , ""CALSS""" menuitem "CAMERARX" "per , ""CAMERARX""" menuitem "CCMR5" "per , ""CCMR5""" menuitem "Compute_Cluster" "per , ""Compute_Cluster""" menuitem "CPU0_ECC_AGGR_CFG_REGS" "per , ""CPU0_ECC_AGGR_CFG_REGS""" menuitem "CPU1_ECC_AGGR_CFG_REGS" "per , ""CPU1_ECC_AGGR_CFG_REGS""" menuitem "CTRL_MMR0" "per , ""CTRL_MMR0""" popup "DCC" ( menuitem "MCU_DCC0" "per , ""DCC,MCU_DCC0""" menuitem "MCU_DCC1" "per , ""DCC,MCU_DCC1""" menuitem "MCU_DCC2" "per , ""DCC,MCU_DCC2""" menuitem "DCC0" "per , ""DCC,DCC0""" menuitem "DCC1" "per , ""DCC,DCC1""" menuitem "DCC2" "per , ""DCC,DCC2""" menuitem "DCC3" "per , ""DCC,DCC3""" menuitem "DCC4" "per , ""DCC,DCC4""" menuitem "DCC5" "per , ""DCC,DCC5""" menuitem "DCC6" "per , ""DCC,DCC6""" menuitem "DCC7" "per , ""DCC,DCC7""" ) menuitem "DDR_Controller" "per , ""DDR_Controller""" menuitem "DDR_PHY" "per , ""DDR_PHY""" menuitem "DDR_Subsystem_Wrapper_Logic" "per , ""DDR_Subsystem_Wrapper_Logic""" menuitem "DRU" "per , ""DRU""" menuitem "DRU_DMA_FW" "per , ""DRU_DMA_FW""" menuitem "DRU_DMA_FW_GLB" "per , ""DRU_DMA_FW_GLB""" menuitem "DRU_MMR_FW" "per , ""DRU_MMR_FW""" menuitem "DRU_MMR_FW_GLB" "per , ""DRU_MMR_FW_GLB""" menuitem "DSS0_COMMON" "per , ""DSS0_COMMON""" menuitem "DSS0_COMMON1" "per , ""DSS0_COMMON1""" popup "DSS0_OVR" ( menuitem "DSS0_OVR1" "per , ""DSS0_OVR,DSS0_OVR1""" menuitem "DSS0_OVR2" "per , ""DSS0_OVR,DSS0_OVR2""" ) popup "DSS0_VID" ( menuitem "DSS0_VIDL1" "per , ""DSS0_VID,DSS0_VIDL1""" ) menuitem "DSS0_VP" "per , ""DSS0_VP""" menuitem "ECAP" "per , ""ECAP""" menuitem "ECC_AGGR0_ECC_AGGR" "per , ""ECC_AGGR0_ECC_AGGR""" menuitem "ECC_Aggregator" "per , ""ECC_Aggregator""" menuitem "ELM" "per , ""ELM""" popup "EPWM" ( menuitem "EHRPWM0_EPWM" "per , ""EPWM,EHRPWM0_EPWM""" menuitem "EHRPWM1_EPWM" "per , ""EPWM,EHRPWM1_EPWM""" menuitem "EHRPWM2_EPWM" "per , ""EPWM,EHRPWM2_EPWM""" menuitem "EHRPWM3_EPWM" "per , ""EPWM,EHRPWM3_EPWM""" menuitem "EHRPWM4_EPWM" "per , ""EPWM,EHRPWM4_EPWM""" menuitem "EHRPWM5_EPWM" "per , ""EPWM,EHRPWM5_EPWM""" ) popup "EQEP" ( menuitem "EQEP0_REG" "per , ""EQEP,EQEP0_REG""" menuitem "EQEP1_REG" "per , ""EQEP,EQEP1_REG""" menuitem "EQEP2_REG" "per , ""EQEP,EQEP2_REG""" ) popup "ESM" ( menuitem "ESM0" "per , ""ESM,ESM0""" menuitem "MCU_ESM0" "per , ""ESM,MCU_ESM0""" menuitem "WKUP_ESM0" "per , ""ESM,WKUP_ESM0""" ) popup "Firewall_Exception" ( menuitem "CBASS0_GLB" "per , ""Firewall_Exception,CBASS0_GLB""" menuitem "CBASS_INFRA0_GLB" "per , ""Firewall_Exception,CBASS_INFRA0_GLB""" menuitem "MCU_CBASS0_GLB" "per , ""Firewall_Exception,MCU_CBASS0_GLB""" menuitem "WKUP_CBASS0_GLB" "per , ""Firewall_Exception,WKUP_CBASS0_GLB""" ) popup "Firewall_Region" ( menuitem "CAL0_CFG_FW" "per , ""Firewall_Region,CAL0_CFG_FW""" menuitem "CBASS0_FW" "per , ""Firewall_Region,CBASS0_FW""" menuitem "CBASS_FW0_FW" "per , ""Firewall_Region,CBASS_FW0_FW""" menuitem "CC_DEBUG_CELL0_FW" "per , ""Firewall_Region,CC_DEBUG_CELL0_FW""" menuitem "CMPEVT_INTRTR0_CFG_FW" "per , ""Firewall_Region,CMPEVT_INTRTR0_CFG_FW""" menuitem "COMPUTE_CLUSTER0_CFG_FW" "per , ""Firewall_Region,COMPUTE_CLUSTER0_CFG_FW""" menuitem "CTRL_MMR0_FW" "per , ""Firewall_Region,CTRL_MMR0_FW""" menuitem "DCC0_FW" "per , ""Firewall_Region,DCC0_FW""" menuitem "DCC1_FW" "per , ""Firewall_Region,DCC1_FW""" menuitem "DCC2_FW" "per , ""Firewall_Region,DCC2_FW""" menuitem "DCC3_FW" "per , ""Firewall_Region,DCC3_FW""" menuitem "DCC4_FW" "per , ""Firewall_Region,DCC4_FW""" menuitem "DCC5_FW" "per , ""Firewall_Region,DCC5_FW""" menuitem "DCC6_FW" "per , ""Firewall_Region,DCC6_FW""" menuitem "DCC7_FW" "per , ""Firewall_Region,DCC7_FW""" menuitem "DDRSS0_CFG_FW" "per , ""Firewall_Region,DDRSS0_CFG_FW""" menuitem "DEBUGSS0_CFG_FW" "per , ""Firewall_Region,DEBUGSS0_CFG_FW""" menuitem "DSS0_CFG_FW" "per , ""Firewall_Region,DSS0_CFG_FW""" menuitem "ECAP0_FW" "per , ""Firewall_Region,ECAP0_FW""" menuitem "ECC_AGGR0_FW" "per , ""Firewall_Region,ECC_AGGR0_FW""" menuitem "ECC_AGGR1_FW" "per , ""Firewall_Region,ECC_AGGR1_FW""" menuitem "ECC_AGGR2_FW" "per , ""Firewall_Region,ECC_AGGR2_FW""" menuitem "ECC_AGGR3_FW" "per , ""Firewall_Region,ECC_AGGR3_FW""" menuitem "EFUSE0_SLV_FW" "per , ""Firewall_Region,EFUSE0_SLV_FW""" menuitem "ELM0_FW" "per , ""Firewall_Region,ELM0_FW""" menuitem "EPWM0_FW" "per , ""Firewall_Region,EPWM0_FW""" menuitem "EPWM1_FW" "per , ""Firewall_Region,EPWM1_FW""" menuitem "EPWM2_FW" "per , ""Firewall_Region,EPWM2_FW""" menuitem "EPWM3_FW" "per , ""Firewall_Region,EPWM3_FW""" menuitem "EPWM4_FW" "per , ""Firewall_Region,EPWM4_FW""" menuitem "EPWM5_FW" "per , ""Firewall_Region,EPWM5_FW""" menuitem "EQEP0_FW" "per , ""Firewall_Region,EQEP0_FW""" menuitem "EQEP1_FW" "per , ""Firewall_Region,EQEP1_FW""" menuitem "EQEP2_FW" "per , ""Firewall_Region,EQEP2_FW""" menuitem "ESM0_CFG_FW" "per , ""Firewall_Region,ESM0_CFG_FW""" menuitem "GIC0_CFG_FW" "per , ""Firewall_Region,GIC0_CFG_FW""" menuitem "GIC0_ECC_AGGR_CFG_FW" "per , ""Firewall_Region,GIC0_ECC_AGGR_CFG_FW""" menuitem "GPIO0_FW" "per , ""Firewall_Region,GPIO0_FW""" menuitem "GPIO1_FW" "per , ""Firewall_Region,GPIO1_FW""" menuitem "GPIOMUX_INTRTR0_CFG_FW" "per , ""Firewall_Region,GPIOMUX_INTRTR0_CFG_FW""" menuitem "GPMC0_SLV_FW" "per , ""Firewall_Region,GPMC0_SLV_FW""" menuitem "GPU0_KLIO_CFG_FW" "per , ""Firewall_Region,GPU0_KLIO_CFG_FW""" menuitem "GPU0_RAT_CFG_FW" "per , ""Firewall_Region,GPU0_RAT_CFG_FW""" menuitem "GTC0_FW" "per , ""Firewall_Region,GTC0_FW""" menuitem "HRPWM0_FW" "per , ""Firewall_Region,HRPWM0_FW""" menuitem "HRPWM1_FW" "per , ""Firewall_Region,HRPWM1_FW""" menuitem "HRPWM2_FW" "per , ""Firewall_Region,HRPWM2_FW""" menuitem "HRPWM3_FW" "per , ""Firewall_Region,HRPWM3_FW""" menuitem "HRPWM4_FW" "per , ""Firewall_Region,HRPWM4_FW""" menuitem "HRPWM5_FW" "per , ""Firewall_Region,HRPWM5_FW""" menuitem "I2C0_FW" "per , ""Firewall_Region,I2C0_FW""" menuitem "I2C1_FW" "per , ""Firewall_Region,I2C1_FW""" menuitem "I2C2_FW" "per , ""Firewall_Region,I2C2_FW""" menuitem "I2C3_FW" "per , ""Firewall_Region,I2C3_FW""" menuitem "INFRA_CBASS0_FW" "per , ""Firewall_Region,INFRA_CBASS0_FW""" menuitem "MAIN2MCU_LVL_INTRTR0_CFG_FW" "per , ""Firewall_Region,MAIN2MCU_LVL_INTRTR0_CFG_FW""" menuitem "MAIN2MCU_PLS_INTRTR0_CFG_FW" "per , ""Firewall_Region,MAIN2MCU_PLS_INTRTR0_CFG_FW""" menuitem "MAIN_DEBUG_CELL0_FW" "per , ""Firewall_Region,MAIN_DEBUG_CELL0_FW""" menuitem "MCASP0_CFG_FW" "per , ""Firewall_Region,MCASP0_CFG_FW""" menuitem "MCASP0_DMA_FW" "per , ""Firewall_Region,MCASP0_DMA_FW""" menuitem "MCASP1_CFG_FW" "per , ""Firewall_Region,MCASP1_CFG_FW""" menuitem "MCASP1_DMA_FW" "per , ""Firewall_Region,MCASP1_DMA_FW""" menuitem "MCASP2_CFG_FW" "per , ""Firewall_Region,MCASP2_CFG_FW""" menuitem "MCASP2_DMA_FW" "per , ""Firewall_Region,MCASP2_DMA_FW""" menuitem "MCSPI0_SLV_FW" "per , ""Firewall_Region,MCSPI0_SLV_FW""" menuitem "MCSPI1_SLV_FW" "per , ""Firewall_Region,MCSPI1_SLV_FW""" menuitem "MCSPI2_SLV_FW" "per , ""Firewall_Region,MCSPI2_SLV_FW""" menuitem "MCSPI3_SLV_FW" "per , ""Firewall_Region,MCSPI3_SLV_FW""" menuitem "MCSPI4_SLV_FW" "per , ""Firewall_Region,MCSPI4_SLV_FW""" menuitem "MCU_ADC0_CFG_FW" "per , ""Firewall_Region,MCU_ADC0_CFG_FW""" menuitem "MCU_ADC0_DMA_FW" "per , ""Firewall_Region,MCU_ADC0_DMA_FW""" menuitem "MCU_ADC1_CFG_FW" "per , ""Firewall_Region,MCU_ADC1_CFG_FW""" menuitem "MCU_ADC1_DMA_FW" "per , ""Firewall_Region,MCU_ADC1_DMA_FW""" menuitem "MCU_ARMSS0_CORE0_CFG_SLV_FW" "per , ""Firewall_Region,MCU_ARMSS0_CORE0_CFG_SLV_FW""" menuitem "MCU_ARMSS0_CORE0_SLV_FW" "per , ""Firewall_Region,MCU_ARMSS0_CORE0_SLV_FW""" menuitem "MCU_ARMSS0_CORE1_CFG_SLV_FW" "per , ""Firewall_Region,MCU_ARMSS0_CORE1_CFG_SLV_FW""" menuitem "MCU_ARMSS0_CORE1_SLV_FW" "per , ""Firewall_Region,MCU_ARMSS0_CORE1_SLV_FW""" menuitem "MCU_CBASS0_FW" "per , ""Firewall_Region,MCU_CBASS0_FW""" menuitem "MCU_CBASS_FW0_FW" "per , ""Firewall_Region,MCU_CBASS_FW0_FW""" menuitem "MCU_CPSW0_FW" "per , ""Firewall_Region,MCU_CPSW0_FW""" menuitem "MCU_CTRL_MMR0_FW" "per , ""Firewall_Region,MCU_CTRL_MMR0_FW""" menuitem "MCU_DCC0_FW" "per , ""Firewall_Region,MCU_DCC0_FW""" menuitem "MCU_DCC1_FW" "per , ""Firewall_Region,MCU_DCC1_FW""" menuitem "MCU_DCC2_FW" "per , ""Firewall_Region,MCU_DCC2_FW""" menuitem "MCU_DEBUG_CELL0_FW" "per , ""Firewall_Region,MCU_DEBUG_CELL0_FW""" menuitem "MCU_ECC_AGGR0_FW" "per , ""Firewall_Region,MCU_ECC_AGGR0_FW""" menuitem "MCU_ECC_AGGR1_FW" "per , ""Firewall_Region,MCU_ECC_AGGR1_FW""" menuitem "MCU_EFUSE0_SLV_FW" "per , ""Firewall_Region,MCU_EFUSE0_SLV_FW""" menuitem "MCU_ESM0_CFG_FW" "per , ""Firewall_Region,MCU_ESM0_CFG_FW""" menuitem "MCU_FSS0_CFG_FW" "per , ""Firewall_Region,MCU_FSS0_CFG_FW""" menuitem "MCU_FSS0_S0_FW" "per , ""Firewall_Region,MCU_FSS0_S0_FW""" menuitem "MCU_FSS0_S1_FW" "per , ""Firewall_Region,MCU_FSS0_S1_FW""" menuitem "MCU_I2C0_FW" "per , ""Firewall_Region,MCU_I2C0_FW""" menuitem "MCU_MCAN0_FW" "per , ""Firewall_Region,MCU_MCAN0_FW""" menuitem "MCU_MCAN1_FW" "per , ""Firewall_Region,MCU_MCAN1_FW""" menuitem "MCU_MCSPI0_SLV_FW" "per , ""Firewall_Region,MCU_MCSPI0_SLV_FW""" menuitem "MCU_MCSPI1_SLV_FW" "per , ""Firewall_Region,MCU_MCSPI1_SLV_FW""" menuitem "MCU_MCSPI2_SLV_FW" "per , ""Firewall_Region,MCU_MCSPI2_SLV_FW""" menuitem "MCU_MSRAM_CFG_FW" "per , ""Firewall_Region,MCU_MSRAM_CFG_FW""" menuitem "MCU_MSRAM_SLV_FW" "per , ""Firewall_Region,MCU_MSRAM_SLV_FW""" menuitem "MCU_PBIST0_CFG_FW" "per , ""Firewall_Region,MCU_PBIST0_CFG_FW""" menuitem "MCU_PDMA0_ECC_AGGR_FW" "per , ""Firewall_Region,MCU_PDMA0_ECC_AGGR_FW""" menuitem "MCU_PDMA1_ECC_AGGR_FW" "per , ""Firewall_Region,MCU_PDMA1_ECC_AGGR_FW""" menuitem "MCU_PLL_MMR0_FW" "per , ""Firewall_Region,MCU_PLL_MMR0_FW""" menuitem "MCU_PSRAM0_FW" "per , ""Firewall_Region,MCU_PSRAM0_FW""" menuitem "MCU_ROM0_SLV_FW" "per , ""Firewall_Region,MCU_ROM0_SLV_FW""" menuitem "MCU_RTI0_SLV_FW" "per , ""Firewall_Region,MCU_RTI0_SLV_FW""" menuitem "MCU_RTI1_SLV_FW" "per , ""Firewall_Region,MCU_RTI1_SLV_FW""" menuitem "MCU_TIMER0_FW" "per , ""Firewall_Region,MCU_TIMER0_FW""" menuitem "MCU_TIMER1_FW" "per , ""Firewall_Region,MCU_TIMER1_FW""" menuitem "MCU_TIMER2_FW" "per , ""Firewall_Region,MCU_TIMER2_FW""" menuitem "MCU_TIMER3_FW" "per , ""Firewall_Region,MCU_TIMER3_FW""" menuitem "MCU_USART0_FW" "per , ""Firewall_Region,MCU_USART0_FW""" menuitem "MMCSD0_CFG_FW" "per , ""Firewall_Region,MMCSD0_CFG_FW""" menuitem "MMCSD1_CFG_FW" "per , ""Firewall_Region,MMCSD1_CFG_FW""" menuitem "NAVSS0_NB0_BP_FW" "per , ""Firewall_Region,NAVSS0_NB0_BP_FW""" menuitem "NAVSS0_NBSS_CFG_FW" "per , ""Firewall_Region,NAVSS0_NBSS_CFG_FW""" menuitem "PBIST0_CFG_FW" "per , ""Firewall_Region,PBIST0_CFG_FW""" menuitem "PBIST1_CFG_FW" "per , ""Firewall_Region,PBIST1_CFG_FW""" menuitem "PCIE0_CFG_FW" "per , ""Firewall_Region,PCIE0_CFG_FW""" menuitem "PCIE0_SLV_FW" "per , ""Firewall_Region,PCIE0_SLV_FW""" menuitem "PCIE1_CFG_FW" "per , ""Firewall_Region,PCIE1_CFG_FW""" menuitem "PCIE1_SLV_FW" "per , ""Firewall_Region,PCIE1_SLV_FW""" menuitem "PDMA0_ECC_AGGR_FW" "per , ""Firewall_Region,PDMA0_ECC_AGGR_FW""" menuitem "PDMA1_ECC_AGGR_FW" "per , ""Firewall_Region,PDMA1_ECC_AGGR_FW""" menuitem "PDMA_DEBUG0_ECC_AGGR_FW" "per , ""Firewall_Region,PDMA_DEBUG0_ECC_AGGR_FW""" menuitem "PLL_MMR0_FW" "per , ""Firewall_Region,PLL_MMR0_FW""" menuitem "PLLCTRL0_SLV_FW" "per , ""Firewall_Region,PLLCTRL0_SLV_FW""" menuitem "PRU_ICSSG0_SLV_FW" "per , ""Firewall_Region,PRU_ICSSG0_SLV_FW""" menuitem "PRU_ICSSG1_SLV_FW" "per , ""Firewall_Region,PRU_ICSSG1_SLV_FW""" menuitem "PRU_ICSSG2_SLV_FW" "per , ""Firewall_Region,PRU_ICSSG2_SLV_FW""" menuitem "PSC0_FW" "per , ""Firewall_Region,PSC0_FW""" menuitem "PSRAM0_ECC_AGGR_FW" "per , ""Firewall_Region,PSRAM0_ECC_AGGR_FW""" menuitem "PSRAM0_FW" "per , ""Firewall_Region,PSRAM0_FW""" menuitem "SERDES0_SLV_FW" "per , ""Firewall_Region,SERDES0_SLV_FW""" menuitem "SERDES1_SLV_FW" "per , ""Firewall_Region,SERDES1_SLV_FW""" menuitem "STM0_FW" "per , ""Firewall_Region,STM0_FW""" menuitem "TIMER0_FW" "per , ""Firewall_Region,TIMER0_FW""" menuitem "TIMER10_FW" "per , ""Firewall_Region,TIMER10_FW""" menuitem "TIMER11_FW" "per , ""Firewall_Region,TIMER11_FW""" menuitem "TIMER1_FW" "per , ""Firewall_Region,TIMER1_FW""" menuitem "TIMER2_FW" "per , ""Firewall_Region,TIMER2_FW""" menuitem "TIMER3_FW" "per , ""Firewall_Region,TIMER3_FW""" menuitem "TIMER4_FW" "per , ""Firewall_Region,TIMER4_FW""" menuitem "TIMER5_FW" "per , ""Firewall_Region,TIMER5_FW""" menuitem "TIMER6_FW" "per , ""Firewall_Region,TIMER6_FW""" menuitem "TIMER7_FW" "per , ""Firewall_Region,TIMER7_FW""" menuitem "TIMER8_FW" "per , ""Firewall_Region,TIMER8_FW""" menuitem "TIMER9_FW" "per , ""Firewall_Region,TIMER9_FW""" menuitem "TIMESYNC_INTRTR0_CFG_FW" "per , ""Firewall_Region,TIMESYNC_INTRTR0_CFG_FW""" menuitem "USART0_FW" "per , ""Firewall_Region,USART0_FW""" menuitem "USART1_FW" "per , ""Firewall_Region,USART1_FW""" menuitem "USART2_FW" "per , ""Firewall_Region,USART2_FW""" menuitem "USB3SS0_SLV0_FW" "per , ""Firewall_Region,USB3SS0_SLV0_FW""" menuitem "USB3SS0_SLV1_FW" "per , ""Firewall_Region,USB3SS0_SLV1_FW""" menuitem "USB3SS1_SLV0_FW" "per , ""Firewall_Region,USB3SS1_SLV0_FW""" menuitem "USB3SS1_SLV1_FW" "per , ""Firewall_Region,USB3SS1_SLV1_FW""" menuitem "WKUP_CBASS0_FW" "per , ""Firewall_Region,WKUP_CBASS0_FW""" menuitem "WKUP_CBASS_FW0_FW" "per , ""Firewall_Region,WKUP_CBASS_FW0_FW""" menuitem "WKUP_CTRL_MMR0_FW" "per , ""Firewall_Region,WKUP_CTRL_MMR0_FW""" menuitem "WKUP_ECC_AGGR0_FW" "per , ""Firewall_Region,WKUP_ECC_AGGR0_FW""" menuitem "WKUP_ESM0_CFG_FW" "per , ""Firewall_Region,WKUP_ESM0_CFG_FW""" menuitem "WKUP_GPIO0_FW" "per , ""Firewall_Region,WKUP_GPIO0_FW""" menuitem "WKUP_GPIOMUX_INTRTR0_CFG_FW" "per , ""Firewall_Region,WKUP_GPIOMUX_INTRTR0_CFG_FW""" menuitem "WKUP_I2C0_FW" "per , ""Firewall_Region,WKUP_I2C0_FW""" menuitem "WKUP_PLLCTRL0_SLV_FW" "per , ""Firewall_Region,WKUP_PLLCTRL0_SLV_FW""" menuitem "WKUP_PSC0_FW" "per , ""Firewall_Region,WKUP_PSC0_FW""" menuitem "WKUP_USART0_FW" "per , ""Firewall_Region,WKUP_USART0_FW""" menuitem "WKUP_VTM0_FW" "per , ""Firewall_Region,WKUP_VTM0_FW""" ) menuitem "FSS" "per , ""FSS""" menuitem "GIC_ECC_Aggregator" "per , ""GIC_ECC_Aggregator""" popup "GPIO" ( menuitem "GPIO0" "per , ""GPIO,GPIO0""" menuitem "GPIO1" "per , ""GPIO,GPIO1""" menuitem "WKUP_GPIO0" "per , ""GPIO,WKUP_GPIO0""" ) menuitem "GPMC" "per , ""GPMC""" menuitem "GPU" "per , ""GPU""" menuitem "GTC0_GTC_CFG0" "per , ""GTC0_GTC_CFG0""" menuitem "GTC0_GTC_CFG1" "per , ""GTC0_GTC_CFG1""" menuitem "GTC0_GTC_CFG2" "per , ""GTC0_GTC_CFG2""" menuitem "GTC0_GTC_CFG3" "per , ""GTC0_GTC_CFG3""" popup "HyperBus" ( menuitem "MCU_FSS0_HPB_CTRL" "per , ""HyperBus,MCU_FSS0_HPB_CTRL""" menuitem "MCU_FSS0_HPB_ECC_AGGR" "per , ""HyperBus,MCU_FSS0_HPB_ECC_AGGR""" menuitem "MCU_FSS0_HPB_SS_CFG" "per , ""HyperBus,MCU_FSS0_HPB_SS_CFG""" ) popup "I2C" ( menuitem "I2C0_CFG" "per , ""I2C,I2C0_CFG""" menuitem "I2C1_CFG" "per , ""I2C,I2C1_CFG""" menuitem "I2C2_CFG" "per , ""I2C,I2C2_CFG""" menuitem "I2C3_CFG" "per , ""I2C,I2C3_CFG""" menuitem "MCU_I2C0_CFG" "per , ""I2C,MCU_I2C0_CFG""" menuitem "WKUP_I2C0_CFG" "per , ""I2C,WKUP_I2C0_CFG""" ) popup "INTR0_INTR_ROUTER_CFG" ( menuitem "MCU_NAVSS0_INTR0_CFG" "per , ""INTR0_INTR_ROUTER_CFG,MCU_NAVSS0_INTR0_CFG""" menuitem "NAVSS0_INTR0_INTR_ROUTER_CFG" "per , ""INTR0_INTR_ROUTER_CFG,NAVSS0_INTR0_INTR_ROUTER_CFG""" ) popup "Mailbox" ( popup "MAILBOX0_REGS0" ( menuitem "MAILBOX0_REGS0" "per , ""Mailbox,MAILBOX0_REGS0""" menuitem "MAILBOX0_REGS1" "per , ""Mailbox,MAILBOX0_REGS1""" menuitem "MAILBOX0_REGS2" "per , ""Mailbox,MAILBOX0_REGS2""" menuitem "MAILBOX0_REGS3" "per , ""Mailbox,MAILBOX0_REGS3""" menuitem "MAILBOX0_REGS4" "per , ""Mailbox,MAILBOX0_REGS4""" menuitem "MAILBOX0_REGS5" "per , ""Mailbox,MAILBOX0_REGS5""" menuitem "MAILBOX0_REGS6" "per , ""Mailbox,MAILBOX0_REGS6""" menuitem "MAILBOX0_REGS7" "per , ""Mailbox,MAILBOX0_REGS7""" menuitem "MAILBOX0_REGS8" "per , ""Mailbox,MAILBOX0_REGS8""" menuitem "MAILBOX0_REGS9" "per , ""Mailbox,MAILBOX0_REGS9""" menuitem "MAILBOX0_REGS10" "per , ""Mailbox,MAILBOX0_REGS10""" menuitem "MAILBOX0_REGS11" "per , ""Mailbox,MAILBOX0_REGS11""" ) ) popup "MCAN" ( menuitem "MCU_MCAN0_CFG" "per , ""MCAN,MCU_MCAN0_CFG""" menuitem "MCU_MCAN1_CFG" "per , ""MCAN,MCU_MCAN1_CFG""" menuitem "MCU_MCAN0_MSGMEM_RAM" "per , ""MCAN,MCU_MCAN0_MSGMEM_RAM""" menuitem "MCU_MCAN1_MSGMEM_RAM" "per , ""MCAN,MCU_MCAN1_MSGMEM_RAM""" menuitem "MCU_MCAN0_SS" "per , ""MCAN,MCU_MCAN0_SS""" menuitem "MCU_MCAN1_SS" "per , ""MCAN,MCU_MCAN1_SS""" ) popup "MCASP" ( menuitem "MCASP0_CFG" "per , ""MCASP,MCASP0_CFG""" menuitem "MCASP1_CFG" "per , ""MCASP,MCASP1_CFG""" menuitem "MCASP2_CFG" "per , ""MCASP,MCASP2_CFG""" menuitem "MCASP0_DMA" "per , ""MCASP,MCASP0_DMA""" menuitem "MCASP1_DMA" "per , ""MCASP,MCASP1_DMA""" menuitem "MCASP2_DMA" "per , ""MCASP,MCASP2_DMA""" ) popup "MCSPI" ( menuitem "MCSPI0_CFG" "per , ""MCSPI,MCSPI0_CFG""" menuitem "MCSPI1_CFG" "per , ""MCSPI,MCSPI1_CFG""" menuitem "MCSPI2_CFG" "per , ""MCSPI,MCSPI2_CFG""" menuitem "MCSPI3_CFG" "per , ""MCSPI,MCSPI3_CFG""" menuitem "MCSPI4_CFG" "per , ""MCSPI,MCSPI4_CFG""" menuitem "MCU_MCSPI0_CFG" "per , ""MCSPI,MCU_MCSPI0_CFG""" menuitem "MCU_MCSPI1_CFG" "per , ""MCSPI,MCU_MCSPI1_CFG""" menuitem "MCU_MCSPI2_CFG" "per , ""MCSPI,MCU_MCSPI2_CFG""" ) menuitem "MCU_CPSW0_ALE" "per , ""MCU_CPSW0_ALE""" menuitem "MCU_CPSW0_CONTROL" "per , ""MCU_CPSW0_CONTROL""" menuitem "MCU_CPSW0_CPINT" "per , ""MCU_CPSW0_CPINT""" menuitem "MCU_CPSW0_CPTS" "per , ""MCU_CPSW0_CPTS""" menuitem "MCU_CPSW0_ECC" "per , ""MCU_CPSW0_ECC""" menuitem "MCU_CPSW0_MDIO" "per , ""MCU_CPSW0_MDIO""" menuitem "MCU_CPSW0_NUSS_Subsystem__SS_" "per , ""MCU_CPSW0_NUSS_Subsystem__SS_""" menuitem "MCU_CPSW0_RAM" "per , ""MCU_CPSW0_RAM""" menuitem "MCU_CPSW0_SGMII" "per , ""MCU_CPSW0_SGMII""" menuitem "MCU_CPSW0_STATS0" "per , ""MCU_CPSW0_STATS0""" menuitem "MCU_CPSW0_STATS1" "per , ""MCU_CPSW0_STAT1""" menuitem "MCU_CTRL_MMR0" "per , ""MCU_CTRL_MMR0""" menuitem "MCU_ECC_AGGR0_ECC_AGGR" "per , ""MCU_ECC_AGGR0_ECC_AGGR""" menuitem "MCU_NAVSS0_UDMASS_ECCAGGR0" "per , ""MCU_NAVSS0_UDMASS_ECCAGGR0""" menuitem "MCU_PDMA0" "per , ""MCU_PDMA0""" menuitem "MCU_PDMA1" "per , ""MCU_PDMA1""" popup "MCU_PLL0_CFG" ( menuitem "MCU_PLL0_CFG" "per , ""MCU_PLL0_CFG,MCU_PLL0_CFG""" menuitem "PLL0_CFG" "per , ""MCU_PLL0_CFG,PLL0_CFG""" ) menuitem "MCU_SEC_MMR0_CFG0" "per , ""MCU_SEC_MMR0_CFG0""" popup "MMCSD" ( menuitem "MMC0_CTL_CFG" "per , ""MMCSD,MMC0_CTL_CFG""" menuitem "MMC0_ECC_AGGR_RXMEM" "per , ""MMCSD,MMC0_ECC_AGGR_RXMEM""" menuitem "MMC0_ECC_AGGR_TXMEM" "per , ""MMCSD,MMC0_ECC_AGGR_TXMEM""" menuitem "MMC0_SS_CFG" "per , ""MMCSD,MMC0_SS_CFG""" menuitem "MMC1_CTL_CFG" "per , ""MMCSD,MMC1_CTL_CFG""" menuitem "MMC1_ECC_AGGR_RXMEM" "per , ""MMCSD,MMC1_ECC_AGGR_RXMEM""" menuitem "MMC1_ECC_AGGR_TXMEM" "per , ""MMCSD,MMC1_ECC_AGGR_TXMEM""" menuitem "MMC1_SS_CFG" "per , ""MMCSD,MMC1_SS_CFG""" ) popup "MODSS_INTA_CFG" ( menuitem "NAVSS0_MODSS_INTA0_CFG" "per , ""MODSS_INTA_CFG,NAVSS0_MODSS_INTA0_CFG""" menuitem "NAVSS0_MODSS_INTA1_CFG" "per , ""MODSS_INTA_CFG,NAVSS0_MODSS_INTA1_CFG""" ) popup "MODSS_INTA_CFG_IMAP" ( menuitem "NAVSS0_MODSS_INTA0_CFG_IMAP" "per , ""MODSS_INTA_CFG_IMAP,NAVSS0_MODSS_INTA0_CFG_IMAP""" menuitem "NAVSS0_MODSS_INTA1_CFG_IMAP" "per , ""MODSS_INTA_CFG_IMAP,NAVSS0_MODSS_INTA1_CFG_IMAP""" ) popup "MODSS_INTA_CFG_INTR" ( menuitem "NAVSS0_MODSS_INTA0_CFG_INTR" "per , ""MODSS_INTA_CFG_INTR,NAVSS0_MODSS_INTA0_CFG_INTR""" menuitem "NAVSS0_MODSS_INTA1_CFG_INTR" "per , ""MODSS_INTA_CFG_INTR,NAVSS0_MODSS_INTA1_CFG_INTR""" ) menuitem "MSMC" "per , ""MSMC""" menuitem "NAVSS0_CFG" "per , ""NAVSS0_CFG""" menuitem "NAVSS0_CPTS" "per , ""NAVSS0_CPTS""" popup "NAVSS0_MCRC" ( menuitem "MCU_NAVSS0_MCRC" "per , ""NAVSS0_MCRC,MCU_NAVSS0_MCRC""" menuitem "NAVSS0_MCRC" "per , ""NAVSS0_MCRC,NAVSS0_MCRC""" ) menuitem "NAVSS0_MSMC0_SLV_VIRTID_CFG_MMRS" "per , ""NAVSS0_MSMC0_SLV_VIRTID_CFG_MMRS""" menuitem "NAVSS0_MSMC1_SLV_VIRTID_CFG_MMRS" "per , ""NAVSS0_MSMC1_SLV_VIRTID_CFG_MMRS""" menuitem "NAVSS0_NAV_DDR_HI_VIRTID_CFG_MMRS" "per , ""NAVSS0_NAV_DDR_HI_VIRTID_CFG_MMRS""" menuitem "NAVSS0_NAV_DDR_LO_VIRTID_CFG_MMRS" "per , ""NAVSS0_NAV_DDR_LO_VIRTID_CFG_MMRS""" menuitem "NAVSS0_NBSS_CFG_REGS0_MMRS" "per , ""NAVSS0_NBSS_CFG_REGS0_MMRS""" menuitem "NAVSS0_NBSS_NB0_MEM_ATTR0_CFG" "per , ""NAVSS0_NBSS_NB0_MEM_ATTR0_CFG""" menuitem "NAVSS0_NBSS_NB0_MEM_ATTR1_CFG" "per , ""NAVSS0_NBSS_NB0_MEM_ATTR1_CFG""" popup "NAVSS0_NBSS_NB1_CFG_MMRS" ( menuitem "NAVSS0_NBSS_NB1_CFG_MMRS" "per , ""NAVSS0_NBSS_NB1_CFG_MMRS,NAVSS0_NBSS_NB1_CFG_MMRS""" ) menuitem "NAVSS0_NBSS_NB1_MEM_ATTR0_CFG" "per , ""NAVSS0_NBSS_NB1_MEM_ATTR0_CFG""" menuitem "NAVSS0_NBSS_NB1_MEM_ATTR1_CFG" "per , ""NAVSS0_NBSS_NB1_MEM_ATTR1_CFG""" popup "NAVSS0_NBSS_NB_CFG_MMRS" ( menuitem "NAVSS0_NBSS_NB0_CFG_MMRS" "per , ""NAVSS0_NBSS_NB_CFG_MMRS,NAVSS0_NBSS_NB0_CFG_MMRS""" menuitem "NAVSS0_NBSS_NB1_CFG_MMRS" "per , ""NAVSS0_NBSS_NB_CFG_MMRS,NAVSS0_NBSS_NB1_CFG_MMRS""" ) popup "NAVSS0_PROXY0_BUF_CFG" ( menuitem "MCU_NAVSS0_PROXY0_BUF_CFG" "per , ""NAVSS0_PROXY0_BUF_CFG,MCU_NAVSS0_PROXY0_BUF_CFG""" menuitem "NAVSS0_PROXY0_BUF_CFG" "per , ""NAVSS0_PROXY0_BUF_CFG,NAVSS0_PROXY0_BUF_CFG""" ) popup "NAVSS0_PROXY0_CFG_BUF_CFG" ( menuitem "MCU_NAVSS0_PROXY_CFG_GCFG" "per , ""NAVSS0_PROXY0_CFG_BUF_CFG,MCU_NAVSS0_PROXY_CFG_GCFG""" menuitem "NAVSS0_PROXY0_CFG_BUF_CFG" "per , ""NAVSS0_PROXY0_CFG_BUF_CFG,NAVSS0_PROXY0_CFG_BUF_CFG""" ) popup "NAVSS0_PROXY_BUF" ( menuitem "MCU_NAVSS0_PROXY_CFG_BUF" "per , ""NAVSS0_PROXY_BUF,MCU_NAVSS0_PROXY_CFG_BUF""" menuitem "NAVSS0_PROXY_BUF" "per , ""NAVSS0_PROXY_BUF,NAVSS0_PROXY_BUF""" ) popup "NAVSS0_PROXY_TARGET0_DATA" ( menuitem "MCU_NAVSS0_PROXY0_TARGET0_DATA" "per , ""NAVSS0_PROXY_TARGET0_DATA,MCU_NAVSS0_PROXY0_TARGET0_DATA""" menuitem "NAVSS0_PROXY_TARGET0_DATA" "per , ""NAVSS0_PROXY_TARGET0_DATA,NAVSS0_PROXY_TARGET0_DATA""" ) popup "NAVSS0_PVU_CFG_TLBIF" ( menuitem "NAVSS0_PVU0_CFG_TLBIF" "per , ""NAVSS0_PVU_CFG_TLBIF,NAVSS0_PVU0_CFG_TLBIF""" menuitem "NAVSS0_PVU1_CFG_TLBIF" "per , ""NAVSS0_PVU_CFG_TLBIF,NAVSS0_PVU1_CFG_TLBIF""" ) popup "NAVSS0_SEC_PROXY0_CFG_MMRS" ( menuitem "MCU_NAVSS0_SEC_PROXY0_CFG" "per , ""NAVSS0_SEC_PROXY0_CFG_MMRS,MCU_NAVSS0_SEC_PROXY0_CFG""" menuitem "NAVSS0_SEC_PROXY0_CFG_MMRS" "per , ""NAVSS0_SEC_PROXY0_CFG_MMRS,NAVSS0_SEC_PROXY0_CFG_MMRS""" ) popup "NAVSS0_SEC_PROXY0_CFG_RT" ( menuitem "MCU_NAVSS0_SEC_PROXY0_CFG_RT" "per , ""NAVSS0_SEC_PROXY0_CFG_RT,MCU_NAVSS0_SEC_PROXY0_CFG_RT""" menuitem "NAVSS0_SEC_PROXY0_CFG_RT" "per , ""NAVSS0_SEC_PROXY0_CFG_RT,NAVSS0_SEC_PROXY0_CFG_RT""" ) popup "NAVSS0_SEC_PROXY0_CFG_SCFG" ( menuitem "MCU_NAVSS0_SEC_PROXY0_CFG_SCFG" "per , ""NAVSS0_SEC_PROXY0_CFG_SCFG,MCU_NAVSS0_SEC_PROXY0_CFG_SCFG""" menuitem "NAVSS0_SEC_PROXY0_CFG_SCFG" "per , ""NAVSS0_SEC_PROXY0_CFG_SCFG,NAVSS0_SEC_PROXY0_CFG_SCFG""" ) popup "NAVSS0_SEC_PROXY0_SRC_TARGET_DATA" ( menuitem "MCU_NAVSS0_SEC_PROXY0_TARGET_DATA" "per , ""NAVSS0_SEC_PROXY0_SRC_TARGET_DATA,MCU_NAVSS0_SEC_PROXY0_TARGET_DATA""" menuitem "NAVSS0_SEC_PROXY0_SRC_TARGET_DATA" "per , ""NAVSS0_SEC_PROXY0_SRC_TARGET_DATA,NAVSS0_SEC_PROXY0_SRC_TARGET_DATA""" ) popup "NAVSS0_UDMASS_RINGACC0_CFG" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG" "per , ""NAVSS0_UDMASS_RINGACC0_CFG,MCU_NAVSS0_UDMASS_RINGACC0_CFG""" menuitem "NAVSS0_UDMASS_RINGACC0_CFG" "per , ""NAVSS0_UDMASS_RINGACC0_CFG,NAVSS0_UDMASS_RINGACC0_CFG""" ) popup "NAVSS0_UDMASS_RINGACC0_CFG_MON" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_MON,MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON""" menuitem "NAVSS0_UDMASS_RINGACC0_CFG_MON" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_MON,NAVSS0_UDMASS_RINGACC0_CFG_MON""" ) popup "NAVSS0_UDMASS_RINGACC0_CFG_RT" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_RT,MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT""" menuitem "NAVSS0_UDMASS_RINGACC0_CFG_RT" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_RT,NAVSS0_UDMASS_RINGACC0_CFG_RT""" ) popup "NAVSS0_UDMASS_RINGACC0_GCFG" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG" "per , ""NAVSS0_UDMASS_RINGACC0_GCFG,MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG""" menuitem "NAVSS0_UDMASS_RINGACC0_GCFG" "per , ""NAVSS0_UDMASS_RINGACC0_GCFG,NAVSS0_UDMASS_RINGACC0_GCFG""" ) popup "NAVSS0_UDMASS_RINGACC0_SRC_FIFOS" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_FIFOS" "per , ""NAVSS0_UDMASS_RINGACC0_SRC_FIFOS,MCU_NAVSS0_UDMASS_RINGACC0_FIFOS""" menuitem "NAVSS0_UDMASS_RINGACC0_SRC_FIFOS" "per , ""NAVSS0_UDMASS_RINGACC0_SRC_FIFOS,NAVSS0_UDMASS_RINGACC0_SRC_FIFOS""" ) popup "NAVSS_PVU_CFG" ( menuitem "NAVSS0_PVU0_CFG" "per , ""NAVSS_PVU_CFG,NAVSS0_PVU0_CFG""" menuitem "NAVSS0_PVU1_CFG" "per , ""NAVSS_PVU_CFG,NAVSS0_PVU1_CFG""" ) popup "OSPI" ( menuitem "MCU_FSS0_OSPI0_CTRL" "per , ""OSPI,MCU_FSS0_OSPI0_CTRL""" menuitem "MCU_FSS0_OSPI1_CTRL" "per , ""OSPI,MCU_FSS0_OSPI1_CTRL""" menuitem "MCU_FSS0_OSPI0_SS_CFG" "per , ""OSPI,MCU_FSS0_OSPI0_SS_CFG""" menuitem "MCU_FSS0_OSPI1_SS_CFG" "per , ""OSPI,MCU_FSS0_OSPI1_SS_CFG""" menuitem "MCU_FSS0_OSPI0_ECC_AGGR" "per , ""OSPI,MCU_FSS0_OSPI0_ECC_AGGR""" menuitem "MCU_FSS0_OSPI1_ECC_AGGR" "per , ""OSPI,MCU_FSS0_OSPI1_ECC_AGGR""" ) popup "PCIE_CORE_EP" ( menuitem "PCIE0_DAT" "per , ""PCIE_CORE_EP,PCIE0_DAT""" menuitem "PCIE1_DAT" "per , ""PCIE_CORE_EP,PCIE1_DAT""" ) popup "PCIE_CPTS" ( menuitem "PCIE0_CPTS" "per , ""PCIE_CPTS,PCIE0_CPTS""" menuitem "PCIE1_CPTS" "per , ""PCIE_CPTS,PCIE1_CPTS""" ) popup "PCIE_DAT0" ( menuitem "PCIE1_DAT0" "per , ""PCIE_DAT0,PCIE1_DAT0""" ) popup "PCIE_DAT1" ( menuitem "PCIE1_DAT0" "per , ""PCIE_DAT1,PCIE1_DAT0""" ) popup "PCIE_ECC_AGGR0" ( menuitem "PCIE0_CORE_ECC_AGGR0" "per , ""PCIE_ECC_AGGR0,PCIE0_CORE_ECC_AGGR0""" menuitem "PCIE1_CORE_ECC_AGGR0" "per , ""PCIE_ECC_AGGR0,PCIE1_CORE_ECC_AGGR0""" ) popup "PCIE_ECC_AGGR1" ( menuitem "PCIE0_CORE_ECC_AGGR0" "per , ""PCIE_ECC_AGGR1,PCIE0_CORE_ECC_AGGR0""" menuitem "PCIE1_CORE_ECC_AGGR0" "per , ""PCIE_ECC_AGGR1,PCIE1_CORE_ECC_AGGR0""" ) popup "PCIE_VMAP_HP" ( menuitem "PCIE0_CORE_VMAP_HP_MMRS" "per , ""PCIE_VMAP_HP,PCIE0_CORE_VMAP_HP_MMRS""" menuitem "PCIE1_CORE_VMAP_HP_MMRS" "per , ""PCIE_VMAP_HP,PCIE1_CORE_VMAP_HP_MMRS""" ) popup "PCIE_VMAP_LP" ( menuitem "PCIE0_CORE_VMAP_LP_MMRS" "per , ""PCIE_VMAP_LP,PCIE0_CORE_VMAP_LP_MMRS""" menuitem "PCIE1_CORE_VMAP_LP_MMRS" "per , ""PCIE_VMAP_LP,PCIE1_CORE_VMAP_LP_MMRS""" ) menuitem "PDMA0" "per , ""PDMA0""" menuitem "PDMA1" "per , ""PDMA1""" menuitem "PDMA_DEBUG" "per , ""PDMA_DEBUG""" popup "PLL_Controller" ( menuitem "PLLCTRL0" "per , ""PLL_Controller,PLLCTRL0""" menuitem "WKUP_PLLCTRL0" "per , ""PLL_Controller,WKUP_PLLCTRL0""" ) popup "PSC" ( menuitem "PSC0" "per , ""PSC,PSC0""" menuitem "WKUP_PSC0" "per , ""PSC,WKUP_PSC0""" ) popup "PSI_L_CFG_PROXY" ( menuitem "MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY" "per , ""PSI_L_CFG_PROXY,MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY""" menuitem "NAVSS0_UDMASS_PSILCFG0_CFG_PROXY" "per , ""PSI_L_CFG_PROXY,NAVSS0_UDMASS_PSILCFG0_CFG_PROXY""" ) popup "RTI" ( menuitem "MCU_RTI0" "per , ""RTI,MCU_RTI0""" menuitem "MCU_RTI1" "per , ""RTI,MCU_RTI1""" menuitem "RTI0" "per , ""RTI,RTI0""" menuitem "RTI1" "per , ""RTI,RTI1""" menuitem "RTI2" "per , ""RTI,RTI2""" menuitem "RTI3" "per , ""RTI,RTI3""" ) popup "SerDes" ( menuitem "SERDES0" "per , ""SerDes,SERDES0""" menuitem "SERDES1" "per , ""SerDes,SERDES1""" ) menuitem "Spinlock" "per , ""Spinlock""" popup "Time_Sync_Routers" ( menuitem "CMPEVT_INTRTR0" "per , ""Time_Sync_Routers,CMPEVT_INTRTR0""" menuitem "TIMESYNC_INTRTR0" "per , ""Time_Sync_Routers,TIMESYNC_INTRTR0""" ) popup "TIMERMGR_CFG_CFG" ( menuitem "NAVSS0_TIMERMGR0_CFG" "per , ""TIMERMGR_CFG_CFG,NAVSS0_TIMERMGR0_CFG""" menuitem "NAVSS0_TIMERMGR1_CFG" "per , ""TIMERMGR_CFG_CFG,NAVSS0_TIMERMGR1_CFG""" ) popup "TIMERMGR_CFG_OES" ( menuitem "NAVSS0_TIMERMGR0_CFG_OES" "per , ""TIMERMGR_CFG_OES,NAVSS0_TIMERMGR0_CFG_OES""" menuitem "NAVSS0_TIMERMGR1_CFG_OES" "per , ""TIMERMGR_CFG_OES,NAVSS0_TIMERMGR1_CFG_OES""" ) popup "TIMERMGR_CFG_TIMERS" ( menuitem "NAVSS0_TIMERMGR0_CFG_TIMERS" "per , ""TIMERMGR_CFG_TIMERS,NAVSS0_TIMERMGR0_CFG_TIMERS""" menuitem "NAVSS0_TIMERMGR1_CFG_TIMERS" "per , ""TIMERMGR_CFG_TIMERS,NAVSS0_TIMERMGR1_CFG_TIMERS""" ) popup "Timers" ( menuitem "MCU_TIMER0" "per , ""Timers,MCU_TIMER0""" menuitem "MCU_TIMER1" "per , ""Timers,MCU_TIMER1""" menuitem "MCU_TIMER2" "per , ""Timers,MCU_TIMER2""" menuitem "MCU_TIMER3" "per , ""Timers,MCU_TIMER3""" menuitem "TIMER0" "per , ""Timers,TIMER0""" menuitem "TIMER1" "per , ""Timers,TIMER1""" menuitem "TIMER2" "per , ""Timers,TIMER2""" menuitem "TIMER3" "per , ""Timers,TIMER3""" menuitem "TIMER4" "per , ""Timers,TIMER4""" menuitem "TIMER5" "per , ""Timers,TIMER5""" menuitem "TIMER6" "per , ""Timers,TIMER6""" menuitem "TIMER7" "per , ""Timers,TIMER7""" menuitem "TIMER8" "per , ""Timers,TIMER8""" menuitem "TIMER9" "per , ""Timers,TIMER9""" menuitem "TIMER10" "per , ""Timers,TIMER10""" menuitem "TIMER11" "per , ""Timers,TIMER11""" ) popup "UART" ( menuitem "MCU_UART0" "per , ""UART,MCU_UART0""" menuitem "UART0" "per , ""UART,UART0""" menuitem "UART1" "per , ""UART,UART1""" menuitem "UART2" "per , ""UART,UART2""" menuitem "WKUP_UART0" "per , ""UART,WKUP_UART0""" ) popup "UDMASS_INTA0_CFG" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG" "per , ""UDMASS_INTA0_CFG,MCU_NAVSS0_UDMASS_INTA0_CFG""" menuitem "NAVSS0_UDMASS_INTA0_CFG" "per , ""UDMASS_INTA0_CFG,NAVSS0_UDMASS_INTA0_CFG""" ) popup "UDMASS_INTA0_CFG_GCNTCFG" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG" "per , ""UDMASS_INTA0_CFG_GCNTCFG,MCU_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG""" menuitem "NAVSS0_UDMASS_INTA0_CFG_GCNTCFG" "per , ""UDMASS_INTA0_CFG_GCNTCFG,NAVSS0_UDMASS_INTA0_CFG_GCNTCFG""" ) popup "UDMASS_INTA0_CFG_GCNTRTI" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_GCNTRTI" "per , ""UDMASS_INTA0_CFG_GCNTRTI,MCU_NAVSS0_UDMASS_INTA0_GCNTRTI""" menuitem "NAVSS0_UDMASS_INTA0_CFG_GCNTRTI" "per , ""UDMASS_INTA0_CFG_GCNTRTI,NAVSS0_UDMASS_INTA0_CFG_GCNTRTI""" ) popup "UDMASS_INTA0_CFG_IMAP" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP" "per , ""UDMASS_INTA0_CFG_IMAP,MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP""" menuitem "NAVSS0_UDMASS_INTA0_CFG_IMAP" "per , ""UDMASS_INTA0_CFG_IMAP,NAVSS0_UDMASS_INTA0_CFG_IMAP""" ) popup "UDMASS_INTA0_CFG_INTR" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_INTR" "per , ""UDMASS_INTA0_CFG_INTR,MCU_NAVSS0_UDMASS_INTA0_CFG_INTR""" menuitem "NAVSS0_UDMASS_INTA0_CFG_INTR" "per , ""UDMASS_INTA0_CFG_INTR,NAVSS0_UDMASS_INTA0_CFG_INTR""" ) popup "UDMASS_INTA0_CFG_L2G" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_L2G" "per , ""UDMASS_INTA0_CFG_L2G,MCU_NAVSS0_UDMASS_INTA0_CFG_L2G""" menuitem "NAVSS0_UDMASS_INTA0_CFG_L2G" "per , ""UDMASS_INTA0_CFG_L2G,NAVSS0_UDMASS_INTA0_CFG_L2G""" ) popup "UDMASS_INTA0_CFG_MCAST" ( menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST" "per , ""UDMASS_INTA0_CFG_MCAST,MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST""" menuitem "NAVSS0_UDMASS_INTA0_CFG_MCAST" "per , ""UDMASS_INTA0_CFG_MCAST,NAVSS0_UDMASS_INTA0_CFG_MCAST""" ) popup "UDMASS_RINGACC0_ISC_ISC" ( menuitem "MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC" "per , ""UDMASS_RINGACC0_ISC_ISC,MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC""" menuitem "NAVSS0_UDMASS_RINGACC0_ISC_ISC" "per , ""UDMASS_RINGACC0_ISC_ISC,NAVSS0_UDMASS_RINGACC0_ISC_ISC""" ) popup "UDMASS_UDMAP0_CFG" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG" "per , ""UDMASS_UDMAP0_CFG,MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG" "per , ""UDMASS_UDMAP0_CFG,NAVSS0_UDMASS_UDMAP0_CFG""" ) popup "UDMASS_UDMAP0_CFG_RCHAN" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP0_RCHAN" "per , ""UDMASS_UDMAP0_CFG_RCHAN,MCU_NAVSS0_UDMASS_UDMAP0_RCHAN""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG_RCHAN" "per , ""UDMASS_UDMAP0_CFG_RCHAN,NAVSS0_UDMASS_UDMAP0_CFG_RCHAN""" ) popup "UDMASS_UDMAP0_CFG_RCHANRT" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" "per , ""UDMASS_UDMAP0_CFG_RCHANRT,MCU_NAVSS0_UDMASS_UDMAP_RCHANRT""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT" "per , ""UDMASS_UDMAP0_CFG_RCHANRT,NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT""" ) popup "UDMASS_UDMAP0_CFG_RFLOW" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW" "per , ""UDMASS_UDMAP0_CFG_RFLOW,MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG_RFLOW" "per , ""UDMASS_UDMAP0_CFG_RFLOW,NAVSS0_UDMASS_UDMAP0_CFG_RFLOW""" ) popup "UDMASS_UDMAP0_CFG_TCHAN" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP0_TCHAN" "per , ""UDMASS_UDMAP0_CFG_TCHAN,MCU_NAVSS0_UDMASS_UDMAP0_TCHAN""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG_TCHAN" "per , ""UDMASS_UDMAP0_CFG_TCHAN,NAVSS0_UDMASS_UDMAP0_CFG_TCHAN""" ) popup "UDMASS_UDMAP0_CFG_TCHANRT" ( menuitem "MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" "per , ""UDMASS_UDMAP0_CFG_TCHANRT,MCU_NAVSS0_UDMASS_UDMAP_TCHANRT""" menuitem "NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT" "per , ""UDMASS_UDMAP0_CFG_TCHANRT,NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT""" ) popup "USB" ( menuitem "USB3SS0" "per , ""USB,USB3SS0""" menuitem "USB3SS1" "per , ""USB,USB3SS1""" menuitem "USB3SS0_ECC_AGGR" "per , ""USB,USB3SS0_ECC_AGGR""" menuitem "USB3SS1_ECC_AGGR" "per , ""USB,USB3SS1_ECC_AGGR""" menuitem "USB3SS0_PHY2" "per , ""USB,USB3SS0_PHY2""" menuitem "USB3SS1_PHY2" "per , ""USB,USB3SS1_PHY2""" ) menuitem "VBUSM_C_ECC_Aggregator" "per , ""VBUSM_C_ECC_Aggregator""" popup "VIM" ( menuitem "VIM_CFG0" "per , ""VIM,VIM_CFG0""" menuitem "VIM_CFG1" "per , ""VIM,VIM_CFG1""" ) popup "VIRTID_CFG_MMRS" ( menuitem "NAV_DDR0_VIRTID_CFG_MMRS" "per , ""VIRTID_CFG_MMRS,NAV_DDR0_VIRTID_CFG_MMRS""" menuitem "NAV_DDR1_VIRTID_CFG_MMRS" "per , ""VIRTID_CFG_MMRS,NAV_DDR1_VIRTID_CFG_MMRS""" menuitem "NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS" "per , ""VIRTID_CFG_MMRS,NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS""" ) menuitem "WKUP_CTRL_MMR0" "per , ""WKUP_CTRL_MMR0""" menuitem "WKUP_ECC_AGGR0" "per , ""WKUP_ECC_AGGR0""" menuitem "WKUP_VTM0" "per , ""WKUP_VTM0""" ) else ( popup "PRU_ECAP_ECAP0" ( menuitem "PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV" "per , ""PRU_ECAP_ECAP0,PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV""" menuitem "PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV" "per , ""PRU_ECAP_ECAP0,PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV""" ) popup "PRU_ICSS_INTC_INTC" ( menuitem "PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV" "per , ""PRU_ICSS_INTC_INTC,PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV""" menuitem "PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV" "per , ""PRU_ICSS_INTC_INTC,PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV""" ) popup "PRU_ICSSG_CFG" ( menuitem "PRU_ICSSG0_PR1_CFG_SLV" "per , ""PRU_ICSSG_CFG,PRU_ICSSG0_PR1_CFG_SLV""" menuitem "PRU_ICSSG1_PR1_CFG_SLV" "per , ""PRU_ICSSG_CFG,PRU_ICSSG1_PR1_CFG_SLV""" menuitem "PRU_ICSSG2_PR1_CFG_SLV" "per , ""PRU_ICSSG_CFG,PRU_ICSSG2_PR1_CFG_SLV""" ) popup "PRU_ICSSG_DDRAM" ( menuitem "PRU_ICSSG0_DRAM0_SLV_RAM" "per , ""PRU_ICSSG_DDRAM,PRU_ICSSG0_DRAM0_SLV_RAM""" menuitem "PRU_ICSSG0_DRAM1_SLV_RAM" "per , ""PRU_ICSSG_DDRAM,PRU_ICSSG0_DRAM1_SLV_RAM""" menuitem "PRU_ICSSG1_DRAM0_SLV_RAM" "per , ""PRU_ICSSG_DDRAM,PRU_ICSSG1_DRAM0_SLV_RAM""" menuitem "PRU_ICSSG1_DRAM1_SLV_RAM" "per , ""PRU_ICSSG_DDRAM,PRU_ICSSG1_DRAM1_SLV_RAM""" menuitem "PRU_ICSSG2_DRAM0_SLV_RAM" "per , ""PRU_ICSSG_DDRAM,PRU_ICSSG2_DRAM0_SLV_RAM""" menuitem "PRU_ICSSG2_DRAM1_SLV_RAM" "per , ""PRU_ICSSG_DDRAM,PRU_ICSSG2_DRAM1_SLV_RAM""" ) popup "PRU_ICSSG_ECC_AGGR" ( menuitem "PRU_ICSSG0_ECC_AGGR" "per , ""PRU_ICSSG_ECC_AGGR,PRU_ICSSG0_ECC_AGGR""" menuitem "PRU_ICSSG1_ECC_AGGR" "per , ""PRU_ICSSG_ECC_AGGR,PRU_ICSSG1_ECC_AGGR""" ) popup "PRU_ICSSG_PA_STAT" ( menuitem "PRU_ICSSG0_PA_STAT_WRAP_PA_SLV" "per , ""PRU_ICSSG_PA_STAT,PRU_ICSSG0_PA_STAT_WRAP_PA_SLV""" menuitem "PRU_ICSSG1_PA_STAT_WRAP_PA_SLV" "per , ""PRU_ICSSG_PA_STAT,PRU_ICSSG1_PA_STAT_WRAP_PA_SLV""" ) popup "PRU_ICSSG_PA_STAT_CSTAT" ( menuitem "PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_CSTAT" "per , ""PRU_ICSSG_PA_STAT_CSTAT,PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_CSTAT""" menuitem "PRU_ICSSG1_PA_STAT_WRAP_PA_SLV_CSTAT" "per , ""PRU_ICSSG_PA_STAT_CSTAT,PRU_ICSSG1_PA_STAT_WRAP_PA_SLV_CSTAT""" ) popup "PRU_ICSSG_PA_STAT_QSTAT" ( menuitem "PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_QSTAT" "per , ""PRU_ICSSG_PA_STAT_QSTAT,PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_QSTAT""" menuitem "PRU_ICSSG1_PA_STAT_WRAP_PA_SLV_QSTAT" "per , ""PRU_ICSSG_PA_STAT_QSTAT,PRU_ICSSG1_PA_STAT_WRAP_PA_SLV_QSTAT""" ) popup "PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL" ( menuitem "PRU_ICSSG0_PR1_PDSP0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_PDSP0_IRAM""" menuitem "PRU_ICSSG0_PR1_PDSP1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_PDSP1_IRAM""" menuitem "PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM""" menuitem "PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM""" menuitem "PRU_ICSSG0_PR1_TX_PDSP0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_TX_PDSP0_IRAM""" menuitem "PRU_ICSSG0_PR1_TX_PDSP1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG0_PR1_TX_PDSP1_IRAM""" menuitem "PRU_ICSSG1_PR1_PDSP0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_PDSP0_IRAM""" menuitem "PRU_ICSSG1_PR1_PDSP1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_PDSP1_IRAM""" menuitem "PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM""" menuitem "PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM""" menuitem "PRU_ICSSG1_PR1_TX_PDSP0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_TX_PDSP0_IRAM""" menuitem "PRU_ICSSG1_PR1_TX_PDSP1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG1_PR1_TX_PDSP1_IRAM""" menuitem "PRU_ICSSG2_PR1_PDSP0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG2_PR1_PDSP0_IRAM""" menuitem "PRU_ICSSG2_PR1_PDSP1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG2_PR1_PDSP1_IRAM""" menuitem "PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM""" menuitem "PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM""" menuitem "PRU_ICSSG2_PR1_TX_PDSP0_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG2_PR1_TX_PDSP0_IRAM""" menuitem "PRU_ICSSG2_PR1_TX_PDSP1_IRAM" "per , ""PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL,PRU_ICSSG2_PR1_TX_PDSP1_IRAM""" ) popup "PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG" ( menuitem "PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG""" menuitem "PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG""" menuitem "PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG""" menuitem "PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG""" menuitem "PRU_ICSSG0_PR1_TX_PDSP0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_TX_PDSP0_IRAM_DEBUG""" menuitem "PRU_ICSSG0_PR1_TX_PDSP1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG0_PR1_TX_PDSP1_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_TX_PDSP0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_TX_PDSP0_IRAM_DEBUG""" menuitem "PRU_ICSSG1_PR1_TX_PDSP1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG1_PR1_TX_PDSP1_IRAM_DEBUG""" menuitem "PRU_ICSSG2_PR1_PDSP0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG2_PR1_PDSP0_IRAM_DEBUG""" menuitem "PRU_ICSSG2_PR1_PDSP1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG2_PR1_PDSP1_IRAM_DEBUG""" menuitem "PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_DEBUG""" menuitem "PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_DEBUG""" menuitem "PRU_ICSSG2_PR1_TX_PDSP0_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG2_PR1_TX_PDSP0_IRAM_DEBUG""" menuitem "PRU_ICSSG2_PR1_TX_PDSP1_IRAM_DEBUG" "per , ""PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG,PRU_ICSSG2_PR1_TX_PDSP1_IRAM_DEBUG""" ) popup "PRU_ICSSG_RAM" ( menuitem "PRU_ICSSG0_RAM_SLV_RAM" "per , ""PRU_ICSSG_RAM,PRU_ICSSG0_RAM_SLV_RAM""" menuitem "PRU_ICSSG1_RAM_SLV_RAM" "per , ""PRU_ICSSG_RAM,PRU_ICSSG1_RAM_SLV_RAM""" ) popup "PRU_IEP_IEP" ( menuitem "PRU_ICSSG0_IEP0" "per , ""PRU_IEP_IEP,PRU_ICSSG0_IEP0""" menuitem "PRU_ICSSG0_IEP1" "per , ""PRU_IEP_IEP,PRU_ICSSG0_IEP1""" menuitem "PRU_ICSSG1_IEP0" "per , ""PRU_IEP_IEP,PRU_ICSSG1_IEP0""" menuitem "PRU_ICSSG1_IEP1" "per , ""PRU_IEP_IEP,PRU_ICSSG1_IEP1""" menuitem "PRU_ICSSG2_IEP0" "per , ""PRU_IEP_IEP,PRU_ICSSG2_IEP0""" menuitem "PRU_ICSSG2_IEP1" "per , ""PRU_IEP_IEP,PRU_ICSSG2_IEP1""" ) popup "PRU_MDIO_MDIO" ( menuitem "PRU_ICSSG0_PR1_MDIO_V1P7_MDIO" "per , ""PRU_MDIO_MDIO,PRU_ICSSG0_PR1_MDIO_V1P7_MDIO""" menuitem "PRU_ICSSG1_PR1_MDIO_V1P7_MDIO" "per , ""PRU_MDIO_MDIO,PRU_ICSSG1_PR1_MDIO_V1P7_MDIO""" ) popup "PRU_MII_G_RT_MII_G_RT" ( menuitem "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" "per , ""PRU_MII_G_RT_MII_G_RT,PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G""" menuitem "PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" "per , ""PRU_MII_G_RT_MII_G_RT,PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G""" menuitem "PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" "per , ""PRU_MII_G_RT_MII_G_RT,PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G""" ) popup "PRU_MII_RT_MII_RT" ( menuitem "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG" "per , ""PRU_MII_RT_MII_RT,PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG""" menuitem "PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG" "per , ""PRU_MII_RT_MII_RT,PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG""" menuitem "PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_CFG" "per , ""PRU_MII_RT_MII_RT,PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_CFG""" ) popup "PRU_PROT_PROTECT" ( menuitem "PRU_ICSSG0_PR1_PROT_SLV" "per , ""PRU_PROT_PROTECT,PRU_ICSSG0_PR1_PROT_SLV""" menuitem "PRU_ICSSG1_PR1_PROT_SLV" "per , ""PRU_PROT_PROTECT,PRU_ICSSG1_PR1_PROT_SLV""" menuitem "PRU_ICSSG2_PR1_PROT_SLV" "per , ""PRU_PROT_PROTECT,PRU_ICSSG2_PR1_PROT_SLV""" ) popup "PRU_RAT_SLICE_RAT_SLICE" ( menuitem "PRU_ICSSG0_RAT_SLICE0_CFG" "per , ""PRU_RAT_SLICE_RAT_SLICE,PRU_ICSSG0_RAT_SLICE0_CFG""" menuitem "PRU_ICSSG0_RAT_SLICE1_CFG" "per , ""PRU_RAT_SLICE_RAT_SLICE,PRU_ICSSG0_RAT_SLICE1_CFG""" menuitem "PRU_ICSSG1_RAT_SLICE0_CFG" "per , ""PRU_RAT_SLICE_RAT_SLICE,PRU_ICSSG1_RAT_SLICE0_CFG""" menuitem "PRU_ICSSG1_RAT_SLICE1_CFG" "per , ""PRU_RAT_SLICE_RAT_SLICE,PRU_ICSSG1_RAT_SLICE1_CFG""" ) popup "PRU_SGMII_SGMII" ( menuitem "PRU_ICSSG1_PR1_MII_RT_PR1_SGMII0_CFG_SGMII0" "per , ""PRU_SGMII_SGMII,PRU_ICSSG1_PR1_MII_RT_PR1_SGMII0_CFG_SGMII0""" menuitem "PRU_ICSSG1_PR1_MII_RT_PR1_SGMII1_CFG_SGMII1" "per , ""PRU_SGMII_SGMII,PRU_ICSSG1_PR1_MII_RT_PR1_SGMII1_CFG_SGMII1""" ) popup "PRU_TASKS_MGR_TASKS_MGR_PRU_RTU" ( menuitem "PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR" "per , ""PRU_TASKS_MGR_TASKS_MGR_PRU_RTU,PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR""" menuitem "PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR" "per , ""PRU_TASKS_MGR_TASKS_MGR_PRU_RTU,PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR""" menuitem "PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR" "per , ""PRU_TASKS_MGR_TASKS_MGR_PRU_RTU,PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR""" menuitem "PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR" "per , ""PRU_TASKS_MGR_TASKS_MGR_PRU_RTU,PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR""" menuitem "PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR" "per , ""PRU_TASKS_MGR_TASKS_MGR_PRU_RTU,PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR""" menuitem "PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR" "per , ""PRU_TASKS_MGR_TASKS_MGR_PRU_RTU,PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR""" menuitem "PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR" "per , ""PRU_TASKS_MGR_TASKS_MGR_PRU_RTU,PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR""" menuitem "PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR" "per , ""PRU_TASKS_MGR_TASKS_MGR_PRU_RTU,PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR""" ) popup "PRU_UART_UART0" ( menuitem "PRU_ICSSG0_PR1_ICSS_UART_UART_SLV" "per , ""PRU_UART_UART0,PRU_ICSSG0_PR1_ICSS_UART_UART_SLV""" menuitem "PRU_ICSSG1_PR1_ICSS_UART_UART_SLV" "per , ""PRU_UART_UART0,PRU_ICSSG1_PR1_ICSS_UART_UART_SLV""" ) ) ) )