; --------------------------------------------------------------------------------
; @Title: Generic Hyper FLASH Program script for the R-Car Gen3 devices
; @Description:
;  Generic Hyper FLASH Program script for the R-Car Gen3 devices using a small
;  application code on the Cortex-A5x to program the flash.
;  The KL512S (Spansion Hyper flash) is connected to the SPI Multi I/O Bus
;  Controller (RPC)
;
;  Prerequisites:
;    * Set the Cortex-A5x as boot core to flash using Cortex-A5x
;    * Set the Cortex-R7 as boot core to flash using Cortex-R7
;
;   SRAM:                          0xE6300000--0xE6307FFF
;   QuadSPI(controller)   Base:    0xEE200000
;   QuadSPI memory mapped ADDRESS: 0x8000000
;
;  Calling convention
;   Do rcar_gen3-hyper.cmm <cpu> <option>
;     <cpu>      SoC name / R-Car Gen3 device to be programmed.
;                Optional, if empty CPU selection dialog will appear
;     <option>   Optional parameter. If "PREPAREONLY" is pased, flash programming
;                is prepared (flash declaration), but flash is not programmed
;
;  Example for R8A77951 (R-Car H3):
;     Do rcar_gen3-hyper.cmm R8A77951 "PREPAREONLY"
;     Do rcar_gen3-cr7-hyper.cmm R8A77951-CR7 "PREPAREONLY"
;
; @Author: JIM
; @Keywords: KL512 Spansion HyperFlash QuadSPI
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: rcar_gen3-hyper.cmm 12741 2023-11-17 07:55:15Z mschaeffner $
LOCAL &cpu &arg1 &BASE
ENTRY &cpu &arg1
&arg1=STRing.UPpeR("&arg1")  // for example "PREPAREONLY"

&BASE=0xEE200000

RESet
SYStem.RESet

IF "&cpu"==""
(
  SYStem.CPU R8A779*
  &cpu=CPU()
)
ELSE
  SYStem.CPU &cpu

; --------------------------------------------------------------------------------
; Setup CPU
SYStem.JtagClock CTCK 10MHz
CORE.ASSIGN 1. // boot core
; CORE.ASSIGN 2. // Alternate boot core if previoius line does not work
Trace.DISable
SYStem.Up

; Cortex-A5x or Cortex-R7?
IF ARMARCHVERSION()<8.
  GOSUB MPU_CONFIG

; enable SRAM
Data.Set A:0xE67F0018 %LE %Long 0x1

IF ARMARCHVERSION()>=8.
(
  Register.Set I 0
  Register.Set M 0x5 ;EL1h
)
//Enable RPC PowerON & Clock
Data.Set A:0xE6150900 %LE %Long ~(0x3F1E017)
Data.Set A:0xE6150994 %LE %Long   0x3F1E017    ;  Module STOP register, BIT17 RPC  SMSTPCR9 (System module stop control register 9)

Data.Set A:0xE6150900 %LE %Long ~(0x13)
Data.Set A:0xE6150238 %LE %Long   0x13         ;80Mhz, 0x17=40Mhz  RPCCKCR(RPC Clock frequency control register)

IF ARMARCHVERSION()>=8.
  GOSUB WDOG_DISABLE

//FLASH READ ID TEST
 AREA.CLEAR
 AREA.view
 GOSUB READ_ID_TEST

LOCAL &pdd
&pdd=OS.PresentDemoDirectory()

Break.RESet

FLASHFILE.RESet

//FLASHFILE.CONFIG <RPC Base Address>
  FLASHFILE.CONFIG &BASE

//FLASHFILE.TARGET <code range>       <data range>        <Algorithm file>
  FLASHFILE.TARGET 0xE6300000++0x1FFF 0xE6302000++0x21FF  &pdd/flash/word/hyper256_shrpc.bin   /KEEP

//Read FLASH Manufacture and Device ID
  FLASHFILE.GETID

//End of the test prepareonly
IF "&arg1"=="PREPAREONLY"
  ENDDO

//Dump window for Hyper FLASH
  FLASHFILE.DUMP 0x0

//Erase Hyper FLASH
; FLASHFILE.ERASE 0x0--0xFFFFF

//Write Hyper FLASH
; FLASHFILE.LOAD  * 0x0

ENDDO

; --------------------------------------------------------------------------------
WDOG_DISABLE:
//RCLK Watchdog Timer disable
Data.Set EZAXI:0xE6020004 %Long  0xA5A5A500|0x00   ; Write 0 to the RCLK Watchdog Timer Control Register A
Data.Set EZAXI:0xE6020008 %Long  0xA5A5A500|0x00   ; Write 0 to the RCLK Watchdog Timer Control Register B

//System Watchdog Timer disable
Data.Set EZAXI:0xE6030004 %Long  0xA5A5A500|0x00   ; Write 0 to the System Watchdog Timer Control Register A
Data.Set EZAXI:0xE6030008 %Long  0xA5A5A500|0x00   ; Write 0 to the System Watchdog Timer Control Register B
RETURN

; --------------------------------------------------------------------------------
READ_ID_TEST:
(
  &backup_cmncr=Data.Long(A:(&BASE+0x00))

  Data.Set A:(&BASE+0x7C) %Long 0x80000263  ;physical calibration.
  Data.Set A:(&BASE+0x00) %Long 0x81fff301
  Data.Set A:(&BASE+0x24) %Long 0x0  ;write memory
  Data.Set A:(&BASE+0x28) %Long 0x555
  Data.Set A:(&BASE+0x2C) %Long 0x0
  Data.Set A:(&BASE+0x64) %Long 0x5101
  Data.Set A:(&BASE+0x30) %Long 0xA2225408
  Data.Set A:(&BASE+0x40) %Long 0xF0000000  ; Reset(0xF0)
  Data.Set A:(&BASE+0x20) %Long 0x3  ;write access

  Data.Set A:(&BASE+0x7C) %Long 0x80000263  ;physical calibration.
  Data.Set A:(&BASE+0x00) %Long 0x81fff301
  Data.Set A:(&BASE+0x24) %Long 0x0  ;write memory
  Data.Set A:(&BASE+0x28) %Long 0x555
  Data.Set A:(&BASE+0x2C) %Long 0x0
  Data.Set A:(&BASE+0x64) %Long 0x5101
  Data.Set A:(&BASE+0x30) %Long 0xA2225408
  Data.Set A:(&BASE+0x40) %Long 0x98000000 ; CFI Enter(0x98)
  Data.Set A:(&BASE+0x20) %Long 0x3  ;write access

  Data.Set A:(&BASE+0x7C) %Long 0x80000263 ;physical calibration.
  Data.Set A:(&BASE+0x00) %Long 0x81fff301
  Data.Set A:(&BASE+0x24) %Long 0x00800000 ;read memory
  Data.Set A:(&BASE+0x28) %Long 0x0  ;addr
  Data.Set A:(&BASE+0x2C) %Long 0x0
  Data.Set A:(&BASE+0x60) %Long 0xE  ;dummy cycle
  Data.Set A:(&BASE+0x64) %Long 0x5101
  Data.Set A:(&BASE+0x30) %Long 0xA222D40C ; 32bit read with dummy cycle
  Data.Set A:(&BASE+0x20) %Long 0x5  ;read access

  WAIT 10.ms
  //print "read_buffer[31:0]: 0x" data.long(A:(&BASE+0x38))
  &temp=Data.Long(A:(&BASE+0x38))
  PRINT "Read 1st: 0x" (&temp>>8.)&0xFF  " (Manufacturer)"
  PRINT "Read 2nd: 0x" (&temp>>24.)&0xFF  " (Device ID)"

  Data.Set A:(&BASE+0x00) %Long &backup_cmncr
)
RETURN