; -------------------------------------------------------------------------------- ; @Title: SPINAND FLASH Program script for the J721S2-EVM ; @Description: ; The SPINAND flash is connected to the OSPI_CS0 controller. ; Supported SPINAND flash memories: ; - W25N01JWxxxG ; - W35N01JWxxxG ; ; SRAM: ; OSPI(controller) Base: 0x47040000 ; OSPI memory mapped ADDRESS: 0x50000000 ; ; @Author: CMO, JIM ; @Chip: TDA4AL88, TDA4VE88, TDA4VL21, AM68AX ; @Board: J721S2-EVM ; @Keywords: SPINAND ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: j721s2-spinand.cmm 12107 2023-05-11 13:19:26Z cmorgenstern $ WinCLEAR LOCAL &arg1 &prepateOnly &tmp &isW25 ENTRY &arg1 &arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY", "MEM=W25", "MEM=W35" &prepateOnly=(STRing.SCAN("&arg1","PREPAREONLY",0)!=-1) &tmp=STRing.SCANAndExtract("&arg1","MEM=","") &isW25=FALSE() IF ("&tmp"=="W25") &isW25=TRUE() LOCAL &pdd &pdd=OS.PresentDemoDirectory() ; -------------------------------------------------------------------------------- LOCAL &OSPI_BASE &OSPI_MEMORY_BASE &flash_algorithm &OSPI_BASE=0x47040000 &OSPI_MEMORY_BASE=0x50000000 ; flash contents memory mapped address IF (&isW25) &flash_algorithm="~~/demo/arm/flash/byte/spinand2k6_tiospi.bin" ELSE &flash_algorithm="~~/demo/arm/flash/byte/spinand4k7_tiospi.bin" ; -------------------------------------------------------------------------------- ; Open the master core(CM4) to configure system ; Close leftover GUIs InterCom OTHERS QUIT ; Open all SLAVE GUIs IF !INTERCOM.PING(CM4) TargetSystem.NewInstance CM4 /ARCHitecture ARM InterCom CM4 TITLE "TRACE32 for ARM - J721S2-CM4 - SLAVE" ; set GUI title InterCom CM4 RESet InterCom CM4 SYStem.RESet InterCom CM4 SYStem.CPU TDA4VE88-CM4-0 InterCom CM4 SYStem.CONFIG CORE 2. 1. InterCom CM4 SYStem.CONFIG SLAVE OFF InterCom CM4 SYStem.Option RESBREAK OFF InterCom CM4 SYStem.Option EnReset OFF InterCom CM4 SYSTEM.JTAGCLOCK CTCK 10MHz IF COMBIPROBE()||UTRACE() ( InterCom CM4 SYStem.CONFIG.CONNECTOR MIPI34 ; because of converter LA-3782 ) InterCom CM4 SYStem.Mode Prepare InterCom CM4 Data.Set EDBG:0x400003f0 %Long 0x00190000 ; Ensure Power-AP unlocked InterCom CM4 Data.Set EDBG:0x400003f0 %Long 0yxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1 ; Soft reset system InterCom CM4 WAIT 500.ms ; Wait some time for system to stabilize ; Basic board setup via CortexM4 ; Disbale CR5-MCU lockstep InterCom CM4 Data.Set EZAXI:0x45A50040 %Long 0x00000000 ; Basic board setup via CortexM4 InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_pll.cmm" MAIN InterCom.WAIT CM4 InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_pll.cmm" DEBUG InterCom.WAIT CM4 ; Enable Power InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 0. 0x1 0x3 ; LPSC_WKUP_ALWAYSON InterCom.WAIT CM4 InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 1. 0x1 0x3 ; LPSC_DMSC InterCom.WAIT CM4 InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 2. 0x1 0x3 ; LPSC_DEBUG2DMSC InterCom.WAIT CM4 InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 7. 0x1 0x3 ; LPSC_MCU_DEBUG InterCom.WAIT CM4 InterCom CM4 DO "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 10. 0x1 0x3 ; LPSC_MCU_OSPI_0 InterCom.WAIT CM4 InterCom CM4 DO "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 11. 0x1 0x3 ; LPSC_MCU_OSPI_1 InterCom.WAIT CM4 ; Close CM4 GUI InterCom OTHERS QUIT ; -------------------------------------------------------------------------------- ; Connect to MCU-CR5 to program flash SYStem.CPU TDA4VE88-CR5-MCU SYStem.CONFIG.CORE 3. 1. CORE.ASSIGN 1. SYStem.Option.ResBreak OFF SYStem.Option.EnReset OFF SYStem.MemAccess DAP ;Enable to use the dualport SYStem.Option.TRST OFF SYStem.Attach Break ; ------------------------------------------------------------------------------ ; Flash Controller Power & Clock Enable GOSUB CLK_INIT ; ------------------------------------------------------------------------------ ; Flash Pin Mux Configuration GOSUB PIN_MUX ; ------------------------------------------------------------------------------ ; Flash Controller Init GOSUB OSPI_INIT GOSUB CACHE_MMU_INIT ; ------------------------------------------------------------------------------ ; Flash Read ID Test GOSUB READ_ID_TEST ; ------------------------------------------------------------------------------ ; Flash declaration &pdd=OS.PresentDemoDirectory() Break.RESet FLASHFILE.RESet FLASHFILE.Create 0x0--0x7FFFFFF 0x20000 ; W25N01JWxxxG, 128KB uniform blocks //FLASFILE.CONFIG FLASHFILE.CONFIG &OSPI_BASE &OSPI_MEMORY_BASE FLASHFILE.TARGET 0x41C00000++0x1FFF E:0x41C02000++0x23FF &flash_algorithm /KEEP /DualPort // Read FLASH Manufacturer and Device ID FLASHFILE.GETID ;GOSUB FLASHFILE_ONFI_TEST ;Read out the onfi registers in spinand flash ; ------------------------------------------------------------------------------ ; SPINAND specific function to read memory GOSUB FLASHFILE_CHECK_SPINAND_READMODE ;Check BUF flag in the SR-2[3], it changes the spinand read method //Unlock SPI NAND FLASH FLASHFILE.UNLOCK 0x0--0x7FFFFFF //End of the test prepareonly IF &prepateOnly ENDDO ; ------------------------------------------------------------------------------ ; Flash programming example //Dump window for Serial FLASH FLASHFILE.DUMP 0x0 ;FLASHFILE.DUMP 0x0 /SPARE /Track //Write Serial FLASH ;FLASHFILE.ERASE 0x0--0xFFFFF //Write Serial FLASH ;FLASHFILE.LOAD * 0x0 ;FLASHFILE.LOAD * 0x0 /ComPare //Reset device PRINT "Please power-cycle the board after flash program is complete" ENDDO READ_ID_TEST: ( ; In case of errors you can try to read the ID via: ; GOSUB READ_ID_TEST ; ; Check the output of the AREA window. ; Expected output ID: ; 0xFF (Dummy) ; 0xEF (Manufacture) ; 0xBC ; 0x21 LOCAL &rdata &CTRLREG=&OSPI_BASE+0x090 &RXDATA0=&OSPI_BASE+0x0A0 &RXDATA1=&OSPI_BASE+0x0A4 &cmd=0x9f<<24. //cmd &rd=0x1<<23. //rd data enable &rd_num=0x7<<20. //7+1==8bytes, max &cmd_exec=0x1 //cmd execution Data.Set EZAXI:&CTRLREG %LE %Long (&cmd|&cmd_exec|&rd_num|&rd) ;write cmd + write data WAIT 100.ms &rdata=Data.Long(EZAXI:&RXDATA0) ;read lower , 8byte fifo PRINT "1st 0x" (&rdata)&0xFF " (Dummy)" ; //RXFIFO0 PRINT "2nd 0x" (&rdata>>8.)&0xFF " (Manufacture)" PRINT "3rd 0x" (&rdata>>16.)&0xFF " (Device ID)[15:8]" PRINT "4th 0x" (&rdata>>24.)&0xFF " (Device ID)[7:0]" &rdata=Data.Long(EZAXI:&RXDATA1) ;read upper , 8byte fifo ;PRINT "5th 0x" (&rdata)&0xFF ;PRINT "6th 0x" (&rdata>>8.)&0xFF ;PRINT "7th 0x" (&rdata>>16.)&0xFF ;PRINT "8th 0x" (&rdata>>24.)&0xFF RETURN ) FLASHFILE_ONFI_TEST: ( FLASHFILE.GETONFI /VM PRINT "A page size: " %Decimal Data.Long(VM:0x50) "./" Data.Long(VM:0x54) ".Bytes (main/spare)" PRINT "A block size: 0x" Data.Long(VM:0x50)*Data.Long(VM:0x5C) " (" %Decimal Data.Long(VM:0x5C) ".Pages)" PRINT "A device size: 0x" Data.Long(VM:0x50)*Data.Long(VM:0x5C)*Data.Long(VM:0x60) " Bytes" RETURN ) FLASHFILE_CHECK_SPINAND_READMODE: ( LOCAL &status //The Buffer Read Mode (BUF=1) requires a Column Address to start outputting the existing data inside //the Data Buffer, and once it reaches the end of the data buffer (Byte 2,111), DO (IO1) pin will become //high-Z state. //The Continuous Read Mode (BUF=0) doesn't require the starting Column Address. The device will //always start output the data from the first column (Byte 0) of the Data buffer, and once the end of the //data buffer (Byte 2,048) is reached, the data output will continue through the next memory page. //2048+64, Buffer Read Mode (BUF=1), bcz the OSPI RX buffer is not large enough (Not A nand page size) FLASHFILE.SPI.CMD 0x0F 0xB0 /READ 0x4 VM:0 &status=Data.Byte(VM:0x0) //old flash algorithm needs the ecc enable, but new one needs the ecc disable IF FLASHFILE.TARGET.BUILD(&flash_algorithm)<11484. ( &status=&status|0x18 ;Set ECC[4]=1, BUF[3]=1 in Status Register-2 ) ELSE ( &status=&status|0x8 // Set BUF[3]=1 in Status Register-2 &status=(&status&~0x10)&0xFF // Set ECC[4]=0, ECC disable ) FLASHFILE.SPI.CMD 0x1F 0xB0 &status RETURN ) OSPI_INIT: ( Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x0 Data.Set EZAXI:&OSPI_BASE+0x4 %LE %Long 0x00000013 ; 4B Addr Read Data.Set EZAXI:&OSPI_BASE+0x8 %LE %Long 0x00000012 ; 4B Addr Write Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x80800000 Data.Set EZAXI:&OSPI_BASE+0x14 %LE %Long 0x1003; 4B Address mode, 3B Addr: 0x1002 Data.Set EZAXI:&OSPI_BASE+0x10 %LE %Long 0x21 Data.Set EZAXI:&OSPI_BASE+0x1C %LE %Long 0xFFFFFFFF //Data.Set EZAXI:&OSPI_BASE+0xC %LE %Long (0xFF<<16.)|(0xFF<<8.) ; !!!!! OSPI_DEV_DELAY_REG because of writing !!!!! Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x00000081|(0x1<<19.)|(0xE<<10.) ; 0x1==baudrate_div4, enable usage of OSPI_CS0 Data.Set EZAXI:&OSPI_BASE+0x1C %LE %Long 0x04000000 ;ospi_setdirectcutoff, end of the flash address RETURN ) PIN_MUX: ( ;MMR_unlock Data.Set EZAXI:0x4301D008 %Long 0x68EF3490 ;CTRLMMR_WKUP_LOCK7_KICK0 Data.Set EZAXI:0x4301D00C %Long 0xD172BC5A Data.Set EZAXI:0x4301C000 %Long 0x00040000 ;CTRLMMR_WKUP_PADCONFIG0 Data.Set EZAXI:0x4301C004 %Long 0x00040000 Data.Set EZAXI:0x4301C008 %Long 0x00040000 Data.Set EZAXI:0x4301C00C %Long 0x00040000 Data.Set EZAXI:0x4301C010 %Long 0x00040000 Data.Set EZAXI:0x4301C014 %Long 0x00040000 Data.Set EZAXI:0x4301C018 %Long 0x00040000 Data.Set EZAXI:0x4301C01C %Long 0x00040000 Data.Set EZAXI:0x4301C020 %Long 0x00040000 Data.Set EZAXI:0x4301C024 %Long 0x00040000 Data.Set EZAXI:0x4301C028 %Long 0x00040000 Data.Set EZAXI:0x4301C02C %Long 0x00040000 Data.Set EZAXI:0x4301C030 %Long 0x00040000 Data.Set EZAXI:0x4301C038 %Long 0x00040001 Data.Set EZAXI:0x4301C03C %Long 0x00040001 RETURN ) CLK_INIT: ( PRIVATE &HSDIV_OPTION ; If there are flashing issues or if it fails, try to modfy the following value. ; The valid range is: 0x3 <= &HSDIV_OPTION <= 0x8 &HSDIV_OPTION=0x5 ; Set clock source Data.Set EZAXI:0x40F09008 %Long 0x68EF3490 ; CTRLMMR_MCU_LOCK2_KICK0 Data.Set EZAXI:0x40F0900C %Long 0xD172BC5A Data.Set EZAXI:0x40F08030 %Long 0x1 ; CTRLMMR_MCU_OSPI0_CLKSEL: 0x1 = MCU_PLL2_HSDIV4_CLKOUT ; Adjust PLL for MCU_PLL2_HSDIV4_CLKOUT DO &pdd/hardware/j721e/scripts/configure_pll _CFG_ BYPASS MCU 2. DO &pdd/hardware/j721e/scripts/configure_pll _CFG_ DIV MCU 2. 0x2 0x1 0x1 0x68 0x2AAAAB DO &pdd/hardware/j721e/scripts/configure_pll _CFG_ HSDIV MCU 2. 4. &HSDIV_OPTION DO &pdd/hardware/j721e/scripts/configure_pll _CFG_ ENABLE MCU 2. RETURN ) CACHE_MMU_INIT: ( PRIVATE &i &tmpReg ; Enable MPU and disable I and D caches &tmpReg=Data.Long(C15:0x1) &tmpReg=&tmpReg|0x1 ; enable MPU &tmpReg=(&tmpReg&(~(0x1<<2.))) ; disable D cache &tmpReg=(&tmpReg&(~(0x1<<12.))) ; disable I cache Data.Set C15:0x1 %Long &tmpReg ; Configure small region setup for flash programming PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x016 %Long 0x00000000 ; set default PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x216 %Long 0x0000003F PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x416 %Long 0x00001310 PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x016 %Long 0x50000000 ; setup flash window PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x216 %Long 0x00000035 PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x416 %Long 0x00001301 PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x016 %Long 0x41C00000 ; setup buffer space PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x216 %Long 0x00000027 PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x416 %Long 0x0000030C ; Reset all other MPU regions &i=3. WHILE &i<16. ( PER.Set.SaveIndex C15:0x026 %Long &i C15:0x016 %Long 0x0 PER.Set.SaveIndex C15:0x026 %Long &i C15:0x216 %Long 0x0 PER.Set.SaveIndex C15:0x026 %Long &i C15:0x416 %Long 0x0 &i=&i+1. ) RETURN ) // detect the flash address mode by the internal flash register (0x0080_0003) // CR2V : should come 0x08(3B) or 0x88(4B) SPI_4B_ADDRMODE_ENABLE: ( SILENT.FLASH.SPI.CMD 1. 0x06 SILENT.FLASH.SPI.CMD 1. 0x71 0x80 0x00 0x03 0x88 ; write 0x88 to CR2V , switch 3B->4B address mode Data.Set VM:0x0--0xFF %Long 0x0 SILENT.FLASH.SPI.CMD 1. 0x65 0x00 0x80 0x00 0x03 0x0 /READ 0x4 vm:0x0 ;4Bytes Address mode ®Data=Data.Byte(vm:0x0) IF ®Data!=0x88 ( PRINT "We expect 0x08 latency(dummy) cycles but we got the dummy cycle 0x" %Hex ®Data ENDDO ) RETURN )