; --------------------------------------------------------------------------------
; @Title:  TMDSCNCD263 EVM QSPI FLASH (S25FL128SAGNFI000) Program script
; @Description:
;   SRAM: 0x70001000
;   QSPI Base Register Address : 0x48200000
;   Prerequisites:
;    * Plug TMDSCNCD263 onto TI debug&trace adapter TMDSHSECDOCK-AM263
;    * Remove R47 on TMDSHSECDOCK-AM263 (disconnect RTCK).
;      It caused issues especially when using the offchip trace script.
;    * Connect Debug Cable to J9 via adapter LA-3818
;    * SW5=OFF to deactivate onboard debugger
;    * SW3.1=OFF, SW3.2=OFF, SW3.3=ON, SW3.4=OFF for boot mode QSPI (UART fallback)
;      Alternatively: any QSPI boot mode or DevBoot mode
;    * The board is equipped with a high-security device. It has a code part in the
;      QSPI which unlocks the device. If this code part is lost you won't be able to
;      debug without authentification.
;
; @Keywords: ARM, Cortex-R5F
; @Author: PEG, JIM
; @Board: TMDSCNCD263
; @Chip: AM2634
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: am263x-spi.cmm 12265 2023-06-29 08:48:56Z jjeong $

&QSPI_BASE=0x48200000

LOCAL &arg1
ENTRY &arg1
&arg1=STRing.UPpeR("&arg1")  // for example "PREPAREONLY"

; --------------------------------------------------------------------------------
; initialize and start the debugger
RESet
SYStem.CPU AM2634-SS0
CORE.ASSIGN 1.

; --------------------------------------------------------------------------------
; Attach to system bus and make some preparations
SYStem.Mode Prepare

; Unlock MSS_CTRL (MSS_CTRL_LOCK0_KICKx)
Data.Set EAHB:0x50D01008 %Long 0x01234567
Data.Set EAHB:0x50D0100c %Long 0x0fedcba8

; Eclipse ROM, use RAM in ATCM (MSS_CTRL_R5SS0_ROM_ECLIPSE)
Data.Set EAHB:0x50D00080 %Long 0x00000007

; Let core run (MSS_CTRL_R5SS0_CORE0_HALT)
Data.Set EAHB:0x50D00024 %Long 0x00000000

; --------------------------------------------------------------------------------
; Attach to the cores
SYStem.Mode Attach
IF STATE.RUN()
  Break

; --------------------------------------------------------------------------------
; Disable the MPU and the caches that may have been enabled by the firmware (SCTLR)
Data.Set C15:0x1 %Long (Data.Long(C15:0x1)&(~0x1005))

GOSUB CACHE_MMU_INIT
GOSUB PIN_MUX
GOSUB CLK_INIT
GOSUB QSPI_INIT
GOSUB READ_ID_TEST

programFlash:
FLASHFILE.RESet

FLASHFILE.Create 0x0--0x0FFFFFF   0x10000      ;if uniform 64KB sectors

//FLASHFILE.CONFIG  <QuadSPI Base>  0x0 0x0 <cs>
FLASHFILE.CONFIG  &QSPI_BASE      0x0 0x0  0x0

//FLASHFILE.TARGET <Code_range>     <Data_range>              <Algorithm file>
FLASHFILE.TARGET 0x70001000++0x1FFF   EAHB:0x70003000++0x27FF ~~/demo/arm/flash/byte/spi64_tiqspi.bin  /STACKSIZE 0x200 /DualPort /KEEP

FLASHFILE.GETID

//End of the test prepareonly
IF "&arg1"=="PREPAREONLY"
  ENDDO

FLASHFILE.DUMP 0x0

;FLASHFILE.Erase 0x0--0xFFFFF  ; erase range
;FLASHFILE.LOAD *  0x0

ENDDO

READ_ID_TEST:
(
  &QSPI_CMD_REG=&QSPI_BASE+0x48
  &QSPI_DAT_REG=&QSPI_BASE+0x50
  &QSPI_STAT_REG=&QSPI_BASE+0x4C

  &RE=(0x1<<16.)  ; read
  &WR=(0x2<<16.)  ; write
  &END=(0x4<<16.) ;
  &cmd_reg_def=0x0|(0x7<<19.)|(0x0<<28.)|0xFFF ;

  Data.Set AD:&QSPI_DAT_REG %Long 0x9F              ;write data reg
  Data.Set AD:&QSPI_CMD_REG %Long (&cmd_reg_def|&WR);cmd reg
  //print "status 0x" data.long(A:&QSPI_STAT_REG)  ;read status reg

  Data.Set AD:&QSPI_CMD_REG %Long (&cmd_reg_def|&RE)                   ;cmd reg
  PRINT "read 1st 0x" Data.Long(AD:&QSPI_DAT_REG)  " (manufacture ID)" ; read data reg

  Data.Set AD:&QSPI_CMD_REG %Long (&cmd_reg_def|&RE)             ;cmd reg
  PRINT "read 2nd 0x" Data.Long(AD:&QSPI_DAT_REG) " (device ID)" ; read data reg

  Data.Set AD:&QSPI_CMD_REG %Long (&cmd_reg_def|&RE);cmd reg
  PRINT "read 3rd 0x" Data.Long(AD:&QSPI_DAT_REG)  ; read data reg

  Data.Set AD:&QSPI_BASE+0x48 %Long (&cmd_reg_def|&END)
  WAIT 100.ms

  RETURN
)

QSPI_INIT:
(
  Data.Set A:&QSPI_BASE+0x40 %LE %Long 0x00000009 ; QSPI_SPI_CLOCK_CNTRL_REG, clk DIV (can be faster)
  Data.Set A:&QSPI_BASE+0x40 %LE %Long 0x80000009 ; QSPI_SPI_CLOCK_CNTRL_REG, clken[31] + clk div[11:0]
  Data.Set A:&QSPI_BASE+0x44 %LE %Long 0x00000005 ; QSPI_SPI_DC_REG, sck-parks-at-1, falling edge shift

  //[28:24] dummy bits if Dbyte=0 (0)
  //[23:16] write command   	(use cmd2 for writes)
  //[13:12] read type       	(reads are quad using all dataX)
  //[11:10] Number of Dummy bytes (0 dummy bytes)
  //[9:8] Number of Bytes n-1	(3 addr bytes)
  //[7:0] Read CMD                (use cmd3 for reads)
  ;Data.Set A:&QSPI_BASE+0x54 %LE %Long 0x20203  ; QSPI_SPI_SETUP0_REG

  //[28:24] dummy bits if Dbyte=0 (0)
  //[23:16] write command   	(use cmd12 for writes)
  //[13:12] read type       	(reads are quad using all dataX)
  //[11:10] Number of Dummy bytes (1 dummy byte for fast read)
  //[9:8] Number of Bytes n-1	(3 addr bytes)
  //[7:0] Read CMD                (use cmd-0x6c/108 for reads)
  Data.Set A:&QSPI_BASE+0x54 %LE %Long 0x0012376c  ; QSPI_SPI_SETUP0_REG

  RETURN
)

PIN_MUX:
(
  ; Need to find proper mapping
  LOCAL &__IOMUX_U_BASE
  &__MSS_IOMUX_U_BASE=(0x53100000)

  Data.Set EAHB:0x53100298 %Long 0x83E70B13   ; ; kick0
  Data.Set EAHB:0x5310029C %Long 0x95A4F1E0     ; kick1
  WAIT 10.ms
  Data.Set EAHB:(((Var.VALUE(&__MSS_IOMUX_U_BASE)+Var.VALUE(0x0)))) %Long Var.VALUE(0x200)  ; IOMUX_QSPI0_CSN0_CFG_REG
  Data.Set EAHB:(((Var.VALUE(&__MSS_IOMUX_U_BASE)+Var.VALUE(0x4)))) %Long Var.VALUE(0x200)  ; IOMUX_QSPI0_CSN1_CFG_REG
  Data.Set EAHB:(((Var.VALUE(&__MSS_IOMUX_U_BASE)+Var.VALUE(0x8)))) %Long Var.VALUE(0x000)  ; IOMUX_QSPI0_CLK_CFG_REG
  Data.Set EAHB:(((Var.VALUE(&__MSS_IOMUX_U_BASE)+Var.VALUE(0xc)))) %Long Var.VALUE(0x200)  ; IOMUX_QSPI0_D0_CFG_REG
  Data.Set EAHB:(((Var.VALUE(&__MSS_IOMUX_U_BASE)+Var.VALUE(0x10)))) %Long Var.VALUE(0x200) ; IOMUX_QSPI0_D1_CFG_REG
  Data.Set EAHB:(((Var.VALUE(&__MSS_IOMUX_U_BASE)+Var.VALUE(0x14)))) %Long Var.VALUE(0x200) ; IOMUX_QSPI0_D2_CFG_REG
  Data.Set EAHB:(((Var.VALUE(&__MSS_IOMUX_U_BASE)+Var.VALUE(0x18)))) %Long Var.VALUE(0x200) ; IOMUX_QSPI0_D3_CFG_REG
  Data.Set EAHB:(((Var.VALUE(&__MSS_IOMUX_U_BASE)+Var.VALUE(0x244)))) %Long Var.VALUE(0x50) ; IOMUX_QSPI0_CLKLB_CFG_REG
  RETURN
)

CLK_INIT:
(
  LOCAL &__MSS_RCM_U_BASE
  &__MSS_RCM_U_BASE=(0x53208000)
  LOCAL &__MSS_RCM_QSPI0_CLK_DIV_VAL
  &__MSS_RCM_QSPI0_CLK_DIV_VAL=(0x00000210)
  LOCAL &__MSS_RCM_QSPI0_CLK_SRC_SEL
  &__MSS_RCM_QSPI0_CLK_SRC_SEL=(0x00000110)

  Data.Set EAHB:(&__MSS_RCM_U_BASE+&__MSS_RCM_QSPI0_CLK_DIV_VAL) %Long 0x444
  WAIT 100.mS
  Data.Set EAHB:(&__MSS_RCM_U_BASE+&__MSS_RCM_QSPI0_CLK_SRC_SEL) %Long 0x444
  RETURN
)

WATCHDOG_DISABLE:
(
  RETURN
)

CACHE_MMU_INIT:
(
  PRIVATE &i &tmpReg

  ; Enable MPU and disable I and D caches
  &tmpReg=Data.Long(C15:0x1)
  &tmpReg=&tmpReg|0x1             ; enable MPU
  &tmpReg=(&tmpReg&(~(0x1<<2.)))  ; disable D cache
  &tmpReg=(&tmpReg&(~(0x1<<12.))) ; disable I cache
  Data.Set C15:0x1 %Long &tmpReg

  ; Configure small region setup for flash programming
  PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x016 %Long 0x00000000 ; set default
  PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x216 %Long 0x0000003F
  PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x416 %Long 0x00001310
  PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x016 %Long 0x40160000 ; setup flash window
  PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x216 %Long 0x00000035
  PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x416 %Long 0x00001301
  PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x016 %Long 0x70000000 ; setup buffer space
  PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x216 %Long 0x00000027
  PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x416 %Long 0x0000030C
  ; Reset all other MPU regions
  &i=3.
  WHILE &i<16.
  (
    PER.Set.SaveIndex C15:0x026 %Long &i C15:0x016 %Long 0x0
    PER.Set.SaveIndex C15:0x026 %Long &i C15:0x216 %Long 0x0
    PER.Set.SaveIndex C15:0x026 %Long &i C15:0x416 %Long 0x0
    &i=&i+1.
  )

  RETURN
)