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2025-12-09 11:23:46 +09:00
parent 56d7259bc5
commit 8532a4c95c

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// T32_1000138 Fri Sep 20 11:55:12 2019
SYStem.CPU R8A779G-CR52
CORE.ASSIGN 1. ; Reset both cores
CORE 0.
SYStem.Option IMASKASM ON
SYStem.Option IMASKHLL ON
SYStem.Option DUALPORT ON
SYStem.MemAccess StopAndGo
SYStem.JtagClock 10.MHz
SYStem.Mode.Attach
break
// 01. Download ELF File
Data.LOAD.Elf C:\Work\3_Work_Src_Backup\MOBIS\MCAL-v4h-1_19.3.0.D_release(WDG)\rel\modules\wdg\sample_application\V4H\obj\arm\App_WDG_V4H_Sample.elf
// 02. Warm Reset
CD.DO C:\Work\3_Src\Gen4_R-Car_Trace32\2_Trunk\demo\arm\hardware\rcar_v4h\r_carv4h-cr52\r_carv4h-cr52_warm_reset.cmm
Go.direct main
ENDDO