72 lines
2.8 KiB
Plaintext
72 lines
2.8 KiB
Plaintext
OS에서 I2C 우선순위 확인 몇가지 ISR이 있음. 10~ 15까지. 10이 우선순위 높음. -> 관계없음
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Write 리턴값 확인 = 0 -> 관계 없는 듯.
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연결된 HW 디바이스가 뭐뭐 있는지 확인.
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PMIC와 1010(이건 뭐지?) VDD Power Control IC, 저항(분리함) 삭제후 NG
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I2C 속도,(400kbps) 200kbps로 Test중 NG 재현됨.
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스핀락 걸면 효과가 있는듯
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I2C 레지스터
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>SCSS
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Slave Clock Stretch Select
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This bit is used to select the timing of Clock Stretch.
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0: Clock Stretch is in front of ACK/NACK
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1: Clock Stretch is next to ACK/NACK
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>MIE
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Master Interface Enable
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When this bit is set to 1, the master interface is enabled.
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The master interface is disabled when this interface loses in arbitration of
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bus mastership even MIE bit indicates 1. If 0 is not subsequently written to
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the bit, the master interface is restored on detection of a STOP condition on
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the I2C bus. Regarding the state following a loss in arbitration of bus
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mastership, see the description of the MAL bit in ICMSR
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>FSB
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Forced Stop onto the Bus
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When this bit is set to 1, the master transmits a STOP condition on the bus
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at the end of the current transfer. If ESG is also set, the master immediately
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transmits a START condition and begins transmitting a new data packet. If
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ESG is not set, the master enters the idle state
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>SCGD
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SCL Clock Generation Divider
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When operation is in master mode, the SCL clock is generated from
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the internal clock by using SCGD as the ratio. This is also the
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operating clock in slave-mode operation while SCL is being held low
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to stop the bus after an overflow has occurred. SCGD must be
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specified in both master and slave modes. The formula expressing the
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relationship is:
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Equation 2: SCL rate calculation
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SCLfreq = I2Cck/(20 + SCGD 8 + F[(tICF + tr + IntDelay)
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I2Cck])
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I2Cck: I2C internal clock frequency
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tICF: I2C SCL falling time (depending on external load)
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tr: I2C SCL rising time (depending on external load)
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IntDelay: LSI internal delay corresponds to output buffer type.
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Open drain buffer: 50 ns (typ.), 110 ns (max.)
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F[n]: n rounded down to an integer
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Suggested settings for CDF and SCGD for CPU speeds and the two
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I2C bus speeds are given in table 107.3.
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Slave control register ICSCR
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Master control register ICMCR
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Slave status register ICSSR
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Master status register ICMSR
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Slave interrupt enable register ICSIER
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Master interrupt enable register ICMIER
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Clock control register ICCCR
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Slave address register ICSAR
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Master address register ICMAR
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Receive data register ICRXD
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Transmit data register ICTXD
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Clock control register 2 ICCCR2
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SCL mask control register ICMPR
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SCL high control register ICHPR
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SCL low control register ICLPR
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DMA enable register ICDMAER
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First bit setup cycle register ICFBSCR |