OS에서 I2C 우선순위 확인 몇가지 ISR이 있음. 10~ 15까지. 10이 우선순위 높음. -> 관계없음
Write 리턴값 확인 = 0 -> 관계 없는 듯.

연결된 HW 디바이스가 뭐뭐 있는지 확인.
PMIC와 1010(이건 뭐지?) VDD Power Control IC, 저항(분리함) 삭제후 NG

I2C 속도,(400kbps) 200kbps로 Test중 NG 재현됨.

스핀락 걸면 효과가 있는듯

I2C 레지스터

>SCSS
Slave Clock Stretch Select
This bit is used to select the timing of Clock Stretch.
0: Clock Stretch is in front of ACK/NACK
1: Clock Stretch is next to ACK/NACK

>MIE
Master Interface Enable
When this bit is set to 1, the master interface is enabled.
The master interface is disabled when this interface loses in arbitration of
bus mastership even MIE bit indicates 1. If 0 is not subsequently written to
the bit, the master interface is restored on detection of a STOP condition on
the I2C bus. Regarding the state following a loss in arbitration of bus
mastership, see the description of the MAL bit in ICMSR

>FSB
Forced Stop onto the Bus
When this bit is set to 1, the master transmits a STOP condition on the bus
at the end of the current transfer. If ESG is also set, the master immediately
transmits a START condition and begins transmitting a new data packet. If
ESG is not set, the master enters the idle state

>SCGD
SCL Clock Generation Divider
When operation is in master mode, the SCL clock is generated from
the internal clock by using SCGD as the ratio. This is also the
operating clock in slave-mode operation while SCL is being held low
to stop the bus after an overflow has occurred. SCGD must be
specified in both master and slave modes. The formula expressing the
relationship is:
Equation 2: SCL rate calculation
SCLfreq = I2Cck/(20 + SCGD  8 + F[(tICF + tr + IntDelay) 
I2Cck])
I2Cck: I2C internal clock frequency
tICF: I2C SCL falling time (depending on external load)
tr: I2C SCL rising time (depending on external load)
IntDelay: LSI internal delay corresponds to output buffer type.
Open drain buffer: 50 ns (typ.), 110 ns (max.)
F[n]: n rounded down to an integer
Suggested settings for CDF and SCGD for CPU speeds and the two
I2C bus speeds are given in table 107.3.


Slave control register						ICSCR
Master control register					ICMCR
Slave status register						ICSSR
Master status register						ICMSR
Slave interrupt enable register		ICSIER
Master interrupt enable register	ICMIER
Clock control register						ICCCR
Slave address register						ICSAR
Master address register					ICMAR
Receive data register						ICRXD
Transmit data register						ICTXD
Clock control register 2					ICCCR2
SCL mask control register				ICMPR
SCL high control register					ICHPR
SCL low control register					ICLPR
DMA enable register						ICDMAER
First bit setup cycle register			ICFBSCR