diff --git a/MOBIS/PRK3_(ADAS_Parking3)/Issue/Open_Multi_CR-Core_Abort/Multi_CR-Core_Abort_20251016.pptx b/MOBIS/PRK3_(ADAS_Parking3)/Issue/Open_Multi_CR-Core_Abort/Multi_CR-Core_Abort_20251016.pptx new file mode 100644 index 0000000..c085396 Binary files /dev/null and b/MOBIS/PRK3_(ADAS_Parking3)/Issue/Open_Multi_CR-Core_Abort/Multi_CR-Core_Abort_20251016.pptx differ diff --git a/MOBIS/PRK3_(ADAS_Parking3)/Issue/Open_Multi_CR-Core_Abort/Readme.txt b/MOBIS/PRK3_(ADAS_Parking3)/Issue/Open_Multi_CR-Core_Abort/Readme.txt new file mode 100644 index 0000000..432cb1a --- /dev/null +++ b/MOBIS/PRK3_(ADAS_Parking3)/Issue/Open_Multi_CR-Core_Abort/Readme.txt @@ -0,0 +1,297 @@ + +BSW_RTE->Source->BrsMainStartup.c +void Brs_PreMainStartup(void) -> 어셈블리어 이후 바로 실행되는 함수 +/* Core 0~2: Copy ATCM code from DDR load address to Core 0's TCM base address */ +I&D Cache Enable + +■ Core0~2 Interrupt Priority 변경 +C:\Renesas\r1015\BSW_RTE\GenData\Os_Hal_Context_Lcfg.c + + 435,45: /* .Entry = */ (uint32)&Os_Isr_Os_XSigRecvIsrHandler, /* PRQA S 0305 */ /* MD_Os_Hal_Rule11.1_0305 */ /* COMP_WARN_OS_HAL_EXPR_NOT_ARITHMETIC_TYPE */ + 802,45: /* .Entry = */ (uint32)&Os_Isr_Os_XSigRecvIsrHandler, /* PRQA S 0305 */ /* MD_Os_Hal_Rule11.1_0305 */ /* COMP_WARN_OS_HAL_EXPR_NOT_ARITHMETIC_TYPE */ + 1029,45: /* .Entry = */ (uint32)&Os_Isr_Os_XSigRecvIsrHandler, /* PRQA S 0305 */ /* MD_Os_Hal_Rule11.1_0305 */ /* COMP_WARN_OS_HAL_EXPR_NOT_ARITHMETIC_TYPE */ + + /* .IntLevel = */ (uint32)10u, -> Core0 (default 10u) + /* .IntLevel = */ (uint32)11u, -> Core1 (default 10u) + /* .IntLevel = */ (uint32)12u, -> Core2 (default 10u) + +BSW_RTE->Source->BrsMain.c +BSW_RTE->GenData>Rte.c>Rte_Start() + +Os_Core.c -> Os_CoreInit() + +Filter +\\*\*\*test*flg* + +Rte.c>Rte_Start> (void)SetRelAlarm(Rte_Al_TE_CtApUISP_FreeRunning_RCtApUISP_FreeRunning_10ms, + +#define OsTask_ASW_RCtApCOM_5ms OsTask_ASW_RCtApCOM_5ms + + +LDREX + + +EX_ADR_MASK + +Stuck 분석용 코드 +/********************************************************************************************************************** + +* INCLUDES + +*********************************************************************************************************************/ + +#include "Os_Cfg.h" + +#if defined(OS_CFG_COMPILER_IAR) + +# include "Os_Hal_Entry_IAR.inc" + +#elif defined(OS_CFG_COMPILER_ARM6) || defined(OS_CFG_COMPILER_ARM) + +# include "Os_Hal_Entry_ARM6.inc" + +#else + +# include "Os_Hal_Entry.inc" + +#endif + +/*********************************************************************************************************************** + +* DECLARATIONS + +**********************************************************************************************************************/ + + + OS_HAL_ASM_ARM_CODE + + OS_HAL_ASM_CODE_SECTION(OS_CODE) + + OS_HAL_ASM_IMPORT(Os_Hal_IrqHandler2) + + /* GIC first level interrupt handler */ + + OS_HAL_ASM_EXPORT(Os_Hal_IrqHandler1) + +OS_HAL_ASM_FUNCTION_BEGIN(Os_Hal_IrqHandler1) + + Os_Hal_IsrEntry_Interrupt_Gic Os_Hal_IrqHandler2 + + OS_HAL_ASM_FUNCTION_END(Os_Hal_IrqHandler1) + +/*********************************************************************************************************************** + +* Exception tables + +**********************************************************************************************************************/ + + /* ---------------------------------------------------------------------------------- + + * Exception Table - OsCore0 - Logical core 0 - Physical core 0 + + * --------------------------------------------------------------------------------- */ + + /* Entry symbol declaration */ + + OS_HAL_ASM_IMPORT(brsStartupEntryHyp) + + /* Exception Table - OsCore0 - Logical core 0 - Physical core 0 */ + + OS_HAL_ASM_CODE_SECTION(OS_EXCVEC_CORE0_CODE) + + OS_HAL_ASM_EXPORT(OsCfg_Hal_Core_OsCore0_ExceptionTable) + +OS_HAL_ASM_DEFINE_LABEL(OsCfg_Hal_Core_OsCore0_ExceptionTable) + + ldr pc,[pc,#0x18] /* Exception 0: Reset */ + + ldr pc,[pc,#0x18] /* Exception 1: Undefined Instruction */ + + ldr pc,[pc,#0x18] /* Exception 2: SVCall */ + + ldr pc,[pc,#0x18] /* Exception 3: Abort Prefetch */ + + ldr pc,[pc,#0x18] /* Exception 4: Abort Data */ + + ldr pc,[pc,#0x18] /* Exception 5: Reserved */ + + ldr pc,[pc,#0x18] /* Exception 6: IRQ */ + + ldr pc,[pc,#0x18] /* Exception 7: FIQ */ + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_0_Exception_0_Address) + + OS_HAL_ASM_DEFINE_WORD(brsStartupEntryHyp) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_0_Exception_1_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UndefinedInstructionExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_0_Exception_2_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UnhandledSysCallExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_0_Exception_3_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_PrefetchAbortExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_0_Exception_4_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_DataAbortExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_0_Exception_5_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UnhandledExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_0_Exception_6_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_IrqHandler1) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_0_Exception_7_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UnhandledExceptionEntry) + + /* ---------------------------------------------------------------------------------- + + * Exception Table - OsCore1 - Logical core 1 - Physical core 1 + + * --------------------------------------------------------------------------------- */ + + /* Exception Table - OsCore1 - Logical core 1 - Physical core 1 */ + + OS_HAL_ASM_CODE_SECTION(OS_EXCVEC_CORE1_CODE) + + OS_HAL_ASM_EXPORT(OsCfg_Hal_Core_OsCore1_ExceptionTable) + +OS_HAL_ASM_DEFINE_LABEL(OsCfg_Hal_Core_OsCore1_ExceptionTable) + + ldr pc,[pc,#0x18] /* Exception 0: Reset */ + + ldr pc,[pc,#0x18] /* Exception 1: Undefined Instruction */ + + ldr pc,[pc,#0x18] /* Exception 2: SVCall */ + + ldr pc,[pc,#0x18] /* Exception 3: Abort Prefetch */ + + ldr pc,[pc,#0x18] /* Exception 4: Abort Data */ + + ldr pc,[pc,#0x18] /* Exception 5: Reserved */ + + ldr pc,[pc,#0x18] /* Exception 6: IRQ */ + + ldr pc,[pc,#0x18] /* Exception 7: FIQ */ + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_1_Exception_0_Address) + + OS_HAL_ASM_DEFINE_WORD(brsStartupEntryHyp) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_1_Exception_1_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UndefinedInstructionExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_1_Exception_2_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UnhandledSysCallExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_1_Exception_3_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_PrefetchAbortExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_1_Exception_4_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_DataAbortExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_1_Exception_5_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UnhandledExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_1_Exception_6_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_IrqHandler1) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_1_Exception_7_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UnhandledExceptionEntry) + + /* ---------------------------------------------------------------------------------- + + * Exception Table - OsCore2 - Logical core 2 - Physical core 2 + + * --------------------------------------------------------------------------------- */ + + /* Exception Table - OsCore2 - Logical core 2 - Physical core 2 */ + + OS_HAL_ASM_CODE_SECTION(OS_EXCVEC_CORE2_CODE) + + OS_HAL_ASM_EXPORT(OsCfg_Hal_Core_OsCore2_ExceptionTable) + +OS_HAL_ASM_DEFINE_LABEL(OsCfg_Hal_Core_OsCore2_ExceptionTable) + + ldr pc,[pc,#0x18] /* Exception 0: Reset */ + + ldr pc,[pc,#0x18] /* Exception 1: Undefined Instruction */ + + ldr pc,[pc,#0x18] /* Exception 2: SVCall */ + + ldr pc,[pc,#0x18] /* Exception 3: Abort Prefetch */ + + ldr pc,[pc,#0x18] /* Exception 4: Abort Data */ + + ldr pc,[pc,#0x18] /* Exception 5: Reserved */ + + ldr pc,[pc,#0x18] /* Exception 6: IRQ */ + + ldr pc,[pc,#0x18] /* Exception 7: FIQ */ + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_2_Exception_0_Address) + + OS_HAL_ASM_DEFINE_WORD(brsStartupEntryHyp) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_2_Exception_1_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UndefinedInstructionExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_2_Exception_2_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UnhandledSysCallExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_2_Exception_3_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_PrefetchAbortExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_2_Exception_4_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_DataAbortExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_2_Exception_5_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UnhandledExceptionEntry) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_2_Exception_6_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_IrqHandler1) + +OS_HAL_ASM_DEFINE_LABEL(Os_Hal_Core_2_Exception_7_Address) + + OS_HAL_ASM_DEFINE_WORD(Os_Hal_UnhandledExceptionEntry) + + +/*********************************************************************************************************************** + +* Interrupt wrappers + +**********************************************************************************************************************/ + + + OS_HAL_ASM_MODULE_END + + + + + + + + + + + \ No newline at end of file diff --git a/MOBIS/PRK3_(ADAS_Parking3)/Issue/Open_PMIC_Jira/Readme.txt b/MOBIS/PRK3_(ADAS_Parking3)/Issue/Open_PMIC_Jira/Readme.txt new file mode 100644 index 0000000..2331610 --- /dev/null +++ b/MOBIS/PRK3_(ADAS_Parking3)/Issue/Open_PMIC_Jira/Readme.txt @@ -0,0 +1,25 @@ +Mobis CRC 계산 + +void write_i2c_with_crc_test(const uint8 *data, uint32 length, IicSlaveConfigPtr LpSlaveConfig) { + + //uint8 buffer[256]; // Ensure this is large enough + + if (length + 2 > sizeof(buffer)) return; // Prevent overflow + + // Copy data + + for (uint8 i = 0; i < length+1; ++i) { + + buffer[i] = data[i]; + + } + + // Calculate and append CRC + + buffer[length+1] = crc8(data, length+1); + + // Send data + CRC over I2C + + CddIic_Ch5Write(&buffer[1], length+1, LpSlaveConfig); + +}