67 lines
2.2 KiB
Plaintext
67 lines
2.2 KiB
Plaintext
/*******************************************************************************
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** Global Symbols **
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*******************************************************************************/
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#define PFC_GP1_BASE (0xE6060100u)
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/* CPG */
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#define CPG_BASE_ADDR (0xE6150000)
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#define CPG_SCIF *((volatile unsigned int *)(CPG_BASE_ADDR + 0x2D18)) /* SCIF1 */
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#define CPG_CPGWPR *((volatile unsigned int *)(CPG_BASE_ADDR + 0x0000))
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#define CPG_SCIF_MASK ((unsigned int)(1 << 3)) /* SCIF1 is bit 3 */
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/* PFC for SCIF1: P1_6 (TX), P1_7 (RX) */
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#define PFC_PMMR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0000))
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#define PFC_GPSR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0040))
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#define PFC_IP0SR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0060)) /* ALT select for P1_6 */
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#define PFC_IP1SR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0064)) /* ALT select for P1_7 */
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#define PFC_P1_6_MASK ((unsigned int)(1 << 6))
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#define PFC_P1_7_MASK ((unsigned int)(1 << 7))
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#define PFC_IP0SR1_TX_MASK ((unsigned int)(0xF << 24)) /* P1_6 is bit[27:24] */
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#define PFC_IP0SR1_TX_VAL ((unsigned int)(0x2 << 24)) /* ALT2 = SCIF1_TX */
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#define PFC_IP1SR1_RX_MASK ((unsigned int)(0xF << 0)) /* P1_7 is bit[3:0] */
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#define PFC_IP1SR1_RX_VAL ((unsigned int)(0x2 << 0)) /* ALT2 = SCIF1_RX */
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/* Initialize clocks and pins */
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void Clock_Pin_Init_SCIF1(void)
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{
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unsigned int val;
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/* === Enable SCIF1 clock === */
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/* Using SCIF HWIP for MCAL Console print */
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/* CPG setting */
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CPG_CPGWPR = ~(CPG_SCIF & ~CPG_SCIF_MASK);
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CPG_SCIF &= ~CPG_SCIF_MASK;
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/* PFC setting */
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/* SCIF1 TX */
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val = PFC_IP0SR1;
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val &= ~PFC_IP0SR1_TX_MASK;
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val |= PFC_IP0SR1_TX_VAL;
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PFC_PMMR1 = ~val;
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PFC_IP0SR1 = val;
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val = PFC_GPSR1;
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val |= PFC_P1_6_MASK;
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PFC_PMMR1 = ~val;
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PFC_GPSR1 = val;
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/* === Set P1_7 as SCIF1_RX === */
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val = PFC_IP1SR1;
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val &= ~PFC_IP1SR1_RX_MASK;
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val |= PFC_IP1SR1_RX_VAL;
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PFC_PMMR1 = ~val;
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PFC_IP1SR1 = val;
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val = PFC_GPSR1;
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val |= PFC_P1_7_MASK;
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PFC_PMMR1 = ~val;
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PFC_GPSR1 = val;
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} |