/******************************************************************************* ** Global Symbols ** *******************************************************************************/ #define PFC_GP1_BASE (0xE6060100u) /* CPG */ #define CPG_BASE_ADDR (0xE6150000) #define CPG_SCIF *((volatile unsigned int *)(CPG_BASE_ADDR + 0x2D18)) /* SCIF1 */ #define CPG_CPGWPR *((volatile unsigned int *)(CPG_BASE_ADDR + 0x0000)) #define CPG_SCIF_MASK ((unsigned int)(1 << 3)) /* SCIF1 is bit 3 */ /* PFC for SCIF1: P1_6 (TX), P1_7 (RX) */ #define PFC_PMMR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0000)) #define PFC_GPSR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0040)) #define PFC_IP0SR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0060)) /* ALT select for P1_6 */ #define PFC_IP1SR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0064)) /* ALT select for P1_7 */ #define PFC_P1_6_MASK ((unsigned int)(1 << 6)) #define PFC_P1_7_MASK ((unsigned int)(1 << 7)) #define PFC_IP0SR1_TX_MASK ((unsigned int)(0xF << 24)) /* P1_6 is bit[27:24] */ #define PFC_IP0SR1_TX_VAL ((unsigned int)(0x2 << 24)) /* ALT2 = SCIF1_TX */ #define PFC_IP1SR1_RX_MASK ((unsigned int)(0xF << 0)) /* P1_7 is bit[3:0] */ #define PFC_IP1SR1_RX_VAL ((unsigned int)(0x2 << 0)) /* ALT2 = SCIF1_RX */ /* Initialize clocks and pins */ void Clock_Pin_Init_SCIF1(void) { unsigned int val; /* === Enable SCIF1 clock === */ /* Using SCIF HWIP for MCAL Console print */ /* CPG setting */ CPG_CPGWPR = ~(CPG_SCIF & ~CPG_SCIF_MASK); CPG_SCIF &= ~CPG_SCIF_MASK; /* PFC setting */ /* SCIF1 TX */ val = PFC_IP0SR1; val &= ~PFC_IP0SR1_TX_MASK; val |= PFC_IP0SR1_TX_VAL; PFC_PMMR1 = ~val; PFC_IP0SR1 = val; val = PFC_GPSR1; val |= PFC_P1_6_MASK; PFC_PMMR1 = ~val; PFC_GPSR1 = val; /* === Set P1_7 as SCIF1_RX === */ val = PFC_IP1SR1; val &= ~PFC_IP1SR1_RX_MASK; val |= PFC_IP1SR1_RX_VAL; PFC_PMMR1 = ~val; PFC_IP1SR1 = val; val = PFC_GPSR1; val |= PFC_P1_7_MASK; PFC_PMMR1 = ~val; PFC_GPSR1 = val; }