From 6df92d6ae0e8cb751636b7784faca959d6462987 Mon Sep 17 00:00:00 2001 From: woody Date: Tue, 30 Sep 2025 01:27:57 +0900 Subject: [PATCH] =?UTF-8?q?SCIF=20=ED=8C=8C=EC=9D=BC=20=EC=97=85=EB=A1=9C?= =?UTF-8?q?=EB=93=9C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- 정리필요/SCIF0.txt | 72 ++++++++++++++++++++++++++++++++++++++++++++++ 정리필요/SCIF1.txt | 67 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 정리필요/SCIF0.txt create mode 100644 정리필요/SCIF1.txt diff --git a/정리필요/SCIF0.txt b/정리필요/SCIF0.txt new file mode 100644 index 0000000..0957cbd --- /dev/null +++ b/정리필요/SCIF0.txt @@ -0,0 +1,72 @@ +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + +/* CPG */ +#define CPG_BASE_ADDR (0xE6150000) +#define CPG_SCIF *((volatile uint32 *)(CPG_BASE_ADDR + 0x2D1C)) +#define CPG_HSCIF *((volatile uint32 *)(CPG_BASE_ADDR + 0x2D14)) +#define CPG_PFC *((volatile uint32 *)(CPG_BASE_ADDR + 0x2D24)) +#define CPG_TMU0 *((volatile uint32 *)(CPG_BASE_ADDR + 0x2D1C)) +#define CPG_CPGWPR *((volatile uint32 *)(CPG_BASE_ADDR + 0x0000)) +#define CPG_SCIF_MASK ((uint32)(1 << 2)) +#define CPG_HSCIF_MASK ((uint32)(1 << 14)) +#define CPG_PFC_MASK ((uint32)(1 << 16)) +#define CPG_TMU0_MASK ((uint32)(1 << 13)) + +/* Using SCIF HWIP for MCAL Console print */ +/* PFC */ +#define PFC_PMMR1 *((volatile uint32 *)(PFC_GP1_BASE + 0x0000)) +#define PFC_GPSR1_TX *((volatile uint32 *)(PFC_GP1_BASE + 0x0040)) +#define PFC_GPSR1_RX *((volatile uint32 *)(PFC_GP1_BASE + 0x0040)) +#define PFC_IP1SR1_TX *((volatile uint32 *)(PFC_GP1_BASE + 0x0064)) +#define PFC_IP2SR1_RX *((volatile uint32 *)(PFC_GP1_BASE + 0x0068)) + +#define PFC_GPSR1_TX_MASK ((uint32)(1 << 12)) +#define PFC_GPSR1_RX_MASK ((uint32)(1 << 16)) +#define PFC_IP1SR1_TX_MASK ((uint32)(0xF << 16)) +#define PFC_IP1SR1_TX_VAL ((uint32)(1 << 16)) +#define PFC_IP2SR1_RX_MASK ((uint32)(0xF << 0)) +#define PFC_IP2SR1_RX_VAL ((uint32)(1 << 0)) +/* Initialize clocks and pins */ +static void Clock_Pin_Init() +{ + uint32 Value; + + /* CPG setting */ + CPG_CPGWPR = ~(CPG_TMU0 & ~CPG_TMU0_MASK); + CPG_TMU0 &= ~CPG_TMU0_MASK; + + /* Using SCIF HWIP for MCAL Console print */ + /* CPG setting */ + CPG_CPGWPR = ~(CPG_SCIF & ~CPG_SCIF_MASK); + CPG_SCIF &= ~CPG_SCIF_MASK; + CPG_CPGWPR = ~(CPG_PFC & ~CPG_PFC_MASK); + CPG_PFC &= ~CPG_PFC_MASK; + + /* PFC setting */ + /* SCIF TX */ + Value = PFC_IP1SR1_TX; + Value &= (~PFC_IP1SR1_TX_MASK); + Value |= PFC_IP1SR1_TX_VAL; + PFC_PMMR1 = ~Value; + PFC_IP1SR1_TX = Value; + + Value = PFC_GPSR1_TX; + Value |= PFC_GPSR1_TX_MASK; + PFC_PMMR1 = ~Value; + PFC_GPSR1_TX = Value; + + /* SCIF RX */ + Value = PFC_IP2SR1_RX; + Value &= (~PFC_IP2SR1_RX_MASK); + Value |= PFC_IP2SR1_RX_VAL; + PFC_PMMR1 = ~Value; + PFC_IP2SR1_RX = Value; + + Value = PFC_GPSR1_RX; + Value |= PFC_GPSR1_RX_MASK; + PFC_PMMR1 = ~Value; + PFC_GPSR1_RX = Value; + +} \ No newline at end of file diff --git a/정리필요/SCIF1.txt b/정리필요/SCIF1.txt new file mode 100644 index 0000000..7135ba6 --- /dev/null +++ b/정리필요/SCIF1.txt @@ -0,0 +1,67 @@ +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + +#define PFC_GP1_BASE (0xE6060100u) + +/* CPG */ +#define CPG_BASE_ADDR (0xE6150000) +#define CPG_SCIF *((volatile unsigned int *)(CPG_BASE_ADDR + 0x2D18)) /* SCIF1 */ +#define CPG_CPGWPR *((volatile unsigned int *)(CPG_BASE_ADDR + 0x0000)) +#define CPG_SCIF_MASK ((unsigned int)(1 << 3)) /* SCIF1 is bit 3 */ + +/* PFC for SCIF1: P1_6 (TX), P1_7 (RX) */ +#define PFC_PMMR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0000)) +#define PFC_GPSR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0040)) +#define PFC_IP0SR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0060)) /* ALT select for P1_6 */ +#define PFC_IP1SR1 *((volatile unsigned int *)(PFC_GP1_BASE + 0x0064)) /* ALT select for P1_7 */ + +#define PFC_P1_6_MASK ((unsigned int)(1 << 6)) +#define PFC_P1_7_MASK ((unsigned int)(1 << 7)) + +#define PFC_IP0SR1_TX_MASK ((unsigned int)(0xF << 24)) /* P1_6 is bit[27:24] */ +#define PFC_IP0SR1_TX_VAL ((unsigned int)(0x2 << 24)) /* ALT2 = SCIF1_TX */ +#define PFC_IP1SR1_RX_MASK ((unsigned int)(0xF << 0)) /* P1_7 is bit[3:0] */ +#define PFC_IP1SR1_RX_VAL ((unsigned int)(0x2 << 0)) /* ALT2 = SCIF1_RX */ + + + + + + + +/* Initialize clocks and pins */ +void Clock_Pin_Init_SCIF1(void) +{ + unsigned int val; + + /* === Enable SCIF1 clock === */ + /* Using SCIF HWIP for MCAL Console print */ + /* CPG setting */ + CPG_CPGWPR = ~(CPG_SCIF & ~CPG_SCIF_MASK); + CPG_SCIF &= ~CPG_SCIF_MASK; + /* PFC setting */ + /* SCIF1 TX */ + val = PFC_IP0SR1; + val &= ~PFC_IP0SR1_TX_MASK; + val |= PFC_IP0SR1_TX_VAL; + PFC_PMMR1 = ~val; + PFC_IP0SR1 = val; + + val = PFC_GPSR1; + val |= PFC_P1_6_MASK; + PFC_PMMR1 = ~val; + PFC_GPSR1 = val; + + /* === Set P1_7 as SCIF1_RX === */ + val = PFC_IP1SR1; + val &= ~PFC_IP1SR1_RX_MASK; + val |= PFC_IP1SR1_RX_VAL; + PFC_PMMR1 = ~val; + PFC_IP1SR1 = val; + + val = PFC_GPSR1; + val |= PFC_P1_7_MASK; + PFC_PMMR1 = ~val; + PFC_GPSR1 = val; +} \ No newline at end of file